2 * Copyright (c) 2013 Thomas Skibo
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Zynq-7000 Devcfg driver. This allows programming the PL (FPGA) section
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
34 * (v1.4) November 16, 2012. Xilinx doc UG585. PL Configuration is
35 * covered in section 6.4.5.
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/sysctl.h>
48 #include <sys/mutex.h>
49 #include <sys/resource.h>
53 #include <machine/bus.h>
54 #include <machine/resource.h>
55 #include <machine/stdarg.h>
57 #include <dev/fdt/fdt_common.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_bus_subr.h>
61 #include <arm/xilinx/zy7_slcr.h>
63 struct zy7_devcfg_softc {
66 struct resource *mem_res;
67 struct resource *irq_res;
68 struct cdev *sc_ctl_dev;
71 bus_dma_tag_t dma_tag;
77 static struct zy7_devcfg_softc *zy7_devcfg_softc_p;
79 #define DEVCFG_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
80 #define DEVCFG_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
81 #define DEVCFG_SC_LOCK_INIT(sc) \
82 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
83 "zy7_devcfg", MTX_DEF)
84 #define DEVCFG_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx);
85 #define DEVCFG_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED);
87 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
88 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
90 SYSCTL_NODE(_hw, OID_AUTO, fpga, CTLFLAG_RD, 0, \
91 "Xilinx Zynq-7000 PL (FPGA) section");
93 static int zy7_devcfg_sysctl_pl_done(SYSCTL_HANDLER_ARGS);
94 SYSCTL_PROC(_hw_fpga, OID_AUTO, pl_done, CTLTYPE_INT | CTLFLAG_RD, NULL, 0,
95 zy7_devcfg_sysctl_pl_done, "I", "PL section config DONE signal");
97 static int zy7_en_level_shifters = 1;
98 SYSCTL_INT(_hw_fpga, OID_AUTO, en_level_shifters, CTLFLAG_RW,
99 &zy7_en_level_shifters, 0,
100 "Enable PS-PL level shifters after device config");
102 static int zy7_ps_vers = 0;
103 SYSCTL_INT(_hw, OID_AUTO, ps_vers, CTLFLAG_RD, &zy7_ps_vers, 0,
104 "Zynq-7000 PS version");
107 /* cdev entry points. */
108 static int zy7_devcfg_open(struct cdev *, int, int, struct thread *);
109 static int zy7_devcfg_write(struct cdev *, struct uio *, int);
110 static int zy7_devcfg_close(struct cdev *, int, int, struct thread *);
113 struct cdevsw zy7_devcfg_cdevsw = {
114 .d_version = D_VERSION,
115 .d_open = zy7_devcfg_open,
116 .d_write = zy7_devcfg_write,
117 .d_close = zy7_devcfg_close,
121 /* Devcfg block registers. */
122 #define ZY7_DEVCFG_CTRL 0x0000
123 #define ZY7_DEVCFG_CTRL_FORCE_RST (1<<31)
124 #define ZY7_DEVCFG_CTRL_PCFG_PROG_B (1<<30)
125 #define ZY7_DEVCFG_CTRL_PCFG_POR_CNT_4K (1<<29)
126 #define ZY7_DEVCFG_CTRL_PCAP_PR (1<<27)
127 #define ZY7_DEVCFG_CTRL_PCAP_MODE (1<<26)
128 #define ZY7_DEVCFG_CTRL_QTR_PCAP_RATE_EN (1<<25)
129 #define ZY7_DEVCFG_CTRL_MULTIBOOT_EN (1<<24)
130 #define ZY7_DEVCFG_CTRL_JTAG_CHAIN_DIS (1<<23)
131 #define ZY7_DEVCFG_CTRL_USER_MODE (1<<15)
132 #define ZY7_DEVCFG_CTRL_RESVD_WR11 (3<<13) /* always write 11 */
133 #define ZY7_DEVCFG_CTRL_PCFG_AES_FUSE (1<<12)
134 #define ZY7_DEVCFG_CTRL_PCFG_AES_EN_MASK (7<<9) /* all 1's or 0's */
135 #define ZY7_DEVCFG_CTRL_SEU_EN (1<<8)
136 #define ZY7_DEVCFG_CTRL_SEC_EN (1<<7)
137 #define ZY7_DEVCFG_CTRL_SPNIDEN (1<<6)
138 #define ZY7_DEVCFG_CTRL_SPIDEN (1<<5)
139 #define ZY7_DEVCFG_CTRL_NIDEN (1<<4)
140 #define ZY7_DEVCFG_CTRL_DBGEN (1<<3)
141 #define ZY7_DEVCFG_CTRL_DAP_EN_MASK (7<<0) /* all 1's to enable */
143 #define ZY7_DEVCFG_LOCK 0x004
144 #define ZY7_DEVCFG_LOCK_AES_FUSE_LOCK (1<<4)
145 #define ZY7_DEVCFG_LOCK_AES_EN (1<<3)
146 #define ZY7_DEVCFG_LOCK_SEU_LOCK (1<<2)
147 #define ZY7_DEVCFG_LOCK_SEC_LOCK (1<<1)
148 #define ZY7_DEVCFG_LOCK_DBG_LOCK (1<<0)
150 #define ZY7_DEVCFG_CFG 0x008
151 #define ZY7_DEVCFG_CFG_RFIFO_TH_MASK (3<<10)
152 #define ZY7_DEVCFG_CFG_WFIFO_TH_MASK (3<<8)
153 #define ZY7_DEVCFG_CFG_RCLK_EDGE (1<<7)
154 #define ZY7_DEVCFG_CFG_WCLK_EDGE (1<<6)
155 #define ZY7_DEVCFG_CFG_DIS_SRC_INC (1<<5)
156 #define ZY7_DEVCFG_CFG_DIS_DST_INC (1<<4)
158 #define ZY7_DEVCFG_INT_STATUS 0x00C
159 #define ZY7_DEVCFG_INT_MASK 0x010
160 #define ZY7_DEVCFG_INT_PSS_GTS_USR_B (1<<31)
161 #define ZY7_DEVCFG_INT_PSS_FST_CFG_B (1<<30)
162 #define ZY7_DEVCFG_INT_PSS_GPWRDWN_B (1<<29)
163 #define ZY7_DEVCFG_INT_PSS_GTS_CFG_B (1<<28)
164 #define ZY7_DEVCFG_INT_CFG_RESET_B (1<<27)
165 #define ZY7_DEVCFG_INT_AXI_WTO (1<<23) /* axi write timeout */
166 #define ZY7_DEVCFG_INT_AXI_WERR (1<<22) /* axi write err */
167 #define ZY7_DEVCFG_INT_AXI_RTO (1<<21) /* axi read timeout */
168 #define ZY7_DEVCFG_INT_AXI_RERR (1<<20) /* axi read err */
169 #define ZY7_DEVCFG_INT_RX_FIFO_OV (1<<18) /* rx fifo overflow */
170 #define ZY7_DEVCFG_INT_WR_FIFO_LVL (1<<17) /* wr fifo < level */
171 #define ZY7_DEVCFG_INT_RD_FIFO_LVL (1<<16) /* rd fifo >= level */
172 #define ZY7_DEVCFG_INT_DMA_CMD_ERR (1<<15)
173 #define ZY7_DEVCFG_INT_DMA_Q_OV (1<<14)
174 #define ZY7_DEVCFG_INT_DMA_DONE (1<<13)
175 #define ZY7_DEVCFG_INT_DMA_PCAP_DONE (1<<12)
176 #define ZY7_DEVCFG_INT_P2D_LEN_ERR (1<<11)
177 #define ZY7_DEVCFG_INT_PCFG_HMAC_ERR (1<<6)
178 #define ZY7_DEVCFG_INT_PCFG_SEU_ERR (1<<5)
179 #define ZY7_DEVCFG_INT_PCFG_POR_B (1<<4)
180 #define ZY7_DEVCFG_INT_PCFG_CFG_RST (1<<3)
181 #define ZY7_DEVCFG_INT_PCFG_DONE (1<<2)
182 #define ZY7_DEVCFG_INT_PCFG_INIT_PE (1<<1)
183 #define ZY7_DEVCFG_INT_PCFG_INIT_NE (1<<0)
184 #define ZY7_DEVCFG_INT_ERRORS 0x00f0f860
185 #define ZY7_DEVCFG_INT_ALL 0xf8f7f87f
187 #define ZY7_DEVCFG_STATUS 0x014
188 #define ZY7_DEVCFG_STATUS_DMA_CMD_Q_F (1<<31) /* cmd queue full */
189 #define ZY7_DEVCFG_STATUS_DMA_CMD_Q_E (1<<30) /* cmd queue empty */
190 #define ZY7_DEVCFG_STATUS_DONE_COUNT_MASK (3<<28)
191 #define ZY7_DEVCFG_STATUS_DONE_COUNT_SHIFT 28
192 #define ZY7_DEVCFG_STATUS_RX_FIFO_LVL_MASK (0x1f<<20)
193 #define ZY7_DEVCFG_STATUS_RX_FIFO_LVL_SHIFT 20
194 #define ZY7_DEVCFG_STATUS_TX_FIFO_LVL_MASK (0x7f<<12)
195 #define ZY7_DEVCFG_STATUS_TX_FIFO_LVL_SHIFT 12
196 #define ZY7_DEVCFG_STATUS_PSS_GTS_USR_B (1<<11)
197 #define ZY7_DEVCFG_STATUS_PSS_FST_CFG_B (1<<10)
198 #define ZY7_DEVCFG_STATUS_PSS_GPWRDWN_B (1<<9)
199 #define ZY7_DEVCFG_STATUS_PSS_GTS_CFG_B (1<<8)
200 #define ZY7_DEVCFG_STATUS_ILL_APB_ACCE (1<<6)
201 #define ZY7_DEVCFG_STATUS_PSS_CFG_RESET_B (1<<5)
202 #define ZY7_DEVCFG_STATUS_PCFG_INIT (1<<4)
203 #define ZY7_DEVCFG_STATUS_EFUSE_BBRAM_KEY_DIS (1<<3)
204 #define ZY7_DEVCFG_STATUS_EFUSE_SEC_EN (1<<2)
205 #define ZY7_DEVCFG_STATUS_EFUSE_JTAG_DIS (1<<1)
207 #define ZY7_DEVCFG_DMA_SRC_ADDR 0x018
208 #define ZY7_DEVCFG_DMA_DST_ADDR 0x01c
209 #define ZY7_DEVCFG_DMA_ADDR_WAIT_PCAP 1
210 #define ZY7_DEVCFG_DMA_ADDR_ILLEGAL 0xffffffff
212 #define ZY7_DEVCFG_DMA_SRC_LEN 0x020 /* in 4-byte words. */
213 #define ZY7_DEVCFG_DMA_SRC_LEN_MAX 0x7ffffff
214 #define ZY7_DEVCFG_DMA_DST_LEN 0x024
215 #define ZY7_DEVCFG_ROM_SHADOW 0x028
216 #define ZY7_DEVCFG_MULTIBOOT_ADDR 0x02c
217 #define ZY7_DEVCFG_SW_ID 0x030
218 #define ZY7_DEVCFG_UNLOCK 0x034
219 #define ZY7_DEVCFG_UNLOCK_MAGIC 0x757bdf0d
220 #define ZY7_DEVCFG_MCTRL 0x080
221 #define ZY7_DEVCFG_MCTRL_PS_VERS_MASK (0xf<<28)
222 #define ZY7_DEVCFG_MCTRL_PS_VERS_SHIFT 28
223 #define ZY7_DEVCFG_MCTRL_PCFG_POR_B (1<<8)
224 #define ZY7_DEVCFG_MCTRL_INT_PCAP_LPBK (1<<4)
225 #define ZY7_DEVCFG_XADCIF_CFG 0x100
226 #define ZY7_DEVCFG_XADCIF_INT_STAT 0x104
227 #define ZY7_DEVCFG_XADCIF_INT_MASK 0x108
228 #define ZY7_DEVCFG_XADCIF_MSTS 0x10c
229 #define ZY7_DEVCFG_XADCIF_CMD_FIFO 0x110
230 #define ZY7_DEVCFG_XADCIF_RD_FIFO 0x114
231 #define ZY7_DEVCFG_XADCIF_MCTL 0x118
234 /* Enable programming the PL through PCAP. */
236 zy7_devcfg_init_hw(struct zy7_devcfg_softc *sc)
239 DEVCFG_SC_ASSERT_LOCKED(sc);
241 /* Set devcfg control register. */
242 WR4(sc, ZY7_DEVCFG_CTRL,
243 ZY7_DEVCFG_CTRL_PCFG_PROG_B |
244 ZY7_DEVCFG_CTRL_PCAP_PR |
245 ZY7_DEVCFG_CTRL_PCAP_MODE |
246 ZY7_DEVCFG_CTRL_USER_MODE |
247 ZY7_DEVCFG_CTRL_RESVD_WR11 |
248 ZY7_DEVCFG_CTRL_SPNIDEN |
249 ZY7_DEVCFG_CTRL_SPIDEN |
250 ZY7_DEVCFG_CTRL_NIDEN |
251 ZY7_DEVCFG_CTRL_DBGEN |
252 ZY7_DEVCFG_CTRL_DAP_EN_MASK);
254 /* Turn off internal PCAP loopback. */
255 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) &
256 ~ZY7_DEVCFG_MCTRL_INT_PCAP_LPBK);
259 /* Clear previous configuration of the PL by asserting PROG_B. */
261 zy7_devcfg_reset_pl(struct zy7_devcfg_softc *sc)
266 DEVCFG_SC_ASSERT_LOCKED(sc);
268 devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL);
270 /* Clear sticky bits and set up INIT signal positive edge interrupt. */
271 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
272 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE);
274 /* Deassert PROG_B (active low). */
275 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B;
276 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
279 * Wait for INIT to assert. If it is already asserted, we may not get
280 * an edge interrupt so cancel it and continue.
282 if ((RD4(sc, ZY7_DEVCFG_STATUS) &
283 ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) {
284 /* Already asserted. Cancel interrupt. */
285 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0);
288 /* Wait for positive edge interrupt. */
289 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i1", hz);
294 /* Reassert PROG_B (active low). */
295 devcfg_ctl &= ~ZY7_DEVCFG_CTRL_PCFG_PROG_B;
296 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
298 /* Wait for INIT deasserted. This happens almost instantly. */
300 while ((RD4(sc, ZY7_DEVCFG_STATUS) &
301 ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) {
307 /* Clear sticky bits and set up INIT positive edge interrupt. */
308 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
309 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE);
311 /* Deassert PROG_B again. */
312 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B;
313 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
316 * Wait for INIT asserted indicating FPGA internal initialization
319 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i2", hz);
323 /* Clear sticky DONE bit in interrupt status. */
324 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
329 /* Callback function for bus_dmamap_load(). */
331 zy7_dma_cb2(void *arg, bus_dma_segment_t *seg, int nsegs, int error)
333 if (!error && nsegs == 1)
334 *(bus_addr_t *)arg = seg[0].ds_addr;
339 zy7_devcfg_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
341 struct zy7_devcfg_softc *sc = dev->si_drv1;
346 DEVCFG_SC_UNLOCK(sc);
351 err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 4, 0,
352 BUS_SPACE_MAXADDR_32BIT,
363 DEVCFG_SC_UNLOCK(sc);
368 DEVCFG_SC_UNLOCK(sc);
373 zy7_devcfg_write(struct cdev *dev, struct uio *uio, int ioflag)
375 struct zy7_devcfg_softc *sc = dev->si_drv1;
377 bus_addr_t dma_physaddr;
382 /* First write? Reset PL. */
383 if (uio->uio_offset == 0 && uio->uio_resid > 0) {
384 zy7_devcfg_init_hw(sc);
385 zy7_slcr_preload_pl();
386 err = zy7_devcfg_reset_pl(sc);
388 DEVCFG_SC_UNLOCK(sc);
393 /* Allocate dma memory and load. */
394 err = bus_dmamem_alloc(sc->dma_tag, &dma_mem, BUS_DMA_NOWAIT,
397 DEVCFG_SC_UNLOCK(sc);
400 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, dma_mem, PAGE_SIZE,
401 zy7_dma_cb2, &dma_physaddr, 0);
403 bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map);
404 DEVCFG_SC_UNLOCK(sc);
408 while (uio->uio_resid > 0) {
409 /* If DONE signal has been set, we shouldn't write anymore. */
410 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
411 ZY7_DEVCFG_INT_PCFG_DONE) != 0) {
416 /* uiomove the data from user buffer to our dma map. */
417 segsz = MIN(PAGE_SIZE, uio->uio_resid);
418 DEVCFG_SC_UNLOCK(sc);
419 err = uiomove(dma_mem, segsz, uio);
424 /* Flush the cache to memory. */
425 bus_dmamap_sync(sc->dma_tag, sc->dma_map,
426 BUS_DMASYNC_PREWRITE);
428 /* Program devcfg's DMA engine. The ordering of these
429 * register writes is critical.
431 if (uio->uio_resid > segsz)
432 WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR,
433 (uint32_t) dma_physaddr);
435 WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR,
436 (uint32_t) dma_physaddr |
437 ZY7_DEVCFG_DMA_ADDR_WAIT_PCAP);
438 WR4(sc, ZY7_DEVCFG_DMA_DST_ADDR, ZY7_DEVCFG_DMA_ADDR_ILLEGAL);
439 WR4(sc, ZY7_DEVCFG_DMA_SRC_LEN, (segsz+3)/4);
440 WR4(sc, ZY7_DEVCFG_DMA_DST_LEN, 0);
442 /* Now clear done bit and set up DMA done interrupt. */
443 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
444 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_DMA_DONE);
446 /* Wait for DMA done interrupt. */
447 err = mtx_sleep(sc->dma_map, &sc->sc_mtx, PCATCH,
452 bus_dmamap_sync(sc->dma_tag, sc->dma_map,
453 BUS_DMASYNC_POSTWRITE);
455 /* Check DONE signal. */
456 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
457 ZY7_DEVCFG_INT_PCFG_DONE) != 0)
458 zy7_slcr_postload_pl(zy7_en_level_shifters);
461 bus_dmamap_unload(sc->dma_tag, sc->dma_map);
462 bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map);
463 DEVCFG_SC_UNLOCK(sc);
468 zy7_devcfg_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
470 struct zy7_devcfg_softc *sc = dev->si_drv1;
474 bus_dma_tag_destroy(sc->dma_tag);
475 DEVCFG_SC_UNLOCK(sc);
482 zy7_devcfg_intr(void *arg)
484 struct zy7_devcfg_softc *sc = (struct zy7_devcfg_softc *)arg;
485 uint32_t istatus, imask;
489 istatus = RD4(sc, ZY7_DEVCFG_INT_STATUS);
490 imask = ~RD4(sc, ZY7_DEVCFG_INT_MASK);
492 /* Turn interrupt off. */
493 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0);
495 if ((istatus & imask) == 0) {
496 DEVCFG_SC_UNLOCK(sc);
501 if ((istatus & ZY7_DEVCFG_INT_DMA_DONE) != 0)
504 /* INIT_B positive edge? */
505 if ((istatus & ZY7_DEVCFG_INT_PCFG_INIT_PE) != 0)
508 DEVCFG_SC_UNLOCK(sc);
511 /* zy7_devcfg_sysctl_pl_done() returns status of the PL_DONE signal.
514 zy7_devcfg_sysctl_pl_done(SYSCTL_HANDLER_ARGS)
516 struct zy7_devcfg_softc *sc = zy7_devcfg_softc_p;
522 /* PCFG_DONE bit is sticky. Clear it before checking it. */
523 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_PCFG_DONE);
524 pl_done = ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
525 ZY7_DEVCFG_INT_PCFG_DONE) != 0);
527 DEVCFG_SC_UNLOCK(sc);
529 return (sysctl_handle_int(oidp, &pl_done, 0, req));
533 zy7_devcfg_probe(device_t dev)
536 if (!ofw_bus_status_okay(dev))
539 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_devcfg"))
542 device_set_desc(dev, "Zynq devcfg block");
546 static int zy7_devcfg_detach(device_t dev);
549 zy7_devcfg_attach(device_t dev)
551 struct zy7_devcfg_softc *sc = device_get_softc(dev);
554 /* Allow only one attach. */
555 if (zy7_devcfg_softc_p != NULL)
560 DEVCFG_SC_LOCK_INIT(sc);
562 /* Get memory resource. */
564 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
566 if (sc->mem_res == NULL) {
567 device_printf(dev, "could not allocate memory resources.\n");
568 zy7_devcfg_detach(dev);
574 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
576 if (sc->irq_res == NULL) {
577 device_printf(dev, "cannot allocate IRQ\n");
578 zy7_devcfg_detach(dev);
582 /* Activate the interrupt. */
583 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
584 NULL, zy7_devcfg_intr, sc, &sc->intrhandle);
586 device_printf(dev, "cannot setup IRQ\n");
587 zy7_devcfg_detach(dev);
591 /* Create /dev/devcfg */
592 sc->sc_ctl_dev = make_dev(&zy7_devcfg_cdevsw, 0,
593 UID_ROOT, GID_WHEEL, 0600, "devcfg");
594 if (sc->sc_ctl_dev == NULL) {
595 device_printf(dev, "failed to create /dev/devcfg");
596 zy7_devcfg_detach(dev);
599 sc->sc_ctl_dev->si_drv1 = sc;
601 zy7_devcfg_softc_p = sc;
603 /* Unlock devcfg registers. */
604 WR4(sc, ZY7_DEVCFG_UNLOCK, ZY7_DEVCFG_UNLOCK_MAGIC);
606 /* Make sure interrupts are completely disabled. */
607 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
608 WR4(sc, ZY7_DEVCFG_INT_MASK, 0xffffffff);
610 /* Get PS_VERS for SYSCTL. */
611 zy7_ps_vers = (RD4(sc, ZY7_DEVCFG_MCTRL) &
612 ZY7_DEVCFG_MCTRL_PS_VERS_MASK) >>
613 ZY7_DEVCFG_MCTRL_PS_VERS_SHIFT;
619 zy7_devcfg_detach(device_t dev)
621 struct zy7_devcfg_softc *sc = device_get_softc(dev);
623 if (device_is_attached(dev))
624 bus_generic_detach(dev);
626 /* Get rid of /dev/devcfg0. */
627 if (sc->sc_ctl_dev != NULL)
628 destroy_dev(sc->sc_ctl_dev);
630 /* Teardown and release interrupt. */
631 if (sc->irq_res != NULL) {
633 bus_teardown_intr(dev, sc->irq_res, sc->intrhandle);
634 bus_release_resource(dev, SYS_RES_IRQ,
635 rman_get_rid(sc->irq_res), sc->irq_res);
638 /* Release memory resource. */
639 if (sc->mem_res != NULL)
640 bus_release_resource(dev, SYS_RES_MEMORY,
641 rman_get_rid(sc->mem_res), sc->mem_res);
643 zy7_devcfg_softc_p = NULL;
645 DEVCFG_SC_LOCK_DESTROY(sc);
650 static device_method_t zy7_devcfg_methods[] = {
652 DEVMETHOD(device_probe, zy7_devcfg_probe),
653 DEVMETHOD(device_attach, zy7_devcfg_attach),
654 DEVMETHOD(device_detach, zy7_devcfg_detach),
659 static driver_t zy7_devcfg_driver = {
662 sizeof(struct zy7_devcfg_softc),
664 static devclass_t zy7_devcfg_devclass;
666 DRIVER_MODULE(zy7_devcfg, simplebus, zy7_devcfg_driver, zy7_devcfg_devclass, \
668 MODULE_DEPEND(zy7_devcfg, zy7_slcr, 1, 1, 1);