1 /* $NetBSD: i80321_timer.c,v 1.7 2003/07/27 04:52:28 thorpej Exp $ */
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Timer/clock support for the Intel i80321 I/O processor.
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
51 #include <sys/resource.h>
53 #include <sys/timetc.h>
55 #include <machine/bus.h>
56 #include <machine/cpu.h>
57 #include <machine/cpufunc.h>
58 #include <machine/frame.h>
59 #include <machine/resource.h>
60 #include <machine/intr.h>
61 #include <arm/xscale/i80321/i80321reg.h>
62 #include <arm/xscale/i80321/i80321var.h>
64 #ifdef CPU_XSCALE_81342
65 #define ICU_INT_TIMER0 (8) /* XXX: Can't include i81342reg.h because
66 definitions overrides the ones from i80321reg.h
69 #include <arm/xscale/xscalevar.h>
71 #include "opt_timer.h"
73 void (*i80321_hardclock_hook)(void) = NULL;
74 struct i80321_timer_softc {
79 static unsigned i80321_timer_get_timecount(struct timecounter *tc);
82 static uint32_t counts_per_hz;
84 #if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342)
85 static uint32_t offset;
86 static uint32_t last = -1;
89 static int ticked = 0;
91 #ifndef COUNTS_PER_SEC
92 #define COUNTS_PER_SEC 200000000 /* 200MHz */
95 #define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000)
97 static struct timecounter i80321_timer_timecounter = {
98 i80321_timer_get_timecount, /* get_timecount */
99 NULL, /* no poll_pps */
100 ~0u, /* counter_mask */
101 #if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342)
104 COUNTS_PER_SEC * 3, /* frequency */
106 "i80321 timer", /* name */
111 i80321_timer_probe(device_t dev)
114 device_set_desc(dev, "i80321 timer");
119 i80321_timer_attach(device_t dev)
121 timer_softc.dev = dev;
126 static device_method_t i80321_timer_methods[] = {
127 DEVMETHOD(device_probe, i80321_timer_probe),
128 DEVMETHOD(device_attach, i80321_timer_attach),
132 static driver_t i80321_timer_driver = {
134 i80321_timer_methods,
135 sizeof(struct i80321_timer_softc),
137 static devclass_t i80321_timer_devclass;
139 DRIVER_MODULE(itimer, iq, i80321_timer_driver, i80321_timer_devclass, 0, 0);
141 int clockhandler(void *);
144 static __inline uint32_t
149 #ifdef CPU_XSCALE_81342
150 __asm __volatile("mrc p6, 0, %0, c1, c9, 0"
152 __asm __volatile("mrc p6, 0, %0, c1, c1, 0"
159 tmr1_write(uint32_t val)
163 #ifdef CPU_XSCALE_81342
164 __asm __volatile("mcr p6, 0, %0, c1, c9, 0"
166 __asm __volatile("mcr p6, 0, %0, c1, c1, 0"
172 static __inline uint32_t
177 #ifdef CPU_XSCALE_81342
178 __asm __volatile("mrc p6, 0, %0, c3, c9, 0"
180 __asm __volatile("mrc p6, 0, %0, c3, c1, 0"
186 tcr1_write(uint32_t val)
189 #ifdef CPU_XSCALE_81342
190 __asm __volatile("mcr p6, 0, %0, c3, c9, 0"
192 __asm __volatile("mcr p6, 0, %0, c3, c1, 0"
199 trr1_write(uint32_t val)
202 #ifdef CPU_XSCALE_81342
203 __asm __volatile("mcr p6, 0, %0, c5, c9, 0"
205 __asm __volatile("mcr p6, 0, %0, c5, c1, 0"
211 static __inline uint32_t
216 #ifdef CPU_XSCALE_81342
217 __asm __volatile("mrc p6, 0, %0, c0, c9, 0"
219 __asm __volatile("mrc p6, 0, %0, c0, c1, 0"
226 tmr0_write(uint32_t val)
229 #ifdef CPU_XSCALE_81342
230 __asm __volatile("mcr p6, 0, %0, c0, c9, 0"
232 __asm __volatile("mcr p6, 0, %0, c0, c1, 0"
238 static __inline uint32_t
243 #ifdef CPU_XSCALE_81342
244 __asm __volatile("mrc p6, 0, %0, c2, c9, 0"
246 __asm __volatile("mrc p6, 0, %0, c2, c1, 0"
252 tcr0_write(uint32_t val)
255 #ifdef CPU_XSCALE_81342
256 __asm __volatile("mcr p6, 0, %0, c2, c9, 0"
258 __asm __volatile("mcr p6, 0, %0, c2, c1, 0"
265 trr0_write(uint32_t val)
268 #ifdef CPU_XSCALE_81342
269 __asm __volatile("mcr p6, 0, %0, c4, c9, 0"
271 __asm __volatile("mcr p6, 0, %0, c4, c1, 0"
278 tisr_write(uint32_t val)
281 #ifdef CPU_XSCALE_81342
282 __asm __volatile("mcr p6, 0, %0, c6, c9, 0"
284 __asm __volatile("mcr p6, 0, %0, c6, c1, 0"
290 static __inline uint32_t
295 #ifdef CPU_XSCALE_81342
296 __asm __volatile("mrc p6, 0, %0, c6, c9, 0" : "=r" (ret));
298 __asm __volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (ret));
304 i80321_timer_get_timecount(struct timecounter *tc)
306 #if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342)
307 uint32_t cur = tcr0_read();
309 if (cur > last && last != -1) {
310 offset += counts_per_hz;
315 offset += ticked * counts_per_hz;
318 return (counts_per_hz - cur + offset);
322 __asm __volatile("mrc p14, 0, %0, c1, c0, 0\n"
329 * i80321_calibrate_delay:
331 * Calibrate the delay loop.
334 i80321_calibrate_delay(void)
338 * Just use hz=100 for now -- we'll adjust it, if necessary,
339 * in cpu_initclocks().
341 counts_per_hz = COUNTS_PER_SEC / 100;
343 tmr0_write(0); /* stop timer */
344 tisr_write(TISR_TMR0); /* clear interrupt */
345 trr0_write(counts_per_hz); /* reload value */
346 tcr0_write(counts_per_hz); /* current value */
348 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
354 * Initialize the clock and get them going.
360 struct resource *irq;
363 device_t dev = timer_softc.dev;
365 if (hz < 50 || COUNTS_PER_SEC % hz) {
366 printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
369 tick = 1000000 / hz; /* number of microseconds between interrupts */
372 * We only have one timer available; stathz and profhz are
373 * always left as 0 (the upper-layer clock code deals with
377 printf("Cannot get %d Hz statclock\n", stathz);
381 printf("Cannot get %d Hz profclock\n", profhz);
384 /* Report the clock frequency. */
386 oldirqstate = disable_interrupts(I32_bit);
388 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
389 #ifdef CPU_XSCALE_81342
390 ICU_INT_TIMER0, ICU_INT_TIMER0,
392 ICU_INT_TMR0, ICU_INT_TMR0,
396 panic("Unable to setup the clock irq handler.\n");
398 bus_setup_intr(dev, irq, INTR_TYPE_CLK, clockhandler, NULL,
400 tmr0_write(0); /* stop timer */
401 tisr_write(TISR_TMR0); /* clear interrupt */
403 counts_per_hz = COUNTS_PER_SEC / hz;
405 trr0_write(counts_per_hz); /* reload value */
406 tcr0_write(counts_per_hz); /* current value */
407 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
409 tc_init(&i80321_timer_timecounter);
410 restore_interrupts(oldirqstate);
412 #if !defined(XSCALE_DISABLE_CCNT) && !defined(CPU_XSCALE_81342)
413 /* Enable the clock count register. */
414 __asm __volatile("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (rid));
417 __asm __volatile("mcr p14, 0, %0, c0, c0, 0\n"
426 * Delay for at least N microseconds.
431 uint32_t cur, last, delta, usecs;
434 * This works by polling the timer and counting the
435 * number of microseconds that go by.
443 /* Check to see if the timer has wrapped around. */
445 delta += (last + (counts_per_hz - cur));
447 delta += (last - cur);
451 if (delta >= COUNTS_PER_USEC) {
452 usecs += delta / COUNTS_PER_USEC;
453 delta %= COUNTS_PER_USEC;
461 * Handle the hardclock interrupt.
464 clockhandler(void *arg)
466 struct trapframe *frame = arg;
469 tisr_write(TISR_TMR0);
470 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
472 if (i80321_hardclock_hook != NULL)
473 (*i80321_hardclock_hook)();
474 return (FILTER_HANDLED);
478 cpu_startprofclock(void)
483 cpu_stopprofclock(void)