2 * Copyright (c) 2010, Andrew Thompson <thompsa@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * GPIO driver for Gateworks Cambria
32 * The Cambria PLD does not set the i2c ack bit after each write, if we used the
33 * regular iicbus interface it would abort the xfer after the address byte
34 * times out and not write our latch. To get around this we grab the iicbus and
35 * then do our own bit banging. This is a comprimise to changing all the iicbb
36 * device methods to allow a flag to be passed down and is similir to how Linux
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/param.h>
45 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
52 #include <sys/mutex.h>
55 #include <arm/xscale/ixp425/ixp425reg.h>
56 #include <arm/xscale/ixp425/ixp425var.h>
57 #include <arm/xscale/ixp425/ixdp425reg.h>
59 #include <dev/iicbus/iiconf.h>
60 #include <dev/iicbus/iicbus.h>
65 #define IIC_M_WR 0 /* write operation */
66 #define PLD_ADDR 0xac /* slave address */
70 #define GPIO_CONF_CLR(sc, reg, mask) \
71 GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) &~ (mask))
72 #define GPIO_CONF_SET(sc, reg, mask) \
73 GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) | (mask))
75 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
76 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
77 #define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
80 struct cambria_gpio_softc {
82 bus_space_tag_t sc_iot;
83 bus_space_handle_t sc_gpio_ioh;
85 struct gpio_pin sc_pins[GPIO_PINS];
90 struct cambria_gpio_pin {
96 extern struct ixp425_softc *ixp425_softc;
98 static struct cambria_gpio_pin cambria_gpio_pins[GPIO_PINS] = {
99 { "GPIO0", 0, GPIO_PIN_OUTPUT },
100 { "GPIO1", 1, GPIO_PIN_OUTPUT },
101 { "GPIO2", 2, GPIO_PIN_OUTPUT },
102 { "GPIO3", 3, GPIO_PIN_OUTPUT },
103 { "GPIO4", 4, GPIO_PIN_OUTPUT },
109 static int cambria_gpio_read(struct cambria_gpio_softc *, uint32_t, unsigned int *);
110 static int cambria_gpio_write(struct cambria_gpio_softc *);
115 static int cambria_gpio_probe(device_t dev);
116 static int cambria_gpio_attach(device_t dev);
117 static int cambria_gpio_detach(device_t dev);
122 static int cambria_gpio_pin_max(device_t dev, int *maxpin);
123 static int cambria_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
124 static int cambria_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
126 static int cambria_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
127 static int cambria_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
128 static int cambria_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
129 static int cambria_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
130 static int cambria_gpio_pin_toggle(device_t dev, uint32_t pin);
133 i2c_getsda(struct cambria_gpio_softc *sc)
138 GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
140 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR);
141 IXP4XX_GPIO_UNLOCK();
142 return (reg & GPIO_I2C_SDA_BIT);
146 i2c_setsda(struct cambria_gpio_softc *sc, int val)
150 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SDA_BIT);
152 GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
154 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
155 IXP4XX_GPIO_UNLOCK();
160 i2c_setscl(struct cambria_gpio_softc *sc, int val)
164 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SCL_BIT);
166 GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
168 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
169 IXP4XX_GPIO_UNLOCK();
174 i2c_sendstart(struct cambria_gpio_softc *sc)
183 i2c_sendstop(struct cambria_gpio_softc *sc)
192 i2c_sendbyte(struct cambria_gpio_softc *sc, u_char data)
196 for (i=7; i>=0; i--) {
197 i2c_setsda(sc, data & (1<<i));
207 i2c_readbyte(struct cambria_gpio_softc *sc)
210 unsigned char data=0;
223 cambria_gpio_read(struct cambria_gpio_softc *sc, uint32_t pin, unsigned int *val)
225 device_t dev = sc->sc_dev;
228 error = iicbus_request_bus(device_get_parent(dev), dev,
234 i2c_sendbyte(sc, PLD_ADDR | LSB);
235 *val = (i2c_readbyte(sc) & (1 << pin)) != 0;
238 iicbus_release_bus(device_get_parent(dev), dev);
244 cambria_gpio_write(struct cambria_gpio_softc *sc)
246 device_t dev = sc->sc_dev;
249 error = iicbus_request_bus(device_get_parent(dev), dev,
255 i2c_sendbyte(sc, PLD_ADDR & ~LSB);
256 i2c_sendbyte(sc, sc->sc_latch);
259 iicbus_release_bus(device_get_parent(dev), dev);
265 cambria_gpio_pin_max(device_t dev, int *maxpin)
268 *maxpin = GPIO_PINS - 1;
273 cambria_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
275 struct cambria_gpio_softc *sc = device_get_softc(dev);
277 if (pin >= GPIO_PINS)
280 *caps = sc->sc_pins[pin].gp_caps;
285 cambria_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
287 struct cambria_gpio_softc *sc = device_get_softc(dev);
289 if (pin >= GPIO_PINS)
292 *flags = sc->sc_pins[pin].gp_flags;
297 cambria_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
299 struct cambria_gpio_softc *sc = device_get_softc(dev);
301 if (pin >= GPIO_PINS)
304 memcpy(name, sc->sc_pins[pin].gp_name, GPIOMAXNAME);
309 cambria_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
311 struct cambria_gpio_softc *sc = device_get_softc(dev);
317 if (pin >= GPIO_PINS)
320 /* Check for unwanted flags. */
321 if ((flags & sc->sc_pins[pin].gp_caps) != flags)
324 /* Can't mix input/output together */
325 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) ==
326 (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT))
330 sc->sc_pins[pin].gp_flags = flags;
333 * Writing a logical one sets the signal high and writing a logical
334 * zero sets the signal low. To configure a digital I/O signal as an
335 * input, a logical one must first be written to the data bit to
336 * three-state the associated output.
338 if (flags & GPIO_PIN_INPUT || sc->sc_val & mask)
339 sc->sc_latch |= mask; /* input or output & high */
341 sc->sc_latch &= ~mask;
342 error = cambria_gpio_write(sc);
349 cambria_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
351 struct cambria_gpio_softc *sc = device_get_softc(dev);
357 if (pin >= GPIO_PINS)
365 if (sc->sc_pins[pin].gp_flags != GPIO_PIN_OUTPUT) {
366 /* just save, altering the latch will disable input */
372 sc->sc_latch |= mask;
374 sc->sc_latch &= ~mask;
375 error = cambria_gpio_write(sc);
382 cambria_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
384 struct cambria_gpio_softc *sc = device_get_softc(dev);
387 if (pin >= GPIO_PINS)
391 if (sc->sc_pins[pin].gp_flags == GPIO_PIN_OUTPUT)
392 *val = (sc->sc_latch & (1 << pin)) ? 1 : 0;
394 error = cambria_gpio_read(sc, pin, val);
401 cambria_gpio_pin_toggle(device_t dev, uint32_t pin)
403 struct cambria_gpio_softc *sc = device_get_softc(dev);
406 if (pin >= GPIO_PINS)
410 sc->sc_val ^= (1 << pin);
411 if (sc->sc_pins[pin].gp_flags == GPIO_PIN_OUTPUT) {
412 sc->sc_latch ^= (1 << pin);
413 error = cambria_gpio_write(sc);
421 cambria_gpio_probe(device_t dev)
424 device_set_desc(dev, "Gateworks Cambria GPIO driver");
429 cambria_gpio_attach(device_t dev)
431 struct cambria_gpio_softc *sc = device_get_softc(dev);
435 sc->sc_iot = ixp425_softc->sc_iot;
436 sc->sc_gpio_ioh = ixp425_softc->sc_gpio_ioh;
438 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
441 for (pin = 0; pin < GPIO_PINS; pin++) {
442 struct cambria_gpio_pin *p = &cambria_gpio_pins[pin];
444 strncpy(sc->sc_pins[pin].gp_name, p->name, GPIOMAXNAME);
445 sc->sc_pins[pin].gp_pin = pin;
446 sc->sc_pins[pin].gp_caps = GPIO_PIN_INPUT|GPIO_PIN_OUTPUT;
447 sc->sc_pins[pin].gp_flags = 0;
448 cambria_gpio_pin_setflags(dev, pin, p->flags);
451 device_add_child(dev, "gpioc", device_get_unit(dev));
452 device_add_child(dev, "gpiobus", device_get_unit(dev));
453 return (bus_generic_attach(dev));
457 cambria_gpio_detach(device_t dev)
459 struct cambria_gpio_softc *sc = device_get_softc(dev);
461 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
463 bus_generic_detach(dev);
465 mtx_destroy(&sc->sc_mtx);
470 static device_method_t cambria_gpio_methods[] = {
471 DEVMETHOD(device_probe, cambria_gpio_probe),
472 DEVMETHOD(device_attach, cambria_gpio_attach),
473 DEVMETHOD(device_detach, cambria_gpio_detach),
476 DEVMETHOD(gpio_pin_max, cambria_gpio_pin_max),
477 DEVMETHOD(gpio_pin_getname, cambria_gpio_pin_getname),
478 DEVMETHOD(gpio_pin_getflags, cambria_gpio_pin_getflags),
479 DEVMETHOD(gpio_pin_getcaps, cambria_gpio_pin_getcaps),
480 DEVMETHOD(gpio_pin_setflags, cambria_gpio_pin_setflags),
481 DEVMETHOD(gpio_pin_get, cambria_gpio_pin_get),
482 DEVMETHOD(gpio_pin_set, cambria_gpio_pin_set),
483 DEVMETHOD(gpio_pin_toggle, cambria_gpio_pin_toggle),
487 static driver_t cambria_gpio_driver = {
489 cambria_gpio_methods,
490 sizeof(struct cambria_gpio_softc),
492 static devclass_t cambria_gpio_devclass;
493 extern devclass_t gpiobus_devclass, gpioc_devclass;
494 extern driver_t gpiobus_driver, gpioc_driver;
496 DRIVER_MODULE(gpio_cambria, iicbus, cambria_gpio_driver, cambria_gpio_devclass, 0, 0);
497 DRIVER_MODULE(gpiobus, gpio_cambria, gpiobus_driver, gpiobus_devclass, 0, 0);
498 DRIVER_MODULE(gpioc, gpio_cambria, gpioc_driver, gpioc_devclass, 0, 0);
499 MODULE_VERSION(gpio_cambria, 1);
500 MODULE_DEPEND(gpio_cambria, iicbus, 1, 1, 1);