2 * Copyright (c) 2006 Benno Rice. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
28 #include <sys/param.h>
29 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
33 #include <sys/malloc.h>
35 #include <sys/timetc.h>
36 #include <machine/bus.h>
37 #include <machine/intr.h>
39 #include <arm/xscale/pxa/pxavar.h>
40 #include <arm/xscale/pxa/pxareg.h>
42 struct pxa_icu_softc {
43 struct resource * pi_res[1];
44 bus_space_tag_t pi_bst;
45 bus_space_handle_t pi_bsh;
48 static struct resource_spec pxa_icu_spec[] = {
49 { SYS_RES_MEMORY, 0, RF_ACTIVE },
53 static struct pxa_icu_softc *pxa_icu_softc = NULL;
55 static int pxa_icu_probe(device_t);
56 static int pxa_icu_attach(device_t);
58 uint32_t pxa_icu_get_icip(void);
59 void pxa_icu_clear_icip(int);
60 uint32_t pxa_icu_get_icfp(void);
61 void pxa_icu_clear_icfp(int);
62 uint32_t pxa_icu_get_icmr(void);
63 void pxa_icu_set_icmr(uint32_t);
64 uint32_t pxa_icu_get_iclr(void);
65 void pxa_icu_set_iclr(uint32_t);
66 uint32_t pxa_icu_get_icpr(void);
67 void pxa_icu_idle_enable(void);
68 void pxa_icu_idle_disable(void);
70 extern uint32_t pxa_gpio_intr_flags[];
73 pxa_icu_probe(device_t dev)
76 device_set_desc(dev, "Interrupt Controller");
81 pxa_icu_attach(device_t dev)
84 struct pxa_icu_softc *sc;
86 sc = (struct pxa_icu_softc *)device_get_softc(dev);
88 if (pxa_icu_softc != NULL)
92 error = bus_alloc_resources(dev, pxa_icu_spec, sc->pi_res);
94 device_printf(dev, "could not allocate resources\n");
98 sc->pi_bst = rman_get_bustag(sc->pi_res[0]);
99 sc->pi_bsh = rman_get_bushandle(sc->pi_res[0]);
101 /* Disable all interrupts. */
104 /* Route all interrupts to IRQ rather than FIQ. */
107 /* XXX: This should move to configure_final or something. */
108 enable_interrupts(I32_bit|F32_bit);
113 static device_method_t pxa_icu_methods[] = {
114 DEVMETHOD(device_probe, pxa_icu_probe),
115 DEVMETHOD(device_attach, pxa_icu_attach),
120 static driver_t pxa_icu_driver = {
123 sizeof(struct pxa_icu_softc),
126 static devclass_t pxa_icu_devclass;
128 DRIVER_MODULE(pxaicu, pxa, pxa_icu_driver, pxa_icu_devclass, 0, 0);
131 arm_get_next_irq(int last __unused)
135 if ((irq = pxa_icu_get_icip()) != 0) {
136 return (ffs(irq) - 1);
139 return (pxa_gpio_get_next_irq());
143 arm_mask_irq(uintptr_t nb)
147 if (nb >= IRQ_GPIO0) {
148 pxa_gpio_mask_irq(nb);
152 mr = pxa_icu_get_icmr();
154 pxa_icu_set_icmr(mr);
158 arm_unmask_irq(uintptr_t nb)
162 if (nb >= IRQ_GPIO0) {
163 pxa_gpio_unmask_irq(nb);
167 mr = pxa_icu_get_icmr();
169 pxa_icu_set_icmr(mr);
176 return (bus_space_read_4(pxa_icu_softc->pi_bst,
177 pxa_icu_softc->pi_bsh, ICU_IP));
181 pxa_icu_clear_icip(int irq)
184 bus_space_write_4(pxa_icu_softc->pi_bst,
185 pxa_icu_softc->pi_bsh, ICU_IP, (1 << irq));
192 return (bus_space_read_4(pxa_icu_softc->pi_bst,
193 pxa_icu_softc->pi_bsh, ICU_FP));
197 pxa_icu_clear_icfp(int irq)
200 bus_space_write_4(pxa_icu_softc->pi_bst,
201 pxa_icu_softc->pi_bsh, ICU_FP, (1 << irq));
208 return (bus_space_read_4(pxa_icu_softc->pi_bst,
209 pxa_icu_softc->pi_bsh, ICU_MR));
213 pxa_icu_set_icmr(uint32_t val)
216 bus_space_write_4(pxa_icu_softc->pi_bst,
217 pxa_icu_softc->pi_bsh, ICU_MR, val);
224 return (bus_space_read_4(pxa_icu_softc->pi_bst,
225 pxa_icu_softc->pi_bsh, ICU_LR));
229 pxa_icu_set_iclr(uint32_t val)
232 bus_space_write_4(pxa_icu_softc->pi_bst,
233 pxa_icu_softc->pi_bsh, ICU_LR, val);
240 return (bus_space_read_4(pxa_icu_softc->pi_bst,
241 pxa_icu_softc->pi_bsh, ICU_PR));
245 pxa_icu_idle_enable()
248 bus_space_write_4(pxa_icu_softc->pi_bst,
249 pxa_icu_softc->pi_bsh, ICU_CR, 0x0);
253 pxa_icu_idle_disable()
256 bus_space_write_4(pxa_icu_softc->pi_bst,
257 pxa_icu_softc->pi_bsh, ICU_CR, 0x1);