2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 compatible = "rockchip,rk3188";
41 compatible = "simple-bus";
45 GIC: interrupt-controller@1013d000 {
46 compatible = "arm,gic";
47 reg = <0x1013d000 0x1000>, /* Distributor Registers */
48 <0x1013c100 0x0100>; /* CPU Interface Registers */
50 #interrupt-cells = <1>;
54 compatible = "rockchip,rk30xx-pmu";
57 reg = <0x20004000 0x100>;
61 compatible = "rockchip,rk30xx-grf";
64 reg = < 0x20008000 0x2000 >;
68 compatible = "arm,mpcore-timers";
71 clock-frequency = < 148500000 >;
72 reg = <0x1013c200 0x100>, /* Global Timer Regs */
73 <0x1013c600 0x20>; /* Private Timer Regs */
74 interrupts = < 27 29 >;
75 interrupt-parent = <&GIC>;
79 compatible = "rockchip,rk30xx-timer";
80 reg = <0x20038000 0x20>;
82 clock-frequency = <24000000>;
87 compatible = "rockchip,rk30xx-timer";
88 reg = <0x20038020 0x20>;
90 clock-frequency = <24000000>;
95 compatible = "rockchip,rk30xx-timer";
96 reg = <0x20038060 0x20>;
98 clock-frequency = <24000000>;
103 compatible = "rockchip,rk30xx-timer";
104 reg = <0x20038080 0x20>;
106 clock-frequency = <24000000>;
111 compatible = "rockchip,rk30xx-timer";
112 reg = <0x200380a0 0x20>;
114 clock-frequency = <24000000>;
119 compatible = "rockchip,rk30xx-wdt";
120 reg = <0x2004c000 0x100>;
121 clock-frequency = < 66000000 >;
124 gpio0: gpio@2000a000 {
125 compatible = "rockchip,rk30xx-gpio";
128 reg = <0x2000a000 0x100>;
130 interrupt-parent = <&GIC>;
133 gpio1: gpio@2003c000 {
134 compatible = "rockchip,rk30xx-gpio";
137 reg = <0x2003c000 0x100>;
139 interrupt-parent = <&GIC>;
142 gpio2: gpio@2003e000 {
143 compatible = "rockchip,rk30xx-gpio";
146 reg = <0x2003e000 0x100>;
148 interrupt-parent = <&GIC>;
151 gpio3: gpio@20080000 {
152 compatible = "rockchip,rk30xx-gpio";
155 reg = <0x20080000 0x100>;
157 interrupt-parent = <&GIC>;
161 compatible = "synopsys,designware-hs-otg2";
162 reg = <0x10180000 0x40000>;
164 interrupt-parent = <&GIC>;
165 #address-cells = <1>;
170 compatible = "synopsys,designware-hs-otg2";
171 reg = <0x101c0000 0x40000>;
173 interrupt-parent = <&GIC>;
174 #address-cells = <1>;
176 gpios = <&gpio0 3 2 2>;
179 uart0: serial@10124000 {
180 compatible = "ns16550";
181 reg = <0x10124000 0x400>;
184 interrupt-parent = <&GIC>;
185 current-speed = <115200>;
186 clock-frequency = < 24000000 >;
192 uart1: serial@10126000 {
193 compatible = "ns16550";
194 reg = <0x10126000 0x400>;
197 interrupt-parent = <&GIC>;
198 current-speed = <115200>;
199 clock-frequency = < 24000000 >;
205 uart2: serial@20064000 {
206 compatible = "ns16550";
207 reg = <0x20064000 0x400>;
210 interrupt-parent = <&GIC>;
211 current-speed = <115200>;
212 clock-frequency = < 24000000 >;
218 uart3: serial@20068000 {
219 compatible = "ns16550";
220 reg = <0x20068000 0x400>;
223 interrupt-parent = <&GIC>;
224 current-speed = <115200>;
225 clock-frequency = < 24000000 >;
232 compatible = "rockchip,rk30xx-mmc";
233 reg = <0x10214000 0x1000>;
235 #address-cells = <1>;
237 clock-frequency = <24000000>; /* TODO: verify freq */
242 compatible = "rockchip,rk30xx-mmc";
243 reg = <0x10218000 0x1000>;
245 #address-cells = <1>;
247 clock-frequency = <24000000>; /* TODO: verify freq */