2 * Copyright (c) 2012 The FreeBSD Foundation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
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14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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33 compatible = "digilent,zedboard";
36 interrupt-parent = <&GIC>;
39 // #address-cells = <1>;
42 // device-type = "cpu";
43 // model = "ARM Cortex-A9";
48 // First megabyte isn't accessible by all interconnect masters.
49 device_type = "memory";
50 reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */
53 // Zynq PS System registers.
57 compatible = "simple-bus";
60 ranges = <0x0 0xf8000000 0xf10000>;
64 compatible = "xlnx,zy7_slcr";
66 clock-frequency = <33333333>; // 33Mhz PS_CLK
69 // Interrupt controller
71 compatible = "arm,gic";
74 #interrupt-cells = <1>;
75 reg = <0xf01000 0x1000>, // distributer registers
76 <0xf00100 0x0100>; // CPU if registers
79 // L2 cache controller
81 compatible = "arm,pl310";
82 reg = <0xf02000 0x1000>;
84 interrupt-parent = <&GIC>;
89 compatible = "xlnx,zy7_devcfg";
90 reg = <0x7000 0x1000>;
92 interrupt-parent = <&GIC>;
95 // triple timer counters0,1
97 compatible = "xlnx,ttc";
98 reg = <0x1000 0x1000>;
101 compatible = "xlnx,ttc";
102 reg = <0x2000 0x1000>;
105 // ARM Cortex A9 TWD Timer
107 compatible = "arm,mpcore-timers";
108 clock-frequency = <333333333>; // 333Mhz
109 #address-cells = <1>;
111 reg = <0xf00200 0x100>, // Global Timer Regs
112 <0xf00600 0x20>; // Private Timer Regs
113 interrupts = < 27 29 >;
114 interrupt-parent = <&GIC>;
117 // system watch-dog timer
119 device_type = "watchdog";
120 compatible = "xlnx,zy7_wdt";
121 reg = <0x5000 0x1000>;
123 interrupt-parent = <&GIC>;
127 device_type = "watchdog";
128 compatible = "arm,mpcore_wdt";
129 reg = <0xf00620 0x20>;
131 interrupt-parent = <&GIC>;
136 // Zynq PS I/O Peripheral registers.
140 compatible = "simple-bus";
141 #address-cells = <1>;
143 ranges = <0x0 0xe0000000 0x300000>;
145 // uart0: uart@0000 {
146 // device_type = "serial";
147 // compatible = "cadence,uart";
148 // reg = <0x0000 0x1000>;
149 // interrupts = <59>;
150 // interrupt-parent = <&GIC>;
151 // clock-frequency = <50000000>;
155 device_type = "serial";
156 compatible = "cadence,uart";
157 reg = <0x1000 0x1000>;
159 interrupt-parent = <&GIC>;
160 clock-frequency = <50000000>;
161 current-speed = <115200>;
165 compatible = "xlnx,zy7_gpio";
166 reg = <0xa000 0x1000>;
168 interrupt-parent = <&GIC>;
173 // device_type = "network";
175 compatible = "cadence,gem";
176 reg = <0xb000 0x1000>;
177 interrupts = <54 55>;
178 interrupt-parent = <&GIC>;
183 sdhci0: sdhci@100000 {
184 compatible = "xlnx,zy7_sdhci";
185 reg = <0x100000 0x1000>;
187 interrupt-parent = <&GIC>;
188 max-frequency = <50000000>;
193 compatible = "xlnx,zy7_qspi";
194 reg = <0xd000 0x1000>;
196 interrupt-parent = <&GIC>;
197 spi-clock = <50000000>;
198 ref-clock = <190476000>;
203 compatible = "xlnx,zy7_ehci";
204 reg = <0x2000 0x1000>;
206 interrupt-parent = <&GIC>;