2 * Copyright (c) 2010 The FreeBSD Foundation
5 * This software was developed by Semihalf under sponsorship from
6 * the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Marvell DB-78100 Device Tree Source.
37 model = "mrvl,DB-78100";
38 compatible = "DB-78100-BP", "DB-78100-BP-A";
55 compatible = "ARM,88FR571";
57 d-cache-line-size = <32>; // 32 bytes
58 i-cache-line-size = <32>; // 32 bytes
59 d-cache-size = <0x4000>; // L1, 16K
60 i-cache-size = <0x4000>; // L1, 16K
61 timebase-frequency = <0>;
63 clock-frequency = <0>;
68 device_type = "memory";
69 reg = <0x0 0x20000000>; // 512M at 0x0
75 compatible = "mrvl,lbc";
78 /* This reflects CPU decode windows setup. */
79 ranges = <0x0 0x0f 0xf9300000 0x00100000
80 0x1 0x1e 0xfa000000 0x00100000
81 0x2 0x1d 0xfa100000 0x02000000
82 0x3 0x1b 0xfc100000 0x00000400>;
87 compatible = "cfi-flash";
88 reg = <0x0 0x0 0x00100000>;
97 reg = <0x1 0x0 0x00100000>;
101 #address-cells = <1>;
103 compatible = "cfi-flash";
104 reg = <0x2 0x0 0x02000000>;
110 #address-cells = <1>;
112 reg = <0x3 0x0 0x00100000>;
119 #address-cells = <1>;
121 compatible = "simple-bus";
122 ranges = <0x0 0xf1000000 0x00100000>;
126 interrupt-controller;
127 #address-cells = <0>;
128 #interrupt-cells = <1>;
129 reg = <0x20200 0x3c>;
130 compatible = "mrvl,pic";
134 compatible = "mrvl,timer";
135 reg = <0x20300 0x30>;
137 interrupt-parent = <&PIC>;
143 compatible = "mrvl,mpp";
144 reg = <0x10000 0x34>;
147 0 2 /* MPP[0]: GE1_TXCLK */
148 1 2 /* MPP[1]: GE1_TXCTL */
149 2 2 /* MPP[2]: GE1_RXCTL */
150 3 2 /* MPP[3]: GE1_RXCLK */
151 4 2 /* MPP[4]: GE1_TXD[0] */
152 5 2 /* MPP[5]: GE1_TXD[1] */
153 6 2 /* MPP[6]: GE1_TXD[2] */
154 7 2 /* MPP[7]: GE1_TXD[3] */
155 8 2 /* MPP[8]: GE1_RXD[0] */
156 9 2 /* MPP[9]: GE1_RXD[1] */
157 10 2 /* MPP[10]: GE1_RXD[2] */
158 11 2 /* MPP[11]: GE1_RXD[3] */
159 13 3 /* MPP[13]: SYSRST_OUTn */
160 14 3 /* MPP[14]: SATA1_ACTn */
161 15 3 /* MPP[15]: SATA0_ACTn */
162 16 4 /* MPP[16]: UA2_TXD */
163 17 4 /* MPP[17]: UA2_RXD */
164 18 3 /* MPP[18]: <UNKNOWN> */
165 19 3 /* MPP[19]: <UNKNOWN> */
166 20 3 /* MPP[20]: <UNKNOWN> */
167 21 3 /* MPP[21]: <UNKNOWN> */
168 22 4 /* MPP[22]: UA3_TXD */
169 23 4 >; /* MPP[21]: UA3_RXD */
174 compatible = "mrvl,gpio";
175 reg = <0x10100 0x20>;
177 interrupts = <56 57 58 59>;
178 interrupt-parent = <&PIC>;
182 compatible = "mrvl,rtc";
183 reg = <0x10300 0x08>;
187 #address-cells = <1>;
189 compatible = "mrvl,twsi";
190 reg = <0x11000 0x20>;
192 interrupt-parent = <&PIC>;
196 #address-cells = <1>;
198 compatible = "mrvl,twsi";
199 reg = <0x11100 0x20>;
201 interrupt-parent = <&PIC>;
204 enet0: ethernet@72000 {
205 #address-cells = <1>;
208 compatible = "mrvl,ge";
209 reg = <0x72000 0x2000>;
210 ranges = <0x0 0x72000 0x2000>;
211 local-mac-address = [ 00 00 00 00 00 00 ];
212 interrupts = <41 42 43 40 70>;
213 interrupt-parent = <&PIC>;
214 phy-handle = <&phy0>;
217 #address-cells = <1>;
219 compatible = "mrvl,mdio";
221 phy0: ethernet-phy@0 {
227 enet1: ethernet@76000 {
228 #address-cells = <1>;
231 compatible = "mrvl,ge";
232 reg = <0x76000 0x2000>;
233 ranges = <0x0 0x76000 0x2000>;
234 local-mac-address = [ 00 00 00 00 00 00 ];
235 interrupts = <45 46 47 44 70>;
236 interrupt-parent = <&PIC>;
237 phy-handle = <&phy0>;
240 #address-cells = <1>;
242 compatible = "mrvl,mdio";
244 phy0: ethernet-phy@0 {
250 serial0: serial@12000 {
251 compatible = "ns16550";
252 reg = <0x12000 0x20>;
254 clock-frequency = <0>;
256 interrupt-parent = <&PIC>;
259 serial1: serial@12100 {
260 compatible = "ns16550";
261 reg = <0x12100 0x20>;
263 clock-frequency = <0>;
265 interrupt-parent = <&PIC>;
269 compatible = "mrvl,usb-ehci", "usb-ehci";
270 reg = <0x50000 0x1000>;
271 interrupts = <72 16>;
272 interrupt-parent = <&PIC>;
276 compatible = "mrvl,usb-ehci", "usb-ehci";
277 reg = <0x51000 0x1000>;
278 interrupts = <72 17>;
279 interrupt-parent = <&PIC>;
283 compatible = "mrvl,usb-ehci", "usb-ehci";
284 reg = <0x52000 0x1000>;
285 interrupts = <72 18>;
286 interrupt-parent = <&PIC>;
290 compatible = "mrvl,xor";
291 reg = <0x60000 0x1000>;
292 interrupts = <22 23>;
293 interrupt-parent = <&PIC>;
297 compatible = "mrvl,cesa";
298 reg = <0x90000 0x10000>;
300 interrupt-parent = <&PIC>;
304 compatible = "mrvl,sata";
305 reg = <0xa0000 0x6000>;
307 interrupt-parent = <&PIC>;
311 pci0: pcie@f1040000 {
312 compatible = "mrvl,pcie";
314 #interrupt-cells = <1>;
316 #address-cells = <3>;
317 reg = <0xf1040000 0x2000>;
319 ranges = <0x02000000 0x0 0xf2000000 0xf2000000 0x0 0x04000000
320 0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
321 clock-frequency = <33333333>;
322 interrupt-parent = <&PIC>;
324 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
327 0x0800 0x0 0x0 0x1 &PIC 0x20
328 0x0800 0x0 0x0 0x2 &PIC 0x21
329 0x0800 0x0 0x0 0x3 &PIC 0x22
330 0x0800 0x0 0x0 0x4 &PIC 0x23
335 compatible = "mrvl,cesa-sram";
336 reg = <0xfd000000 0x00100000>;