2 * Copyright (c) 2012-2013 Robert N. M. Watson
3 * Copyright (c) 2013 SRI International
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
8 * ("CTSRD"), as part of the DARPA CRASH research programme.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * Device names here have been largely made up on the spot, especially for the
38 * "compatible" strings, and might want to be revised.
40 * For now, use 32-bit addressing as our Avalon bus is 32-bit. However, in
41 * the future, we should likely change to 64-bit.
45 model = "SRI/Cambridge BERI simulation";
46 compatible = "sri-cambridge,beri-sim";
55 * Secondary CPUs all start disabled and use the
56 * spin-table enable method. cpu-release-addr must be
57 * specified for each cpu other than cpu@0. Values of
58 * cpu-release-addr grow down from 0x100000 (kernel).
61 enable-method = "spin-table";
65 compatible = "sri-cambridge,beri";
74 compatible = "sri-cambridge,beri";
77 // XXX: should we need cached prefix?
78 cpu-release-addr = <0xffffffff 0x800fffe0>;
86 #interrupt-cells = <1>;
89 * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so
90 * we use mips4k coprocessor 0 interrupt management directly.
92 compatible = "simple-bus", "mips,mips4k";
96 device_type = "memory";
97 reg = <0x0 0x4000000>; // 64M at 0x0
100 beripic: beripic@7f804000 {
101 compatible = "sri-cambridge,beri-pic";
102 interrupt-controller;
103 #address-cells = <0>;
104 #interrupt-cells = <1>;
105 reg = <0x7f804000 0x400
109 interrupts = <0 1 2 3 4>;
110 hard-interrupt-sources = <64>;
111 soft-interrupt-sources = <64>;
115 compatible = "altera,jtag_uart-11_0";
116 reg = <0x7f000000 0x40>;
118 interrupt-parent = <&beripic>;
122 compatible = "altera,jtag_uart-11_0";
123 reg = <0x7f001000 0x40>;
127 compatible = "altera,jtag_uart-11_0";
128 reg = <0x7f002000 0x40>;
132 compatible = "altera,sdcard_11_2011";
133 reg = <0x7f008000 0x400>;
137 compatible = "sri-cambridge,avgen";
138 reg = <0x7f00a000 0x14>;
139 sri-cambridge,width = <4>;
140 sri-cambridge,fileio = "rw";
141 sri-cambridge,devname = "berirom";