2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
40 #include <bootstrap.h>
43 #include "fwohcireg.h"
44 #include <dev/firewire/firewire_phy.h>
46 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
47 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
51 #define device_printf(a, x, ...) printf("FW1394: " x, ## __VA_ARGS__)
53 #define device_printf(a, x, ...)
57 #define DELAY(x) delay(x)
60 #define MAXREC(x) (2 << (x))
62 "S100", "S200", "S400", "S800",
63 "S1600", "S3200", "undef", "undef"
66 #define FW_EUI64_BYTE(eui, x) \
68 ((eui)->hi >> (8*(3-(x)))): \
69 ((eui)->lo >> (8*(7-(x)))) \
73 * Communication with PHY device
76 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
83 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
84 OWRITE(sc, OHCI_PHYACCESS, fun);
87 return(fwphy_rddata( sc, addr));
91 fwphy_rddata(struct fwohci_softc *sc, u_int addr)
99 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
100 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
101 OWRITE(sc, OHCI_PHYACCESS, fun);
102 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
103 fun = OREAD(sc, OHCI_PHYACCESS);
104 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
110 device_printf(sc->fc.dev, "phy read failed(1).\n");
111 if (++retry < MAX_RETRY) {
116 /* Make sure that SCLK is started */
117 stat = OREAD(sc, FWOHCI_INTSTAT);
118 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
119 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
121 device_printf(sc->fc.dev, "phy read failed(2).\n");
122 if (++retry < MAX_RETRY) {
127 if (firewire_debug || retry >= MAX_RETRY)
128 device_printf(sc->fc.dev,
129 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
131 return((fun >> PHYDEV_RDDATA )& 0xff);
136 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
142 * probe PHY parameters
143 * 0. to prove PHY version, whether compliance of 1394a.
144 * 1. to probe maximum speed supported by the PHY and
145 * number of port supported by core-logic.
146 * It is not actually available port on your PC .
148 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
151 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
153 if((reg >> 5) != 7 ){
154 nport = reg & FW_PHY_NP;
155 speed = reg & FW_PHY_SPD >> 6;
156 if (speed > MAX_SPEED) {
157 device_printf(dev, "invalid speed %d (fixed to %d).\n",
162 "Phy 1394 only %s, %d ports.\n",
163 linkspeed[speed], nport);
165 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
166 nport = reg & FW_PHY_NP;
167 speed = (reg2 & FW_PHY_ESPD) >> 5;
168 if (speed > MAX_SPEED) {
169 device_printf(dev, "invalid speed %d (fixed to %d).\n",
174 "Phy 1394a available %s, %d ports.\n",
175 linkspeed[speed], nport);
177 /* check programPhyEnable */
178 reg2 = fwphy_rddata(sc, 5);
180 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
181 #else /* XXX force to enable 1394a */
186 "Enable 1394a Enhancements\n");
189 /* set aPhyEnhanceEnable */
190 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
191 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
196 reg2 = fwphy_wrdata(sc, 5, reg2);
200 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
201 if((reg >> 5) == 7 ){
202 reg = fwphy_rddata(sc, 4);
204 fwphy_wrdata(sc, 4, reg);
205 reg = fwphy_rddata(sc, 4);
212 fwohci_reset(struct fwohci_softc *sc, device_t dev)
214 int i, max_rec, speed;
217 /* Disable interrupts */
218 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
220 /* FLUSH FIFO and reset Transmitter/Reciever */
221 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
223 device_printf(dev, "resetting OHCI...");
225 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
226 if (i++ > 100) break;
230 printf("done (loop=%d)\n", i);
233 fwohci_probe_phy(sc, dev);
236 reg = OREAD(sc, OHCI_BUS_OPT);
237 reg2 = reg | OHCI_BUSFNC;
238 max_rec = (reg & 0x0000f000) >> 12;
239 speed = (reg & 0x00000007);
240 device_printf(dev, "Link %s, max_rec %d bytes.\n",
241 linkspeed[speed], MAXREC(max_rec));
242 /* XXX fix max_rec */
243 sc->maxrec = sc->speed + 8;
244 if (max_rec != sc->maxrec) {
245 reg2 = (reg2 & 0xffff0fff) | (sc->maxrec << 12);
246 device_printf(dev, "max_rec %d -> %d\n",
247 MAXREC(max_rec), MAXREC(sc->maxrec));
250 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
251 OWRITE(sc, OHCI_BUS_OPT, reg2);
253 /* Initialize registers */
254 OWRITE(sc, OHCI_CROMHDR, sc->config_rom[0]);
255 OWRITE(sc, OHCI_CROMPTR, VTOP(sc->config_rom));
257 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
259 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
260 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
262 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
266 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
270 fwohci_init(struct fwohci_softc *sc, device_t dev)
277 reg = OREAD(sc, OHCI_VERSION);
278 mver = (reg >> 16) & 0xff;
279 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
280 mver, reg & 0xff, (reg>>24) & 1);
281 if (mver < 1 || mver > 9) {
282 device_printf(dev, "invalid OHCI version\n");
286 /* Available Isochronous DMA channel probe */
287 OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
288 OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
289 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
290 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
291 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
292 for (i = 0; i < 0x20; i++)
293 if ((reg & (1 << i)) == 0)
295 device_printf(dev, "No. of Isochronous channels is %d.\n", i);
300 /* SID recieve buffer must align 2^11 */
301 #define OHCI_SIDSIZE (1 << 11)
302 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
303 &sc->sid_dma, BUS_DMA_WAITOK);
304 if (sc->sid_buf == NULL) {
305 device_printf(dev, "sid_buf alloc failed.");
310 sc->eui.hi = OREAD(sc, FWOHCIGUID_H);
311 sc->eui.lo = OREAD(sc, FWOHCIGUID_L);
312 for( i = 0 ; i < 8 ; i ++)
313 ui[i] = FW_EUI64_BYTE(&sc->eui,i);
314 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
315 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
316 fwohci_reset(sc, dev);
322 fwohci_ibr(struct fwohci_softc *sc)
326 device_printf(sc->dev, "Initiate bus reset\n");
329 * Make sure our cached values from the config rom are
332 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
333 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
336 * Set root hold-off bit so that non cyclemaster capable node
337 * shouldn't became the root node.
340 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
342 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
343 #else /* Short bus reset */
344 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
346 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
352 fwohci_sid(struct fwohci_softc *sc)
357 node_id = OREAD(sc, FWOHCI_NODEID);
358 if (!(node_id & OHCI_NODE_VALID)) {
360 printf("Bus reset failure\n");
365 /* Enable bus reset interrupt */
366 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
367 /* Allow async. request to us */
368 OWRITE(sc, OHCI_AREQHI, 1 << 31);
369 /* XXX insecure ?? */
370 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
371 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
372 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
373 /* Set ATRetries register */
374 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
376 ** Checking whether the node is root or not. If root, turn on
379 plen = OREAD(sc, OHCI_SID_CNT);
380 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
381 node_id, (plen >> 16) & 0xff);
382 if (node_id & OHCI_NODE_ROOT) {
383 device_printf(sc->dev, "CYCLEMASTER mode\n");
384 OWRITE(sc, OHCI_LNKCTL,
385 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
387 device_printf(sc->dev, "non CYCLEMASTER mode\n");
388 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
389 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
391 if (plen & OHCI_SID_ERR) {
392 device_printf(fc->dev, "SID Error\n");
395 device_printf(sc->dev, "bus reset phase done\n");
396 sc->state = FWOHCI_STATE_NORMAL;
400 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count)
405 if(stat & OREAD(sc, FWOHCI_INTMASK))
409 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
410 stat & OHCI_INT_EN ? "DMA_EN ":"",
411 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
412 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
413 stat & OHCI_INT_ERR ? "INT_ERR ":"",
414 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
415 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
416 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
417 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
418 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
419 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
420 stat & OHCI_INT_PHY_SID ? "SID ":"",
421 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
422 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
423 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
424 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
425 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
426 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
427 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
428 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
429 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
430 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
431 stat, OREAD(sc, FWOHCI_INTMASK)
435 if(stat & OHCI_INT_PHY_BUS_R ){
436 device_printf(fc->dev, "BUS reset\n");
437 if (sc->state == FWOHCI_STATE_BUSRESET)
439 sc->state = FWOHCI_STATE_BUSRESET;
440 /* Disable bus reset interrupt until sid recv. */
441 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
443 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
444 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
446 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
447 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
448 } else if (sc->state == FWOHCI_STATE_BUSRESET) {
456 fwochi_check_stat(struct fwohci_softc *sc)
460 stat = OREAD(sc, FWOHCI_INTSTAT);
461 if (stat == 0xffffffff) {
462 device_printf(sc->fc.dev,
463 "device physically ejected?\n");
467 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
472 fwohci_poll(struct fwohci_softc *sc)
476 stat = fwochi_check_stat(sc);
477 if (stat != 0xffffffff)
478 fwohci_intr_body(sc, stat, 1);