2 * Initial implementation:
3 * Copyright (c) 2001 Robert Drehmel
6 * As long as the above copyright statement and this notice remain
7 * unchanged, you can do what ever you want with this file.
10 * Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org>
11 * All rights reserved.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * FreeBSD/sparc64 kernel loader - machine dependent part
41 * - implements copyin and readin functions that map kernel
42 * pages on demand. The machine independent code does not
43 * know the size of the kernel early enough to pre-enter
44 * TTEs and install just one 4MB mapping seemed to limiting
49 #include <sys/param.h>
51 #include <sys/linker.h>
52 #include <sys/queue.h>
53 #include <sys/types.h>
56 #include <machine/asi.h>
57 #include <machine/cmt.h>
58 #include <machine/cpufunc.h>
59 #include <machine/elf.h>
60 #include <machine/fireplane.h>
61 #include <machine/jbus.h>
62 #include <machine/lsu.h>
63 #include <machine/metadata.h>
64 #include <machine/tte.h>
65 #include <machine/tlb.h>
66 #include <machine/upa.h>
67 #include <machine/ver.h>
68 #include <machine/vmparam.h>
70 #include "bootstrap.h"
75 #define CTASSERT(x) _CTASSERT(x, __LINE__)
76 #define _CTASSERT(x, y) __CTASSERT(x, y)
77 #define __CTASSERT(x, y) typedef char __assert ## y[(x) ? 1 : -1]
80 extern char bootprog_name[], bootprog_rev[], bootprog_date[], bootprog_maker[];
85 LOADSZ = 0x1000000 /* for kernel and modules */
88 /* At least Sun Fire V1280 require page sized allocations to be claimed. */
89 CTASSERT(HEAPSZ % PAGE_SIZE == 0);
91 static struct mmu_ops {
92 void (*tlb_init)(void);
93 int (*mmu_mapin)(vm_offset_t va, vm_size_t len);
96 typedef void kernel_entry_t(vm_offset_t mdp, u_long o1, u_long o2, u_long o3,
99 static inline u_long dtlb_get_data_sun4u(u_int, u_int);
100 static int dtlb_enter_sun4u(u_int, u_long data, vm_offset_t);
101 static vm_offset_t dtlb_va_to_pa_sun4u(vm_offset_t);
102 static inline u_long itlb_get_data_sun4u(u_int, u_int);
103 static int itlb_enter_sun4u(u_int, u_long data, vm_offset_t);
104 static vm_offset_t itlb_va_to_pa_sun4u(vm_offset_t);
105 static void itlb_relocate_locked0_sun4u(void);
106 extern vm_offset_t md_load(char *, vm_offset_t *);
107 static int sparc64_autoload(void);
108 static ssize_t sparc64_readin(const int, vm_offset_t, const size_t);
109 static ssize_t sparc64_copyin(const void *, vm_offset_t, size_t);
110 static void sparc64_maphint(vm_offset_t, size_t);
111 static vm_offset_t claim_virt(vm_offset_t, size_t, int);
112 static vm_offset_t alloc_phys(size_t, int);
113 static int map_phys(int, size_t, vm_offset_t, vm_offset_t);
114 static void release_phys(vm_offset_t, u_int);
115 static int __elfN(exec)(struct preloaded_file *);
116 static int mmu_mapin_sun4u(vm_offset_t, vm_size_t);
117 static int mmu_mapin_sun4v(vm_offset_t, vm_size_t);
118 static vm_offset_t init_heap(void);
119 static phandle_t find_bsp_sun4u(phandle_t, uint32_t);
120 const char *cpu_cpuid_prop_sun4u(void);
121 uint32_t cpu_get_mid_sun4u(void);
122 static void tlb_init_sun4u(void);
123 static void tlb_init_sun4v(void);
126 typedef u_int64_t tte_t;
128 static void pmap_print_tlb_sun4u(void);
129 static void pmap_print_tte_sun4u(tte_t, tte_t);
132 static struct mmu_ops mmu_ops_sun4u = { tlb_init_sun4u, mmu_mapin_sun4u };
133 static struct mmu_ops mmu_ops_sun4v = { tlb_init_sun4v, mmu_mapin_sun4v };
136 struct tlb_entry *dtlb_store;
137 struct tlb_entry *itlb_store;
141 static u_int dtlb_slot_max;
142 static u_int itlb_slot_max;
143 static u_int tlb_locked;
146 static struct tlb_entry *tlb_store;
147 static int is_sun4v = 0;
149 * no direct TLB access on sun4v
150 * we somewhat arbitrarily declare enough
151 * slots to cover a 4GB AS with 4MB pages
153 #define SUN4V_TLB_SLOT_MAX (1 << 10)
155 static vm_offset_t curkva = 0;
156 static vm_offset_t heapva;
158 static phandle_t root;
161 * Machine dependent structures that the machine independent
164 struct devsw *devsw[] = {
165 #ifdef LOADER_DISK_SUPPORT
168 #ifdef LOADER_NET_SUPPORT
173 struct arch_switch archsw;
175 static struct file_format sparc64_elf = {
179 struct file_format *file_formats[] = {
183 struct fs_ops *file_system[] = {
184 #ifdef LOADER_UFS_SUPPORT
187 #ifdef LOADER_CD9660_SUPPORT
190 #ifdef LOADER_ZIP_SUPPORT
193 #ifdef LOADER_GZIP_SUPPORT
196 #ifdef LOADER_BZIP2_SUPPORT
199 #ifdef LOADER_NFS_SUPPORT
202 #ifdef LOADER_TFTP_SUPPORT
207 struct netif_driver *netif_drivers[] = {
208 #ifdef LOADER_NET_SUPPORT
214 extern struct console ofwconsole;
215 struct console *consoles[] = {
222 watch_phys_set_mask(vm_offset_t pa, u_long mask)
226 stxa(AA_DMMU_PWPR, ASI_DMMU, pa & (((2UL << 38) - 1) << 3));
227 lsucr = ldxa(0, ASI_LSU_CTL_REG);
228 lsucr = ((lsucr | LSU_PW) & ~LSU_PM_MASK) |
229 (mask << LSU_PM_SHIFT);
230 stxa(0, ASI_LSU_CTL_REG, lsucr);
235 watch_phys_set(vm_offset_t pa, int sz)
239 off = (u_long)pa & 7;
240 /* Test for misaligned watch points. */
243 return (watch_phys_set_mask(pa, ((1 << sz) - 1) << off));
248 watch_virt_set_mask(vm_offset_t va, u_long mask)
252 stxa(AA_DMMU_VWPR, ASI_DMMU, va & (((2UL << 41) - 1) << 3));
253 lsucr = ldxa(0, ASI_LSU_CTL_REG);
254 lsucr = ((lsucr | LSU_VW) & ~LSU_VM_MASK) |
255 (mask << LSU_VM_SHIFT);
256 stxa(0, ASI_LSU_CTL_REG, lsucr);
261 watch_virt_set(vm_offset_t va, int sz)
265 off = (u_long)va & 7;
266 /* Test for misaligned watch points. */
269 return (watch_virt_set_mask(va, ((1 << sz) - 1) << off));
277 sparc64_autoload(void)
284 sparc64_readin(const int fd, vm_offset_t va, const size_t len)
287 mmu_ops->mmu_mapin(va, len);
288 return (read(fd, (void *)va, len));
292 sparc64_copyin(const void *src, vm_offset_t dest, size_t len)
295 mmu_ops->mmu_mapin(dest, len);
296 memcpy((void *)dest, src, len);
301 sparc64_maphint(vm_offset_t va, size_t len)
306 int i, free_excess = 0;
311 if (tlb_store[va >> 22].te_pa != -1)
314 /* round up to nearest 4MB page */
315 size = (len + PAGE_MASK_4M) & ~PAGE_MASK_4M;
317 pa = alloc_phys(PAGE_SIZE_256M, PAGE_SIZE_256M);
323 pa = alloc_phys(size, PAGE_SIZE_256M);
325 pa = alloc_phys(size, PAGE_SIZE_4M);
327 panic("%s: out of memory", __func__);
329 for (i = 0; i < size; i += PAGE_SIZE_4M) {
330 mva = claim_virt(va + i, PAGE_SIZE_4M, 0);
332 panic("%s: can't claim virtual page "
333 "(wanted %#lx, got %#lx)",
336 tlb_store[mva >> 22].te_pa = pa + i;
337 if (map_phys(-1, PAGE_SIZE_4M, mva, pa + i) != 0)
338 printf("%s: can't map physical page\n", __func__);
341 release_phys(pa, PAGE_SIZE_256M);
348 claim_virt(vm_offset_t virt, size_t size, int align)
352 if (OF_call_method("claim", mmu, 3, 1, virt, size, align, &mva) == -1)
353 return ((vm_offset_t)-1);
358 alloc_phys(size_t size, int align)
360 cell_t phys_hi, phys_low;
362 if (OF_call_method("claim", memory, 2, 2, size, align, &phys_low,
364 return ((vm_offset_t)-1);
365 return ((vm_offset_t)phys_hi << 32 | phys_low);
369 map_phys(int mode, size_t size, vm_offset_t virt, vm_offset_t phys)
372 return (OF_call_method("map", mmu, 5, 0, (uint32_t)phys,
373 (uint32_t)(phys >> 32), virt, size, mode));
377 release_phys(vm_offset_t phys, u_int size)
380 (void)OF_call_method("release", memory, 3, 0, (uint32_t)phys,
381 (uint32_t)(phys >> 32), size);
385 __elfN(exec)(struct preloaded_file *fp)
387 struct file_metadata *fmp;
393 if ((fmp = file_findmetadata(fp, MODINFOMD_ELFHDR)) == 0)
395 e = (Elf_Ehdr *)&fmp->md_data;
397 if ((error = md_load(fp->f_args, &mdp)) != 0)
400 printf("jumping to kernel entry at %#lx.\n", e->e_entry);
402 pmap_print_tlb_sun4u();
409 OF_release((void *)heapva, HEAPSZ);
411 ((kernel_entry_t *)entry)(mdp, 0, 0, 0, openfirmware);
413 panic("%s: exec returned", __func__);
417 dtlb_get_data_sun4u(u_int tlb, u_int slot)
421 slot = TLB_DAR_SLOT(tlb, slot);
423 * We read ASI_DTLB_DATA_ACCESS_REG twice back-to-back in order to
424 * work around errata of USIII and beyond.
426 pstate = rdpr(pstate);
427 wrpr(pstate, pstate & ~PSTATE_IE, 0);
428 (void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
429 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
430 wrpr(pstate, pstate, 0);
435 itlb_get_data_sun4u(u_int tlb, u_int slot)
439 slot = TLB_DAR_SLOT(tlb, slot);
441 * We read ASI_DTLB_DATA_ACCESS_REG twice back-to-back in order to
442 * work around errata of USIII and beyond.
444 pstate = rdpr(pstate);
445 wrpr(pstate, pstate & ~PSTATE_IE, 0);
446 (void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
447 data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
448 wrpr(pstate, pstate, 0);
453 dtlb_va_to_pa_sun4u(vm_offset_t va)
458 pstate = rdpr(pstate);
459 wrpr(pstate, pstate & ~PSTATE_IE, 0);
460 for (i = 0; i < dtlb_slot_max; i++) {
461 reg = ldxa(TLB_DAR_SLOT(tlb_locked, i),
462 ASI_DTLB_TAG_READ_REG);
463 if (TLB_TAR_VA(reg) != va)
465 reg = dtlb_get_data_sun4u(tlb_locked, i);
466 wrpr(pstate, pstate, 0);
468 if (cpu_impl == CPU_IMPL_SPARC64V ||
469 cpu_impl >= CPU_IMPL_ULTRASPARCIII)
470 return (reg & TD_PA_CH_MASK);
471 return (reg & TD_PA_SF_MASK);
473 wrpr(pstate, pstate, 0);
478 itlb_va_to_pa_sun4u(vm_offset_t va)
483 pstate = rdpr(pstate);
484 wrpr(pstate, pstate & ~PSTATE_IE, 0);
485 for (i = 0; i < itlb_slot_max; i++) {
486 reg = ldxa(TLB_DAR_SLOT(tlb_locked, i),
487 ASI_ITLB_TAG_READ_REG);
488 if (TLB_TAR_VA(reg) != va)
490 reg = itlb_get_data_sun4u(tlb_locked, i);
491 wrpr(pstate, pstate, 0);
493 if (cpu_impl == CPU_IMPL_SPARC64V ||
494 cpu_impl >= CPU_IMPL_ULTRASPARCIII)
495 return (reg & TD_PA_CH_MASK);
496 return (reg & TD_PA_SF_MASK);
498 wrpr(pstate, pstate, 0);
503 dtlb_enter_sun4u(u_int index, u_long data, vm_offset_t virt)
506 return (OF_call_method("SUNW,dtlb-load", mmu, 3, 0, index, data,
511 itlb_enter_sun4u(u_int index, u_long data, vm_offset_t virt)
514 if (cpu_impl == CPU_IMPL_ULTRASPARCIIIp && index == 0 &&
516 panic("%s: won't enter locked TLB entry at index 0 on USIII+",
518 return (OF_call_method("SUNW,itlb-load", mmu, 3, 0, index, data,
523 itlb_relocate_locked0_sun4u(void)
525 u_long data, pstate, tag;
528 if (cpu_impl != CPU_IMPL_ULTRASPARCIIIp)
531 pstate = rdpr(pstate);
532 wrpr(pstate, pstate & ~PSTATE_IE, 0);
534 data = itlb_get_data_sun4u(tlb_locked, 0);
535 if ((data & (TD_V | TD_L)) != (TD_V | TD_L)) {
536 wrpr(pstate, pstate, 0);
540 /* Flush the mapping of slot 0. */
541 tag = ldxa(TLB_DAR_SLOT(tlb_locked, 0), ASI_ITLB_TAG_READ_REG);
542 stxa(TLB_DEMAP_VA(TLB_TAR_VA(tag)) | TLB_DEMAP_PRIMARY |
543 TLB_DEMAP_PAGE, ASI_IMMU_DEMAP, 0);
544 flush(0); /* The USIII-family ignores the address. */
547 * Search a replacement slot != 0 and enter the data and tag
548 * that formerly were in slot 0.
550 for (i = 1; i < itlb_slot_max; i++) {
551 if ((itlb_get_data_sun4u(tlb_locked, i) & TD_V) != 0)
554 stxa(AA_IMMU_TAR, ASI_IMMU, tag);
555 stxa(TLB_DAR_SLOT(tlb_locked, i), ASI_ITLB_DATA_ACCESS_REG,
557 flush(0); /* The USIII-family ignores the address. */
560 wrpr(pstate, pstate, 0);
561 if (i == itlb_slot_max)
562 panic("%s: could not find a replacement slot", __func__);
566 mmu_mapin_sun4u(vm_offset_t va, vm_size_t len)
572 if (va + len > curkva)
575 pa = (vm_offset_t)-1;
576 len += va & PAGE_MASK_4M;
579 if (dtlb_va_to_pa_sun4u(va) == (vm_offset_t)-1 ||
580 itlb_va_to_pa_sun4u(va) == (vm_offset_t)-1) {
581 /* Allocate a physical page, claim the virtual area. */
582 if (pa == (vm_offset_t)-1) {
583 pa = alloc_phys(PAGE_SIZE_4M, PAGE_SIZE_4M);
584 if (pa == (vm_offset_t)-1)
585 panic("%s: out of memory", __func__);
586 mva = claim_virt(va, PAGE_SIZE_4M, 0);
588 panic("%s: can't claim virtual page "
589 "(wanted %#lx, got %#lx)",
592 * The mappings may have changed, be paranoid.
597 * Actually, we can only allocate two pages less at
598 * most (depending on the kernel TSB size).
600 if (dtlb_slot >= dtlb_slot_max)
601 panic("%s: out of dtlb_slots", __func__);
602 if (itlb_slot >= itlb_slot_max)
603 panic("%s: out of itlb_slots", __func__);
604 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP |
606 dtlb_store[dtlb_slot].te_pa = pa;
607 dtlb_store[dtlb_slot].te_va = va;
608 index = dtlb_slot_max - dtlb_slot - 1;
609 if (dtlb_enter_sun4u(index, data, va) < 0)
610 panic("%s: can't enter dTLB slot %d data "
611 "%#lx va %#lx", __func__, index, data,
614 itlb_store[itlb_slot].te_pa = pa;
615 itlb_store[itlb_slot].te_va = va;
616 index = itlb_slot_max - itlb_slot - 1;
617 if (itlb_enter_sun4u(index, data, va) < 0)
618 panic("%s: can't enter iTLB slot %d data "
619 "%#lx va %#lxd", __func__, index, data,
622 pa = (vm_offset_t)-1;
624 len -= len > PAGE_SIZE_4M ? PAGE_SIZE_4M : len;
627 if (pa != (vm_offset_t)-1)
628 release_phys(pa, PAGE_SIZE_4M);
633 mmu_mapin_sun4v(vm_offset_t va, vm_size_t len)
637 if (va + len > curkva)
640 pa = (vm_offset_t)-1;
641 len += va & PAGE_MASK_4M;
644 if ((va >> 22) > SUN4V_TLB_SLOT_MAX)
645 panic("%s: trying to map more than 4GB", __func__);
646 if (tlb_store[va >> 22].te_pa == -1) {
647 /* Allocate a physical page, claim the virtual area */
648 if (pa == (vm_offset_t)-1) {
649 pa = alloc_phys(PAGE_SIZE_4M, PAGE_SIZE_4M);
650 if (pa == (vm_offset_t)-1)
651 panic("%s: out of memory", __func__);
652 mva = claim_virt(va, PAGE_SIZE_4M, 0);
654 panic("%s: can't claim virtual page "
655 "(wanted %#lx, got %#lx)",
659 tlb_store[va >> 22].te_pa = pa;
660 if (map_phys(-1, PAGE_SIZE_4M, va, pa) == -1)
661 printf("%s: can't map physical page\n",
663 pa = (vm_offset_t)-1;
665 len -= len > PAGE_SIZE_4M ? PAGE_SIZE_4M : len;
668 if (pa != (vm_offset_t)-1)
669 release_phys(pa, PAGE_SIZE_4M);
677 /* There is no need for continuous physical heap memory. */
678 heapva = (vm_offset_t)OF_claim((void *)HEAPVA, HEAPSZ, 32);
683 find_bsp_sun4u(phandle_t node, uint32_t bspid)
685 char type[sizeof("cpu")];
689 for (; node > 0; node = OF_peer(node)) {
690 child = OF_child(node);
692 child = find_bsp_sun4u(child, bspid);
696 if (OF_getprop(node, "device_type", type,
699 if (strcmp(type, "cpu") != 0)
701 if (OF_getprop(node, cpu_cpuid_prop_sun4u(), &cpuid,
712 cpu_cpuid_prop_sun4u(void)
716 case CPU_IMPL_SPARC64:
717 case CPU_IMPL_SPARC64V:
718 case CPU_IMPL_ULTRASPARCI:
719 case CPU_IMPL_ULTRASPARCII:
720 case CPU_IMPL_ULTRASPARCIIi:
721 case CPU_IMPL_ULTRASPARCIIe:
722 return ("upa-portid");
723 case CPU_IMPL_ULTRASPARCIII:
724 case CPU_IMPL_ULTRASPARCIIIp:
725 case CPU_IMPL_ULTRASPARCIIIi:
726 case CPU_IMPL_ULTRASPARCIIIip:
728 case CPU_IMPL_ULTRASPARCIV:
729 case CPU_IMPL_ULTRASPARCIVp:
737 cpu_get_mid_sun4u(void)
741 case CPU_IMPL_SPARC64:
742 case CPU_IMPL_SPARC64V:
743 case CPU_IMPL_ULTRASPARCI:
744 case CPU_IMPL_ULTRASPARCII:
745 case CPU_IMPL_ULTRASPARCIIi:
746 case CPU_IMPL_ULTRASPARCIIe:
747 return (UPA_CR_GET_MID(ldxa(0, ASI_UPA_CONFIG_REG)));
748 case CPU_IMPL_ULTRASPARCIII:
749 case CPU_IMPL_ULTRASPARCIIIp:
750 return (FIREPLANE_CR_GET_AID(ldxa(AA_FIREPLANE_CONFIG,
751 ASI_FIREPLANE_CONFIG_REG)));
752 case CPU_IMPL_ULTRASPARCIIIi:
753 case CPU_IMPL_ULTRASPARCIIIip:
754 return (JBUS_CR_GET_JID(ldxa(0, ASI_JBUS_CONFIG_REG)));
755 case CPU_IMPL_ULTRASPARCIV:
756 case CPU_IMPL_ULTRASPARCIVp:
757 return (INTR_ID_GET_ID(ldxa(AA_INTR_ID, ASI_INTR_ID)));
768 cpu_impl = VER_IMPL(rdpr(ver));
770 case CPU_IMPL_SPARC64:
771 case CPU_IMPL_ULTRASPARCI:
772 case CPU_IMPL_ULTRASPARCII:
773 case CPU_IMPL_ULTRASPARCIIi:
774 case CPU_IMPL_ULTRASPARCIIe:
775 tlb_locked = TLB_DAR_T32;
777 case CPU_IMPL_ULTRASPARCIII:
778 case CPU_IMPL_ULTRASPARCIIIp:
779 case CPU_IMPL_ULTRASPARCIIIi:
780 case CPU_IMPL_ULTRASPARCIIIip:
781 case CPU_IMPL_ULTRASPARCIV:
782 case CPU_IMPL_ULTRASPARCIVp:
783 tlb_locked = TLB_DAR_T16;
785 case CPU_IMPL_SPARC64V:
786 tlb_locked = TLB_DAR_FTLB;
789 bsp = find_bsp_sun4u(OF_child(root), cpu_get_mid_sun4u());
791 panic("%s: no node for bootcpu?!?!", __func__);
793 if (OF_getprop(bsp, "#dtlb-entries", &dtlb_slot_max,
794 sizeof(dtlb_slot_max)) == -1 ||
795 OF_getprop(bsp, "#itlb-entries", &itlb_slot_max,
796 sizeof(itlb_slot_max)) == -1)
797 panic("%s: can't get TLB slot max.", __func__);
799 if (cpu_impl == CPU_IMPL_ULTRASPARCIIIp) {
801 printf("pre fixup:\n");
802 pmap_print_tlb_sun4u();
806 * Relocate the locked entry in it16 slot 0 (if existent)
807 * as part of working around Cheetah+ erratum 34.
809 itlb_relocate_locked0_sun4u();
812 printf("post fixup:\n");
813 pmap_print_tlb_sun4u();
817 dtlb_store = malloc(dtlb_slot_max * sizeof(*dtlb_store));
818 itlb_store = malloc(itlb_slot_max * sizeof(*itlb_store));
819 if (dtlb_store == NULL || itlb_store == NULL)
820 panic("%s: can't allocate TLB store", __func__);
827 tlb_store = malloc(SUN4V_TLB_SLOT_MAX * sizeof(*tlb_store));
828 memset(tlb_store, 0xFF, SUN4V_TLB_SLOT_MAX * sizeof(*tlb_store));
832 main(int (*openfirm)(void *))
839 * Tell the Open Firmware functions where they find the OFW gate.
843 archsw.arch_getdev = ofw_getdev;
844 archsw.arch_copyin = sparc64_copyin;
845 archsw.arch_copyout = ofw_copyout;
846 archsw.arch_readin = sparc64_readin;
847 archsw.arch_autoload = sparc64_autoload;
848 archsw.arch_maphint = sparc64_maphint;
850 if (init_heap() == (vm_offset_t)-1)
852 setheap((void *)heapva, (void *)(heapva + HEAPSZ));
855 * Probe for a console.
859 if ((root = OF_peer(0)) == -1)
860 panic("%s: can't get root phandle", __func__);
861 OF_getprop(root, "compatible", compatible, sizeof(compatible));
862 if (!strcmp(compatible, "sun4v")) {
863 printf("\nBooting with sun4v support.\n");
864 mmu_ops = &mmu_ops_sun4v;
867 printf("\nBooting with sun4u support.\n");
868 mmu_ops = &mmu_ops_sun4u;
874 * Initialize devices.
876 for (dp = devsw; *dp != 0; dp++) {
877 if ((*dp)->dv_init != 0)
882 * Set up the current device.
884 OF_getprop(chosen, "bootpath", bootpath, sizeof(bootpath));
887 * Sun compatible bootable CD-ROMs have a disk label placed
888 * before the cd9660 data, with the actual filesystem being
889 * in the first partition, while the other partitions contain
890 * pseudo disk labels with embedded boot blocks for different
891 * architectures, which may be followed by UFS filesystems.
892 * The firmware will set the boot path to the partition it
893 * boots from ('f' in the sun4u case), but we want the kernel
894 * to be loaded from the cd9660 fs ('a'), so the boot path
895 * needs to be altered.
897 if (bootpath[strlen(bootpath) - 2] == ':' &&
898 bootpath[strlen(bootpath) - 1] == 'f') {
899 bootpath[strlen(bootpath) - 1] = 'a';
900 printf("Boot path set to %s\n", bootpath);
903 env_setenv("currdev", EV_VOLATILE, bootpath,
904 ofw_setcurrdev, env_nounset);
905 env_setenv("loaddev", EV_VOLATILE, bootpath,
906 env_noset, env_nounset);
909 printf("%s, Revision %s\n", bootprog_name, bootprog_rev);
910 printf("(%s, %s)\n", bootprog_maker, bootprog_date);
911 printf("bootpath=\"%s\"\n", bootpath);
913 /* Give control to the machine independent loader code. */
918 COMMAND_SET(heap, "heap", "show heap usage", command_heap);
921 command_heap(int argc, char *argv[])
925 printf("heap base at %p, top at %p, upper limit at %p\n", heapva,
926 sbrk(0), heapva + HEAPSZ);
930 COMMAND_SET(reboot, "reboot", "reboot the system", command_reboot);
933 command_reboot(int argc, char *argv[])
937 for (i = 0; devsw[i] != NULL; ++i)
938 if (devsw[i]->dv_cleanup != NULL)
939 (devsw[i]->dv_cleanup)();
941 printf("Rebooting...\n");
945 /* provide this for panic, as it's not in the startup code */
954 static const char *const page_sizes[] = {
955 " 8k", " 64k", "512k", " 4m"
959 pmap_print_tte_sun4u(tte_t tag, tte_t tte)
963 page_sizes[(tte >> TD_SIZE_SHIFT) & TD_SIZE_MASK],
964 tag & TD_G ? "G" : " ");
965 printf(tte & TD_W ? "W " : " ");
966 printf(tte & TD_P ? "\e[33mP\e[0m " : " ");
967 printf(tte & TD_E ? "E " : " ");
968 printf(tte & TD_CV ? "CV " : " ");
969 printf(tte & TD_CP ? "CP " : " ");
970 printf(tte & TD_L ? "\e[32mL\e[0m " : " ");
971 printf(tte & TD_IE ? "IE " : " ");
972 printf(tte & TD_NFO ? "NFO " : " ");
973 printf("pa=0x%lx va=0x%lx ctx=%ld\n",
974 TD_PA(tte), TLB_TAR_VA(tag), TLB_TAR_CTX(tag));
978 pmap_print_tlb_sun4u(void)
984 pstate = rdpr(pstate);
985 for (i = 0; i < itlb_slot_max; i++) {
986 wrpr(pstate, pstate & ~PSTATE_IE, 0);
987 tte = itlb_get_data_sun4u(tlb_locked, i);
988 wrpr(pstate, pstate, 0);
991 tag = ldxa(TLB_DAR_SLOT(tlb_locked, i),
992 ASI_ITLB_TAG_READ_REG);
993 printf("iTLB-%2u: ", i);
994 pmap_print_tte_sun4u(tag, tte);
996 for (i = 0; i < dtlb_slot_max; i++) {
997 wrpr(pstate, pstate & ~PSTATE_IE, 0);
998 tte = dtlb_get_data_sun4u(tlb_locked, i);
999 wrpr(pstate, pstate, 0);
1002 tag = ldxa(TLB_DAR_SLOT(tlb_locked, i),
1003 ASI_DTLB_TAG_READ_REG);
1004 printf("dTLB-%2u: ", i);
1005 pmap_print_tte_sun4u(tag, tte);