5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright (c) 2012, Joyent, Inc. All rights reserved.
28 * Copyright (c) 2010, Intel Corporation.
29 * All rights reserved.
32 /* Copyright (c) 1988 AT&T */
33 /* All Rights Reserved */
39 #include "dis_tables.h"
44 * Disassembly begins in dis_distable, which is equivalent to the One-byte
45 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The
46 * decoding loops then traverse out through the other tables as necessary to
47 * decode a given instruction.
49 * The behavior of this file can be controlled by one of the following flags:
51 * DIS_TEXT Include text for disassembly
52 * DIS_MEM Include memory-size calculations
54 * Either or both of these can be defined.
56 * This file is not, and will never be, cstyled. If anything, the tables should
57 * be taken out another tab stop or two so nothing overlaps.
61 * These functions must be provided for the consumer to do disassembly.
64 extern char *strncpy(char *, const char *, size_t);
65 extern size_t strlen(const char *);
66 extern int strcmp(const char *, const char *);
67 extern int strncmp(const char *, const char *, size_t);
68 extern size_t strlcat(char *, const char *, size_t);
72 #define TERM 0 /* used to indicate that the 'indirect' */
73 /* field terminates - no pointer. */
75 /* Used to decode instructions. */
76 typedef struct instable {
77 struct instable *it_indirect; /* for decode op codes */
81 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */
86 uint_t it_invalid64:1; /* opcode invalid in amd64 */
87 uint_t it_always64:1; /* 64 bit when in 64 bit mode */
88 uint_t it_invalid32:1; /* invalid in IA32 */
89 uint_t it_stackop:1; /* push/pop stack operation */
93 * Instruction formats.
107 M, /* register or memory */
108 MG9, /* register or memory in group 9 (prefix optional) */
109 Mb, /* register or memory, always byte sized */
110 MO, /* memory only (no registers) */
119 RM_66r, /* RM, but with a required 0x66 prefix */
132 DSHIFT, /* for double shift that has an 8-bit immediate */
135 NORM, /* instructions w/o ModR/M byte, no memory access */
136 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */
138 JTAB, /* jump table */
139 IMUL, /* for 186 iimul instr */
140 CBW, /* so data16 can be evaluated for cbw and variants */
141 MvI, /* for 186 logicals */
142 ENTER, /* for 186 enter instr */
143 RMw, /* for 286 arpl instr */
144 Ib, /* for push immediate byte */
145 F, /* for 287 instructions */
146 FF, /* for 287 instructions */
147 FFC, /* for 287 instructions */
148 DM, /* 16-bit data */
149 AM, /* 16-bit addr */
150 LSEG, /* for 3-bit seg reg encoding */
151 MIb, /* for 386 logicals */
152 SREG, /* for 386 special registers */
153 PREFIX, /* a REP instruction prefix */
154 LOCK, /* a LOCK instruction prefix */
155 INT3, /* The int 3 instruction, which has a fake operand */
156 INTx, /* The normal int instruction, with explicit int num */
157 DSHIFTcl, /* for double shift that implicitly uses %cl */
158 CWD, /* so data16 can be evaluated for cwd and variants */
159 RET, /* single immediate 16-bit operand */
160 MOVZ, /* for movs and movz, with different size operands */
161 CRC32, /* for crc32, with different size operands */
162 XADDB, /* for xaddb */
163 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */
164 MOVBE, /* movbe instruction */
167 * MMX/SIMD addressing modes.
170 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */
171 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */
172 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */
173 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */
174 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */
175 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */
176 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */
177 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */
178 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */
179 MMOSH, /* Prefixable MMX mm,imm8 */
180 MM, /* MMX/SIMD-Int mm/mem -> mm */
181 MMS, /* MMX/SIMD-Int mm -> mm/mem */
182 MMSH, /* MMX mm,imm8 */
183 XMMO, /* Prefixable SIMD xmm/mem -> xmm */
184 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */
185 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */
186 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */
187 XMMOX3, /* Prefixable SIMD xmm -> r32 */
188 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */
189 XMMOM, /* Prefixable SIMD xmm -> mem */
190 XMMOMS, /* Prefixable SIMD mem -> xmm */
191 XMM, /* SIMD xmm/mem -> xmm */
192 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */
193 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */
194 XMMXIMPL, /* SIMD xmm -> xmm (mem) */
195 XMM3P, /* SIMD xmm -> r32,imm8 */
196 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */
197 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */
198 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */
199 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */
200 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */
201 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */
202 XMMS, /* SIMD xmm -> xmm/mem */
203 XMMM, /* SIMD mem -> xmm */
204 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */
205 XMMMS, /* SIMD xmm -> mem */
206 XMM3MX, /* SIMD r32/mem -> xmm */
207 XMM3MXS, /* SIMD xmm -> r32/mem */
208 XMMSH, /* SIMD xmm,imm8 */
209 XMMXM3, /* SIMD xmm/mem -> r32 */
210 XMMX3, /* SIMD xmm -> r32 */
211 XMMXMM, /* SIMD xmm/mem -> mm */
212 XMMMX, /* SIMD mm -> xmm */
213 XMMXM, /* SIMD xmm -> mm */
214 XMMX2I, /* SIMD xmm -> xmm, imm, imm */
215 XMM2I, /* SIMD xmm, imm, imm */
216 XMMFENCE, /* SIMD lfence or mfence */
217 XMMSFNC, /* SIMD sfence (none or mem) */
219 VEX_NONE, /* VEX no operand */
220 VEX_MO, /* VEX mod_rm -> implicit reg */
221 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
222 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */
223 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */
224 VEX_MX, /* VEX mod_rm -> mod_reg */
225 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */
226 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */
227 VEX_MR, /* VEX mod_rm -> mod_reg */
228 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */
229 VEX_RX, /* VEX mod_reg -> mod_rm */
230 VEX_RR, /* VEX mod_rm -> mod_reg */
231 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
232 VEX_RM, /* VEX mod_reg -> mod_rm */
233 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
234 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
235 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */
236 VMxo, /* VMx instruction with optional prefix */
237 SVM /* AMD SVM instructions */
243 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */
244 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */
246 #define FILL 0x90 /* Fill byte used for alignment (nop) */
249 ** Register numbers for the i386
261 * modes for immediate values
264 #define MODE_IPREL 1 /* signed IP relative value */
265 #define MODE_SIGNED 2 /* sign extended immediate */
266 #define MODE_IMPLIED 3 /* constant value implied from opcode */
267 #define MODE_OFFSET 4 /* offset part of an address */
268 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */
271 * The letters used in these macros are:
272 * IND - indirect to another to another table
273 * "T" - means to Terminate indirections (this is the final opcode)
274 * "S" - means "operand length suffix required"
275 * "NS" - means "no suffix" which is the operand length suffix of the opcode
276 * "Z" - means instruction size arg required
277 * "u" - means the opcode is invalid in IA32 but valid in amd64
278 * "x" - means the opcode is invalid in amd64, but not IA32
279 * "y" - means the operand size is always 64 bits in 64 bit mode
280 * "p" - means push/pop stack operation
283 #if defined(DIS_TEXT) && defined(DIS_MEM)
284 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0}
285 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0}
286 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0}
287 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0}
288 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0}
289 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0}
290 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1}
291 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0}
292 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0}
293 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0}
294 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0}
295 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0}
296 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1}
297 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0}
298 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0}
299 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0}
300 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
301 #elif defined(DIS_TEXT)
302 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0}
303 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0}
304 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0}
305 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0}
306 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0}
307 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0}
308 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1}
309 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0}
310 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0}
311 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0}
312 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0}
313 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0}
314 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1}
315 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0}
316 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0}
317 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0}
318 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
319 #elif defined(DIS_MEM)
320 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0}
321 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0}
322 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
323 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0}
324 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
325 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1}
326 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
327 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
328 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
329 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
330 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
331 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
332 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1}
333 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
334 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0}
335 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
336 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0}
338 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0}
339 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0}
340 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0}
341 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0}
342 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0}
343 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1}
344 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0}
345 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
346 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
347 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0}
348 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0}
349 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0}
350 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1}
351 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
352 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0}
353 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
354 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0}
359 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
361 const char *const dis_addr16[3][8] = {
362 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "",
364 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)",
366 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)",
372 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
374 const char *const dis_addr32_mode0[16] = {
375 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)",
376 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)"
379 const char *const dis_addr32_mode12[16] = {
380 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)",
381 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)"
385 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
387 const char *const dis_addr64_mode0[16] = {
388 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)",
389 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)"
391 const char *const dis_addr64_mode12[16] = {
392 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)",
393 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)"
397 * decode for scale from SIB byte
399 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" };
402 * register decoding for normal references to registers (ie. not addressing)
404 const char *const dis_REG8[16] = {
405 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
406 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
409 const char *const dis_REG8_REX[16] = {
410 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
411 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
414 const char *const dis_REG16[16] = {
415 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
416 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
419 const char *const dis_REG32[16] = {
420 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
421 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
424 const char *const dis_REG64[16] = {
425 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
426 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
429 const char *const dis_DEBUGREG[16] = {
430 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7",
431 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
434 const char *const dis_CONTROLREG[16] = {
435 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?",
436 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?"
439 const char *const dis_TESTREG[16] = {
440 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7",
441 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7"
444 const char *const dis_MMREG[16] = {
445 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7",
446 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7"
449 const char *const dis_XMMREG[16] = {
450 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
451 "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15"
454 const char *const dis_YMMREG[16] = {
455 "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7",
456 "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15"
459 const char *const dis_SEGREG[16] = {
460 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
461 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"
465 * SIMD predicate suffixes
467 const char *const dis_PREDSUFFIX[8] = {
468 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
471 const char *const dis_AVXvgrp7[3][8] = {
473 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""},
474 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""},
475 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"}
478 #endif /* DIS_TEXT */
481 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
483 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ);
486 * "decode table" for pause and clflush instructions
488 const instable_t dis_opPause = TNS("pause", NORM);
491 * Decode table for 0x0F00 opcodes
493 const instable_t dis_op0F00[8] = {
495 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M),
496 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID,
501 * Decode table for 0x0F01 opcodes
503 const instable_t dis_op0F01[8] = {
505 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6),
506 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP),
510 * Decode table for 0x0F18 opcodes -- SIMD prefetch
512 const instable_t dis_op0F18[8] = {
514 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),
515 /* [4] */ INVALID, INVALID, INVALID, INVALID,
519 * Decode table for 0x0FAE opcodes -- SIMD state save/restore
521 const instable_t dis_op0FAE[8] = {
522 /* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512), TNS("ldmxcsr",M), TNS("stmxcsr",M),
523 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),
527 * Decode table for 0x0FBA opcodes
530 const instable_t dis_op0FBA[8] = {
532 /* [0] */ INVALID, INVALID, INVALID, INVALID,
533 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb),
537 * Decode table for 0x0FC7 opcode (group 9)
540 const instable_t dis_op0FC7[8] = {
542 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, INVALID,
543 /* [4] */ INVALID, INVALID, TNS("vmptrld",MG9), TNS("vmptrst",MG9),
547 * Decode table for 0x0FC7 opcode (group 9) mode 3
550 const instable_t dis_op0FC7m3[8] = {
552 /* [0] */ INVALID, INVALID, INVALID, INVALID,
553 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), INVALID,
557 * Decode table for 0x0FC7 opcode with 0x66 prefix
560 const instable_t dis_op660FC7[8] = {
562 /* [0] */ INVALID, INVALID, INVALID, INVALID,
563 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID,
567 * Decode table for 0x0FC7 opcode with 0xF3 prefix
570 const instable_t dis_opF30FC7[8] = {
572 /* [0] */ INVALID, INVALID, INVALID, INVALID,
573 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID,
577 * Decode table for 0x0FC8 opcode -- 486 bswap instruction
579 *bit pattern: 0000 1111 1100 1reg
581 const instable_t dis_op0FC8[4] = {
582 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID,
586 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
588 const instable_t dis_op0F7123[4][8] = {
590 /* [70].0 */ INVALID, INVALID, INVALID, INVALID,
591 /* .4 */ INVALID, INVALID, INVALID, INVALID,
593 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID,
594 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID,
596 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID,
597 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID,
599 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH),
600 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH),
604 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
606 const instable_t dis_opSIMD7123[32] = {
607 /* [70].0 */ INVALID, INVALID, INVALID, INVALID,
608 /* .4 */ INVALID, INVALID, INVALID, INVALID,
610 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID,
611 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID,
613 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID,
614 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID,
616 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH),
617 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH),
621 * SIMD instructions have been wedged into the existing IA32 instruction
622 * set through the use of prefixes. That is, while 0xf0 0x58 may be
623 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
624 * instruction - addss. At present, three prefixes have been coopted in
625 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The
626 * following tables are used to provide the prefixed instruction names.
627 * The arrays are sparse, but they're fast.
631 * Decode table for SIMD instructions with the address size (0x66) prefix.
633 const instable_t dis_opSIMDdata16[256] = {
634 /* [00] */ INVALID, INVALID, INVALID, INVALID,
635 /* [04] */ INVALID, INVALID, INVALID, INVALID,
636 /* [08] */ INVALID, INVALID, INVALID, INVALID,
637 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
639 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8),
640 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8),
641 /* [18] */ INVALID, INVALID, INVALID, INVALID,
642 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
644 /* [20] */ INVALID, INVALID, INVALID, INVALID,
645 /* [24] */ INVALID, INVALID, INVALID, INVALID,
646 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
647 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
649 /* [30] */ INVALID, INVALID, INVALID, INVALID,
650 /* [34] */ INVALID, INVALID, INVALID, INVALID,
651 /* [38] */ INVALID, INVALID, INVALID, INVALID,
652 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
654 /* [40] */ INVALID, INVALID, INVALID, INVALID,
655 /* [44] */ INVALID, INVALID, INVALID, INVALID,
656 /* [48] */ INVALID, INVALID, INVALID, INVALID,
657 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
659 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID,
660 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16),
661 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
662 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16),
664 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
665 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16),
666 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
667 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
669 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID,
670 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID,
671 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID,
672 /* [7C] */ INVALID, INVALID, TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16),
674 /* [80] */ INVALID, INVALID, INVALID, INVALID,
675 /* [84] */ INVALID, INVALID, INVALID, INVALID,
676 /* [88] */ INVALID, INVALID, INVALID, INVALID,
677 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
679 /* [90] */ INVALID, INVALID, INVALID, INVALID,
680 /* [94] */ INVALID, INVALID, INVALID, INVALID,
681 /* [98] */ INVALID, INVALID, INVALID, INVALID,
682 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
684 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
685 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
686 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
687 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
689 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
690 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
691 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
692 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
694 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID,
695 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID,
696 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
697 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
699 /* [D0] */ INVALID, TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16),
700 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3),
701 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16),
702 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16),
704 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16),
705 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
706 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16),
707 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16),
709 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16),
710 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16),
711 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16),
712 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID,
715 const instable_t dis_opAVX660F[256] = {
716 /* [00] */ INVALID, INVALID, INVALID, INVALID,
717 /* [04] */ INVALID, INVALID, INVALID, INVALID,
718 /* [08] */ INVALID, INVALID, INVALID, INVALID,
719 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
721 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8),
722 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8),
723 /* [18] */ INVALID, INVALID, INVALID, INVALID,
724 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
726 /* [20] */ INVALID, INVALID, INVALID, INVALID,
727 /* [24] */ INVALID, INVALID, INVALID, INVALID,
728 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16),
729 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8),
731 /* [30] */ INVALID, INVALID, INVALID, INVALID,
732 /* [34] */ INVALID, INVALID, INVALID, INVALID,
733 /* [38] */ INVALID, INVALID, INVALID, INVALID,
734 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
736 /* [40] */ INVALID, INVALID, INVALID, INVALID,
737 /* [44] */ INVALID, INVALID, INVALID, INVALID,
738 /* [48] */ INVALID, INVALID, INVALID, INVALID,
739 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
741 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID,
742 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16),
743 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
744 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16),
746 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
747 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16),
748 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
749 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
751 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16),
752 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID,
753 /* [78] */ INVALID, INVALID, INVALID, INVALID,
754 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16),
756 /* [80] */ INVALID, INVALID, INVALID, INVALID,
757 /* [84] */ INVALID, INVALID, INVALID, INVALID,
758 /* [88] */ INVALID, INVALID, INVALID, INVALID,
759 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
761 /* [90] */ INVALID, INVALID, INVALID, INVALID,
762 /* [94] */ INVALID, INVALID, INVALID, INVALID,
763 /* [98] */ INVALID, INVALID, INVALID, INVALID,
764 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
766 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
767 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
768 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
769 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
771 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
772 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
773 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
774 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
776 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID,
777 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID,
778 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
779 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
781 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16),
782 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR),
783 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16),
784 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16),
786 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16),
787 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
788 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16),
789 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16),
791 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16),
792 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX),
793 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16),
794 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID,
798 * Decode table for SIMD instructions with the repnz (0xf2) prefix.
800 const instable_t dis_opSIMDrepnz[256] = {
801 /* [00] */ INVALID, INVALID, INVALID, INVALID,
802 /* [04] */ INVALID, INVALID, INVALID, INVALID,
803 /* [08] */ INVALID, INVALID, INVALID, INVALID,
804 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
806 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), INVALID, INVALID,
807 /* [14] */ INVALID, INVALID, INVALID, INVALID,
808 /* [18] */ INVALID, INVALID, INVALID, INVALID,
809 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
811 /* [20] */ INVALID, INVALID, INVALID, INVALID,
812 /* [24] */ INVALID, INVALID, INVALID, INVALID,
813 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8),
814 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID,
816 /* [30] */ INVALID, INVALID, INVALID, INVALID,
817 /* [34] */ INVALID, INVALID, INVALID, INVALID,
818 /* [38] */ INVALID, INVALID, INVALID, INVALID,
819 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
821 /* [40] */ INVALID, INVALID, INVALID, INVALID,
822 /* [44] */ INVALID, INVALID, INVALID, INVALID,
823 /* [48] */ INVALID, INVALID, INVALID, INVALID,
824 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
826 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID,
827 /* [54] */ INVALID, INVALID, INVALID, INVALID,
828 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID,
829 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8),
831 /* [60] */ INVALID, INVALID, INVALID, INVALID,
832 /* [64] */ INVALID, INVALID, INVALID, INVALID,
833 /* [68] */ INVALID, INVALID, INVALID, INVALID,
834 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
836 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID,
837 /* [74] */ INVALID, INVALID, INVALID, INVALID,
838 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID,
839 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
841 /* [80] */ INVALID, INVALID, INVALID, INVALID,
842 /* [84] */ INVALID, INVALID, INVALID, INVALID,
843 /* [88] */ INVALID, INVALID, INVALID, INVALID,
844 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
846 /* [90] */ INVALID, INVALID, INVALID, INVALID,
847 /* [94] */ INVALID, INVALID, INVALID, INVALID,
848 /* [98] */ INVALID, INVALID, INVALID, INVALID,
849 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
851 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
852 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
853 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
854 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
856 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
857 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
858 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
859 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
861 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID,
862 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
863 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
864 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
866 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
867 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID,
868 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
869 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
871 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
872 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID,
873 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
874 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
876 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
877 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
878 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
879 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
882 const instable_t dis_opAVXF20F[256] = {
883 /* [00] */ INVALID, INVALID, INVALID, INVALID,
884 /* [04] */ INVALID, INVALID, INVALID, INVALID,
885 /* [08] */ INVALID, INVALID, INVALID, INVALID,
886 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
888 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID,
889 /* [14] */ INVALID, INVALID, INVALID, INVALID,
890 /* [18] */ INVALID, INVALID, INVALID, INVALID,
891 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
893 /* [20] */ INVALID, INVALID, INVALID, INVALID,
894 /* [24] */ INVALID, INVALID, INVALID, INVALID,
895 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID,
896 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID,
898 /* [30] */ INVALID, INVALID, INVALID, INVALID,
899 /* [34] */ INVALID, INVALID, INVALID, INVALID,
900 /* [38] */ INVALID, INVALID, INVALID, INVALID,
901 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
903 /* [40] */ INVALID, INVALID, INVALID, INVALID,
904 /* [44] */ INVALID, INVALID, INVALID, INVALID,
905 /* [48] */ INVALID, INVALID, INVALID, INVALID,
906 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
908 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID,
909 /* [54] */ INVALID, INVALID, INVALID, INVALID,
910 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID,
911 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8),
913 /* [60] */ INVALID, INVALID, INVALID, INVALID,
914 /* [64] */ INVALID, INVALID, INVALID, INVALID,
915 /* [68] */ INVALID, INVALID, INVALID, INVALID,
916 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
918 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID,
919 /* [74] */ INVALID, INVALID, INVALID, INVALID,
920 /* [78] */ INVALID, INVALID, INVALID, INVALID,
921 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID,
923 /* [80] */ INVALID, INVALID, INVALID, INVALID,
924 /* [84] */ INVALID, INVALID, INVALID, INVALID,
925 /* [88] */ INVALID, INVALID, INVALID, INVALID,
926 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
928 /* [90] */ INVALID, INVALID, INVALID, INVALID,
929 /* [94] */ INVALID, INVALID, INVALID, INVALID,
930 /* [98] */ INVALID, INVALID, INVALID, INVALID,
931 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
933 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
934 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
935 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
936 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
938 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
939 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
940 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
941 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
943 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID,
944 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
945 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
946 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
948 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID,
949 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
950 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
951 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
953 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
954 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID,
955 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
956 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
958 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID,
959 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
960 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
961 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
965 * Decode table for SIMD instructions with the repz (0xf3) prefix.
967 const instable_t dis_opSIMDrepz[256] = {
968 /* [00] */ INVALID, INVALID, INVALID, INVALID,
969 /* [04] */ INVALID, INVALID, INVALID, INVALID,
970 /* [08] */ INVALID, INVALID, INVALID, INVALID,
971 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
973 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), INVALID, INVALID,
974 /* [14] */ INVALID, INVALID, INVALID, INVALID,
975 /* [18] */ INVALID, INVALID, INVALID, INVALID,
976 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
978 /* [20] */ INVALID, INVALID, INVALID, INVALID,
979 /* [24] */ INVALID, INVALID, INVALID, INVALID,
980 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
981 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID,
983 /* [30] */ INVALID, INVALID, INVALID, INVALID,
984 /* [34] */ INVALID, INVALID, INVALID, INVALID,
985 /* [38] */ INVALID, INVALID, INVALID, INVALID,
986 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
988 /* [40] */ INVALID, INVALID, INVALID, INVALID,
989 /* [44] */ INVALID, INVALID, INVALID, INVALID,
990 /* [48] */ INVALID, INVALID, INVALID, INVALID,
991 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
993 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4),
994 /* [54] */ INVALID, INVALID, INVALID, INVALID,
995 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16),
996 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4),
998 /* [60] */ INVALID, INVALID, INVALID, INVALID,
999 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1000 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1001 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16),
1003 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID,
1004 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1005 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1006 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16),
1008 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1009 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1010 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1011 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1013 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1014 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1015 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1016 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1018 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1019 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1020 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1021 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1023 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1024 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1025 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID,
1026 /* [BC] */ INVALID, TS("lzcnt",MRw), INVALID, INVALID,
1028 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID,
1029 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1030 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1031 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1033 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1034 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID,
1035 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1036 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1038 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1039 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID,
1040 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1041 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1043 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1044 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1045 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1046 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1049 const instable_t dis_opAVXF30F[256] = {
1050 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1051 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1052 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1053 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1055 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID,
1056 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID,
1057 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1058 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1060 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1061 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1062 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID,
1063 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID,
1065 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1066 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1067 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1068 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1070 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1071 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1072 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1073 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1075 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4),
1076 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1077 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16),
1078 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4),
1080 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1081 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1082 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1083 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16),
1085 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID,
1086 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1087 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1088 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16),
1090 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1091 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1092 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1093 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1095 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1096 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1097 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1098 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1100 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1101 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1102 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1103 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1105 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1106 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1107 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1108 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1110 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID,
1111 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1112 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1113 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1115 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1116 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1117 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1118 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1120 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1121 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID,
1122 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1123 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1125 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1126 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1127 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1128 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1131 * The following two tables are used to encode crc32 and movbe
1132 * since they share the same opcodes.
1134 const instable_t dis_op0F38F0[2] = {
1135 /* [00] */ TNS("crc32b",CRC32),
1139 const instable_t dis_op0F38F1[2] = {
1140 /* [00] */ TS("crc32",CRC32),
1144 const instable_t dis_op0F38[256] = {
1145 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
1146 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
1147 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
1148 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1150 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID,
1151 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16),
1152 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1153 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID,
1155 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
1156 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID,
1157 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
1158 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1160 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
1161 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16),
1162 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
1163 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
1165 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID,
1166 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1167 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1168 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1170 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1171 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1172 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1173 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1175 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1176 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1177 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1178 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1180 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1181 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1182 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1183 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1185 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID,
1186 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1187 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1188 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1190 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1191 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1192 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1193 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1195 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1196 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1197 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1198 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1200 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1201 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1202 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1203 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1205 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1206 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1207 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1208 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1210 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1211 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1212 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16),
1213 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
1215 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1216 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1217 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1218 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1219 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID,
1220 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1221 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1222 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1225 const instable_t dis_opAVX660F38[256] = {
1226 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
1227 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
1228 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
1229 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
1231 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16),
1232 /* [14] */ INVALID, INVALID, INVALID, TNSZ("vptest",VEX_RRI,16),
1233 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
1234 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
1236 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
1237 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID,
1238 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
1239 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
1241 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
1242 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),INVALID, TNSZ("vpcmpgtq",VEX_RMrX,16),
1243 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
1244 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
1246 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID,
1247 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1248 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1249 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1251 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1252 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1253 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1254 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1256 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1257 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1258 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1259 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1261 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1262 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1263 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1264 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1266 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1267 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1268 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1269 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1271 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1272 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1273 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1274 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1276 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1277 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1278 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1279 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1281 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1282 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1283 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1284 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1286 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1287 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1288 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1289 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1291 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1292 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1293 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16),
1294 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
1296 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1297 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1298 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1299 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1300 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID,
1301 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1302 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1303 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1306 const instable_t dis_op0F3A[256] = {
1307 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1308 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1309 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
1310 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
1312 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1313 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
1314 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1315 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1317 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
1318 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1319 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1320 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1322 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1323 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1324 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1325 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1327 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
1328 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID,
1329 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1330 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1332 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1333 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1334 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1335 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1337 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
1338 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1339 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1340 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1342 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1343 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1344 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1345 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1347 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1348 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1349 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1350 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1352 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1353 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1354 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1355 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1357 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1358 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1359 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1360 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1362 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1363 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1364 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1365 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1367 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1368 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1369 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1370 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1372 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1373 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1374 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1375 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16),
1377 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1378 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1379 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1380 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1382 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1383 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1384 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1385 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1388 const instable_t dis_opAVX660F3A[256] = {
1389 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1390 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
1391 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
1392 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
1394 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1395 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
1396 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID,
1397 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID,
1399 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
1400 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1401 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1402 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1404 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1405 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1406 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1407 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1409 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
1410 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, INVALID, INVALID,
1411 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16),
1412 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID,
1414 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1415 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1416 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1417 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1419 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
1420 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1421 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1422 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1424 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1425 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1426 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1427 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1429 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1430 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1431 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1432 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1434 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1435 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1436 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1437 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1439 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1440 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1441 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1442 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1444 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1445 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1446 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1447 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1449 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1450 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1451 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1452 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1454 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1455 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1456 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1457 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16),
1459 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1460 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1461 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1462 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1464 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1465 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1466 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1467 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1471 * Decode table for 0x0F opcodes
1474 const instable_t dis_op0F[16][16] = {
1476 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR),
1477 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM),
1478 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM),
1479 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1481 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
1482 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
1483 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID,
1484 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw),
1486 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG),
1487 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID,
1488 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
1489 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
1491 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM),
1492 /* [34] */ TNSx("sysenter",NORM), TNSx("sysexit",NORM), INVALID, INVALID,
1493 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1494 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1496 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR),
1497 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR),
1498 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR),
1499 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR),
1501 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
1502 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16),
1503 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
1504 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16),
1506 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
1507 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8),
1508 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
1509 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8),
1511 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR),
1512 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM),
1513 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID,
1514 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8),
1516 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D),
1517 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D),
1518 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D),
1519 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D),
1521 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb),
1522 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb),
1523 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb),
1524 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb),
1526 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw),
1527 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID,
1528 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw),
1529 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw),
1531 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw),
1532 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ),
1533 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw),
1534 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ),
1536 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM),
1537 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
1538 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1539 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1541 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8),
1542 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3),
1543 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8),
1544 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8),
1546 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8),
1547 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8),
1548 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8),
1549 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8),
1551 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8),
1552 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8),
1553 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8),
1554 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID,
1557 const instable_t dis_opAVX0F[16][16] = {
1559 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1560 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1561 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1562 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1564 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8),
1565 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
1566 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1567 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1569 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1570 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1571 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16),
1572 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4),
1574 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1575 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1576 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1577 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1579 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1580 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1581 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1582 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1584 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
1585 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16),
1586 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
1587 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16),
1589 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1590 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1591 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1592 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1594 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1595 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE),
1596 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1597 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1599 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1600 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1601 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1602 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1604 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1605 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1606 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1607 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1609 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1610 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1611 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1612 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID,
1614 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1615 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1616 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1617 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1619 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID,
1620 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID,
1621 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1622 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1624 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1625 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1626 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1627 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1629 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1630 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1631 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1632 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1634 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1635 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1636 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1637 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1641 * Decode table for 0x80 opcodes
1644 const instable_t dis_op80[8] = {
1646 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw),
1647 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw),
1652 * Decode table for 0x81 opcodes.
1655 const instable_t dis_op81[8] = {
1657 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw),
1658 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw),
1663 * Decode table for 0x82 opcodes.
1666 const instable_t dis_op82[8] = {
1668 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw),
1669 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw),
1672 * Decode table for 0x83 opcodes.
1675 const instable_t dis_op83[8] = {
1677 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw),
1678 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw),
1682 * Decode table for 0xC0 opcodes.
1685 const instable_t dis_opC0[8] = {
1687 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI),
1688 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI),
1692 * Decode table for 0xD0 opcodes.
1695 const instable_t dis_opD0[8] = {
1697 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv),
1698 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv),
1702 * Decode table for 0xC1 opcodes.
1703 * 186 instruction set
1706 const instable_t dis_opC1[8] = {
1708 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI),
1709 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI),
1713 * Decode table for 0xD1 opcodes.
1716 const instable_t dis_opD1[8] = {
1718 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv),
1719 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv),
1724 * Decode table for 0xD2 opcodes.
1727 const instable_t dis_opD2[8] = {
1729 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv),
1730 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv),
1733 * Decode table for 0xD3 opcodes.
1736 const instable_t dis_opD3[8] = {
1738 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv),
1739 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv),
1744 * Decode table for 0xF6 opcodes.
1747 const instable_t dis_opF6[8] = {
1749 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw),
1750 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA),
1755 * Decode table for 0xF7 opcodes.
1758 const instable_t dis_opF7[8] = {
1760 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw),
1761 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA),
1766 * Decode table for 0xFE opcodes.
1769 const instable_t dis_opFE[8] = {
1771 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID,
1772 /* [4] */ INVALID, INVALID, INVALID, INVALID,
1775 * Decode table for 0xFF opcodes.
1778 const instable_t dis_opFF[8] = {
1780 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM),
1781 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID,
1784 /* for 287 instructions, which are a mess to decode */
1786 const instable_t dis_opFP1n2[8][8] = {
1788 /* bit pattern: 1101 1xxx MODxx xR/M */
1789 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M),
1790 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M),
1792 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M),
1793 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2),
1795 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M),
1796 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M),
1798 /* [3,0] */ TNS("fildl",M), INVALID, TNS("fistl",M), TNS("fistpl",M),
1799 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10),
1801 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8),
1802 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8),
1804 /* [5,0] */ TNSZ("fldl",M,8), INVALID, TNSZ("fstl",M,8), TNSZ("fstpl",M,8),
1805 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2),
1807 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2),
1808 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2),
1810 /* [7,0] */ TNSZ("fild",M,2), INVALID, TNSZ("fist",M,2), TNSZ("fistp",M,2),
1811 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8),
1814 const instable_t dis_opFP3[8][8] = {
1816 /* bit pattern: 1101 1xxx 11xx xREG */
1817 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F),
1818 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF),
1820 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F),
1821 /* [1,4] */ INVALID, INVALID, INVALID, INVALID,
1823 /* [2,0] */ INVALID, INVALID, INVALID, INVALID,
1824 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID,
1826 /* [3,0] */ INVALID, INVALID, INVALID, INVALID,
1827 /* [3,4] */ INVALID, INVALID, INVALID, INVALID,
1829 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F),
1830 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF),
1832 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F),
1833 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID,
1835 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM),
1836 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF),
1838 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F),
1839 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID,
1842 const instable_t dis_opFP4[4][8] = {
1844 /* bit pattern: 1101 1001 111x xxxx */
1845 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID,
1846 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID,
1848 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM),
1849 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID,
1851 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM),
1852 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM),
1854 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM),
1855 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM),
1858 const instable_t dis_opFP5[8] = {
1859 /* bit pattern: 1101 1011 111x xxxx */
1860 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM),
1861 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID,
1864 const instable_t dis_opFP6[8] = {
1865 /* bit pattern: 1101 1011 11yy yxxx */
1866 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF),
1867 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID,
1870 const instable_t dis_opFP7[8] = {
1871 /* bit pattern: 1101 1010 11yy yxxx */
1872 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF),
1873 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1877 * Main decode table for the op codes. The first two nibbles
1878 * will be used as an index into the table. If there is a
1879 * a need to further decode an instruction, the array to be
1880 * referenced is indicated with the other two entries being
1884 const instable_t dis_distable[16][16] = {
1886 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw),
1887 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG),
1888 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw),
1889 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F),
1891 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw),
1892 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG),
1893 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw),
1894 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG),
1896 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw),
1897 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM),
1898 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw),
1899 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM),
1901 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw),
1902 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM),
1903 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw),
1904 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM),
1906 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
1907 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
1908 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
1909 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
1911 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
1912 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
1913 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R),
1914 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R),
1916 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR), TNS("arpl",RMw),
1917 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM),
1918 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL),
1919 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4),
1921 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD),
1922 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD),
1923 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD),
1924 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD),
1926 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83),
1927 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw),
1928 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw),
1929 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M),
1931 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA),
1932 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA),
1933 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM),
1934 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM),
1936 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO),
1937 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD),
1938 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD),
1939 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD),
1941 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
1942 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
1943 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR),
1944 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR),
1946 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM),
1947 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw),
1948 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM),
1949 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM),
1951 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3),
1952 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1),
1954 /* 287 instructions. Note that although the indirect field */
1955 /* indicates opFP1n2 for further decoding, this is not necessarily */
1956 /* the case since the opFP arrays are not partitioned according to key1 */
1957 /* and key2. opFP1n2 is given only to indicate that we haven't */
1958 /* finished decoding the instruction. */
1959 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2),
1960 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2),
1962 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD),
1963 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P),
1964 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD),
1965 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V),
1967 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX),
1968 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7),
1969 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM),
1970 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF),
1976 * common functions to decode and disassemble an x86 or amd64 instruction
1980 * These are the individual fields of a REX prefix. Note that a REX
1981 * prefix with none of these set is still needed to:
1982 * - use the MOVSXD (sign extend 32 to 64 bits) instruction
1983 * - access the %sil, %dil, %bpl, %spl registers
1985 #define REX_W 0x08 /* 64 bit operand size when set */
1986 #define REX_R 0x04 /* high order bit extension of ModRM reg field */
1987 #define REX_X 0x02 /* high order bit extension of SIB index field */
1988 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */
1991 * These are the individual fields of a VEX prefix.
1993 #define VEX_R 0x08 /* REX.R in 1's complement form */
1994 #define VEX_X 0x04 /* REX.X in 1's complement form */
1995 #define VEX_B 0x02 /* REX.B in 1's complement form */
1996 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
1998 #define VEX_W 0x08 /* opcode specific, use like REX.W */
1999 #define VEX_m 0x1F /* VEX m-mmmm field */
2000 #define VEX_v 0x78 /* VEX register specifier */
2001 #define VEX_p 0x03 /* VEX pp field, opcode extension */
2003 /* VEX m-mmmm field, only used by three bytes prefix */
2004 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */
2005 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */
2006 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */
2008 /* VEX pp field, providing equivalent functionality of a SIMD prefix */
2009 #define VEX_p_66 0x01
2010 #define VEX_p_F3 0x02
2011 #define VEX_p_F2 0x03
2014 * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
2016 static int isize[] = {1, 2, 4, 4};
2017 static int isize64[] = {1, 2, 4, 8};
2020 * Just a bunch of useful macros.
2022 #define WBIT(x) (x & 0x1) /* to get w bit */
2023 #define REGNO(x) (x & 0x7) /* to get 3 bit register */
2024 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */
2025 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1)
2026 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1)
2028 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */
2030 #define BYTE_OPND 0 /* w-bit value indicating byte register */
2031 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */
2032 #define MM_OPND 2 /* "value" used to indicate a mmx reg */
2033 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */
2034 #define SEG_OPND 4 /* "value" used to indicate a segment reg */
2035 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */
2036 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */
2037 #define TEST_OPND 7 /* "value" used to indicate a test reg */
2038 #define WORD_OPND 8 /* w-bit value indicating word size reg */
2039 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */
2042 * Get the next byte and separate the op code into the high and low nibbles.
2045 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low)
2050 * x86 instructions have a maximum length of 15 bytes. Bail out if
2051 * we try to read more.
2053 if (x->d86_len >= 15)
2054 return (x->d86_error = 1);
2058 byte = x->d86_get_byte(x->d86_data);
2060 return (x->d86_error = 1);
2061 x->d86_bytes[x->d86_len++] = byte;
2062 *low = byte & 0xf; /* ----xxxx low 4 bits */
2063 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */
2068 * Get and decode an SIB (scaled index base) byte
2071 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base)
2078 byte = x->d86_get_byte(x->d86_data);
2083 x->d86_bytes[x->d86_len++] = byte;
2086 *index = (byte >> 3) & 0x7;
2087 *ss = (byte >> 6) & 0x3;
2091 * Get the byte following the op code and separate it into the
2092 * mode, register, and r/m fields.
2095 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m)
2097 if (x->d86_got_modrm == 0) {
2098 if (x->d86_rmindex == -1)
2099 x->d86_rmindex = x->d86_len;
2100 dtrace_get_SIB(x, mode, reg, r_m);
2101 x->d86_got_modrm = 1;
2106 * Adjust register selection based on any REX prefix bits present.
2110 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)
2112 if (reg != NULL && r_m == NULL) {
2113 if (rex_prefix & REX_B)
2116 if (reg != NULL && (REX_R & rex_prefix) != 0)
2118 if (r_m != NULL && (REX_B & rex_prefix) != 0)
2124 * Adjust register selection based on any VEX prefix bits present.
2125 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
2129 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)
2131 if (reg != NULL && r_m == NULL) {
2132 if (!(vex_byte1 & VEX_B))
2135 if (reg != NULL && ((VEX_R & vex_byte1) == 0))
2137 if (r_m != NULL && ((VEX_B & vex_byte1) == 0))
2143 * Get an immediate operand of the given size, with sign extension.
2146 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex)
2152 if (x->d86_numopnds < opindex + 1)
2153 x->d86_numopnds = opindex + 1;
2160 if (x->d86_opnd_size == SIZE16)
2162 else if (x->d86_opnd_size == SIZE32)
2185 x->d86_opnd[opindex].d86_value = 0;
2186 for (i = 0; i < size; ++i) {
2187 byte = x->d86_get_byte(x->d86_data);
2192 x->d86_bytes[x->d86_len++] = byte;
2193 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8);
2195 /* Do sign extension */
2196 if (x->d86_bytes[x->d86_len - 1] & 0x80) {
2197 for (; i < sizeof (uint64_t); i++)
2198 x->d86_opnd[opindex].d86_value |=
2199 (uint64_t)0xff << (i * 8);
2202 x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
2203 x->d86_opnd[opindex].d86_value_size = valsize;
2204 x->d86_imm_bytes += size;
2209 * Get an ip relative operand of the given size, with sign extension.
2212 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex)
2214 dtrace_imm_opnd(x, wbit, size, opindex);
2216 x->d86_opnd[opindex].d86_mode = MODE_IPREL;
2221 * Check to see if there is a segment override prefix pending.
2222 * If so, print it in the current 'operand' location and set
2223 * the override flag back to false.
2227 dtrace_check_override(dis86_t *x, int opindex)
2230 if (x->d86_seg_prefix) {
2231 (void) strlcat(x->d86_opnd[opindex].d86_prefix,
2232 x->d86_seg_prefix, PFIXLEN);
2235 x->d86_seg_prefix = NULL;
2240 * Process a single instruction Register or Memory operand.
2242 * mode = addressing mode from ModRM byte
2243 * r_m = r_m (or reg if mode == 3) field from ModRM byte
2244 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use.
2245 * o = index of operand that we are processing (0, 1 or 2)
2247 * the value of reg or r_m must have already been adjusted for any REX prefix.
2251 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
2253 int have_SIB = 0; /* flag presence of scale-index-byte */
2254 uint_t ss; /* scale-factor from opcode */
2255 uint_t index; /* index register number */
2256 uint_t base; /* base register number */
2257 int dispsize; /* size of displacement in bytes */
2259 char *opnd = x->d86_opnd[opindex].d86_opnd;
2262 if (x->d86_numopnds < opindex + 1)
2263 x->d86_numopnds = opindex + 1;
2269 * first handle a simple register
2271 if (mode == REG_ONLY) {
2275 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN);
2278 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN);
2281 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN);
2284 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN);
2287 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN);
2290 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN);
2293 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN);
2296 if (x->d86_rex_prefix == 0)
2297 (void) strlcat(opnd, dis_REG8[r_m], OPLEN);
2299 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN);
2302 (void) strlcat(opnd, dis_REG16[r_m], OPLEN);
2305 if (x->d86_opnd_size == SIZE16)
2306 (void) strlcat(opnd, dis_REG16[r_m], OPLEN);
2307 else if (x->d86_opnd_size == SIZE32)
2308 (void) strlcat(opnd, dis_REG32[r_m], OPLEN);
2310 (void) strlcat(opnd, dis_REG64[r_m], OPLEN);
2313 #endif /* DIS_TEXT */
2318 * if symbolic representation, skip override prefix, if any
2320 dtrace_check_override(x, opindex);
2323 * Handle 16 bit memory references first, since they decode
2324 * the mode values more simply.
2325 * mode 1 is r_m + 8 bit displacement
2326 * mode 2 is r_m + 16 bit displacement
2327 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp
2329 if (x->d86_addr_size == SIZE16) {
2330 if ((mode == 0 && r_m == 6) || mode == 2)
2331 dtrace_imm_opnd(x, WORD_OPND, 2, opindex);
2333 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex);
2335 if (mode == 0 && r_m == 6)
2336 x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
2338 x->d86_opnd[opindex].d86_mode = MODE_NONE;
2340 x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
2341 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN);
2347 * 32 and 64 bit addressing modes are more complex since they
2348 * can involve an SIB (scaled index and base) byte to decode.
2350 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) {
2352 dtrace_get_SIB(x, &ss, &index, &base);
2355 if (base != 5 || mode != 0)
2356 if (x->d86_rex_prefix & REX_B)
2358 if (x->d86_rex_prefix & REX_X)
2365 * Compute the displacement size and get its bytes
2373 else if ((r_m & 7) == EBP_REGNO ||
2374 (have_SIB && (base & 7) == EBP_REGNO))
2378 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND,
2386 x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
2388 if (have_SIB == 0) {
2389 if (x->d86_mode == SIZE32) {
2391 (void) strlcat(opnd, dis_addr32_mode0[r_m],
2394 (void) strlcat(opnd, dis_addr32_mode12[r_m],
2398 (void) strlcat(opnd, dis_addr64_mode0[r_m],
2401 x->d86_opnd[opindex].d86_mode =
2405 (void) strlcat(opnd, dis_addr64_mode12[r_m],
2410 uint_t need_paren = 0;
2412 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */
2413 regs = (char **)dis_REG32;
2415 regs = (char **)dis_REG64;
2418 * print the base (if any)
2420 if (base == EBP_REGNO && mode == 0) {
2421 if (index != ESP_REGNO) {
2422 (void) strlcat(opnd, "(", OPLEN);
2426 (void) strlcat(opnd, "(", OPLEN);
2427 (void) strlcat(opnd, regs[base], OPLEN);
2432 * print the index (if any)
2434 if (index != ESP_REGNO) {
2435 (void) strlcat(opnd, ",", OPLEN);
2436 (void) strlcat(opnd, regs[index], OPLEN);
2437 (void) strlcat(opnd, dis_scale_factor[ss], OPLEN);
2440 (void) strlcat(opnd, ")", OPLEN);
2446 * Operand sequence for standard instruction involving one register
2447 * and one register/memory operand.
2448 * wbit indicates a byte(0) or opnd_size(1) operation
2449 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
2451 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \
2452 dtrace_get_modrm(x, &mode, ®, &r_m); \
2453 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2454 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2455 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \
2459 * Similar to above, but allows for the two operands to be of different
2460 * classes (ie. wbit).
2461 * wbit is for the r_m operand
2462 * w2 is for the reg operand
2464 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \
2465 dtrace_get_modrm(x, &mode, ®, &r_m); \
2466 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2467 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2468 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \
2472 * Similar, but for 2 operands plus an immediate.
2473 * vbit indicates direction
2474 * 0 for "opcode imm, r, r_m" or
2475 * 1 for "opcode imm, r_m, r"
2477 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \
2478 dtrace_get_modrm(x, &mode, ®, &r_m); \
2479 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2480 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \
2481 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \
2482 dtrace_imm_opnd(x, wbit, immsize, 0); \
2486 * Similar, but for 2 operands plus two immediates.
2488 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \
2489 dtrace_get_modrm(x, &mode, ®, &r_m); \
2490 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2491 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2492 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \
2493 dtrace_imm_opnd(x, wbit, immsize, 1); \
2494 dtrace_imm_opnd(x, wbit, immsize, 0); \
2498 * 1 operands plus two immediates.
2500 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \
2501 dtrace_get_modrm(x, &mode, ®, &r_m); \
2502 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2503 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2504 dtrace_imm_opnd(x, wbit, immsize, 1); \
2505 dtrace_imm_opnd(x, wbit, immsize, 0); \
2509 * Dissassemble a single x86 or amd64 instruction.
2511 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64)
2512 * for interpreting instructions.
2514 * returns non-zero for bad opcode
2517 dtrace_disx86(dis86_t *x, uint_t cpu_mode)
2519 instable_t *dp; /* decode table being used */
2525 #define NOMEM (nomem = 1)
2527 #define NOMEM /* nothing */
2529 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */
2530 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */
2531 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */
2532 uint_t w2; /* wbit value for second operand */
2534 uint_t mode = 0; /* mode value from ModRM byte */
2535 uint_t reg; /* reg value from ModRM byte */
2536 uint_t r_m; /* r_m value from ModRM byte */
2538 uint_t opcode1; /* high nibble of 1st byte */
2539 uint_t opcode2; /* low nibble of 1st byte */
2540 uint_t opcode3; /* extra opcode bits usually from ModRM byte */
2541 uint_t opcode4; /* high nibble of 2nd byte */
2542 uint_t opcode5; /* low nibble of 2nd byte */
2543 uint_t opcode6; /* high nibble of 3rd byte */
2544 uint_t opcode7; /* low nibble of 3rd byte */
2545 uint_t opcode_bytes = 1;
2548 * legacy prefixes come in 5 flavors, you should have only one of each
2550 uint_t opnd_size_prefix = 0;
2551 uint_t addr_size_prefix = 0;
2552 uint_t segment_prefix = 0;
2553 uint_t lock_prefix = 0;
2554 uint_t rep_prefix = 0;
2555 uint_t rex_prefix = 0; /* amd64 register extension prefix */
2558 * Intel VEX instruction encoding prefix and fields
2561 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
2562 uint_t vex_prefix = 0;
2565 * VEX prefix byte 1, includes vex.r, vex.x and vex.b
2566 * (for 3 bytes prefix)
2568 uint_t vex_byte1 = 0;
2571 * For 32-bit mode, it should prefetch the next byte to
2572 * distinguish between AVX and les/lds
2574 uint_t vex_prefetch = 0;
2591 x->d86_rmindex = -1;
2594 x->d86_numopnds = 0;
2595 x->d86_seg_prefix = NULL;
2597 for (i = 0; i < 4; ++i) {
2598 x->d86_opnd[i].d86_opnd[0] = 0;
2599 x->d86_opnd[i].d86_prefix[0] = 0;
2600 x->d86_opnd[i].d86_value_size = 0;
2601 x->d86_opnd[i].d86_value = 0;
2602 x->d86_opnd[i].d86_mode = MODE_NONE;
2605 x->d86_rex_prefix = 0;
2606 x->d86_got_modrm = 0;
2609 if (cpu_mode == SIZE16) {
2612 } else if (cpu_mode == SIZE32) {
2621 * Get one opcode byte and check for zero padding that follows
2624 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
2627 if (opcode1 == 0 && opcode2 == 0 &&
2628 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) {
2630 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN);
2636 * Gather up legacy x86 prefix bytes.
2639 uint_t *which_prefix = NULL;
2641 dp = (instable_t *)&dis_distable[opcode1][opcode2];
2643 switch (dp->it_adrmode) {
2645 which_prefix = &rep_prefix;
2648 which_prefix = &lock_prefix;
2651 which_prefix = &segment_prefix;
2653 x->d86_seg_prefix = (char *)dp->it_name;
2655 if (dp->it_invalid64 && cpu_mode == SIZE64)
2659 which_prefix = &addr_size_prefix;
2662 which_prefix = &opnd_size_prefix;
2665 if (which_prefix == NULL)
2667 *which_prefix = (opcode1 << 4) | opcode2;
2668 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
2673 * Handle amd64 mode PREFIX values.
2674 * Some of the segment prefixes are no-ops. (only FS/GS actually work)
2675 * We might have a REX prefix (opcodes 0x40-0x4f)
2677 if (cpu_mode == SIZE64) {
2678 if (segment_prefix != 0x64 && segment_prefix != 0x65)
2681 if (opcode1 == 0x4) {
2682 rex_prefix = (opcode1 << 4) | opcode2;
2683 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
2685 dp = (instable_t *)&dis_distable[opcode1][opcode2];
2686 } else if (opcode1 == 0xC &&
2687 (opcode2 == 0x4 || opcode2 == 0x5)) {
2688 /* AVX instructions */
2689 vex_prefix = (opcode1 << 4) | opcode2;
2690 x->d86_rex_prefix = 0x40;
2692 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) {
2693 /* LDS, LES or AVX */
2694 dtrace_get_modrm(x, &mode, ®, &r_m);
2697 if (mode == REG_ONLY) {
2699 vex_prefix = (opcode1 << 4) | opcode2;
2700 x->d86_rex_prefix = 0x40;
2701 opcode3 = (((mode << 3) | reg)>>1) & 0x0F;
2702 opcode4 = ((reg << 3) | r_m) & 0x0F;
2706 if (vex_prefix == VEX_2bytes) {
2707 if (!vex_prefetch) {
2708 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
2711 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3;
2712 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2;
2713 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3;
2714 vex_p = opcode4 & VEX_p;
2716 * The vex.x and vex.b bits are not defined in two bytes
2717 * mode vex prefix, their default values are 1
2719 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B;
2722 x->d86_rex_prefix |= REX_R;
2724 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
2730 &dis_opAVX660F[(opcode1 << 4) | opcode2];
2734 &dis_opAVXF30F[(opcode1 << 4) | opcode2];
2738 &dis_opAVXF20F [(opcode1 << 4) | opcode2];
2742 &dis_opAVX0F[opcode1][opcode2];
2746 } else if (vex_prefix == VEX_3bytes) {
2747 if (!vex_prefetch) {
2748 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
2751 vex_R = (opcode3 & VEX_R) >> 3;
2752 vex_X = (opcode3 & VEX_X) >> 2;
2753 vex_B = (opcode3 & VEX_B) >> 1;
2754 vex_m = (((opcode3 << 4) | opcode4) & VEX_m);
2755 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B);
2758 x->d86_rex_prefix |= REX_R;
2760 x->d86_rex_prefix |= REX_X;
2762 x->d86_rex_prefix |= REX_B;
2764 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0)
2766 vex_W = (opcode5 & VEX_W) >> 3;
2767 vex_L = (opcode6 & VEX_L) >> 2;
2768 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3;
2769 vex_p = opcode6 & VEX_p;
2772 x->d86_rex_prefix |= REX_W;
2774 /* Only these three vex_m values valid; others are reserved */
2775 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) &&
2776 (vex_m != VEX_m_0F3A))
2779 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
2784 if (vex_m == VEX_m_0F) {
2787 [(opcode1 << 4) | opcode2];
2788 } else if (vex_m == VEX_m_0F38) {
2791 [(opcode1 << 4) | opcode2];
2792 } else if (vex_m == VEX_m_0F3A) {
2795 [(opcode1 << 4) | opcode2];
2801 if (vex_m == VEX_m_0F) {
2804 [(opcode1 << 4) | opcode2];
2810 if (vex_m == VEX_m_0F) {
2813 [(opcode1 << 4) | opcode2];
2820 &dis_opAVX0F[opcode1][opcode2];
2832 * Deal with selection of operand and address size now.
2833 * Note that the REX.W bit being set causes opnd_size_prefix to be
2836 if (cpu_mode == SIZE64) {
2837 if ((rex_prefix & REX_W) || vex_W)
2839 else if (opnd_size_prefix)
2842 if (addr_size_prefix)
2844 } else if (cpu_mode == SIZE32) {
2845 if (opnd_size_prefix)
2847 if (addr_size_prefix)
2850 if (opnd_size_prefix)
2852 if (addr_size_prefix)
2856 * The pause instruction - a repz'd nop. This doesn't fit
2857 * with any of the other prefix goop added for SSE, so we'll
2858 * special-case it here.
2860 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) {
2862 dp = (instable_t *)&dis_opPause;
2866 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
2867 * byte so we may need to perform a table indirection.
2869 if (dp->it_indirect == (instable_t *)dis_op0F) {
2870 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0)
2873 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) {
2876 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
2879 subcode = ((opcode6 & 0x3) << 1) |
2880 ((opcode7 & 0x8) >> 3);
2881 dp = (instable_t *)&dis_op0F7123[opcode5][subcode];
2882 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) {
2883 dp = (instable_t *)&dis_op0FC8[0];
2884 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) {
2886 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
2888 if (opnd_size == SIZE16)
2891 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7];
2893 if (strcmp(dp->it_name, "INVALID") == 0)
2896 switch (dp->it_adrmode) {
2900 if (opnd_size_prefix == 0) {
2905 if (opnd_size_prefix == 0) {
2906 /* SSSE3 MMX instructions */
2909 dp->it_adrmode = MMOPM_66o;
2918 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) {
2920 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
2922 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7];
2925 * Both crc32 and movbe have the same 3rd opcode
2926 * byte of either 0xF0 or 0xF1, so we use another
2927 * indirection to distinguish between the two.
2929 if (dp->it_indirect == (instable_t *)dis_op0F38F0 ||
2930 dp->it_indirect == (instable_t *)dis_op0F38F1) {
2932 dp = dp->it_indirect;
2933 if (rep_prefix != 0xF2) {
2939 if (strcmp(dp->it_name, "INVALID") == 0)
2942 switch (dp->it_adrmode) {
2946 if (opnd_size_prefix == 0) {
2951 if (opnd_size_prefix == 0) {
2952 /* SSSE3 MMX instructions */
2955 dp->it_adrmode = MM;
2962 if (rep_prefix != 0xF2) {
2968 if (rep_prefix != 0x0) {
2976 dp = (instable_t *)&dis_op0F[opcode4][opcode5];
2981 * If still not at a TERM decode entry, then a ModRM byte
2982 * exists and its fields further decode the instruction.
2984 x->d86_got_modrm = 0;
2985 if (dp->it_indirect != TERM) {
2986 dtrace_get_modrm(x, &mode, &opcode3, &r_m);
2992 * decode 287 instructions (D8-DF) from opcodeN
2994 if (opcode1 == 0xD && opcode2 >= 0x8) {
2995 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4)
2996 dp = (instable_t *)&dis_opFP5[r_m];
2997 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4)
2998 dp = (instable_t *)&dis_opFP7[opcode3];
2999 else if (opcode2 == 0xB && mode == 0x3)
3000 dp = (instable_t *)&dis_opFP6[opcode3];
3001 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4)
3002 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m];
3003 else if (mode == 0x3)
3005 &dis_opFP3[opcode2 - 8][opcode3];
3008 &dis_opFP1n2[opcode2 - 8][opcode3];
3010 dp = (instable_t *)dp->it_indirect + opcode3;
3015 * In amd64 bit mode, ARPL opcode is changed to MOVSXD
3016 * (sign extend 32bit to 64 bit)
3018 if ((vex_prefix == 0) && cpu_mode == SIZE64 &&
3019 opcode1 == 0x6 && opcode2 == 0x3)
3020 dp = (instable_t *)&dis_opMOVSLD;
3023 * at this point we should have a correct (or invalid) opcode
3025 if (cpu_mode == SIZE64 && dp->it_invalid64 ||
3026 cpu_mode != SIZE64 && dp->it_invalid32)
3028 if (dp->it_indirect != TERM)
3032 * deal with MMX/SSE opcodes which are changed by prefixes
3034 switch (dp->it_adrmode) {
3052 * This is horrible. Some SIMD instructions take the
3053 * form 0x0F 0x?? ..., which is easily decoded using the
3054 * existing tables. Other SIMD instructions use various
3055 * prefix bytes to overload existing instructions. For
3056 * Example, addps is F0, 58, whereas addss is F3 (repz),
3057 * F0, 58. Presumably someone got a raise for this.
3059 * If we see one of the instructions which can be
3060 * modified in this way (if we've got one of the SIMDO*
3061 * address modes), we'll check to see if the last prefix
3062 * was a repz. If it was, we strip the prefix from the
3063 * mnemonic, and we indirect using the dis_opSIMDrepz
3068 * Calculate our offset in dis_op0F
3070 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F))
3073 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
3074 sizeof (instable_t);
3077 * Rewrite if this instruction used one of the magic prefixes.
3080 if (rep_prefix == 0xf2)
3081 dp = (instable_t *)&dis_opSIMDrepnz[off];
3083 dp = (instable_t *)&dis_opSIMDrepz[off];
3085 } else if (opnd_size_prefix) {
3086 dp = (instable_t *)&dis_opSIMDdata16[off];
3087 opnd_size_prefix = 0;
3088 if (opnd_size == SIZE16)
3095 * More horribleness: the group 9 (0xF0 0xC7) instructions are
3096 * allowed an optional prefix of 0x66 or 0xF3. This is similar
3097 * to the SIMD business described above, but with a different
3098 * addressing mode (and an indirect table), so we deal with it
3099 * separately (if similarly).
3101 * Intel further complicated this with the release of Ivy Bridge
3102 * where they overloaded these instructions based on the ModR/M
3103 * bytes. The VMX instructions have a mode of 0 since they are
3104 * memory instructions but rdrand instructions have a mode of
3105 * 0b11 (REG_ONLY) because they only operate on registers. While
3106 * there are different prefix formats, for now it is sufficient
3107 * to use a single different table.
3111 * Calculate our offset in dis_op0FC7 (the group 9 table)
3113 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7))
3116 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) /
3117 sizeof (instable_t);
3120 * If we have a mode of 0b11 then we have to rewrite this.
3122 dtrace_get_modrm(x, &mode, ®, &r_m);
3123 if (mode == REG_ONLY) {
3124 dp = (instable_t *)&dis_op0FC7m3[off];
3129 * Rewrite if this instruction used one of the magic prefixes.
3132 if (rep_prefix == 0xf3)
3133 dp = (instable_t *)&dis_opF30FC7[off];
3137 } else if (opnd_size_prefix) {
3138 dp = (instable_t *)&dis_op660FC7[off];
3139 opnd_size_prefix = 0;
3140 if (opnd_size == SIZE16)
3148 * As with the "normal" SIMD instructions, the MMX
3149 * shuffle instructions are overloaded. These
3150 * instructions, however, are special in that they use
3151 * an extra byte, and thus an extra table. As of this
3152 * writing, they only use the opnd_size prefix.
3156 * Calculate our offset in dis_op0F7123
3158 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 >
3159 sizeof (dis_op0F7123))
3162 if (opnd_size_prefix) {
3163 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) /
3164 sizeof (instable_t);
3165 dp = (instable_t *)&dis_opSIMD7123[off];
3166 opnd_size_prefix = 0;
3167 if (opnd_size == SIZE16)
3173 if (rep_prefix == 0xf3) {
3176 * Calculate our offset in dis_op0F
3178 if ((uintptr_t)dp - (uintptr_t)dis_op0F
3179 > sizeof (dis_op0F))
3182 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
3183 sizeof (instable_t);
3185 dp = (instable_t *)&dis_opSIMDrepz[off];
3195 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64.
3197 if (cpu_mode == SIZE64)
3198 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop))
3203 * At this point most instructions can format the opcode mnemonic
3204 * including the prefixes.
3207 (void) strlcat(x->d86_mnem, "lock ", OPLEN);
3209 if (rep_prefix == 0xf2)
3210 (void) strlcat(x->d86_mnem, "repnz ", OPLEN);
3211 else if (rep_prefix == 0xf3)
3212 (void) strlcat(x->d86_mnem, "repz ", OPLEN);
3214 if (cpu_mode == SIZE64 && addr_size_prefix)
3215 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN);
3217 if (dp->it_adrmode != CBW &&
3218 dp->it_adrmode != CWD &&
3219 dp->it_adrmode != XMMSFNC) {
3220 if (strcmp(dp->it_name, "INVALID") == 0)
3222 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN);
3223 if (dp->it_suffix) {
3224 char *types[] = {"", "w", "l", "q"};
3225 if (opcode_bytes == 2 && opcode4 == 4) {
3226 /* It's a cmovx.yy. Replace the suffix x */
3227 for (i = 5; i < OPLEN; i++) {
3228 if (x->d86_mnem[i] == '.')
3231 x->d86_mnem[i - 1] = *types[opnd_size];
3232 } else if ((opnd_size == 2) && (opcode_bytes == 3) &&
3233 ((opcode6 == 1 && opcode7 == 6) ||
3234 (opcode6 == 2 && opcode7 == 2))) {
3236 * To handle PINSRD and PEXTRD
3238 (void) strlcat(x->d86_mnem, "d", OPLEN);
3240 (void) strlcat(x->d86_mnem, types[opnd_size],
3248 * Process operands based on the addressing modes.
3250 x->d86_mode = cpu_mode;
3252 * In vex mode the rex_prefix has no meaning
3255 x->d86_rex_prefix = rex_prefix;
3256 x->d86_opnd_size = opnd_size;
3257 x->d86_addr_size = addr_size;
3258 vbit = 0; /* initialize for mem/reg -> reg */
3259 switch (dp->it_adrmode) {
3261 * amd64 instruction to sign extend 32 bit reg/mem operands
3262 * into 64 bit register values
3266 if (rex_prefix == 0)
3267 (void) strncpy(x->d86_mnem, "movzld", OPLEN);
3269 dtrace_get_modrm(x, &mode, ®, &r_m);
3270 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3271 x->d86_opnd_size = SIZE64;
3272 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3273 x->d86_opnd_size = opnd_size = SIZE32;
3275 dtrace_get_operand(x, mode, r_m, wbit, 0);
3279 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF)
3280 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7)
3281 * wbit lives in 2nd byte, note that operands
3282 * are different sized
3285 if (rex_prefix & REX_W) {
3286 /* target register size = 64 bit */
3287 x->d86_mnem[5] = 'q';
3289 dtrace_get_modrm(x, &mode, ®, &r_m);
3290 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3291 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3292 x->d86_opnd_size = opnd_size = SIZE16;
3293 wbit = WBIT(opcode5);
3294 dtrace_get_operand(x, mode, r_m, wbit, 0);
3298 if (rex_prefix & REX_W)
3300 x->d86_opnd_size = opnd_size;
3302 dtrace_get_modrm(x, &mode, ®, &r_m);
3303 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3304 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3305 wbit = WBIT(opcode7);
3306 if (opnd_size_prefix)
3307 x->d86_opnd_size = opnd_size = SIZE16;
3308 dtrace_get_operand(x, mode, r_m, wbit, 0);
3312 if (rex_prefix & REX_W)
3314 x->d86_opnd_size = opnd_size;
3316 dtrace_get_modrm(x, &mode, ®, &r_m);
3317 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3318 wbit = WBIT(opcode7);
3319 if (opnd_size_prefix)
3320 x->d86_opnd_size = opnd_size = SIZE16;
3323 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
3324 dtrace_get_operand(x, mode, r_m, wbit, 1);
3327 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3328 dtrace_get_operand(x, mode, r_m, wbit, 0);
3333 * imul instruction, with either 8-bit or longer immediate
3334 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
3338 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND,
3339 OPSIZE(opnd_size, opcode2 == 0x9), 1);
3342 /* memory or register operand to register, with 'w' bit */
3344 wbit = WBIT(opcode2);
3345 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
3348 /* register to memory or register operand, with 'w' bit */
3349 /* arpl happens to fit here also because it is odd */
3351 if (opcode_bytes == 2)
3352 wbit = WBIT(opcode5);
3354 wbit = WBIT(opcode2);
3355 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3358 /* xaddb instruction */
3361 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3364 /* MMX register to memory or register operand */
3368 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
3372 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
3375 /* MMX register to memory */
3377 dtrace_get_modrm(x, &mode, ®, &r_m);
3378 if (mode == REG_ONLY)
3381 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
3384 /* Double shift. Has immediate operand specifying the shift. */
3387 dtrace_get_modrm(x, &mode, ®, &r_m);
3388 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3389 dtrace_get_operand(x, mode, r_m, wbit, 2);
3390 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3391 dtrace_imm_opnd(x, wbit, 1, 0);
3395 * Double shift. With no immediate operand, specifies using %cl.
3399 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3402 /* immediate to memory or register operand */
3404 wbit = WBIT(opcode2);
3405 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3406 dtrace_get_operand(x, mode, r_m, wbit, 1);
3408 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
3410 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0);
3413 /* immediate to memory or register operand with the */
3414 /* 'w' bit present */
3416 wbit = WBIT(opcode2);
3417 dtrace_get_modrm(x, &mode, ®, &r_m);
3418 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3419 dtrace_get_operand(x, mode, r_m, wbit, 1);
3420 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
3423 /* immediate to register with register in low 3 bits */
3426 /* w-bit here (with regs) is bit 3 */
3427 wbit = opcode2 >>3 & 0x1;
3428 reg = REGNO(opcode2);
3429 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
3432 dtrace_get_operand(x, mode, r_m, wbit, 1);
3433 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0);
3436 /* MMX immediate shift of register */
3440 goto mm_shift; /* in next case */
3442 /* SIMD immediate shift of register */
3446 reg = REGNO(opcode7);
3447 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
3448 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
3449 dtrace_imm_opnd(x, wbit, 1, 0);
3453 /* accumulator to memory operand */
3458 /* memory operand to accumulator */
3460 wbit = WBIT(opcode2);
3461 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit);
3462 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit);
3464 x->d86_opnd[vbit].d86_mode = MODE_OFFSET;
3469 /* segment register to memory or register operand */
3474 /* memory or register operand to segment register */
3476 dtrace_get_modrm(x, &mode, ®, &r_m);
3477 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3478 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit);
3479 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit);
3483 * rotate or shift instructions, which may shift by 1 or
3484 * consult the cl register, depending on the 'v' bit
3487 vbit = VBIT(opcode2);
3488 wbit = WBIT(opcode2);
3489 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3490 dtrace_get_operand(x, mode, r_m, wbit, 1);
3493 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN);
3495 x->d86_opnd[0].d86_mode = MODE_SIGNED;
3496 x->d86_opnd[0].d86_value_size = 1;
3497 x->d86_opnd[0].d86_value = 1;
3502 * immediate rotate or shift instructions
3505 wbit = WBIT(opcode2);
3507 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3508 dtrace_get_operand(x, mode, r_m, wbit, 1);
3509 dtrace_imm_opnd(x, wbit, 1, 0);
3512 /* bit test instructions */
3515 goto normal_imm_mem;
3517 /* single memory or register operand with 'w' bit present */
3519 wbit = WBIT(opcode2);
3521 dtrace_get_modrm(x, &mode, ®, &r_m);
3522 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3523 dtrace_get_operand(x, mode, r_m, wbit, 0);
3527 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
3529 (void) strncpy(x->d86_mnem, "swapgs", OPLEN);
3533 } else if (mode == 3 && r_m == 1) {
3535 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN);
3543 /* prefetch instruction - memory operand, but no memory acess */
3548 /* single memory or register operand */
3554 /* single memory or register byte operand */
3569 vminstr = "vmlaunch";
3572 vminstr = "vmresume";
3581 (void) strncpy(x->d86_mnem, vminstr, OPLEN);
3583 if (r_m < 1 || r_m > 4)
3623 (void) strncpy(x->d86_mnem, vinstr, OPLEN);
3633 (void) strncpy(x->d86_mnem, "monitor", OPLEN);
3637 } else if (r_m == 1) {
3639 (void) strncpy(x->d86_mnem, "mwait", OPLEN);
3652 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN);
3656 } else if (r_m == 1) {
3658 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN);
3669 /* Similar to M, but only memory (no direct registers) */
3671 dtrace_get_modrm(x, &mode, ®, &r_m);
3674 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3675 dtrace_get_operand(x, mode, r_m, wbit, 0);
3678 /* move special register to register or reverse if vbit */
3686 wbit = CONTROL_OPND;
3704 dtrace_get_modrm(x, &mode, ®, &r_m);
3705 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3706 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit);
3707 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit);
3712 * single register operand with register in the low 3
3716 if (opcode_bytes == 2)
3717 reg = REGNO(opcode5);
3719 reg = REGNO(opcode2);
3720 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
3721 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
3726 * register to accumulator with register in the low 3
3727 * bits of op code, xchg instructions
3731 reg = REGNO(opcode2);
3732 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
3733 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
3734 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1);
3738 * single segment register operand, with register in
3739 * bits 3-4 of op code byte
3743 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3;
3744 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
3748 * single segment register operand, with register in
3749 * bits 3-5 of op code
3753 /* long seg reg from opcode */
3754 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7;
3755 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
3758 /* memory or register operand to register */
3761 x->d86_got_modrm = 1;
3763 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
3769 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3772 /* MMX/SIMD-Int memory or mm reg to mm reg */
3776 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
3780 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
3785 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
3789 dtrace_get_modrm(x, &mode, ®, &r_m);
3790 if (mode != REG_ONLY)
3793 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3794 dtrace_get_operand(x, mode, r_m, wbit, 0);
3795 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1);
3796 mode = 0; /* change for memory access size... */
3799 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */
3806 dtrace_get_modrm(x, &mode, ®, &r_m);
3807 if (mode != REG_ONLY)
3810 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1,
3816 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND,
3820 /* MMX/SIMD-Int predicated r32/mem to mm reg */
3830 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1);
3833 /* MMX/SIMD-Int predicated mm/mem to mm reg */
3836 wbit = w2 = MM_OPND;
3839 /* MMX/SIMD-Int mm reg to r32 */
3842 dtrace_get_modrm(x, &mode, ®, &r_m);
3843 if (mode != REG_ONLY)
3846 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
3849 /* SIMD memory or xmm reg operand to xmm reg */
3856 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
3858 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY)
3863 * movlps and movhlps share opcodes. They differ in the
3864 * addressing modes allowed for their operands.
3865 * movhps and movlhps behave similarly.
3867 if (mode == REG_ONLY) {
3868 if (strcmp(dp->it_name, "movlps") == 0)
3869 (void) strncpy(x->d86_mnem, "movhlps", OPLEN);
3870 else if (strcmp(dp->it_name, "movhps") == 0)
3871 (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
3874 if (dp->it_adrmode == XMMXIMPL)
3875 mode = 0; /* change for memory access size... */
3878 /* SIMD xmm reg to memory or xmm reg */
3883 dtrace_get_modrm(x, &mode, ®, &r_m);
3885 if ((strcmp(dp->it_name, "movlps") == 0 ||
3886 strcmp(dp->it_name, "movhps") == 0 ||
3887 strcmp(dp->it_name, "movntps") == 0) &&
3892 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
3895 /* SIMD memory to xmm reg */
3900 dtrace_get_modrm(x, &mode, ®, &r_m);
3902 if (mode == REG_ONLY) {
3903 if (strcmp(dp->it_name, "movhps") == 0)
3904 (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
3909 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
3912 /* SIMD memory or r32 to xmm reg */
3915 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
3920 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
3923 /* SIMD memory or mm reg to xmm reg */
3925 /* SIMD mm to xmm */
3928 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
3931 /* SIMD memory or xmm reg to mm reg */
3936 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
3940 /* SIMD memory or xmm reg to r32 */
3943 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
3946 /* SIMD xmm to r32 */
3949 dtrace_get_modrm(x, &mode, ®, &r_m);
3950 if (mode != REG_ONLY)
3952 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3953 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
3954 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3958 /* SIMD predicated memory or xmm reg with/to xmm reg */
3964 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1,
3969 * cmpps and cmpss vary their instruction name based
3970 * on the value of imm8. Other XMMP instructions,
3971 * such as shufps, require explicit specification of
3974 if (dp->it_name[0] == 'c' &&
3975 dp->it_name[1] == 'm' &&
3976 dp->it_name[2] == 'p' &&
3977 strlen(dp->it_name) == 5) {
3978 uchar_t pred = x->d86_opnd[0].d86_value & 0xff;
3980 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *)))
3983 (void) strncpy(x->d86_mnem, "cmp", OPLEN);
3984 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred],
3986 (void) strlcat(x->d86_mnem,
3987 dp->it_name + strlen(dp->it_name) - 2,
3989 x->d86_opnd[0] = x->d86_opnd[1];
3990 x->d86_opnd[1] = x->d86_opnd[2];
3991 x->d86_numopnds = 2;
3997 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND,
4003 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1);
4007 /* immediate operand to accumulator */
4009 wbit = WBIT(opcode2);
4010 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
4011 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
4015 /* memory or register operand to accumulator */
4017 wbit = WBIT(opcode2);
4018 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4019 dtrace_get_operand(x, mode, r_m, wbit, 0);
4022 /* si register to di register used to reference memory */
4025 dtrace_check_override(x, 0);
4026 x->d86_numopnds = 2;
4027 if (addr_size == SIZE64) {
4028 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
4030 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
4032 } else if (addr_size == SIZE32) {
4033 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
4035 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
4038 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
4040 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
4047 /* accumulator to di register */
4049 wbit = WBIT(opcode2);
4051 dtrace_check_override(x, 1);
4052 x->d86_numopnds = 2;
4053 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0);
4054 if (addr_size == SIZE64)
4055 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
4057 else if (addr_size == SIZE32)
4058 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
4061 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
4066 /* si register to accumulator */
4068 wbit = WBIT(opcode2);
4070 dtrace_check_override(x, 0);
4071 x->d86_numopnds = 2;
4072 if (addr_size == SIZE64)
4073 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
4075 else if (addr_size == SIZE32)
4076 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
4079 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
4081 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
4086 * single operand, a 16/32 bit displacement
4090 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
4094 /* jmp/call indirect to memory or register operand */
4097 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN);
4099 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4100 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4105 * for long jumps and long calls -- a new code segment
4106 * register and an offset in IP -- stored in object
4107 * code in reverse order. Note - not valid in amd64
4110 dtrace_check_override(x, 1);
4112 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1);
4114 x->d86_opnd[1].d86_mode = MODE_SIGNED;
4116 /* will now get segment operand */
4117 dtrace_imm_opnd(x, wbit, 2, 0);
4121 * jmp/call. single operand, 8 bit displacement.
4122 * added to current EIP in 'compofff'
4125 dtrace_disp_opnd(x, BYTE_OPND, 1, 0);
4129 /* single 32/16 bit immediate operand */
4132 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
4135 /* single 8 bit immediate operand */
4138 dtrace_imm_opnd(x, wbit, 1, 0);
4143 dtrace_imm_opnd(x, wbit, 2, 0);
4144 dtrace_imm_opnd(x, wbit, 1, 1);
4145 switch (opnd_size) {
4147 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8;
4150 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4;
4153 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2;
4159 /* 16-bit immediate operand */
4162 dtrace_imm_opnd(x, wbit, 2, 0);
4165 /* single 8 bit port operand */
4167 dtrace_check_override(x, 0);
4168 dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
4172 /* single operand, dx register (variable port instruction) */
4174 x->d86_numopnds = 1;
4175 dtrace_check_override(x, 0);
4177 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN);
4183 * The int instruction, which has two forms:
4184 * int 3 (breakpoint) or
4185 * int n, where n is indicated in the subsequent
4186 * byte (format Ib). The int 3 instruction (opcode 0xCC),
4187 * where, although the 3 looks like an operand,
4188 * it is implied by the opcode. It must be converted
4189 * to the correct base and output.
4193 x->d86_numopnds = 1;
4194 x->d86_opnd[0].d86_mode = MODE_SIGNED;
4195 x->d86_opnd[0].d86_value_size = 1;
4196 x->d86_opnd[0].d86_value = 3;
4201 /* single 8 bit immediate operand */
4203 dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
4207 /* an unused byte must be discarded */
4209 if (x->d86_get_byte(x->d86_data) < 0)
4217 if (opnd_size == SIZE16)
4218 (void) strlcat(x->d86_mnem, "cbtw", OPLEN);
4219 else if (opnd_size == SIZE32)
4220 (void) strlcat(x->d86_mnem, "cwtl", OPLEN);
4222 (void) strlcat(x->d86_mnem, "cltq", OPLEN);
4230 if (opnd_size == SIZE16)
4231 (void) strlcat(x->d86_mnem, "cwtd", OPLEN);
4232 else if (opnd_size == SIZE32)
4233 (void) strlcat(x->d86_mnem, "cltd", OPLEN);
4235 (void) strlcat(x->d86_mnem, "cqtd", OPLEN);
4243 * sfence is sfence if mode is REG_ONLY. If mode isn't
4244 * REG_ONLY, mnemonic should be 'clflush'.
4246 dtrace_get_modrm(x, &mode, ®, &r_m);
4248 /* sfence doesn't take operands */
4250 if (mode == REG_ONLY) {
4251 (void) strlcat(x->d86_mnem, "sfence", OPLEN);
4253 (void) strlcat(x->d86_mnem, "clflush", OPLEN);
4254 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
4255 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
4259 if (mode != REG_ONLY) {
4260 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
4261 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4268 * no disassembly, the mnemonic was all there was so go on
4271 if (dp->it_invalid32 && cpu_mode != SIZE64)
4280 * XRSTOR and LFENCE share the same opcode but differ in mode
4282 dtrace_get_modrm(x, &mode, ®, &r_m);
4284 if (mode == REG_ONLY) {
4286 * Only the following exact byte sequences are allowed:
4291 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 &&
4292 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0)
4296 (void) strncpy(x->d86_mnem, "xrstor", OPLEN);
4298 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
4299 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
4306 x->d86_numopnds = 1;
4307 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN);
4308 x->d86_opnd[0].d86_opnd[4] = r_m + '0';
4313 /* float reg to float reg, with ret bit present */
4315 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */
4317 case FFC: /* case for vbit always = 0 */
4319 x->d86_numopnds = 2;
4320 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN);
4321 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN);
4322 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0';
4327 /* AVX instructions */
4329 /* op(ModR/M.r/m) */
4330 x->d86_numopnds = 1;
4331 dtrace_get_modrm(x, &mode, ®, &r_m);
4333 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3))
4334 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN);
4336 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4337 dtrace_get_operand(x, mode, r_m, wbit, 0);
4340 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */
4341 x->d86_numopnds = 3;
4342 dtrace_get_modrm(x, &mode, ®, &r_m);
4343 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4345 if (mode != REG_ONLY) {
4346 if ((dp == &dis_opAVXF20F[0x10]) ||
4347 (dp == &dis_opAVXF30F[0x10])) {
4348 /* vmovsd <m64>, <xmm> */
4349 /* or vmovss <m64>, <xmm> */
4350 x->d86_numopnds = 2;
4355 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4357 * VEX prefix uses the 1's complement form to encode the
4360 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4362 if ((dp == &dis_opAVXF20F[0x2A]) ||
4363 (dp == &dis_opAVXF30F[0x2A])) {
4365 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>,
4371 else if ((mode == REG_ONLY) &&
4372 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */
4373 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN);
4374 } else if ((mode == REG_ONLY) &&
4375 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */
4376 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN);
4379 dtrace_get_operand(x, mode, r_m, wbit, 0);
4384 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
4385 x->d86_numopnds = 3;
4387 dtrace_get_modrm(x, &mode, ®, &r_m);
4388 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4390 if (mode != REG_ONLY) {
4391 if ((dp == &dis_opAVXF20F[0x11]) ||
4392 (dp == &dis_opAVXF30F[0x11])) {
4393 /* vmovsd <xmm>, <m64> */
4394 /* or vmovss <xmm>, <m64> */
4395 x->d86_numopnds = 2;
4400 dtrace_get_operand(x, mode, r_m, wbit, 2);
4401 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4402 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
4406 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */
4407 x->d86_numopnds = 4;
4409 dtrace_get_modrm(x, &mode, ®, &r_m);
4410 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4411 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
4412 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
4413 if (dp == &dis_opAVX660F3A[0x18]) {
4414 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */
4415 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1);
4416 } else if ((dp == &dis_opAVX660F3A[0x20]) ||
4417 (dp == & dis_opAVX660F[0xC4])) {
4418 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */
4419 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */
4420 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
4421 } else if (dp == &dis_opAVX660F3A[0x22]) {
4422 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */
4425 x->d86_mnem[6] = 'q';
4427 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
4429 dtrace_get_operand(x, mode, r_m, wbit, 1);
4432 /* one byte immediate number */
4433 dtrace_imm_opnd(x, wbit, 1, 0);
4435 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */
4436 if ((dp == &dis_opAVX660F3A[0x4A]) ||
4437 (dp == &dis_opAVX660F3A[0x4B]) ||
4438 (dp == &dis_opAVX660F3A[0x4C])) {
4440 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4;
4442 x->d86_opnd[0].d86_mode = MODE_NONE;
4445 (void) strncpy(x->d86_opnd[0].d86_opnd,
4446 dis_YMMREG[regnum], OPLEN);
4448 (void) strncpy(x->d86_opnd[0].d86_opnd,
4449 dis_XMMREG[regnum], OPLEN);
4455 /* ModR/M.reg := op(ModR/M.rm) */
4456 x->d86_numopnds = 2;
4458 dtrace_get_modrm(x, &mode, ®, &r_m);
4459 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4462 if ((dp == &dis_opAVXF20F[0xE6]) ||
4463 (dp == &dis_opAVX660F[0x5A]) ||
4464 (dp == &dis_opAVX660F[0xE6])) {
4465 /* vcvtpd2dq <ymm>, <xmm> */
4466 /* or vcvtpd2ps <ymm>, <xmm> */
4467 /* or vcvttpd2dq <ymm>, <xmm> */
4468 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
4469 dtrace_get_operand(x, mode, r_m, wbit, 0);
4470 } else if ((dp == &dis_opAVXF30F[0xE6]) ||
4471 (dp == &dis_opAVX0F[0x5][0xA]) ||
4472 (dp == &dis_opAVX660F38[0x13])) {
4473 /* vcvtdq2pd <xmm>, <ymm> */
4474 /* or vcvtps2pd <xmm>, <ymm> */
4475 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4476 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
4477 } else if (dp == &dis_opAVX660F[0x6E]) {
4478 /* vmovd/q <reg/mem 32/64>, <xmm> */
4481 x->d86_mnem[4] = 'q';
4483 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4484 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4486 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4487 dtrace_get_operand(x, mode, r_m, wbit, 0);
4493 /* ModR/M.reg := op(ModR/M.rm, imm8) */
4494 x->d86_numopnds = 3;
4496 dtrace_get_modrm(x, &mode, ®, &r_m);
4497 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4499 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4500 dtrace_get_operand(x, mode, r_m, wbit, 1);
4502 /* one byte immediate number */
4503 dtrace_imm_opnd(x, wbit, 1, 0);
4507 /* VEX.vvvv := op(ModR/M.rm, imm8) */
4508 x->d86_numopnds = 3;
4510 dtrace_get_modrm(x, &mode, ®, &r_m);
4512 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg],
4515 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4517 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
4518 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1);
4520 /* one byte immediate number */
4521 dtrace_imm_opnd(x, wbit, 1, 0);
4525 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */
4526 if (dp == &dis_opAVX660F[0xC5]) {
4527 /* vpextrw <imm8>, <xmm>, <reg> */
4528 x->d86_numopnds = 2;
4531 x->d86_numopnds = 2;
4535 dtrace_get_modrm(x, &mode, ®, &r_m);
4536 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4537 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit);
4538 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1);
4541 dtrace_imm_opnd(x, wbit, 1, 0);
4546 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */
4547 x->d86_numopnds = 2;
4549 dtrace_get_modrm(x, &mode, ®, &r_m);
4550 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4551 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4552 dtrace_get_operand(x, mode, r_m, wbit, 0);
4556 /* ModR/M.rm := op(ModR/M.reg) */
4557 /* vextractf128 || vcvtps2ph */
4558 if (dp == &dis_opAVX660F3A[0x19] ||
4559 dp == &dis_opAVX660F3A[0x1d]) {
4560 x->d86_numopnds = 3;
4562 dtrace_get_modrm(x, &mode, ®, &r_m);
4563 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4565 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
4566 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4568 /* one byte immediate number */
4569 dtrace_imm_opnd(x, wbit, 1, 0);
4573 x->d86_numopnds = 2;
4575 dtrace_get_modrm(x, &mode, ®, &r_m);
4576 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4577 dtrace_get_operand(x, mode, r_m, wbit, 1);
4578 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
4582 /* ModR/M.rm := op(ModR/M.reg) */
4583 x->d86_numopnds = 2;
4585 dtrace_get_modrm(x, &mode, ®, &r_m);
4586 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4588 if (dp == &dis_opAVX660F[0x7E]) {
4589 /* vmovd/q <reg/mem 32/64>, <xmm> */
4592 x->d86_mnem[4] = 'q';
4594 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
4596 dtrace_get_operand(x, mode, r_m, wbit, 1);
4598 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
4602 /* ModR/M.rm := op(ModR/M.reg, imm) */
4603 x->d86_numopnds = 3;
4605 dtrace_get_modrm(x, &mode, ®, &r_m);
4606 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4609 if (dp == &dis_opAVX660F3A[0x16]) {
4610 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */
4612 x->d86_mnem[6] = 'q';
4615 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
4616 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4618 /* one byte immediate number */
4619 dtrace_imm_opnd(x, wbit, 1, 0);
4623 /* ModR/M.rm := op(ModR/M.reg) */
4624 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */
4625 x->d86_numopnds = 3;
4627 dtrace_get_modrm(x, &mode, ®, &r_m);
4628 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4630 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
4631 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4632 /* one byte immediate number */
4633 dtrace_imm_opnd(x, wbit, 1, 0);
4636 x->d86_numopnds = 2;
4638 dtrace_get_modrm(x, &mode, ®, &r_m);
4639 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4642 dtrace_get_operand(x, mode, r_m, wbit, vbit);
4643 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1);
4648 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
4649 x->d86_numopnds = 3;
4651 dtrace_get_modrm(x, &mode, ®, &r_m);
4652 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4653 dtrace_get_operand(x, mode, r_m, wbit, 2);
4654 /* VEX use the 1's complement form encode the XMM/YMM regs */
4655 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4656 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
4660 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */
4661 x->d86_numopnds = 3;
4663 dtrace_get_modrm(x, &mode, ®, &r_m);
4664 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4665 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4666 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4667 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0);
4673 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN);
4676 /* an invalid op code */
4692 * compute the size of any memory accessed by the instruction
4694 if (x->d86_memsize != 0) {
4696 } else if (dp->it_stackop) {
4697 switch (opnd_size) {
4708 } else if (nomem || mode == REG_ONLY) {
4711 } else if (dp->it_size != 0) {
4713 * In 64 bit mode descriptor table entries
4714 * go up to 10 bytes and popf/pushf are always 8 bytes
4716 if (x->d86_mode == SIZE64 && dp->it_size == 6)
4717 x->d86_memsize = 10;
4718 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 &&
4719 (opcode2 == 0xc || opcode2 == 0xd))
4722 x->d86_memsize = dp->it_size;
4724 } else if (wbit == 0) {
4727 } else if (wbit == LONG_OPND) {
4728 if (opnd_size == SIZE64)
4730 else if (opnd_size == SIZE32)
4735 } else if (wbit == SEG_OPND) {
4746 (void) strlcat(x->d86_mnem, "undef", OPLEN);
4754 * Some instructions should have immediate operands printed
4755 * as unsigned integers. We compare against this table.
4757 static char *unsigned_ops[] = {
4758 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp",
4759 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl",
4765 isunsigned_op(char *opcode)
4769 int is_unsigned = 0;
4772 * Work back to start of last mnemonic, since we may have
4773 * prefixes on some opcodes.
4775 where = opcode + strlen(opcode) - 1;
4776 while (where > opcode && *where != ' ')
4781 for (i = 0; unsigned_ops[i]; ++i) {
4782 if (strncmp(where, unsigned_ops[i],
4783 strlen(unsigned_ops[i])))
4788 return (is_unsigned);
4792 * Print a numeric immediate into end of buf, maximum length buflen.
4793 * The immediate may be an address or a displacement. Mask is set
4794 * for address size. If the immediate is a "small negative", or
4795 * if it's a negative displacement of any magnitude, print as -<absval>.
4796 * Respect the "octal" flag. "Small negative" is defined as "in the
4797 * interval [NEG_LIMIT, 0)".
4799 * Also, "isunsigned_op()" instructions never print negatives.
4801 * Return whether we decided to print a negative value or not.
4804 #define NEG_LIMIT -255
4806 enum {POS, TRY_NEG};
4809 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf,
4810 size_t buflen, int disp, int try_neg)
4813 int64_t sv = (int64_t)usv;
4814 int octal = dis->d86_flags & DIS_F_OCTAL;
4816 curlen = strlen(buf);
4818 if (try_neg == TRY_NEG && sv < 0 &&
4819 (disp || sv >= NEG_LIMIT) &&
4820 !isunsigned_op(dis->d86_mnem)) {
4821 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
4822 octal ? "-0%llo" : "-0x%llx", (-sv) & mask);
4826 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
4827 octal ? "+0%llo" : "+0x%llx", usv & mask);
4829 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
4830 octal ? "0%llo" : "0x%llx", usv & mask);
4851 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf,
4854 uint64_t reltgt = 0;
4857 int (*lookup)(void *, uint64_t, char *, size_t);
4860 uint64_t usv, mask, save_mask, save_usv;
4861 static uint64_t masks[] =
4862 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL};
4865 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem);
4868 * For PC-relative jumps, the pc is really the next pc after executing
4869 * this instruction, so increment it appropriately.
4873 for (i = 0; i < dis->d86_numopnds; i++) {
4874 d86opnd_t *op = &dis->d86_opnd[i];
4877 (void) strlcat(buf, ",", buflen);
4879 (void) strlcat(buf, op->d86_prefix, buflen);
4882 * sv is for the signed, possibly-truncated immediate or
4883 * displacement; usv retains the original size and
4884 * unsignedness for symbol lookup.
4887 sv = usv = op->d86_value;
4890 * About masks: for immediates that represent
4891 * addresses, the appropriate display size is
4892 * the effective address size of the instruction.
4893 * This includes MODE_OFFSET, MODE_IPREL, and
4894 * MODE_RIPREL. Immediates that are simply
4895 * immediate values should display in the operand's
4896 * size, however, since they don't represent addresses.
4899 /* d86_addr_size is SIZEnn, which is log2(real size) */
4900 mask = masks[dis->d86_addr_size];
4902 /* d86_value_size and d86_imm_bytes are in bytes */
4903 if (op->d86_mode == MODE_SIGNED ||
4904 op->d86_mode == MODE_IMPLIED)
4905 mask = masks[log2(op->d86_value_size)];
4907 switch (op->d86_mode) {
4911 (void) strlcat(buf, op->d86_opnd, buflen);
4920 if (dis->d86_seg_prefix)
4921 (void) strlcat(buf, dis->d86_seg_prefix,
4924 if (op->d86_mode == MODE_SIGNED ||
4925 op->d86_mode == MODE_IMPLIED) {
4926 (void) strlcat(buf, "$", buflen);
4929 if (print_imm(dis, usv, mask, buf, buflen,
4931 (op->d86_mode == MODE_SIGNED ||
4932 op->d86_mode == MODE_IMPLIED)) {
4935 * We printed a negative value for an
4936 * immediate that wasn't a
4937 * displacement. Note that fact so we can
4938 * print the positive value as an
4945 (void) strlcat(buf, op->d86_opnd, buflen);
4956 reltgt = (uint16_t)reltgt;
4959 reltgt = (uint32_t)reltgt;
4963 (void) print_imm(dis, usv, mask, buf, buflen,
4966 if (op->d86_mode == MODE_RIPREL)
4967 (void) strlcat(buf, "(%rip)", buflen);
4973 * The symbol lookups may result in false positives,
4974 * particularly on object files, where small numbers may match
4975 * the 0-relative non-relocated addresses of symbols.
4978 lookup = dis->d86_sym_lookup;
4980 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 &&
4981 lookup(dis->d86_data, tgt, NULL, 0) == 0) {
4982 (void) strlcat(buf, "\t<", buflen);
4983 curlen = strlen(buf);
4984 lookup(dis->d86_data, tgt, buf + curlen,
4986 (void) strlcat(buf, ">", buflen);
4990 * If we printed a negative immediate above, print the
4991 * positive in case our heuristic was unhelpful
4994 (void) strlcat(buf, "\t<", buflen);
4995 (void) print_imm(dis, save_usv, save_mask, buf, buflen,
4997 (void) strlcat(buf, ">", buflen);
5002 /* Print symbol or effective address for reltgt */
5004 (void) strlcat(buf, "\t<", buflen);
5005 curlen = strlen(buf);
5006 lookup(dis->d86_data, reltgt, buf + curlen,
5008 (void) strlcat(buf, ">", buflen);
5012 #endif /* DIS_TEXT */