2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
20 * Values defined in this file may only be changed under exceptional circumstances.
22 * Please ask Fiona Cain before making any changes.
25 #ifndef __ar9300template_wasp_2_h__
26 #define __ar9300template_wasp_2_h__
27 static ar9300_eeprom_t ar9300_template_wasp_2=
32 ar9300_eeprom_template_wasp_2, // templateVersion;
34 {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6];
36 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]=
38 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
40 //static OSPREY_BASE_EEP_HEADER baseEepHeader=
43 {0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written after calibration
44 0x33, // txrxMask; //4 bits tx and 4 bits rx
45 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 3}, // opCapFlags;
47 0, // blueToothOptions;
49 4, // deviceType; // takes lower byte in eeprom location
50 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration
51 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don
52 0x0c, //featureEnable; //bit0 - enable tx temp comp
53 //bit1 - enable tx volt comp
54 //bit2 - enable fastClock - default to 1
55 //bit3 - enable doubling - default to 1
56 //bit4 - enable internal regulator - default to 0
57 0, //miscConfiguration: bit0 - turn down drivestrength
58 3, // eepromWriteEnableGpio
61 0xff, // rxBandSelectGpio
67 //static OSPREY_MODAL_EEP_HEADER modalHeader2G=
70 0x220, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting)
71 0x88888, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12
72 {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each)
73 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
74 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
77 {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format
78 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain
79 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved
81 0, // xpaBiasLvl; // 1
82 0x0e, // txFrameToDataStart; // 1
83 0x0e, // txFrameToPaOn; // 1
84 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck
85 0, // antennaGain; // 1
86 0x2c, // switchSettling; // 1
87 -30, // adcDesiredSize; // 1
88 0, // txEndToXpaOff; // 1
89 0x2, // txEndToRxOn; // 1
90 0xe, // txFrameToXpaOn; // 1
92 0x0c80C080, // papdRateMaskHt20 // 4
93 0x0080C080, // papdRateMaskHt40
94 0, // switchcomspdt; // 2
95 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
98 {0,0,0,0,0} //futureModal[5];
102 0, // ant_div_control
105 {0,0,0,0,0,0,0,0}, // temp slop extension
107 0, // quick drop high
110 //static A_UINT8 calFreqPier2G[OSPREY_NUM_2G_CAL_PIERS]=
117 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData2G[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]=
119 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
120 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
121 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
124 //A_UINT8 calTarget_freqbin_Cck[OSPREY_NUM_2G_CCK_TARGET_POWERS];
131 //static CAL_TARGET_POWER_LEG calTarget_freqbin_2G[OSPREY_NUM_2G_20_TARGET_POWERS]
138 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]
145 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]
152 //static CAL_TARGET_POWER_LEG calTargetPowerCck[OSPREY_NUM_2G_CCK_TARGET_POWERS]=
159 //static CAL_TARGET_POWER_LEG calTargetPower2G[OSPREY_NUM_2G_20_TARGET_POWERS]=
167 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]=
169 //0_8_16,1-3_9-11_17-19,
170 // 4,5,6,7,12,13,14,15,20,21,22,23
171 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
172 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
173 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
176 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]=
178 //0_8_16,1-3_9-11_17-19,
179 // 4,5,6,7,12,13,14,15,20,21,22,23
180 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
181 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
182 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
185 //static A_UINT8 ctlIndex_2G[OSPREY_NUM_CTLS_2G]=
204 //A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G];
227 {/*Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
228 /*Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
229 /*Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
230 /*Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(2484, 1)},
232 {/*Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
233 /*Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
234 /*Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
237 {/*Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
238 /*Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
242 {/*Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1),
243 /*Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1),
244 /*Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1),
245 /*Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)},
247 {/*Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
248 /*Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
249 /*Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
252 {/*Data[9].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
253 /*Data[9].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
254 /*Data[9].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
257 {/*Data[10].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
258 /*Data[10].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
259 /*Data[10].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
262 {/*Data[11].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1),
263 /*Data[11].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1),
264 /*Data[11].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1),
265 /*Data[11].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)}
269 //OSP_CAL_CTL_DATA_2G ctlPowerData_2G[OSPREY_NUM_CTLS_2G];
271 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
274 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
275 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
276 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}},
278 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}},
279 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
280 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
282 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}},
283 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
284 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
286 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
287 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}},
288 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}},
293 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
294 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
295 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}},
297 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}},
298 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
299 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
301 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}},
302 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
303 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
305 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
306 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
307 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
311 //static OSPREY_MODAL_EEP_HEADER modalHeader5G=
315 0x440, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting)
316 0x11111, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12
317 {0x000,0x000,0x000}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each)
318 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
319 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
322 {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format
323 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain
324 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved
326 0, // xpaBiasLvl; // 1
327 0x0e, // txFrameToDataStart; // 1
328 0x0e, // txFrameToPaOn; // 1
329 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck
330 0, // antennaGain; // 1
331 0x2d, // switchSettling; // 1
332 -30, // adcDesiredSize; // 1
333 0, // txEndToXpaOff; // 1
334 0x2, // txEndToRxOn; // 1
335 0xe, // txFrameToXpaOn; // 1
336 28, // thresh62; // 1
337 0x0cf0e0e0, // papdRateMaskHt20 // 4
338 0x6cf0e0e0, // papdRateMaskHt40 // 4
339 0, // switchcomspdt; // 2
340 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
343 {0,0,0,0,0} //futureModal[5];
355 //static A_UINT8 calFreqPier5G[OSPREY_NUM_5G_CAL_PIERS]=
375 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData5G[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]=
378 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}},
379 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}},
380 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}},
384 //static CAL_TARGET_POWER_LEG calTarget_freqbin_5G[OSPREY_NUM_5G_20_TARGET_POWERS]=
397 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]=
410 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]=
424 //static CAL_TARGET_POWER_LEG calTargetPower5G[OSPREY_NUM_5G_20_TARGET_POWERS]=
439 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]=
442 //0_8_16,1-3_9-11_17-19,
443 // 4,5,6,7,12,13,14,15,20,21,22,23
444 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
445 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
446 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
447 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
448 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
449 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
450 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
451 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
454 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]=
456 //0_8_16,1-3_9-11_17-19,
457 // 4,5,6,7,12,13,14,15,20,21,22,23
458 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
459 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
460 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
461 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
462 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
463 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
464 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
465 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
468 //static A_UINT8 ctlIndex_5G[OSPREY_NUM_CTLS_5G]=
491 // A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G];
494 {/* Data[0].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
495 /* Data[0].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
496 /* Data[0].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0),
497 /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
498 /* Data[0].ctlEdges[4].bChannel*/FREQ2FBIN(5600, 0),
499 /* Data[0].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
500 /* Data[0].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
501 /* Data[0].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
503 {/* Data[1].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
504 /* Data[1].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
505 /* Data[1].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0),
506 /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
507 /* Data[1].ctlEdges[4].bChannel*/FREQ2FBIN(5520, 0),
508 /* Data[1].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
509 /* Data[1].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
510 /* Data[1].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
512 {/* Data[2].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
513 /* Data[2].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0),
514 /* Data[2].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0),
515 /* Data[2].ctlEdges[3].bChannel*/FREQ2FBIN(5310, 0),
516 /* Data[2].ctlEdges[4].bChannel*/FREQ2FBIN(5510, 0),
517 /* Data[2].ctlEdges[5].bChannel*/FREQ2FBIN(5550, 0),
518 /* Data[2].ctlEdges[6].bChannel*/FREQ2FBIN(5670, 0),
519 /* Data[2].ctlEdges[7].bChannel*/FREQ2FBIN(5755, 0)},
521 {/* Data[3].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
522 /* Data[3].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0),
523 /* Data[3].ctlEdges[2].bChannel*/FREQ2FBIN(5260, 0),
524 /* Data[3].ctlEdges[3].bChannel*/FREQ2FBIN(5320, 0),
525 /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
526 /* Data[3].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
527 /* Data[3].ctlEdges[6].bChannel*/0xFF,
528 /* Data[3].ctlEdges[7].bChannel*/0xFF},
530 {/* Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
531 /* Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
532 /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0),
533 /* Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(5700, 0),
534 /* Data[4].ctlEdges[4].bChannel*/0xFF,
535 /* Data[4].ctlEdges[5].bChannel*/0xFF,
536 /* Data[4].ctlEdges[6].bChannel*/0xFF,
537 /* Data[4].ctlEdges[7].bChannel*/0xFF},
539 {/* Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
540 /* Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(5270, 0),
541 /* Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(5310, 0),
542 /* Data[5].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0),
543 /* Data[5].ctlEdges[4].bChannel*/FREQ2FBIN(5590, 0),
544 /* Data[5].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0),
545 /* Data[5].ctlEdges[6].bChannel*/0xFF,
546 /* Data[5].ctlEdges[7].bChannel*/0xFF},
548 {/* Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
549 /* Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0),
550 /* Data[6].ctlEdges[2].bChannel*/FREQ2FBIN(5220, 0),
551 /* Data[6].ctlEdges[3].bChannel*/FREQ2FBIN(5260, 0),
552 /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
553 /* Data[6].ctlEdges[5].bChannel*/FREQ2FBIN(5600, 0),
554 /* Data[6].ctlEdges[6].bChannel*/FREQ2FBIN(5700, 0),
555 /* Data[6].ctlEdges[7].bChannel*/FREQ2FBIN(5745, 0)},
557 {/* Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
558 /* Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
559 /* Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(5320, 0),
560 /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
561 /* Data[7].ctlEdges[4].bChannel*/FREQ2FBIN(5560, 0),
562 /* Data[7].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
563 /* Data[7].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
564 /* Data[7].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
566 {/* Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
567 /* Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0),
568 /* Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0),
569 /* Data[8].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0),
570 /* Data[8].ctlEdges[4].bChannel*/FREQ2FBIN(5550, 0),
571 /* Data[8].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0),
572 /* Data[8].ctlEdges[6].bChannel*/FREQ2FBIN(5755, 0),
573 /* Data[8].ctlEdges[7].bChannel*/FREQ2FBIN(5795, 0)}
576 //static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]=
578 #if AH_BYTE_ORDER == AH_BIG_ENDIAN