1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_ASX0_TYPEDEFS_H__
53 #define __CVMX_ASX0_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC()
57 static inline uint64_t CVMX_ASX0_DBG_DATA_DRV_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
60 cvmx_warn("CVMX_ASX0_DBG_DATA_DRV not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x00011800B0000208ull);
64 #define CVMX_ASX0_DBG_DATA_DRV (CVMX_ADD_IO_SEG(0x00011800B0000208ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_ASX0_DBG_DATA_ENABLE CVMX_ASX0_DBG_DATA_ENABLE_FUNC()
68 static inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void)
70 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
71 cvmx_warn("CVMX_ASX0_DBG_DATA_ENABLE not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x00011800B0000200ull);
75 #define CVMX_ASX0_DBG_DATA_ENABLE (CVMX_ADD_IO_SEG(0x00011800B0000200ull))
79 * cvmx_asx0_dbg_data_drv
84 union cvmx_asx0_dbg_data_drv
87 struct cvmx_asx0_dbg_data_drv_s
89 #if __BYTE_ORDER == __BIG_ENDIAN
90 uint64_t reserved_9_63 : 55;
91 uint64_t pctl : 5; /**< These bits control the driving strength of the dbg
93 uint64_t nctl : 4; /**< These bits control the driving strength of the dbg
98 uint64_t reserved_9_63 : 55;
101 struct cvmx_asx0_dbg_data_drv_cn38xx
103 #if __BYTE_ORDER == __BIG_ENDIAN
104 uint64_t reserved_8_63 : 56;
105 uint64_t pctl : 4; /**< These bits control the driving strength of the dbg
107 uint64_t nctl : 4; /**< These bits control the driving strength of the dbg
112 uint64_t reserved_8_63 : 56;
115 struct cvmx_asx0_dbg_data_drv_cn38xx cn38xxp2;
116 struct cvmx_asx0_dbg_data_drv_s cn58xx;
117 struct cvmx_asx0_dbg_data_drv_s cn58xxp1;
119 typedef union cvmx_asx0_dbg_data_drv cvmx_asx0_dbg_data_drv_t;
122 * cvmx_asx0_dbg_data_enable
124 * ASX_DBG_DATA_ENABLE
127 union cvmx_asx0_dbg_data_enable
130 struct cvmx_asx0_dbg_data_enable_s
132 #if __BYTE_ORDER == __BIG_ENDIAN
133 uint64_t reserved_1_63 : 63;
134 uint64_t en : 1; /**< A 1->0 transistion, turns the dbg interface OFF. */
137 uint64_t reserved_1_63 : 63;
140 struct cvmx_asx0_dbg_data_enable_s cn38xx;
141 struct cvmx_asx0_dbg_data_enable_s cn38xxp2;
142 struct cvmx_asx0_dbg_data_enable_s cn58xx;
143 struct cvmx_asx0_dbg_data_enable_s cn58xxp1;
145 typedef union cvmx_asx0_dbg_data_enable cvmx_asx0_dbg_data_enable_t;