1 /***********************license start***************
2 * Copyright (c) 2008 Cavium Networks (support@cavium.com). All rights
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32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
35 * For any questions regarding licensing please contact marketing@caviumnetworks.com
37 ***********************license end**************************************/
41 #include "cvmx-sysinfo.h"
42 #include "cvmx-compactflash.h"
46 #define MAX(a,b) (((a)>(b))?(a):(b))
48 #define FLASH_RoundUP(_Dividend, _Divisor) (((_Dividend)+(_Divisor-1))/(_Divisor))
50 * Convert nanosecond based time to setting used in the
51 * boot bus timing register, based on timing multiple
55 static uint32_t ns_to_tim_reg(int tim_mult, uint32_t nsecs)
59 /* Compute # of eclock periods to get desired duration in nanoseconds */
60 val = FLASH_RoundUP(nsecs * (cvmx_sysinfo_get()->cpu_clock_hz/1000000), 1000);
62 /* Factor in timing multiple, if not 1 */
64 val = FLASH_RoundUP(val, tim_mult);
69 uint64_t cvmx_compactflash_generate_dma_tim(int tim_mult, uint16_t *ident_data, int *mwdma_mode_ptr)
72 cvmx_mio_boot_dma_timx_t dma_tim;
81 uint16_t word53_field_valid;
82 uint16_t word63_mwdma;
83 uint16_t word163_adv_timing_info;
88 word53_field_valid = ident_data[53];
89 word63_mwdma = ident_data[63];
90 word163_adv_timing_info = ident_data[163];
94 /* Check for basic MWDMA modes */
95 if (word53_field_valid & 0x2)
97 if (word63_mwdma & 0x4)
99 else if (word63_mwdma & 0x2)
101 else if (word63_mwdma & 0x1)
105 /* Check for advanced MWDMA modes */
106 switch ((word163_adv_timing_info >> 3) & 0x7)
118 /* DMA is not supported by this card */
122 /* Now set up the DMA timing */
126 dma_tim.s.tim_mult = 1;
129 dma_tim.s.tim_mult = 2;
132 dma_tim.s.tim_mult = 0;
135 dma_tim.s.tim_mult = 3;
138 cvmx_dprintf("ERROR: invalid boot bus dma tim_mult setting\n");
150 oe_a = Td + 20; // Td (Seem to need more margin here....
151 oe_n = MAX(To - oe_a, Tkr); // Tkr from cf spec, lengthened to meet To
153 // oe_n + oe_h must be >= To (cycle time)
157 dma_arq = 8; // not spec'ed, value in eclocks, not affected by tim_mult
158 pause = 25 - dma_arq * 1000/(cvmx_sysinfo_get()->cpu_clock_hz/1000000); // Tz
165 oe_a = Td + 20; // Td (Seem to need more margin here....
166 oe_n = MAX(To - oe_a, Tkr); // Tkr from cf spec, lengthened to meet To
168 // oe_n + oe_h must be >= To (cycle time)
172 dma_arq = 8; // not spec'ed, value in eclocks, not affected by tim_mult
173 pause = 25 - dma_arq * 1000/(cvmx_sysinfo_get()->cpu_clock_hz/1000000); // Tz
184 // oe_a 0 fudge doesn't work; 10 seems to
185 oe_a = Td + 20 + 10; // Td (Seem to need more margin here....
186 oe_n = MAX(To - oe_a, Tkr) + 10; // Tkr from cf spec, lengthened to meet To
187 // oe_n 0 fudge fails;;; 10 boots
189 // 20 ns fudge needed on dma_acks
190 // oe_n + oe_h must be >= To (cycle time)
191 dma_acks = 0 + 20; //Ti
194 dma_arq = 8; // not spec'ed, value in eclocks, not affected by tim_mult
195 pause = 25 - dma_arq * 1000/(cvmx_sysinfo_get()->cpu_clock_hz/1000000); // Tz
196 // no fudge needed on pause
202 cvmx_dprintf("ERROR: Unsupported DMA mode: %d\n", mwdma_mode);
208 *mwdma_mode_ptr = mwdma_mode;
210 dma_tim.s.dmack_pi = 1;
212 dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
213 dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
215 dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, dma_acks);
216 dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh);
218 dma_tim.s.dmarq = dma_arq;
219 dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause);
221 dma_tim.s.rd_dly = 0; /* Sample right on edge */
224 dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n);
225 dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a);
228 cvmx_dprintf("ns to ticks (mult %d) of %d is: %d\n", TIM_MULT, 60, ns_to_tim_reg(60));
229 cvmx_dprintf("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
230 dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s, dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
240 * Setup timing and region config to support a specific IDE PIO
241 * mode over the bootbus.
243 * @param cs0 Bootbus region number connected to CS0 on the IDE device
244 * @param cs1 Bootbus region number connected to CS1 on the IDE device
245 * @param pio_mode PIO mode to set (0-6)
247 void cvmx_compactflash_set_piomode(int cs0, int cs1, int pio_mode)
249 cvmx_mio_boot_reg_cfgx_t mio_boot_reg_cfg;
250 cvmx_mio_boot_reg_timx_t mio_boot_reg_tim;
252 int clocks_us; /* Number of clock cycles per microsec */
254 int use_iordy; /* Set for PIO0-4, not set for PIO5-6 */
255 int t1; /* These t names are timing parameters from the ATA spec */
263 /* PIO modes 0-4 all allow the device to deassert IORDY to slow down
267 /* Use the PIO mode to determine timing parameters */
270 /* CF spec say IORDY should be ignore in PIO 5 */
281 /* CF spec say IORDY should be ignore in PIO 6 */
337 /* Convert times in ns to clock cycles, rounding up */
338 clocks_us = FLASH_RoundUP((uint64_t)cvmx_sysinfo_get()->cpu_clock_hz, 1000000);
340 /* Convert times in clock cycles, rounding up. Octeon parameters are in
341 minus one notation, so take off one after the conversion */
342 t1 = FLASH_RoundUP(t1 * clocks_us, 1000);
345 t2 = FLASH_RoundUP(t2 * clocks_us, 1000);
348 t2i = FLASH_RoundUP(t2i * clocks_us, 1000);
351 t4 = FLASH_RoundUP(t4 * clocks_us, 1000);
354 t6 = FLASH_RoundUP(t6 * clocks_us, 1000);
357 t6z = FLASH_RoundUP(t6z * clocks_us, 1000);
360 t9 = FLASH_RoundUP(t9 * clocks_us, 1000);
364 /* Start using a scale factor of one cycle. Keep doubling it until
365 the parameters fit in their fields. Since t2 is the largest number,
366 we only need to check it */
370 t1 = FLASH_RoundUP(t1, 2);
371 t2 = FLASH_RoundUP(t2, 2);
372 t2i = FLASH_RoundUP(t2i, 2);
373 t4 = FLASH_RoundUP(t4, 2);
374 t6 = FLASH_RoundUP(t6, 2);
375 t6z = FLASH_RoundUP(t6z, 2);
376 t9 = FLASH_RoundUP(t9, 2);
382 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
383 mio_boot_reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */
386 mio_boot_reg_cfg.s.tim_mult = 1;
389 mio_boot_reg_cfg.s.tim_mult = 2;
392 mio_boot_reg_cfg.s.tim_mult = 0;
396 mio_boot_reg_cfg.s.tim_mult = 3;
399 mio_boot_reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */
400 mio_boot_reg_cfg.s.sam = 0; /* Don't combine write and output enable */
401 mio_boot_reg_cfg.s.we_ext = 0; /* No write enable extension */
402 mio_boot_reg_cfg.s.oe_ext = 0; /* No read enable extension */
403 mio_boot_reg_cfg.s.en = 1; /* Enable this region */
404 mio_boot_reg_cfg.s.orbit = 0; /* Don't combine with previos region */
405 mio_boot_reg_cfg.s.width = 1; /* 16 bits wide */
406 cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), mio_boot_reg_cfg.u64);
413 mio_boot_reg_tim.u64 = 0;
414 mio_boot_reg_tim.s.pagem = 0; /* Disable page mode */
415 mio_boot_reg_tim.s.waitm = use_iordy; /* Enable dynamic timing */
416 mio_boot_reg_tim.s.pages = 0; /* Pages are disabled */
417 mio_boot_reg_tim.s.ale = 8; /* If someone uses ALE, this seems to work */
418 mio_boot_reg_tim.s.page = 0; /* Not used */
419 mio_boot_reg_tim.s.wait = 0; /* Time after IORDY to coninue to assert the data */
420 mio_boot_reg_tim.s.pause = 0; /* Time after CE that signals stay valid */
421 mio_boot_reg_tim.s.wr_hld = t9; /* How long to hold after a write */
422 mio_boot_reg_tim.s.rd_hld = t9; /* How long to wait after a read for device to tristate */
423 mio_boot_reg_tim.s.we = t2; /* How long write enable is asserted */
424 mio_boot_reg_tim.s.oe = t2; /* How long read enable is asserted */
425 mio_boot_reg_tim.s.ce = t1; /* Time after CE that read/write starts */
426 mio_boot_reg_tim.s.adr = 1; /* Time before CE that address is valid */
428 /* Program the bootbus region timing for both chip selects */
429 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs0), mio_boot_reg_tim.u64);
430 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs1), mio_boot_reg_tim.u64);