1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_DBG_TYPEDEFS_H__
53 #define __CVMX_DBG_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC()
57 static inline uint64_t CVMX_DBG_DATA_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
60 cvmx_warn("CVMX_DBG_DATA not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x00011F00000001E8ull);
64 #define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
70 * DBG_DATA = Debug Data Register
72 * Value returned on the debug-data lines from the RSLs
77 struct cvmx_dbg_data_s
79 #if __BYTE_ORDER == __BIG_ENDIAN
80 uint64_t reserved_23_63 : 41;
81 uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */
82 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
83 debug select value. */
84 uint64_t data : 17; /**< Value on the debug data lines. */
87 uint64_t dsel_ext : 1;
89 uint64_t reserved_23_63 : 41;
92 struct cvmx_dbg_data_cn30xx
94 #if __BYTE_ORDER == __BIG_ENDIAN
95 uint64_t reserved_31_63 : 33;
96 uint64_t pll_mul : 3; /**< pll_mul pins sampled at DCOK assertion */
97 uint64_t reserved_23_27 : 5;
98 uint64_t c_mul : 5; /**< Core PLL multiplier sampled at DCOK assertion */
99 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
100 debug select value. */
101 uint64_t data : 17; /**< Value on the debug data lines. */
104 uint64_t dsel_ext : 1;
106 uint64_t reserved_23_27 : 5;
107 uint64_t pll_mul : 3;
108 uint64_t reserved_31_63 : 33;
111 struct cvmx_dbg_data_cn30xx cn31xx;
112 struct cvmx_dbg_data_cn38xx
114 #if __BYTE_ORDER == __BIG_ENDIAN
115 uint64_t reserved_29_63 : 35;
116 uint64_t d_mul : 4; /**< D_MUL pins sampled on DCOK assertion */
117 uint64_t dclk_mul2 : 1; /**< Should always be set for fast DDR-II operation */
118 uint64_t cclk_div2 : 1; /**< Should always be clear for fast core clock */
119 uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */
120 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
121 debug select value. */
122 uint64_t data : 17; /**< Value on the debug data lines. */
125 uint64_t dsel_ext : 1;
127 uint64_t cclk_div2 : 1;
128 uint64_t dclk_mul2 : 1;
130 uint64_t reserved_29_63 : 35;
133 struct cvmx_dbg_data_cn38xx cn38xxp2;
134 struct cvmx_dbg_data_cn30xx cn50xx;
135 struct cvmx_dbg_data_cn58xx
137 #if __BYTE_ORDER == __BIG_ENDIAN
138 uint64_t reserved_29_63 : 35;
139 uint64_t rem : 6; /**< Remaining debug_select pins sampled at DCOK */
140 uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */
141 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
142 debug select value. */
143 uint64_t data : 17; /**< Value on the debug data lines. */
146 uint64_t dsel_ext : 1;
149 uint64_t reserved_29_63 : 35;
152 struct cvmx_dbg_data_cn58xx cn58xxp1;
154 typedef union cvmx_dbg_data cvmx_dbg_data_t;