1 /***********************license start***************
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38 ***********************license end**************************************/
45 #include <asm/regdef.h>
47 #include <machine/asm.h>
48 #include <machine/regdef.h>
51 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
52 #include <asm/octeon/cvmx-asm.h>
53 #include <asm/octeon/octeon-boot-info.h>
55 #include "executive-config.h"
58 #ifndef __OCTEON_NEWLIB__
59 #include "../../bootloader/u-boot/include/octeon_mem_map.h"
61 #include "octeon-boot-info.h"
66 /* The registers saving/restoring is split into two because k0 is stored in the COP0_DESAVE register. */
67 #define REGS0 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25
68 #define REGS1 27,28,29,30,31
70 #define SAVE_REGISTER(reg) \
74 #define RESTORE_REGISTER(reg) \
78 #define SAVE_COP0(reg) \
83 #define RESTORE_COP0(reg) \
88 #define SAVE_ADDRESS(addr) \
94 #define RESTORE_ADDRESS(addr) \
100 #define REG_SAVE_BASE_DIV_4 (BOOTLOADER_DEBUG_REG_SAVE_BASE >> 2)
103 #define HW_INSTRUCTION_BREAKPOINT_STATUS (0xFFFFFFFFFF301000)
104 #define HW_INSTRUCTION_BREAKPOINT_ADDRESS(num) (0xFFFFFFFFFF301100 + 0x100 * (num))
105 #define HW_INSTRUCTION_BREAKPOINT_ADDRESS_MASK(num) (0xFFFFFFFFFF301108 + 0x100 * (num))
106 #define HW_INSTRUCTION_BREAKPOINT_ASID(num) (0xFFFFFFFFFF301110 + 0x100 * (num))
107 #define HW_INSTRUCTION_BREAKPOINT_CONTROL(num) (0xFFFFFFFFFF301118 + 0x100 * (num))
109 #define HW_DATA_BREAKPOINT_STATUS (0xFFFFFFFFFF302000)
110 #define HW_DATA_BREAKPOINT_ADDRESS(num) (0xFFFFFFFFFF302100 + 0x100 * (num))
111 #define HW_DATA_BREAKPOINT_ADDRESS_MASK(num) (0xFFFFFFFFFF302108 + 0x100 * (num))
112 #define HW_DATA_BREAKPOINT_ASID(num) (0xFFFFFFFFFF302110 + 0x100 * (num))
113 #define HW_DATA_BREAKPOINT_CONTROL(num) (0xFFFFFFFFFF302118 + 0x100 * (num))
116 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
117 #define loadaddr(reg, addr, shift) \
118 dla reg, addr##_all; \
124 #define loadaddr(reg, addr, shift) \
134 // Detect debug-mode exception, save all registers, create a stack and then
135 // call the stage3 C function.
137 .ent __cvmx_debug_handler_stage2
138 .globl __cvmx_debug_handler_stage2
139 __cvmx_debug_handler_stage2:
140 // Save off k0 in COP0_DESAVE
141 dmtc0 k0, COP0_DESAVE
143 // Use reserved space in kseg0 to save off some temp regs
144 mfc0 k0, $15, 1 // read exception base reg.
145 andi k0, 0xff // mask off core ID
146 sll k0, 12 // multiply by 4096 (512 dwords) DEBUG_NUMREGS
148 addiu k0, REG_SAVE_BASE_DIV_4
149 addiu k0, REG_SAVE_BASE_DIV_4
150 addiu k0, REG_SAVE_BASE_DIV_4
151 addiu k0, REG_SAVE_BASE_DIV_4
152 // add base offset - after exeption vectors for all cores
154 rotr k0, k0, 31 // set bit 31 for kseg0 access
158 // save off k1 and at ($1) off to the bootloader reg save area
160 sd $1, 8(k0) // save at for temp usage
161 sd k1, 216(k0) // save k1 for temp usage
164 // Detect debug-mode exception.
165 // If COP0_MULTICOREDEBUG[DExecC] is set,
166 dmfc0 k1, COP0_MULTICOREDEBUG
170 // COP0_DEBUG[DINT,DIB,DDBS,DBp,DSS] are not set and
176 // COP0_DEBUG[DExecC] is set.
182 // We don't handle debug-mode exceptions in delay-slots so DEBUG[DBD]
183 // should not be set. If yes spin forever.
189 // It's a debug-mode exception. Flag the occurence. Also if it's
190 // expected just ignore it but returning the subsequent instruction
193 loadaddr (k1, __cvmx_debug_mode_exception_occured, 3)
196 loadaddr (k1, __cvmx_debug_mode_exception_ignore, 3)
201 // Restore k1 and at from the bootloader reg save area
202 ld $1, 8(k0) // save at for temp usage
203 ld k1, 216(k0) // save k1 for temp usage
206 // Skip the faulting instruction.
209 dmfc0 k0, COP0_DESAVE
213 loadaddr (k1, __cvmx_debug_save_regs_area, 8)
216 ld $1, 8(k0) // restore at for temp usage
224 ld k1, 216(k0) // restore k1 for temp usage
227 // Store out k0, we can use $25 here because we just saved it
228 dmfc0 $25, COP0_DESAVE
237 loadaddr(sp, __cvmx_debug_stack_top, 3)
238 // Load the stack pointer as a pointer size.
244 jal __cvmx_debug_handler_stage3
247 loadaddr(k0, __cvmx_debug_save_regs_area, 8)
254 // Restore k0 to COP0_DESAVE via k1
257 dmtc0 k1, COP0_DESAVE
264 dmfc0 k0, COP0_DESAVE
265 // Flush the icache; by adding and removing SW breakpoints we change
266 // the instruction stream.
271 .end __cvmx_debug_handler_stage2