1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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7 * modification, are permitted provided that the following conditions are
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_DFA_TYPEDEFS_H__
53 #define __CVMX_DFA_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_DFA_BIST0 CVMX_DFA_BIST0_FUNC()
57 static inline uint64_t CVMX_DFA_BIST0_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
60 cvmx_warn("CVMX_DFA_BIST0 not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x00011800370007F0ull);
64 #define CVMX_DFA_BIST0 (CVMX_ADD_IO_SEG(0x00011800370007F0ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_DFA_BIST1 CVMX_DFA_BIST1_FUNC()
68 static inline uint64_t CVMX_DFA_BIST1_FUNC(void)
70 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
71 cvmx_warn("CVMX_DFA_BIST1 not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x00011800370007F8ull);
75 #define CVMX_DFA_BIST1 (CVMX_ADD_IO_SEG(0x00011800370007F8ull))
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_DFA_BST0 CVMX_DFA_BST0_FUNC()
79 static inline uint64_t CVMX_DFA_BST0_FUNC(void)
81 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
82 cvmx_warn("CVMX_DFA_BST0 not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x00011800300007F0ull);
86 #define CVMX_DFA_BST0 (CVMX_ADD_IO_SEG(0x00011800300007F0ull))
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_DFA_BST1 CVMX_DFA_BST1_FUNC()
90 static inline uint64_t CVMX_DFA_BST1_FUNC(void)
92 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
93 cvmx_warn("CVMX_DFA_BST1 not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x00011800300007F8ull);
97 #define CVMX_DFA_BST1 (CVMX_ADD_IO_SEG(0x00011800300007F8ull))
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 #define CVMX_DFA_CFG CVMX_DFA_CFG_FUNC()
101 static inline uint64_t CVMX_DFA_CFG_FUNC(void)
103 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
104 cvmx_warn("CVMX_DFA_CFG not supported on this chip\n");
105 return CVMX_ADD_IO_SEG(0x0001180030000000ull);
108 #define CVMX_DFA_CFG (CVMX_ADD_IO_SEG(0x0001180030000000ull))
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111 #define CVMX_DFA_CONFIG CVMX_DFA_CONFIG_FUNC()
112 static inline uint64_t CVMX_DFA_CONFIG_FUNC(void)
114 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
115 cvmx_warn("CVMX_DFA_CONFIG not supported on this chip\n");
116 return CVMX_ADD_IO_SEG(0x0001180037000000ull);
119 #define CVMX_DFA_CONFIG (CVMX_ADD_IO_SEG(0x0001180037000000ull))
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
122 #define CVMX_DFA_CONTROL CVMX_DFA_CONTROL_FUNC()
123 static inline uint64_t CVMX_DFA_CONTROL_FUNC(void)
125 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
126 cvmx_warn("CVMX_DFA_CONTROL not supported on this chip\n");
127 return CVMX_ADD_IO_SEG(0x0001180037000020ull);
130 #define CVMX_DFA_CONTROL (CVMX_ADD_IO_SEG(0x0001180037000020ull))
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 #define CVMX_DFA_DBELL CVMX_DFA_DBELL_FUNC()
134 static inline uint64_t CVMX_DFA_DBELL_FUNC(void)
136 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
137 cvmx_warn("CVMX_DFA_DBELL not supported on this chip\n");
138 return CVMX_ADD_IO_SEG(0x0001370000000000ull);
141 #define CVMX_DFA_DBELL (CVMX_ADD_IO_SEG(0x0001370000000000ull))
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
144 #define CVMX_DFA_DDR2_ADDR CVMX_DFA_DDR2_ADDR_FUNC()
145 static inline uint64_t CVMX_DFA_DDR2_ADDR_FUNC(void)
147 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
148 cvmx_warn("CVMX_DFA_DDR2_ADDR not supported on this chip\n");
149 return CVMX_ADD_IO_SEG(0x0001180030000210ull);
152 #define CVMX_DFA_DDR2_ADDR (CVMX_ADD_IO_SEG(0x0001180030000210ull))
154 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
155 #define CVMX_DFA_DDR2_BUS CVMX_DFA_DDR2_BUS_FUNC()
156 static inline uint64_t CVMX_DFA_DDR2_BUS_FUNC(void)
158 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
159 cvmx_warn("CVMX_DFA_DDR2_BUS not supported on this chip\n");
160 return CVMX_ADD_IO_SEG(0x0001180030000080ull);
163 #define CVMX_DFA_DDR2_BUS (CVMX_ADD_IO_SEG(0x0001180030000080ull))
165 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
166 #define CVMX_DFA_DDR2_CFG CVMX_DFA_DDR2_CFG_FUNC()
167 static inline uint64_t CVMX_DFA_DDR2_CFG_FUNC(void)
169 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
170 cvmx_warn("CVMX_DFA_DDR2_CFG not supported on this chip\n");
171 return CVMX_ADD_IO_SEG(0x0001180030000208ull);
174 #define CVMX_DFA_DDR2_CFG (CVMX_ADD_IO_SEG(0x0001180030000208ull))
176 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
177 #define CVMX_DFA_DDR2_COMP CVMX_DFA_DDR2_COMP_FUNC()
178 static inline uint64_t CVMX_DFA_DDR2_COMP_FUNC(void)
180 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
181 cvmx_warn("CVMX_DFA_DDR2_COMP not supported on this chip\n");
182 return CVMX_ADD_IO_SEG(0x0001180030000090ull);
185 #define CVMX_DFA_DDR2_COMP (CVMX_ADD_IO_SEG(0x0001180030000090ull))
187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
188 #define CVMX_DFA_DDR2_EMRS CVMX_DFA_DDR2_EMRS_FUNC()
189 static inline uint64_t CVMX_DFA_DDR2_EMRS_FUNC(void)
191 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
192 cvmx_warn("CVMX_DFA_DDR2_EMRS not supported on this chip\n");
193 return CVMX_ADD_IO_SEG(0x0001180030000268ull);
196 #define CVMX_DFA_DDR2_EMRS (CVMX_ADD_IO_SEG(0x0001180030000268ull))
198 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
199 #define CVMX_DFA_DDR2_FCNT CVMX_DFA_DDR2_FCNT_FUNC()
200 static inline uint64_t CVMX_DFA_DDR2_FCNT_FUNC(void)
202 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
203 cvmx_warn("CVMX_DFA_DDR2_FCNT not supported on this chip\n");
204 return CVMX_ADD_IO_SEG(0x0001180030000078ull);
207 #define CVMX_DFA_DDR2_FCNT (CVMX_ADD_IO_SEG(0x0001180030000078ull))
209 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
210 #define CVMX_DFA_DDR2_MRS CVMX_DFA_DDR2_MRS_FUNC()
211 static inline uint64_t CVMX_DFA_DDR2_MRS_FUNC(void)
213 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
214 cvmx_warn("CVMX_DFA_DDR2_MRS not supported on this chip\n");
215 return CVMX_ADD_IO_SEG(0x0001180030000260ull);
218 #define CVMX_DFA_DDR2_MRS (CVMX_ADD_IO_SEG(0x0001180030000260ull))
220 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
221 #define CVMX_DFA_DDR2_OPT CVMX_DFA_DDR2_OPT_FUNC()
222 static inline uint64_t CVMX_DFA_DDR2_OPT_FUNC(void)
224 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
225 cvmx_warn("CVMX_DFA_DDR2_OPT not supported on this chip\n");
226 return CVMX_ADD_IO_SEG(0x0001180030000070ull);
229 #define CVMX_DFA_DDR2_OPT (CVMX_ADD_IO_SEG(0x0001180030000070ull))
231 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
232 #define CVMX_DFA_DDR2_PLL CVMX_DFA_DDR2_PLL_FUNC()
233 static inline uint64_t CVMX_DFA_DDR2_PLL_FUNC(void)
235 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
236 cvmx_warn("CVMX_DFA_DDR2_PLL not supported on this chip\n");
237 return CVMX_ADD_IO_SEG(0x0001180030000088ull);
240 #define CVMX_DFA_DDR2_PLL (CVMX_ADD_IO_SEG(0x0001180030000088ull))
242 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
243 #define CVMX_DFA_DDR2_TMG CVMX_DFA_DDR2_TMG_FUNC()
244 static inline uint64_t CVMX_DFA_DDR2_TMG_FUNC(void)
246 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
247 cvmx_warn("CVMX_DFA_DDR2_TMG not supported on this chip\n");
248 return CVMX_ADD_IO_SEG(0x0001180030000218ull);
251 #define CVMX_DFA_DDR2_TMG (CVMX_ADD_IO_SEG(0x0001180030000218ull))
253 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
254 #define CVMX_DFA_DEBUG0 CVMX_DFA_DEBUG0_FUNC()
255 static inline uint64_t CVMX_DFA_DEBUG0_FUNC(void)
257 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
258 cvmx_warn("CVMX_DFA_DEBUG0 not supported on this chip\n");
259 return CVMX_ADD_IO_SEG(0x0001180037000040ull);
262 #define CVMX_DFA_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180037000040ull))
264 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
265 #define CVMX_DFA_DEBUG1 CVMX_DFA_DEBUG1_FUNC()
266 static inline uint64_t CVMX_DFA_DEBUG1_FUNC(void)
268 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
269 cvmx_warn("CVMX_DFA_DEBUG1 not supported on this chip\n");
270 return CVMX_ADD_IO_SEG(0x0001180037000048ull);
273 #define CVMX_DFA_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180037000048ull))
275 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
276 #define CVMX_DFA_DEBUG2 CVMX_DFA_DEBUG2_FUNC()
277 static inline uint64_t CVMX_DFA_DEBUG2_FUNC(void)
279 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
280 cvmx_warn("CVMX_DFA_DEBUG2 not supported on this chip\n");
281 return CVMX_ADD_IO_SEG(0x0001180037000050ull);
284 #define CVMX_DFA_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180037000050ull))
286 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
287 #define CVMX_DFA_DEBUG3 CVMX_DFA_DEBUG3_FUNC()
288 static inline uint64_t CVMX_DFA_DEBUG3_FUNC(void)
290 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
291 cvmx_warn("CVMX_DFA_DEBUG3 not supported on this chip\n");
292 return CVMX_ADD_IO_SEG(0x0001180037000058ull);
295 #define CVMX_DFA_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180037000058ull))
297 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
298 #define CVMX_DFA_DIFCTL CVMX_DFA_DIFCTL_FUNC()
299 static inline uint64_t CVMX_DFA_DIFCTL_FUNC(void)
301 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
302 cvmx_warn("CVMX_DFA_DIFCTL not supported on this chip\n");
303 return CVMX_ADD_IO_SEG(0x0001370600000000ull);
306 #define CVMX_DFA_DIFCTL (CVMX_ADD_IO_SEG(0x0001370600000000ull))
308 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
309 #define CVMX_DFA_DIFRDPTR CVMX_DFA_DIFRDPTR_FUNC()
310 static inline uint64_t CVMX_DFA_DIFRDPTR_FUNC(void)
312 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
313 cvmx_warn("CVMX_DFA_DIFRDPTR not supported on this chip\n");
314 return CVMX_ADD_IO_SEG(0x0001370200000000ull);
317 #define CVMX_DFA_DIFRDPTR (CVMX_ADD_IO_SEG(0x0001370200000000ull))
319 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
320 #define CVMX_DFA_DTCFADR CVMX_DFA_DTCFADR_FUNC()
321 static inline uint64_t CVMX_DFA_DTCFADR_FUNC(void)
323 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
324 cvmx_warn("CVMX_DFA_DTCFADR not supported on this chip\n");
325 return CVMX_ADD_IO_SEG(0x0001180037000060ull);
328 #define CVMX_DFA_DTCFADR (CVMX_ADD_IO_SEG(0x0001180037000060ull))
330 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
331 #define CVMX_DFA_ECLKCFG CVMX_DFA_ECLKCFG_FUNC()
332 static inline uint64_t CVMX_DFA_ECLKCFG_FUNC(void)
334 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
335 cvmx_warn("CVMX_DFA_ECLKCFG not supported on this chip\n");
336 return CVMX_ADD_IO_SEG(0x0001180030000200ull);
339 #define CVMX_DFA_ECLKCFG (CVMX_ADD_IO_SEG(0x0001180030000200ull))
341 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
342 #define CVMX_DFA_ERR CVMX_DFA_ERR_FUNC()
343 static inline uint64_t CVMX_DFA_ERR_FUNC(void)
345 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
346 cvmx_warn("CVMX_DFA_ERR not supported on this chip\n");
347 return CVMX_ADD_IO_SEG(0x0001180030000028ull);
350 #define CVMX_DFA_ERR (CVMX_ADD_IO_SEG(0x0001180030000028ull))
352 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
353 #define CVMX_DFA_ERROR CVMX_DFA_ERROR_FUNC()
354 static inline uint64_t CVMX_DFA_ERROR_FUNC(void)
356 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
357 cvmx_warn("CVMX_DFA_ERROR not supported on this chip\n");
358 return CVMX_ADD_IO_SEG(0x0001180037000028ull);
361 #define CVMX_DFA_ERROR (CVMX_ADD_IO_SEG(0x0001180037000028ull))
363 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
364 #define CVMX_DFA_INTMSK CVMX_DFA_INTMSK_FUNC()
365 static inline uint64_t CVMX_DFA_INTMSK_FUNC(void)
367 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
368 cvmx_warn("CVMX_DFA_INTMSK not supported on this chip\n");
369 return CVMX_ADD_IO_SEG(0x0001180037000030ull);
372 #define CVMX_DFA_INTMSK (CVMX_ADD_IO_SEG(0x0001180037000030ull))
374 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
375 #define CVMX_DFA_MEMCFG0 CVMX_DFA_MEMCFG0_FUNC()
376 static inline uint64_t CVMX_DFA_MEMCFG0_FUNC(void)
378 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
379 cvmx_warn("CVMX_DFA_MEMCFG0 not supported on this chip\n");
380 return CVMX_ADD_IO_SEG(0x0001180030000008ull);
383 #define CVMX_DFA_MEMCFG0 (CVMX_ADD_IO_SEG(0x0001180030000008ull))
385 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
386 #define CVMX_DFA_MEMCFG1 CVMX_DFA_MEMCFG1_FUNC()
387 static inline uint64_t CVMX_DFA_MEMCFG1_FUNC(void)
389 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
390 cvmx_warn("CVMX_DFA_MEMCFG1 not supported on this chip\n");
391 return CVMX_ADD_IO_SEG(0x0001180030000010ull);
394 #define CVMX_DFA_MEMCFG1 (CVMX_ADD_IO_SEG(0x0001180030000010ull))
396 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
397 #define CVMX_DFA_MEMCFG2 CVMX_DFA_MEMCFG2_FUNC()
398 static inline uint64_t CVMX_DFA_MEMCFG2_FUNC(void)
400 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
401 cvmx_warn("CVMX_DFA_MEMCFG2 not supported on this chip\n");
402 return CVMX_ADD_IO_SEG(0x0001180030000060ull);
405 #define CVMX_DFA_MEMCFG2 (CVMX_ADD_IO_SEG(0x0001180030000060ull))
407 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
408 #define CVMX_DFA_MEMFADR CVMX_DFA_MEMFADR_FUNC()
409 static inline uint64_t CVMX_DFA_MEMFADR_FUNC(void)
411 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
412 cvmx_warn("CVMX_DFA_MEMFADR not supported on this chip\n");
413 return CVMX_ADD_IO_SEG(0x0001180030000030ull);
416 #define CVMX_DFA_MEMFADR (CVMX_ADD_IO_SEG(0x0001180030000030ull))
418 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
419 #define CVMX_DFA_MEMFCR CVMX_DFA_MEMFCR_FUNC()
420 static inline uint64_t CVMX_DFA_MEMFCR_FUNC(void)
422 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
423 cvmx_warn("CVMX_DFA_MEMFCR not supported on this chip\n");
424 return CVMX_ADD_IO_SEG(0x0001180030000038ull);
427 #define CVMX_DFA_MEMFCR (CVMX_ADD_IO_SEG(0x0001180030000038ull))
429 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
430 #define CVMX_DFA_MEMHIDAT CVMX_DFA_MEMHIDAT_FUNC()
431 static inline uint64_t CVMX_DFA_MEMHIDAT_FUNC(void)
433 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
434 cvmx_warn("CVMX_DFA_MEMHIDAT not supported on this chip\n");
435 return CVMX_ADD_IO_SEG(0x0001370700000000ull);
438 #define CVMX_DFA_MEMHIDAT (CVMX_ADD_IO_SEG(0x0001370700000000ull))
440 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
441 #define CVMX_DFA_MEMRLD CVMX_DFA_MEMRLD_FUNC()
442 static inline uint64_t CVMX_DFA_MEMRLD_FUNC(void)
444 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
445 cvmx_warn("CVMX_DFA_MEMRLD not supported on this chip\n");
446 return CVMX_ADD_IO_SEG(0x0001180030000018ull);
449 #define CVMX_DFA_MEMRLD (CVMX_ADD_IO_SEG(0x0001180030000018ull))
451 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
452 #define CVMX_DFA_NCBCTL CVMX_DFA_NCBCTL_FUNC()
453 static inline uint64_t CVMX_DFA_NCBCTL_FUNC(void)
455 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
456 cvmx_warn("CVMX_DFA_NCBCTL not supported on this chip\n");
457 return CVMX_ADD_IO_SEG(0x0001180030000020ull);
460 #define CVMX_DFA_NCBCTL (CVMX_ADD_IO_SEG(0x0001180030000020ull))
462 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
463 #define CVMX_DFA_PFC0_CNT CVMX_DFA_PFC0_CNT_FUNC()
464 static inline uint64_t CVMX_DFA_PFC0_CNT_FUNC(void)
466 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
467 cvmx_warn("CVMX_DFA_PFC0_CNT not supported on this chip\n");
468 return CVMX_ADD_IO_SEG(0x0001180037000090ull);
471 #define CVMX_DFA_PFC0_CNT (CVMX_ADD_IO_SEG(0x0001180037000090ull))
473 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
474 #define CVMX_DFA_PFC0_CTL CVMX_DFA_PFC0_CTL_FUNC()
475 static inline uint64_t CVMX_DFA_PFC0_CTL_FUNC(void)
477 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
478 cvmx_warn("CVMX_DFA_PFC0_CTL not supported on this chip\n");
479 return CVMX_ADD_IO_SEG(0x0001180037000088ull);
482 #define CVMX_DFA_PFC0_CTL (CVMX_ADD_IO_SEG(0x0001180037000088ull))
484 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
485 #define CVMX_DFA_PFC1_CNT CVMX_DFA_PFC1_CNT_FUNC()
486 static inline uint64_t CVMX_DFA_PFC1_CNT_FUNC(void)
488 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
489 cvmx_warn("CVMX_DFA_PFC1_CNT not supported on this chip\n");
490 return CVMX_ADD_IO_SEG(0x00011800370000A0ull);
493 #define CVMX_DFA_PFC1_CNT (CVMX_ADD_IO_SEG(0x00011800370000A0ull))
495 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
496 #define CVMX_DFA_PFC1_CTL CVMX_DFA_PFC1_CTL_FUNC()
497 static inline uint64_t CVMX_DFA_PFC1_CTL_FUNC(void)
499 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
500 cvmx_warn("CVMX_DFA_PFC1_CTL not supported on this chip\n");
501 return CVMX_ADD_IO_SEG(0x0001180037000098ull);
504 #define CVMX_DFA_PFC1_CTL (CVMX_ADD_IO_SEG(0x0001180037000098ull))
506 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
507 #define CVMX_DFA_PFC2_CNT CVMX_DFA_PFC2_CNT_FUNC()
508 static inline uint64_t CVMX_DFA_PFC2_CNT_FUNC(void)
510 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
511 cvmx_warn("CVMX_DFA_PFC2_CNT not supported on this chip\n");
512 return CVMX_ADD_IO_SEG(0x00011800370000B0ull);
515 #define CVMX_DFA_PFC2_CNT (CVMX_ADD_IO_SEG(0x00011800370000B0ull))
517 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
518 #define CVMX_DFA_PFC2_CTL CVMX_DFA_PFC2_CTL_FUNC()
519 static inline uint64_t CVMX_DFA_PFC2_CTL_FUNC(void)
521 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
522 cvmx_warn("CVMX_DFA_PFC2_CTL not supported on this chip\n");
523 return CVMX_ADD_IO_SEG(0x00011800370000A8ull);
526 #define CVMX_DFA_PFC2_CTL (CVMX_ADD_IO_SEG(0x00011800370000A8ull))
528 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
529 #define CVMX_DFA_PFC3_CNT CVMX_DFA_PFC3_CNT_FUNC()
530 static inline uint64_t CVMX_DFA_PFC3_CNT_FUNC(void)
532 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
533 cvmx_warn("CVMX_DFA_PFC3_CNT not supported on this chip\n");
534 return CVMX_ADD_IO_SEG(0x00011800370000C0ull);
537 #define CVMX_DFA_PFC3_CNT (CVMX_ADD_IO_SEG(0x00011800370000C0ull))
539 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
540 #define CVMX_DFA_PFC3_CTL CVMX_DFA_PFC3_CTL_FUNC()
541 static inline uint64_t CVMX_DFA_PFC3_CTL_FUNC(void)
543 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
544 cvmx_warn("CVMX_DFA_PFC3_CTL not supported on this chip\n");
545 return CVMX_ADD_IO_SEG(0x00011800370000B8ull);
548 #define CVMX_DFA_PFC3_CTL (CVMX_ADD_IO_SEG(0x00011800370000B8ull))
550 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
551 #define CVMX_DFA_PFC_GCTL CVMX_DFA_PFC_GCTL_FUNC()
552 static inline uint64_t CVMX_DFA_PFC_GCTL_FUNC(void)
554 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
555 cvmx_warn("CVMX_DFA_PFC_GCTL not supported on this chip\n");
556 return CVMX_ADD_IO_SEG(0x0001180037000080ull);
559 #define CVMX_DFA_PFC_GCTL (CVMX_ADD_IO_SEG(0x0001180037000080ull))
561 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
562 #define CVMX_DFA_RODT_COMP_CTL CVMX_DFA_RODT_COMP_CTL_FUNC()
563 static inline uint64_t CVMX_DFA_RODT_COMP_CTL_FUNC(void)
565 if (!(OCTEON_IS_MODEL(OCTEON_CN58XX)))
566 cvmx_warn("CVMX_DFA_RODT_COMP_CTL not supported on this chip\n");
567 return CVMX_ADD_IO_SEG(0x0001180030000068ull);
570 #define CVMX_DFA_RODT_COMP_CTL (CVMX_ADD_IO_SEG(0x0001180030000068ull))
572 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
573 #define CVMX_DFA_SBD_DBG0 CVMX_DFA_SBD_DBG0_FUNC()
574 static inline uint64_t CVMX_DFA_SBD_DBG0_FUNC(void)
576 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
577 cvmx_warn("CVMX_DFA_SBD_DBG0 not supported on this chip\n");
578 return CVMX_ADD_IO_SEG(0x0001180030000040ull);
581 #define CVMX_DFA_SBD_DBG0 (CVMX_ADD_IO_SEG(0x0001180030000040ull))
583 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
584 #define CVMX_DFA_SBD_DBG1 CVMX_DFA_SBD_DBG1_FUNC()
585 static inline uint64_t CVMX_DFA_SBD_DBG1_FUNC(void)
587 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
588 cvmx_warn("CVMX_DFA_SBD_DBG1 not supported on this chip\n");
589 return CVMX_ADD_IO_SEG(0x0001180030000048ull);
592 #define CVMX_DFA_SBD_DBG1 (CVMX_ADD_IO_SEG(0x0001180030000048ull))
594 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
595 #define CVMX_DFA_SBD_DBG2 CVMX_DFA_SBD_DBG2_FUNC()
596 static inline uint64_t CVMX_DFA_SBD_DBG2_FUNC(void)
598 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
599 cvmx_warn("CVMX_DFA_SBD_DBG2 not supported on this chip\n");
600 return CVMX_ADD_IO_SEG(0x0001180030000050ull);
603 #define CVMX_DFA_SBD_DBG2 (CVMX_ADD_IO_SEG(0x0001180030000050ull))
605 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
606 #define CVMX_DFA_SBD_DBG3 CVMX_DFA_SBD_DBG3_FUNC()
607 static inline uint64_t CVMX_DFA_SBD_DBG3_FUNC(void)
609 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
610 cvmx_warn("CVMX_DFA_SBD_DBG3 not supported on this chip\n");
611 return CVMX_ADD_IO_SEG(0x0001180030000058ull);
614 #define CVMX_DFA_SBD_DBG3 (CVMX_ADD_IO_SEG(0x0001180030000058ull))
620 * DFA_BIST0 = DFA Bist Status (per-DTC)
627 struct cvmx_dfa_bist0_s
629 #if __BYTE_ORDER == __BIG_ENDIAN
630 uint64_t reserved_29_63 : 35;
631 uint64_t mwb : 1; /**< Bist Results for MWB RAM(s)
632 - 0: GOOD (or bist in progress/never run)
634 uint64_t reserved_25_27 : 3;
635 uint64_t gfb : 1; /**< Bist Results for GFB RAM(s)
636 - 0: GOOD (or bist in progress/never run)
638 uint64_t reserved_18_23 : 6;
639 uint64_t stx : 2; /**< Bist Results for STX RAM(s)
640 - 0: GOOD (or bist in progress/never run)
642 uint64_t reserved_10_15 : 6;
643 uint64_t dtx : 2; /**< Bist Results for DTX RAM(s)
644 - 0: GOOD (or bist in progress/never run)
646 uint64_t reserved_5_7 : 3;
647 uint64_t rdf : 1; /**< Bist Results for RWB[3:0] RAM(s)
648 - 0: GOOD (or bist in progress/never run)
650 uint64_t reserved_1_3 : 3;
651 uint64_t pdb : 1; /**< Bist Results for PDB RAM(s)
652 - 0: GOOD (or bist in progress/never run)
656 uint64_t reserved_1_3 : 3;
658 uint64_t reserved_5_7 : 3;
660 uint64_t reserved_10_15 : 6;
662 uint64_t reserved_18_23 : 6;
664 uint64_t reserved_25_27 : 3;
666 uint64_t reserved_29_63 : 35;
669 struct cvmx_dfa_bist0_s cn63xx;
670 struct cvmx_dfa_bist0_s cn63xxp1;
672 typedef union cvmx_dfa_bist0 cvmx_dfa_bist0_t;
677 * DFA_BIST1 = DFA Bist Status (Globals)
684 struct cvmx_dfa_bist1_s
686 #if __BYTE_ORDER == __BIG_ENDIAN
687 uint64_t reserved_13_63 : 51;
688 uint64_t ram3 : 1; /**< Bist Results for RAM3 RAM
689 - 0: GOOD (or bist in progress/never run)
691 uint64_t ram2 : 1; /**< Bist Results for RAM2 RAM
692 - 0: GOOD (or bist in progress/never run)
694 uint64_t ram1 : 1; /**< Bist Results for RAM1 RAM
695 - 0: GOOD (or bist in progress/never run)
697 uint64_t crq : 1; /**< Bist Results for CRQ RAM
698 - 0: GOOD (or bist in progress/never run)
700 uint64_t gutv : 1; /**< Bist Results for GUTV RAM
701 - 0: GOOD (or bist in progress/never run)
703 uint64_t reserved_5_7 : 3;
704 uint64_t gutp : 1; /**< Bist Results for NCD RAM
705 - 0: GOOD (or bist in progress/never run)
707 uint64_t ncd : 1; /**< Bist Results for NCD RAM
708 - 0: GOOD (or bist in progress/never run)
710 uint64_t gif : 1; /**< Bist Results for GIF RAM
711 - 0: GOOD (or bist in progress/never run)
713 uint64_t gib : 1; /**< Bist Results for GIB RAM
714 - 0: GOOD (or bist in progress/never run)
716 uint64_t gfu : 1; /**< Bist Results for GFU RAM
717 - 0: GOOD (or bist in progress/never run)
725 uint64_t reserved_5_7 : 3;
731 uint64_t reserved_13_63 : 51;
734 struct cvmx_dfa_bist1_s cn63xx;
735 struct cvmx_dfa_bist1_s cn63xxp1;
737 typedef union cvmx_dfa_bist1 cvmx_dfa_bist1_t;
742 * DFA_BST0 = DFA Bist Status
749 struct cvmx_dfa_bst0_s
751 #if __BYTE_ORDER == __BIG_ENDIAN
752 uint64_t reserved_32_63 : 32;
753 uint64_t rdf : 16; /**< Bist Results for RDF[3:0] RAM(s)
754 - 0: GOOD (or bist in progress/never run)
756 uint64_t pdf : 16; /**< Bist Results for PDF[3:0] RAM(s)
757 - 0: GOOD (or bist in progress/never run)
762 uint64_t reserved_32_63 : 32;
765 struct cvmx_dfa_bst0_s cn31xx;
766 struct cvmx_dfa_bst0_s cn38xx;
767 struct cvmx_dfa_bst0_s cn38xxp2;
768 struct cvmx_dfa_bst0_cn58xx
770 #if __BYTE_ORDER == __BIG_ENDIAN
771 uint64_t reserved_20_63 : 44;
772 uint64_t rdf : 4; /**< Bist Results for RDF[3:0] RAM(s)
773 - 0: GOOD (or bist in progress/never run)
775 uint64_t reserved_4_15 : 12;
776 uint64_t pdf : 4; /**< Bist Results for PDF[3:0] RAM(s)
777 - 0: GOOD (or bist in progress/never run)
781 uint64_t reserved_4_15 : 12;
783 uint64_t reserved_20_63 : 44;
786 struct cvmx_dfa_bst0_cn58xx cn58xxp1;
788 typedef union cvmx_dfa_bst0 cvmx_dfa_bst0_t;
793 * DFA_BST1 = DFA Bist Status
800 struct cvmx_dfa_bst1_s
802 #if __BYTE_ORDER == __BIG_ENDIAN
803 uint64_t reserved_23_63 : 41;
804 uint64_t crq : 1; /**< Bist Results for CRQ RAM
805 - 0: GOOD (or bist in progress/never run)
807 uint64_t ifu : 1; /**< Bist Results for IFU RAM
808 - 0: GOOD (or bist in progress/never run)
810 uint64_t gfu : 1; /**< Bist Results for GFU RAM
811 - 0: GOOD (or bist in progress/never run)
813 uint64_t drf : 1; /**< Bist Results for DRF RAM
814 - 0: GOOD (or bist in progress/never run)
816 uint64_t crf : 1; /**< Bist Results for CRF RAM
817 - 0: GOOD (or bist in progress/never run)
819 uint64_t p0_bwb : 1; /**< Bist Results for P0_BWB RAM
820 - 0: GOOD (or bist in progress/never run)
822 uint64_t p1_bwb : 1; /**< Bist Results for P1_BWB RAM
823 - 0: GOOD (or bist in progress/never run)
825 uint64_t p0_brf : 8; /**< Bist Results for P0_BRF RAM
826 - 0: GOOD (or bist in progress/never run)
828 uint64_t p1_brf : 8; /**< Bist Results for P1_BRF RAM
829 - 0: GOOD (or bist in progress/never run)
841 uint64_t reserved_23_63 : 41;
844 struct cvmx_dfa_bst1_cn31xx
846 #if __BYTE_ORDER == __BIG_ENDIAN
847 uint64_t reserved_23_63 : 41;
848 uint64_t crq : 1; /**< Bist Results for CRQ RAM
849 - 0: GOOD (or bist in progress/never run)
851 uint64_t ifu : 1; /**< Bist Results for IFU RAM
852 - 0: GOOD (or bist in progress/never run)
854 uint64_t gfu : 1; /**< Bist Results for GFU RAM
855 - 0: GOOD (or bist in progress/never run)
857 uint64_t drf : 1; /**< Bist Results for DRF RAM
858 - 0: GOOD (or bist in progress/never run)
860 uint64_t crf : 1; /**< Bist Results for CRF RAM
861 - 0: GOOD (or bist in progress/never run)
863 uint64_t reserved_0_17 : 18;
865 uint64_t reserved_0_17 : 18;
871 uint64_t reserved_23_63 : 41;
874 struct cvmx_dfa_bst1_s cn38xx;
875 struct cvmx_dfa_bst1_s cn38xxp2;
876 struct cvmx_dfa_bst1_cn58xx
878 #if __BYTE_ORDER == __BIG_ENDIAN
879 uint64_t reserved_23_63 : 41;
880 uint64_t crq : 1; /**< Bist Results for CRQ RAM
881 - 0: GOOD (or bist in progress/never run)
883 uint64_t ifu : 1; /**< Bist Results for IFU RAM
884 - 0: GOOD (or bist in progress/never run)
886 uint64_t gfu : 1; /**< Bist Results for GFU RAM
887 - 0: GOOD (or bist in progress/never run)
889 uint64_t reserved_19_19 : 1;
890 uint64_t crf : 1; /**< Bist Results for CRF RAM
891 - 0: GOOD (or bist in progress/never run)
893 uint64_t p0_bwb : 1; /**< Bist Results for P0_BWB RAM
894 - 0: GOOD (or bist in progress/never run)
896 uint64_t p1_bwb : 1; /**< Bist Results for P1_BWB RAM
897 - 0: GOOD (or bist in progress/never run)
899 uint64_t p0_brf : 8; /**< Bist Results for P0_BRF RAM
900 - 0: GOOD (or bist in progress/never run)
902 uint64_t p1_brf : 8; /**< Bist Results for P1_BRF RAM
903 - 0: GOOD (or bist in progress/never run)
911 uint64_t reserved_19_19 : 1;
915 uint64_t reserved_23_63 : 41;
918 struct cvmx_dfa_bst1_cn58xx cn58xxp1;
920 typedef union cvmx_dfa_bst1 cvmx_dfa_bst1_t;
925 * Specify the RSL base addresses for the block
927 * DFA_CFG = DFA Configuration
934 struct cvmx_dfa_cfg_s
936 #if __BYTE_ORDER == __BIG_ENDIAN
937 uint64_t reserved_4_63 : 60;
938 uint64_t nrpl_ena : 1; /**< When set, allows the per-node replication feature to be
940 In 36-bit mode: The IWORD0[31:30]=SNREPL field AND
941 bits [21:20] of the Next Node ptr are used in generating
942 the next node address (see OCTEON HRM - DFA Chapter for
943 psuedo-code of DTE next node address generation).
944 NOTE: When NRPL_ENA=1 and IWORD0[TY]=1(36b mode),
945 (regardless of IWORD0[NRPLEN]), the Resultant Word1+
946 [[47:44],[23:20]] = Next Node's [27:20] bits. This allows
947 SW to use the RESERVED bits of the final node for SW
948 caching. Also, if required, SW will use [22:21]=Node
949 Replication to re-start the same graph walk(if graph
950 walk prematurely terminated (ie: DATA_GONE).
951 In 18-bit mode: The IWORD0[31:30]=SNREPL field AND
952 bit [16:14] of the Next Node ptr are used in generating
953 the next node address (see OCTEON HRM - DFA Chapter for
954 psuedo-code of DTE next node address generation).
955 If (IWORD0[NREPLEN]=1 and DFA_CFG[NRPL_ENA]=1) [
956 If next node ptr[16] is set [
957 next node ptr[15:14] indicates the next node repl
958 next node ptr[13:0] indicates the position of the
959 node relative to the first normal node (i.e.
960 IWORD3[Msize] must be added to get the final node)
962 else If next node ptr[16] is not set [
963 next node ptr[15:0] indicates the next node id
967 NOTE: For 18b node replication, MAX node space=64KB(2^16)
968 is used in detecting terminal node space(see HRM for full
970 NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
971 aware of the "per-node" replication. */
972 uint64_t nxor_ena : 1; /**< When set, allows the DTE Instruction IWORD0[NXOREN]
973 to be used to enable/disable the per-node address 'scramble'
974 of the LLM address to lessen the effects of bank conflicts.
975 If IWORD0[NXOREN] is also set, then:
976 In 36-bit mode: The node_Id[7:0] 8-bit value is XORed
977 against the LLM address addr[9:2].
978 In 18-bit mode: The node_id[6:0] 7-bit value is XORed
979 against the LLM address addr[8:2]. (note: we don't address
980 scramble outside the mode's node space).
981 NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
982 aware of the "per-node" address scramble.
983 NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph
984 read/write operations. */
985 uint64_t gxor_ena : 1; /**< When set, the DTE Instruction IWORD0[GXOR]
986 field is used to 'scramble' the LLM address
987 to lessen the effects of bank conflicts.
988 In 36-bit mode: The GXOR[7:0] 8-bit value is XORed
989 against the LLM address addr[9:2].
990 In 18-bit mode: GXOR[6:0] 7-bit value is XORed against
991 the LLM address addr[8:2]. (note: we don't address
992 scramble outside the mode's node space)
993 NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
994 aware of the "per-graph" address scramble.
995 NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph
996 read/write operations. */
997 uint64_t sarb : 1; /**< DFA Source Arbiter Mode
998 Selects the arbitration mode used to select DFA
999 requests issued from either CP2 or the DTE (NCB-CSR
1001 - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
1003 NOTE: This should only be written to a different value
1004 during power-on SW initialization. */
1007 uint64_t gxor_ena : 1;
1008 uint64_t nxor_ena : 1;
1009 uint64_t nrpl_ena : 1;
1010 uint64_t reserved_4_63 : 60;
1013 struct cvmx_dfa_cfg_s cn38xx;
1014 struct cvmx_dfa_cfg_cn38xxp2
1016 #if __BYTE_ORDER == __BIG_ENDIAN
1017 uint64_t reserved_1_63 : 63;
1018 uint64_t sarb : 1; /**< DFA Source Arbiter Mode
1019 Selects the arbitration mode used to select DFA
1020 requests issued from either CP2 or the DTE (NCB-CSR
1022 - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
1024 NOTE: This should only be written to a different value
1025 during power-on SW initialization. */
1028 uint64_t reserved_1_63 : 63;
1031 struct cvmx_dfa_cfg_s cn58xx;
1032 struct cvmx_dfa_cfg_s cn58xxp1;
1034 typedef union cvmx_dfa_cfg cvmx_dfa_cfg_t;
1039 * Specify the RSL base addresses for the block
1041 * DFA_CONFIG = DFA Configuration Register
1045 union cvmx_dfa_config
1048 struct cvmx_dfa_config_s
1050 #if __BYTE_ORDER == __BIG_ENDIAN
1051 uint64_t reserved_9_63 : 55;
1052 uint64_t repl_ena : 1; /**< Replication Mode Enable
1054 When set, enables replication mode performance enhancement
1055 feature. This enables the DFA to communicate address
1056 replication information during memory references to the DFM
1057 (memory controller). This in turn is used by the DFM to support
1058 graph data in multiple banks (or bank sets), so that the least
1059 full bank can be selected to minimize the effects of DDR3 bank
1060 conflicts (ie: tRC=row cycle time).
1061 SWNOTE: Using this mode requires the DFA SW compiler and DFA
1062 driver to be aware of the o63-P2 address replication changes.
1063 This involves changes to the MLOAD/GWALK DFA instruction format
1064 (see: IWORD2.SREPL), as well as changes to node arc and metadata
1065 definitions which now support an additional REPL field.
1066 When clear, replication mode is disabled, and DFA will interpret
1067 o63-P1 DFA instructions and node-arc formats which DO NOT have
1068 address replication information. */
1069 uint64_t clmskcrip : 4; /**< Cluster Cripple Mask
1070 A one in each bit of the mask represents which DTE cluster to
1072 NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0]
1073 is the only bit used.
1074 o2 has 4 clusters, where all CLMSKCRIP mask bits are used.
1075 SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will
1076 be forced into this register at reset. Any fuse bits that
1077 contain '1' will be disallowed during a write and will always
1079 uint64_t cldtecrip : 3; /**< Encoding which represents \#of DTEs to cripple for each
1080 cluster. Typically DTE_CLCRIP=0 which enables all DTEs
1081 within each cluster. However, when the DFA performance
1082 counters are used, SW may want to limit the \#of DTEs
1083 per cluster available, as there are only 4 parallel
1084 performance counters.
1085 DTE_CLCRIP | \#DTEs crippled(per cluster)
1086 ------------+-----------------------------
1088 1 | 1/2 DTE[15:8]:OFF /DTE[7:0]:ON
1089 2 | 1/4 DTE[15:12]:OFF /DTE[11:0]:ON
1090 3 | 3/4 DTE[15:4]:OFF /DTE[3:0]:ON
1091 4 | 1/8 DTE[15:14]:OFF /DTE[13:0]:ON
1092 5 | 5/8 DTE[15:6]:OFF /DTE[5:0]:ON
1093 6 | 3/8 DTE[15:10]:OFF /DTE[9:0]:ON
1094 7 | 7/8 DTE[15:2]:OFF /DTE[1:0]:ON
1095 NOTE: Higher numbered DTEs are crippled first. For instance,
1096 on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then
1097 DTE#s [15:8] within the cluster are crippled and only
1098 DTE#s [7:0] are available.
1099 IMPNOTE: The encodings are done in such a way as to later
1100 be used with fuses (for future o2 revisions which will disable
1101 some \#of DTEs). Blowing a fuse has the effect that there will
1102 always be fewer DTEs available. [ie: we never want a customer
1103 to blow additional fuses to get more DTEs].
1104 SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will
1105 be forced into this register at reset. Any fuse bits that
1106 contain '1' will be disallowed during a write and will always
1108 uint64_t dteclkdis : 1; /**< DFA Clock Disable Source
1109 When SET, the DFA clocks for DTE(thread engine)
1110 operation are disabled (to conserve overall chip clocking
1111 power when the DFA function is not used).
1112 NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR
1113 operations to the DFA (will result in NCB Bus Timeout
1115 NOTE: This should only be written to a different value
1116 during power-on SW initialization.
1117 SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will
1118 be forced into this register at reset. If the fuse bit
1119 contains '1', writes to DTECLKDIS are disallowed and
1120 will always be read as '1'. */
1122 uint64_t dteclkdis : 1;
1123 uint64_t cldtecrip : 3;
1124 uint64_t clmskcrip : 4;
1125 uint64_t repl_ena : 1;
1126 uint64_t reserved_9_63 : 55;
1129 struct cvmx_dfa_config_s cn63xx;
1130 struct cvmx_dfa_config_cn63xxp1
1132 #if __BYTE_ORDER == __BIG_ENDIAN
1133 uint64_t reserved_8_63 : 56;
1134 uint64_t clmskcrip : 4; /**< Cluster Cripple Mask
1135 A one in each bit of the mask represents which DTE cluster to
1137 NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0]
1138 is the only bit used.
1139 o2 has 4 clusters, where all CLMSKCRIP mask bits are used.
1140 SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will
1141 be forced into this register at reset. Any fuse bits that
1142 contain '1' will be disallowed during a write and will always
1144 uint64_t cldtecrip : 3; /**< Encoding which represents \#of DTEs to cripple for each
1145 cluster. Typically DTE_CLCRIP=0 which enables all DTEs
1146 within each cluster. However, when the DFA performance
1147 counters are used, SW may want to limit the \#of DTEs
1148 per cluster available, as there are only 4 parallel
1149 performance counters.
1150 DTE_CLCRIP | \#DTEs crippled(per cluster)
1151 ------------+-----------------------------
1153 1 | 1/2 DTE[15:8]:OFF /DTE[7:0]:ON
1154 2 | 1/4 DTE[15:12]:OFF /DTE[11:0]:ON
1155 3 | 3/4 DTE[15:4]:OFF /DTE[3:0]:ON
1156 4 | 1/8 DTE[15:14]:OFF /DTE[13:0]:ON
1157 5 | 5/8 DTE[15:6]:OFF /DTE[5:0]:ON
1158 6 | 3/8 DTE[15:10]:OFF /DTE[9:0]:ON
1159 7 | 7/8 DTE[15:2]:OFF /DTE[1:0]:ON
1160 NOTE: Higher numbered DTEs are crippled first. For instance,
1161 on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then
1162 DTE#s [15:8] within the cluster are crippled and only
1163 DTE#s [7:0] are available.
1164 IMPNOTE: The encodings are done in such a way as to later
1165 be used with fuses (for future o2 revisions which will disable
1166 some \#of DTEs). Blowing a fuse has the effect that there will
1167 always be fewer DTEs available. [ie: we never want a customer
1168 to blow additional fuses to get more DTEs].
1169 SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will
1170 be forced into this register at reset. Any fuse bits that
1171 contain '1' will be disallowed during a write and will always
1173 uint64_t dteclkdis : 1; /**< DFA Clock Disable Source
1174 When SET, the DFA clocks for DTE(thread engine)
1175 operation are disabled (to conserve overall chip clocking
1176 power when the DFA function is not used).
1177 NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR
1178 operations to the DFA (will result in NCB Bus Timeout
1180 NOTE: This should only be written to a different value
1181 during power-on SW initialization.
1182 SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will
1183 be forced into this register at reset. If the fuse bit
1184 contains '1', writes to DTECLKDIS are disallowed and
1185 will always be read as '1'. */
1187 uint64_t dteclkdis : 1;
1188 uint64_t cldtecrip : 3;
1189 uint64_t clmskcrip : 4;
1190 uint64_t reserved_8_63 : 56;
1194 typedef union cvmx_dfa_config cvmx_dfa_config_t;
1199 * DFA_CONTROL = DFA Control Register
1203 union cvmx_dfa_control
1206 struct cvmx_dfa_control_s
1208 #if __BYTE_ORDER == __BIG_ENDIAN
1209 uint64_t reserved_10_63 : 54;
1210 uint64_t sbdnum : 4; /**< SBD Debug Entry#
1211 *FOR INTERNAL USE ONLY*
1212 DFA Scoreboard debug control
1213 Selects which one of 8 DFA Scoreboard entries is
1214 latched into the DFA_SBD_DBG[0-3] registers. */
1215 uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe
1216 *FOR INTERNAL USE ONLY*
1217 DFA Scoreboard debug control
1218 When written with a '1', the DFA Scoreboard Debug
1219 registers (DFA_SBD_DBG[0-3]) are all locked down.
1220 This allows SW to lock down the contents of the entire
1221 SBD for a single instant in time. All subsequent reads
1222 of the DFA scoreboard registers will return the data
1223 from that instant in time. */
1224 uint64_t reserved_3_4 : 2;
1225 uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode
1226 (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
1227 NOTE: This should only be written to a different value
1228 during power-on SW initialization. */
1229 uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode
1230 (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
1231 NOTE: This should only be written to a different value
1232 during power-on SW initialization. */
1233 uint64_t imode : 1; /**< NCB-Inbound Arbiter
1234 (0=FP [LP=NRQ,HP=NRP], 1=RR)
1235 NOTE: This should only be written to a different value
1236 during power-on SW initialization. */
1241 uint64_t reserved_3_4 : 2;
1242 uint64_t sbdlck : 1;
1243 uint64_t sbdnum : 4;
1244 uint64_t reserved_10_63 : 54;
1247 struct cvmx_dfa_control_s cn63xx;
1248 struct cvmx_dfa_control_s cn63xxp1;
1250 typedef union cvmx_dfa_control cvmx_dfa_control_t;
1255 * DFA_DBELL = DFA Doorbell Register
1258 * NOTE: To write to the DFA_DBELL register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b00.
1259 * To read the DFA_DBELL register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b00.
1261 * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DBELL register do not take effect.
1262 * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DBELL register do not take effect.
1264 union cvmx_dfa_dbell
1267 struct cvmx_dfa_dbell_s
1269 #if __BYTE_ORDER == __BIG_ENDIAN
1270 uint64_t reserved_20_63 : 44;
1271 uint64_t dbell : 20; /**< Represents the cumulative total of pending
1272 DFA instructions which SW has previously written
1273 into the DFA Instruction FIFO (DIF) in main memory.
1274 Each DFA instruction contains a fixed size 32B
1275 instruction word which is executed by the DFA HW.
1276 The DBL register can hold up to 1M-1 (2^20-1)
1277 pending DFA instruction requests.
1278 During a read (by SW), the 'most recent' contents
1279 of the DFA_DBELL register are returned at the time
1280 the NCB-INB bus is driven.
1281 NOTE: Since DFA HW updates this register, its
1282 contents are unpredictable in SW. */
1284 uint64_t dbell : 20;
1285 uint64_t reserved_20_63 : 44;
1288 struct cvmx_dfa_dbell_s cn31xx;
1289 struct cvmx_dfa_dbell_s cn38xx;
1290 struct cvmx_dfa_dbell_s cn38xxp2;
1291 struct cvmx_dfa_dbell_s cn58xx;
1292 struct cvmx_dfa_dbell_s cn58xxp1;
1293 struct cvmx_dfa_dbell_s cn63xx;
1294 struct cvmx_dfa_dbell_s cn63xxp1;
1296 typedef union cvmx_dfa_dbell cvmx_dfa_dbell_t;
1299 * cvmx_dfa_ddr2_addr
1301 * DFA_DDR2_ADDR = DFA DDR2 fclk-domain Memory Address Config Register
1304 * Description: The following registers are used to compose the DFA's DDR2 address into ROW/COL/BNK
1307 union cvmx_dfa_ddr2_addr
1310 struct cvmx_dfa_ddr2_addr_s
1312 #if __BYTE_ORDER == __BIG_ENDIAN
1313 uint64_t reserved_9_63 : 55;
1314 uint64_t rdimm_ena : 1; /**< If there is a need to insert a register chip on the
1315 system (the equivalent of a registered DIMM) to
1316 provide better setup for the command and control bits
1319 0 Registered Mode OFF
1320 1 Registered Mode ON */
1321 uint64_t num_rnks : 2; /**< NUM_RNKS is programmed based on how many ranks there
1322 are in the system. This needs to be programmed correctly
1323 regardless of whether we are in RNK_LO mode or not.
1324 NUM_RNKS \# of Ranks
1329 uint64_t rnk_lo : 1; /**< When this mode is turned on, consecutive addresses
1330 outside the bank boundary
1331 are programmed to go to different ranks in order to
1332 minimize bank conflicts. It is useful in 4-bank DDR2
1333 parts based memory to extend out the \#physical banks
1334 available and minimize bank conflicts.
1335 On 8 bank ddr2 parts, this mode is not very useful
1336 because this mode does come with
1337 a penalty which is that every successive reads that
1338 cross rank boundary will need a 1 cycle bubble
1339 inserted to prevent bus turnaround conflicts.
1343 uint64_t num_colrows : 3; /**< NUM_COLROWS is used to set the MSB of the ROW_ADDR
1344 and the LSB of RANK address when not in RNK_LO mode.
1345 Calculate the sum of \#COL and \#ROW and program the
1346 controller appropriately
1347 RANK_LSB \#COLs + \#ROWs
1348 ------------------------------
1353 - 100-111: RESERVED */
1354 uint64_t num_cols : 2; /**< The Long word address that the controller receives
1355 needs to be converted to Row, Col, Rank and Bank
1356 addresses depending on the memory part's micro arch.
1357 NUM_COL tells the controller how many colum bits
1358 there are and the controller uses this info to map
1359 the LSB of the row address
1365 uint64_t num_cols : 2;
1366 uint64_t num_colrows : 3;
1367 uint64_t rnk_lo : 1;
1368 uint64_t num_rnks : 2;
1369 uint64_t rdimm_ena : 1;
1370 uint64_t reserved_9_63 : 55;
1373 struct cvmx_dfa_ddr2_addr_s cn31xx;
1375 typedef union cvmx_dfa_ddr2_addr cvmx_dfa_ddr2_addr_t;
1380 * DFA_DDR2_BUS = DFA DDR Bus Activity Counter
1383 * Description: This counter counts \# cycles that the memory bus is doing a read/write/command
1384 * Useful to benchmark the bus utilization as a ratio of
1385 * \#Cycles of Data Transfer/\#Cycles since init or
1386 * \#Cycles of Data Transfer/\#Cycles that memory controller is active
1388 union cvmx_dfa_ddr2_bus
1391 struct cvmx_dfa_ddr2_bus_s
1393 #if __BYTE_ORDER == __BIG_ENDIAN
1394 uint64_t reserved_47_63 : 17;
1395 uint64_t bus_cnt : 47; /**< Counter counts the \# cycles of Data transfer */
1397 uint64_t bus_cnt : 47;
1398 uint64_t reserved_47_63 : 17;
1401 struct cvmx_dfa_ddr2_bus_s cn31xx;
1403 typedef union cvmx_dfa_ddr2_bus cvmx_dfa_ddr2_bus_t;
1408 * DFA_DDR2_CFG = DFA DDR2 fclk-domain Memory Configuration \#0 Register
1412 union cvmx_dfa_ddr2_cfg
1415 struct cvmx_dfa_ddr2_cfg_s
1417 #if __BYTE_ORDER == __BIG_ENDIAN
1418 uint64_t reserved_41_63 : 23;
1419 uint64_t trfc : 5; /**< Establishes tRFC(from DDR2 data sheets) in \# of
1422 TRFC(csr) = ROUNDUP[tRFC(data-sheet-ns)/(4 * fclk(ns))]
1424 tRFC(data-sheet-ns) = 127.5ns
1425 Operational Frequency: 533MHz DDR rate
1426 [fclk=266MHz(3.75ns)]
1428 TRFC(csr) = ROUNDUP[127.5ns/(4 * 3.75ns)]
1430 uint64_t mrs_pgm : 1; /**< When clear, the HW initialization sequence fixes
1431 some of the *MRS register bit definitions.
1433 A[14:13] = 0 RESERVED
1434 A[12] = 0 Output Buffers Enabled (FIXED)
1435 A[11] = 0 RDQS Disabled (FIXED)
1436 A[10] = 0 DQSn Enabled (FIXED)
1437 A[9:7] = 0 OCD Not supported (FIXED)
1438 A[6] = 0 RTT Disabled (FIXED)
1439 A[5:3]=DFA_DDR2_TMG[ADDLAT] (if DFA_DDR2_TMG[POCAS]=1)
1440 Additive LATENCY (Programmable)
1441 A[2]=0 RTT Disabled (FIXED)
1442 A[1]=DFA_DDR2_TMG[DIC] (Programmable)
1443 A[0] = 0 DLL Enabled (FIXED)
1445 A[14:13] = 0 RESERVED
1446 A[12] = 0 Fast Active Power Down Mode (FIXED)
1447 A[11:9] = DFA_DDR2_TMG[TWR](Programmable)
1448 A[8] = 1 DLL Reset (FIXED)
1449 A[7] = 0 Test Mode (FIXED)
1450 A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (Programmable)
1451 A[3] = 0 Burst Type(must be 0:Sequential) (FIXED)
1452 A[2:0] = 2 Burst Length=4 (must be 0:Sequential) (FIXED)
1453 When set, the HW initialization sequence sources
1454 the DFA_DDR2_MRS, DFA_DDR2_EMRS registers which are
1455 driven onto the DFA_A[] pins. (this allows the MRS/EMRS
1456 fields to be completely programmable - however care
1457 must be taken by software).
1458 This mode is useful for customers who wish to:
1459 1) override the FIXED definitions(above), or
1460 2) Use a "clamshell mode" of operation where the
1461 address bits(per rank) are swizzled on the
1462 board to reduce stub lengths for optimal
1463 frequency operation.
1464 Use this in combination with DFA_DDR2_CFG[RNK_MSK]
1465 to specify the INIT sequence for each of the 4
1467 uint64_t fpip : 3; /**< Early Fill Programmable Pipe [\#fclks]
1468 This field dictates the \#fclks prior to the arrival
1469 of fill data(in fclk domain), to start the 'early' fill
1470 command pipe (in the eclk domain) so as to minimize the
1471 overall fill latency.
1472 The programmable early fill command signal is synchronized
1473 into the eclk domain, where it is used to pull data out of
1474 asynchronous RAM as fast as possible.
1475 NOTE: A value of FPIP=0 is the 'safest' setting and will
1476 result in the early fill command pipe starting in the
1477 same cycle as the fill data.
1478 General Equation: (for FPIP)
1479 FPIP <= MIN[6, (ROUND_DOWN[6/EF_RATIO] + 1)]
1481 EF_RATIO = ECLK/FCLK Ratio [eclk(MHz)/fclk(MHz)]
1482 Example: FCLK=200MHz/ECLK=600MHz
1483 FPIP = MIN[6, (ROUND_DOWN[6/(600/200))] + 1)]
1485 uint64_t reserved_29_31 : 3;
1486 uint64_t ref_int : 13; /**< Refresh Interval (represented in \#of fclk
1488 Each refresh interval will generate a single
1489 auto-refresh command sequence which implicitly targets
1490 all banks within the device:
1491 Example: For fclk=200MHz(5ns)/400MHz(DDR):
1492 trefint(ns) = [tREFI(max)=3.9us = 3900ns [datasheet]
1493 REF_INT = ROUND_DOWN[(trefint/fclk)]
1494 = ROUND_DOWN[(3900ns/5ns)]
1496 NOTE: This should only be written to a different value
1497 during power-on SW initialization. */
1498 uint64_t reserved_14_15 : 2;
1499 uint64_t tskw : 2; /**< Board Skew (represented in \#fclks)
1500 Represents additional board skew of DQ/DQS.
1501 - 00: board-skew = 0 fclk
1502 - 01: board-skew = 1 fclk
1503 - 10: board-skew = 2 fclk
1504 - 11: board-skew = 3 fclk
1505 NOTE: This should only be written to a different value
1506 during power-on SW initialization. */
1507 uint64_t rnk_msk : 4; /**< Controls the CS_N[3:0] during a) a HW Initialization
1508 sequence (triggered by DFA_DDR2_CFG[INIT]) or
1509 b) during a normal refresh sequence. If
1510 the RNK_MSK[x]=1, the corresponding CS_N[x] is driven.
1511 NOTE: This is required for DRAM used in a
1512 clamshell configuration, since the address lines
1513 carry Mode Register write data that is unique
1514 per rank(or clam). In a clamshell configuration,
1515 the N3K DFA_A[x] pin may be tied into Clam#0's A[x]
1516 and also into Clam#1's 'mirrored' address bit A[y]
1517 (eg: Clam0 sees A[5] and Clam1 sees A[15]).
1518 To support clamshell designs, SW must initiate
1519 separate HW init sequences each unique rank address
1520 mapping. Before each HW init sequence is triggered,
1521 SW must preload the DFA_DDR2_MRS/EMRS registers with
1522 the data that will be driven onto the A[14:0] wires
1523 during the EMRS/MRS mode register write(s).
1524 NOTE: After the final HW initialization sequence has
1525 been triggered, SW must wait 64K eclks before writing
1526 the RNK_MSK[3:0] field = 3'b1111 (so that CS_N[3:0]
1527 is driven during refresh sequences in normal operation.
1528 NOTE: This should only be written to a different value
1529 during power-on SW initialization. */
1530 uint64_t silo_qc : 1; /**< Enables Quarter Cycle move of the Rd sampling window */
1531 uint64_t silo_hc : 1; /**< A combination of SILO_HC, SILO_QC and TSKW
1532 specifies the positioning of the sampling strobe
1533 when receiving read data back from DDR2. This is
1534 done to offset any board trace induced delay on
1535 the DQ and DQS which inherently makes these
1536 asynchronous with respect to the internal clk of
1537 controller. TSKW moves this sampling window by
1538 integer cycles. SILO_QC and HC move this quarter
1539 and half a cycle respectively. */
1540 uint64_t sil_lat : 2; /**< Silo Latency (\#fclks): On reads, determines how many
1541 additional fclks to wait (on top of CASLAT+1) before
1542 pulling data out of the padring silos used for time
1543 domain boundary crossing.
1544 NOTE: This should only be written to a different value
1545 during power-on SW initialization. */
1546 uint64_t bprch : 1; /**< Tristate Enable (back porch) (\#fclks)
1547 On reads, allows user to control the shape of the
1548 tristate disable back porch for the DQ data bus.
1549 This parameter is also very dependent on the
1550 RW_DLY and WR_DLY parameters and care must be
1551 taken when programming these parameters to avoid
1552 data bus contention. Valid range [0..2]
1553 NOTE: This should only be written to a different value
1554 during power-on SW initialization. */
1555 uint64_t fprch : 1; /**< Tristate Enable (front porch) (\#fclks)
1556 On reads, allows user to control the shape of the
1557 tristate disable front porch for the DQ data bus.
1558 This parameter is also very dependent on the
1559 RW_DLY and WR_DLY parameters and care must be
1560 taken when programming these parameters to avoid
1561 data bus contention. Valid range [0..2]
1562 NOTE: This should only be written to a different value
1563 during power-on SW initialization. */
1564 uint64_t init : 1; /**< When a '1' is written (and the previous value was '0'),
1565 the HW init sequence(s) for the LLM Memory Port is
1567 NOTE: To initialize memory, SW must:
1568 1) Enable memory port
1570 2) Wait 200us (to ensure a stable clock
1571 to the DDR2) - as per DDR2 spec.
1572 3) Write a '1' to the INIT which
1573 will initiate a hardware initialization
1575 NOTE: After writing a '1', SW must wait 64K eclk
1576 cycles to ensure the HW init sequence has completed
1577 before writing to ANY of the DFA_DDR2* registers.
1578 NOTE: This should only be written to a different value
1579 during power-on SW initialization. */
1580 uint64_t prtena : 1; /**< Enable DFA Memory
1581 When enabled, this bit lets N3K be the default
1582 driver for DFA-LLM memory port. */
1584 uint64_t prtena : 1;
1588 uint64_t sil_lat : 2;
1589 uint64_t silo_hc : 1;
1590 uint64_t silo_qc : 1;
1591 uint64_t rnk_msk : 4;
1593 uint64_t reserved_14_15 : 2;
1594 uint64_t ref_int : 13;
1595 uint64_t reserved_29_31 : 3;
1597 uint64_t mrs_pgm : 1;
1599 uint64_t reserved_41_63 : 23;
1602 struct cvmx_dfa_ddr2_cfg_s cn31xx;
1604 typedef union cvmx_dfa_ddr2_cfg cvmx_dfa_ddr2_cfg_t;
1607 * cvmx_dfa_ddr2_comp
1609 * DFA_DDR2_COMP = DFA DDR2 I/O PVT Compensation Configuration
1612 * Description: The following are registers to program the DDR2 PLL and DLL
1614 union cvmx_dfa_ddr2_comp
1617 struct cvmx_dfa_ddr2_comp_s
1619 #if __BYTE_ORDER == __BIG_ENDIAN
1620 uint64_t dfa__pctl : 4; /**< DFA DDR pctl from compensation circuit
1621 Internal DBG only */
1622 uint64_t dfa__nctl : 4; /**< DFA DDR nctl from compensation circuit
1623 Internal DBG only */
1624 uint64_t reserved_9_55 : 47;
1625 uint64_t pctl_csr : 4; /**< Compensation control bits */
1626 uint64_t nctl_csr : 4; /**< Compensation control bits */
1627 uint64_t comp_bypass : 1; /**< Compensation Bypass */
1629 uint64_t comp_bypass : 1;
1630 uint64_t nctl_csr : 4;
1631 uint64_t pctl_csr : 4;
1632 uint64_t reserved_9_55 : 47;
1633 uint64_t dfa__nctl : 4;
1634 uint64_t dfa__pctl : 4;
1637 struct cvmx_dfa_ddr2_comp_s cn31xx;
1639 typedef union cvmx_dfa_ddr2_comp cvmx_dfa_ddr2_comp_t;
1642 * cvmx_dfa_ddr2_emrs
1644 * DFA_DDR2_EMRS = DDR2 EMRS Register(s) EMRS1[14:0], EMRS1_OCD[14:0]
1645 * Description: This register contains the data driven onto the Address[14:0] lines during DDR INIT
1646 * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init
1647 * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these
1648 * registers during the HW initialization sequence (see N3K specific restrictions in notes below).
1649 * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature.
1652 * For DDR-II please consult your device's data sheet for further details:
1655 union cvmx_dfa_ddr2_emrs
1658 struct cvmx_dfa_ddr2_emrs_s
1660 #if __BYTE_ORDER == __BIG_ENDIAN
1661 uint64_t reserved_31_63 : 33;
1662 uint64_t emrs1_ocd : 15; /**< Memory Address[14:0] during "EMRS1 (OCD Calibration)"
1663 step \#12a "EMRS OCD Default Command" A[9:7]=111
1664 of DDR2 HW initialization sequence.
1665 (See JEDEC DDR2 specification (JESD79-2):
1666 Power Up and initialization sequence).
1667 A[14:13] = 0, RESERVED
1668 A[12] = 0, Output Buffers Enabled
1669 A[11] = 0, RDQS Disabled (we do not support RDQS)
1670 A[10] = 0, DQSn Enabled
1671 A[9:7] = 7, OCD Calibration Mode Default
1672 A[6] = 0, ODT Disabled
1673 A[5:3]=DFA_DDR2_TMG[ADDLAT] Additive LATENCY (Default 0)
1674 A[2]=0 Termination Res RTT (ODT off Default)
1675 [A6,A2] = 0 -> ODT Disabled
1676 1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved
1677 A[1]=0 Normal Output Driver Imp mode
1678 (1 - weak ie., 60% of normal drive strength)
1679 A[0] = 0 DLL Enabled */
1680 uint64_t reserved_15_15 : 1;
1681 uint64_t emrs1 : 15; /**< Memory Address[14:0] during:
1682 a) Step \#7 "EMRS1 to enable DLL (A[0]=0)"
1683 b) Step \#12b "EMRS OCD Calibration Mode Exit"
1684 steps of DDR2 HW initialization sequence.
1685 (See JEDEC DDR2 specification (JESD79-2): Power Up and
1686 initialization sequence).
1687 A[14:13] = 0, RESERVED
1688 A[12] = 0, Output Buffers Enabled
1689 A[11] = 0, RDQS Disabled (we do not support RDQS)
1690 A[10] = 0, DQSn Enabled
1691 A[9:7] = 0, OCD Calibration Mode exit/maintain
1692 A[6] = 0, ODT Disabled
1693 A[5:3]=DFA_DDR2_TMG[ADDLAT] Additive LATENCY (Default 0)
1694 A[2]=0 Termination Res RTT (ODT off Default)
1695 [A6,A2] = 0 -> ODT Disabled
1696 1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved
1697 A[1]=0 Normal Output Driver Imp mode
1698 (1 - weak ie., 60% of normal drive strength)
1699 A[0] = 0 DLL Enabled */
1701 uint64_t emrs1 : 15;
1702 uint64_t reserved_15_15 : 1;
1703 uint64_t emrs1_ocd : 15;
1704 uint64_t reserved_31_63 : 33;
1707 struct cvmx_dfa_ddr2_emrs_s cn31xx;
1709 typedef union cvmx_dfa_ddr2_emrs cvmx_dfa_ddr2_emrs_t;
1712 * cvmx_dfa_ddr2_fcnt
1714 * DFA_DDR2_FCNT = DFA FCLK Counter
1717 * Description: This FCLK cycle counter gets going after memory has been initialized
1719 union cvmx_dfa_ddr2_fcnt
1722 struct cvmx_dfa_ddr2_fcnt_s
1724 #if __BYTE_ORDER == __BIG_ENDIAN
1725 uint64_t reserved_47_63 : 17;
1726 uint64_t fcyc_cnt : 47; /**< Counter counts FCLK cycles or \# cycles that the memory
1727 controller has requests queued up depending on FCNT_MODE
1728 If FCNT_MODE = 0, this counter counts the \# FCLK cycles
1729 If FCNT_MODE = 1, this counter counts the \# cycles the
1730 controller is active with memory requests. */
1732 uint64_t fcyc_cnt : 47;
1733 uint64_t reserved_47_63 : 17;
1736 struct cvmx_dfa_ddr2_fcnt_s cn31xx;
1738 typedef union cvmx_dfa_ddr2_fcnt cvmx_dfa_ddr2_fcnt_t;
1743 * DFA_DDR2_MRS = DDR2 MRS Register(s) MRS_DLL[14:0], MRS[14:0]
1744 * Description: This register contains the data driven onto the Address[14:0] lines during DDR INIT
1745 * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init
1746 * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these
1747 * registers during the HW initialization sequence (see N3K specific restrictions in notes below).
1748 * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature.
1751 * For DDR-II please consult your device's data sheet for further details:
1754 union cvmx_dfa_ddr2_mrs
1757 struct cvmx_dfa_ddr2_mrs_s
1759 #if __BYTE_ORDER == __BIG_ENDIAN
1760 uint64_t reserved_31_63 : 33;
1761 uint64_t mrs : 15; /**< Memory Address[14:0] during "MRS without resetting
1762 DLL A[8]=0" step of HW initialization sequence.
1763 (See JEDEC DDR2 specification (JESD79-2): Power Up
1764 and initialization sequence - Step \#11).
1765 A[14:13] = 0, RESERVED
1766 A[12] = 0, Fast Active Power Down Mode
1767 A[11:9] = DFA_DDR2_TMG[TWR]
1768 A[8] = 0, for DLL Reset
1769 A[7] =0 Test Mode (must be 0 for normal operation)
1770 A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (default 4)
1771 A[3]=0 Burst Type(must be 0:Sequential)
1772 A[2:0]=2 Burst Length=4(default) */
1773 uint64_t reserved_15_15 : 1;
1774 uint64_t mrs_dll : 15; /**< Memory Address[14:0] during "MRS for DLL_RESET A[8]=1"
1775 step of HW initialization sequence.
1776 (See JEDEC DDR2 specification (JESD79-2): Power Up
1777 and initialization sequence - Step \#8).
1778 A[14:13] = 0, RESERVED
1779 A[12] = 0, Fast Active Power Down Mode
1780 A[11:9] = DFA_DDR2_TMG[TWR]
1781 A[8] = 1, for DLL Reset
1782 A[7] = 0 Test Mode (must be 0 for normal operation)
1783 A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (default 4)
1784 A[3] = 0 Burst Type(must be 0:Sequential)
1785 A[2:0] = 2 Burst Length=4(default) */
1787 uint64_t mrs_dll : 15;
1788 uint64_t reserved_15_15 : 1;
1790 uint64_t reserved_31_63 : 33;
1793 struct cvmx_dfa_ddr2_mrs_s cn31xx;
1795 typedef union cvmx_dfa_ddr2_mrs cvmx_dfa_ddr2_mrs_t;
1800 * DFA_DDR2_OPT = DFA DDR2 Optimization Registers
1803 * Description: The following are registers to tweak certain parameters to boost performance
1805 union cvmx_dfa_ddr2_opt
1808 struct cvmx_dfa_ddr2_opt_s
1810 #if __BYTE_ORDER == __BIG_ENDIAN
1811 uint64_t reserved_10_63 : 54;
1812 uint64_t max_read_batch : 5; /**< Maximum number of consecutive read to service before
1813 allowing write to interrupt. */
1814 uint64_t max_write_batch : 5; /**< Maximum number of consecutive writes to service before
1815 allowing reads to interrupt. */
1817 uint64_t max_write_batch : 5;
1818 uint64_t max_read_batch : 5;
1819 uint64_t reserved_10_63 : 54;
1822 struct cvmx_dfa_ddr2_opt_s cn31xx;
1824 typedef union cvmx_dfa_ddr2_opt cvmx_dfa_ddr2_opt_t;
1829 * DFA_DDR2_PLL = DFA DDR2 PLL and DLL Configuration
1832 * Description: The following are registers to program the DDR2 PLL and DLL
1834 union cvmx_dfa_ddr2_pll
1837 struct cvmx_dfa_ddr2_pll_s
1839 #if __BYTE_ORDER == __BIG_ENDIAN
1840 uint64_t pll_setting : 17; /**< Internal Debug Use Only */
1841 uint64_t reserved_32_46 : 15;
1842 uint64_t setting90 : 5; /**< Contains the setting of DDR DLL; Internal DBG only */
1843 uint64_t reserved_21_26 : 6;
1844 uint64_t dll_setting : 5; /**< Contains the open loop setting value for the DDR90 delay
1846 uint64_t dll_byp : 1; /**< DLL Bypass. When set, the DDR90 DLL is bypassed and
1847 the DLL behaves in Open Loop giving a fixed delay
1848 set by DLL_SETTING */
1849 uint64_t qdll_ena : 1; /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
1850 erst deassertion will reset the DDR 90 DLL. Allow
1851 200 micro seconds for Lock before DDR Init. */
1852 uint64_t bw_ctl : 4; /**< Internal Use Only - for Debug */
1853 uint64_t bw_upd : 1; /**< Internal Use Only - for Debug */
1854 uint64_t pll_div2 : 1; /**< PLL Output is further divided by 2. Useful for slow
1855 fclk frequencies where the PLL may be out of range. */
1856 uint64_t reserved_7_7 : 1;
1857 uint64_t pll_ratio : 5; /**< Bits <6:2> sets the clk multiplication ratio
1858 If the fclk frequency desired is less than 260MHz
1859 (lower end saturation point of the pll), write 2x
1860 the ratio desired in this register and set PLL_DIV2 */
1861 uint64_t pll_bypass : 1; /**< PLL Bypass. Uses the ref_clk without multiplication. */
1862 uint64_t pll_init : 1; /**< Need a 0 to 1 pulse on this CSR to get the DFA
1863 Clk Generator Started. Write this register before
1864 starting anything. Allow 200 uS for PLL Lock before
1867 uint64_t pll_init : 1;
1868 uint64_t pll_bypass : 1;
1869 uint64_t pll_ratio : 5;
1870 uint64_t reserved_7_7 : 1;
1871 uint64_t pll_div2 : 1;
1872 uint64_t bw_upd : 1;
1873 uint64_t bw_ctl : 4;
1874 uint64_t qdll_ena : 1;
1875 uint64_t dll_byp : 1;
1876 uint64_t dll_setting : 5;
1877 uint64_t reserved_21_26 : 6;
1878 uint64_t setting90 : 5;
1879 uint64_t reserved_32_46 : 15;
1880 uint64_t pll_setting : 17;
1883 struct cvmx_dfa_ddr2_pll_s cn31xx;
1885 typedef union cvmx_dfa_ddr2_pll cvmx_dfa_ddr2_pll_t;
1890 * DFA_DDR2_TMG = DFA DDR2 Memory Timing Config Register
1893 * Description: The following are registers to program the DDR2 memory timing parameters.
1895 union cvmx_dfa_ddr2_tmg
1898 struct cvmx_dfa_ddr2_tmg_s
1900 #if __BYTE_ORDER == __BIG_ENDIAN
1901 uint64_t reserved_47_63 : 17;
1902 uint64_t fcnt_mode : 1; /**< If FCNT_MODE = 0, this counter counts the \# FCLK cycles
1903 If FCNT_MODE = 1, this counter counts the \# cycles the
1904 controller is active with memory requests. */
1905 uint64_t cnt_clr : 1; /**< Clears the FCLK Cyc & Bus Util counter */
1906 uint64_t cavmipo : 1; /**< RESERVED */
1907 uint64_t ctr_rst : 1; /**< Reset oneshot pulse for refresh counter & Perf counters
1908 SW should first write this field to a one to clear
1909 & then write to a zero for normal operation */
1910 uint64_t odt_rtt : 2; /**< DDR2 Termination Resistor Setting
1911 These two bits are loaded into the RTT
1912 portion of the EMRS register bits A6 & A2. If DDR2's
1913 termination (for the memory's DQ/DQS/DM pads) is not
1914 desired, set it to 00. If it is, chose between
1915 01 for 75 ohm and 10 for 150 ohm termination.
1917 01 = 75 ohm Termination
1918 10 = 150 ohm Termination
1919 11 = 50 ohm Termination */
1920 uint64_t dqsn_ena : 1; /**< For DDR-II Mode, DIC[1] is used to load into EMRS
1921 bit 10 - DQSN Enable/Disable field. By default, we
1922 program the DDR's to drive the DQSN also. Set it to
1923 1 if DQSN should be Hi-Z.
1926 uint64_t dic : 1; /**< Drive Strength Control:
1927 For DDR-I/II Mode, DIC[0] is
1928 loaded into the Extended Mode Register (EMRS) A1 bit
1929 during initialization. (see DDR-I data sheet EMRS
1933 uint64_t r2r_slot : 1; /**< A 1 on this register will force the controller to
1934 slot a bubble between every reads */
1935 uint64_t tfaw : 5; /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1
1936 Four Access Window time. Relevant only in
1938 TFAW = 5'b0 for DDR2-4bank
1939 TFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1 in DDR2-8bank */
1940 uint64_t twtr : 4; /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)]
1941 Last Wr Data to Rd Command time.
1942 (Represented in fclk cycles)
1948 - 1000-1111: RESERVED */
1949 uint64_t twr : 3; /**< DDR Write Recovery time (tWR). Last Wr Brst to Prech
1950 This is not a direct encoding of the value. Its
1951 programmed as below per DDR2 spec. The decimal number
1952 on the right is RNDUP(tWR(ns) / clkFreq)
1960 - 110-111: RESERVED */
1961 uint64_t trp : 4; /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)]
1962 (Represented in fclk cycles)
1968 - 1000-1111: RESERVED
1969 When using parts with 8 banks (DFA_CFG->MAX_BNK
1970 is 1), load tRP cycles + 1 into this register. */
1971 uint64_t tras : 5; /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)]
1972 (Represented in fclk cycles)
1974 - 00000-0001: RESERVED
1978 - 10101-11111: RESERVED */
1979 uint64_t trrd : 3; /**< tRRD cycles: ACT-ACT timing parameter for different
1980 banks. (Represented in fclk cycles)
1988 - 110-111: RESERVED */
1989 uint64_t trcd : 4; /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)]
1990 (Represented in fclk cycles)
1993 - 0001: 2 (2 is the smallest value allowed)
1997 - 1110-1111: RESERVED */
1998 uint64_t addlat : 3; /**< When in Posted CAS mode ADDLAT needs to be programmed
2000 ADDLAT \#additional latency cycles
2002 001 1 (tRCD = 2 fclk's)
2003 010 2 (tRCD = 3 fclk's)
2004 011 3 (tRCD = 4 fclk's)
2005 100 4 (tRCD = 5 fclk's)
2006 101 5 (tRCD = 6 fclk's)
2007 110 6 (tRCD = 7 fclk's)
2008 111 7 (tRCD = 8 fclk's) */
2009 uint64_t pocas : 1; /**< Posted CAS mode. When 1, we use DDR2's Posted CAS
2010 feature. When using this mode, ADDLAT needs to be
2011 programmed as well */
2012 uint64_t caslat : 3; /**< CAS Latency in \# fclk Cycles
2013 CASLAT \# CAS latency cycles
2020 uint64_t tmrd : 2; /**< tMRD Cycles
2021 (Represented in fclk tCYC)
2022 For DDR2, its TYP 2*tCYC)
2027 uint64_t ddr2t : 1; /**< When 2T mode is turned on, command signals are
2028 setup a cycle ahead of when the CS is enabled
2029 and kept for a total of 2 cycles. This mode is
2030 enabled in higher speeds when there is difficulty
2031 meeting setup. Performance could
2032 be negatively affected in 2T mode */
2036 uint64_t caslat : 3;
2038 uint64_t addlat : 3;
2046 uint64_t r2r_slot : 1;
2048 uint64_t dqsn_ena : 1;
2049 uint64_t odt_rtt : 2;
2050 uint64_t ctr_rst : 1;
2051 uint64_t cavmipo : 1;
2052 uint64_t cnt_clr : 1;
2053 uint64_t fcnt_mode : 1;
2054 uint64_t reserved_47_63 : 17;
2057 struct cvmx_dfa_ddr2_tmg_s cn31xx;
2059 typedef union cvmx_dfa_ddr2_tmg cvmx_dfa_ddr2_tmg_t;
2064 * DFA_DEBUG0 = DFA Scoreboard Debug \#0 Register
2065 * *FOR INTERNAL USE ONLY*
2066 * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down.
2067 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
2069 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
2070 * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
2073 union cvmx_dfa_debug0
2076 struct cvmx_dfa_debug0_s
2078 #if __BYTE_ORDER == __BIG_ENDIAN
2079 uint64_t sbd0 : 64; /**< DFA ScoreBoard \#0 Data
2080 (DFA Scoreboard Debug)
2081 [63:38] (26) rptr[28:3]: Result Base Pointer (QW-aligned)
2082 [37:22] (16) Cumulative Result Write Counter (for HDR write)
2083 [21] (1) Waiting for GRdRsp EOT
2084 [20] (1) Waiting for GRdReq Issue (to NRQ)
2085 [19] (1) GLPTR/GLCNT Valid
2086 [18] (1) Completion Mark Detected
2087 [17:15] (3) Completion Code [0=PDGONE/1=PERR/2=RFULL/3=TERM]
2088 [14] (1) Completion Detected
2089 [13] (1) Waiting for HDR RWrCmtRsp
2090 [12] (1) Waiting for LAST RESULT RWrCmtRsp
2091 [11] (1) Waiting for HDR RWrReq
2092 [10] (1) Waiting for RWrReq
2093 [9] (1) Waiting for WQWrReq issue
2094 [8] (1) Waiting for PRdRsp EOT
2095 [7] (1) Waiting for PRdReq Issue (to NRQ)
2096 [6] (1) Packet Data Valid
2098 [4] (1) WQ Done Point (either WQWrReq issued (for WQPTR<>0) OR HDR RWrCmtRsp)
2099 [3] (1) Resultant write STF/P Mode
2100 [2] (1) Packet Data LDT mode
2107 struct cvmx_dfa_debug0_s cn63xx;
2108 struct cvmx_dfa_debug0_s cn63xxp1;
2110 typedef union cvmx_dfa_debug0 cvmx_dfa_debug0_t;
2115 * DFA_DEBUG1 = DFA Scoreboard Debug \#1 Register
2116 * *FOR INTERNAL USE ONLY*
2117 * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down.
2118 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
2120 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
2121 * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
2124 union cvmx_dfa_debug1
2127 struct cvmx_dfa_debug1_s
2129 #if __BYTE_ORDER == __BIG_ENDIAN
2130 uint64_t sbd1 : 64; /**< DFA ScoreBoard \#1 Data
2131 DFA Scoreboard Debug Data
2133 [55:16] (40) Packet Data Pointer
2134 [15:0] (16) Packet Data Counter */
2139 struct cvmx_dfa_debug1_s cn63xx;
2140 struct cvmx_dfa_debug1_s cn63xxp1;
2142 typedef union cvmx_dfa_debug1 cvmx_dfa_debug1_t;
2147 * DFA_DEBUG2 = DFA Scoreboard Debug \#2 Register
2149 * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down.
2150 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
2152 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
2153 * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
2156 union cvmx_dfa_debug2
2159 struct cvmx_dfa_debug2_s
2161 #if __BYTE_ORDER == __BIG_ENDIAN
2162 uint64_t sbd2 : 64; /**< DFA ScoreBoard \#2 Data
2164 [44:42] (3) Instruction Type
2165 [41:5] (37) rwptr[39:3]: Result Write Pointer
2166 [4:0] (5) prwcnt[4:0]: Pending Result Write Counter */
2171 struct cvmx_dfa_debug2_s cn63xx;
2172 struct cvmx_dfa_debug2_s cn63xxp1;
2174 typedef union cvmx_dfa_debug2 cvmx_dfa_debug2_t;
2179 * DFA_DEBUG3 = DFA Scoreboard Debug \#3 Register
2181 * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down.
2182 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
2184 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
2185 * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an
2188 union cvmx_dfa_debug3
2191 struct cvmx_dfa_debug3_s
2193 #if __BYTE_ORDER == __BIG_ENDIAN
2194 uint64_t sbd3 : 64; /**< DFA ScoreBoard \#3 Data
2195 [63:52] (11) rptr[39:29]: Result Base Pointer (QW-aligned)
2196 [52:16] (37) glptr[39:3]: Gather List Pointer
2197 [15:0] (16) glcnt Gather List Counter */
2202 struct cvmx_dfa_debug3_s cn63xx;
2203 struct cvmx_dfa_debug3_s cn63xxp1;
2205 typedef union cvmx_dfa_debug3 cvmx_dfa_debug3_t;
2210 * DFA_DIFCTL = DFA Instruction FIFO (DIF) Control Register
2213 * NOTE: To write to the DFA_DIFCTL register, a device would issue an IOBST directed at the DFA with addr[34:32]=3'b110.
2214 * To read the DFA_DIFCTL register, a device would issue an IOBLD64 directed at the DFA with addr[34:32]=3'b110.
2216 * NOTE: This register is intended to ONLY be written once (at power-up). Any future writes could
2217 * cause the DFA and FPA HW to become unpredictable.
2219 * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFCTL register do not take effect.
2220 * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFCTL register do not take effect.
2222 union cvmx_dfa_difctl
2225 struct cvmx_dfa_difctl_s
2227 #if __BYTE_ORDER == __BIG_ENDIAN
2228 uint64_t reserved_20_63 : 44;
2229 uint64_t dwbcnt : 8; /**< Represents the \# of cache lines in the instruction
2230 buffer that may be dirty and should not be
2231 written-back to memory when the instruction
2232 chunk is returned to the Free Page list.
2233 NOTE: Typically SW will want to mark all DFA
2234 Instruction memory returned to the Free Page list
2235 as DWB (Don't WriteBack), therefore SW should
2236 seed this register as:
2237 DFA_DIFCTL[DWBCNT] = (DFA_DIFCTL[SIZE] + 4)/4 */
2238 uint64_t pool : 3; /**< Represents the 3bit buffer pool-id used by DFA HW
2239 when the DFA instruction chunk is recycled back
2240 to the Free Page List maintained by the FPA HW
2241 (once the DFA instruction has been issued). */
2242 uint64_t size : 9; /**< Represents the \# of 32B instructions contained
2243 within each DFA instruction chunk. At Power-on,
2244 SW will seed the SIZE register with a fixed
2245 chunk-size. (Must be at least 3)
2246 DFA HW uses this field to determine the size
2247 of each DFA instruction chunk, in order to:
2248 a) determine when to read the next DFA
2249 instruction chunk pointer which is
2250 written by SW at the end of the current
2251 DFA instruction chunk (see DFA description
2252 of next chunk buffer Ptr for format).
2253 b) determine when a DFA instruction chunk
2254 can be returned to the Free Page List
2255 maintained by the FPA HW. */
2259 uint64_t dwbcnt : 8;
2260 uint64_t reserved_20_63 : 44;
2263 struct cvmx_dfa_difctl_s cn31xx;
2264 struct cvmx_dfa_difctl_s cn38xx;
2265 struct cvmx_dfa_difctl_s cn38xxp2;
2266 struct cvmx_dfa_difctl_s cn58xx;
2267 struct cvmx_dfa_difctl_s cn58xxp1;
2268 struct cvmx_dfa_difctl_s cn63xx;
2269 struct cvmx_dfa_difctl_s cn63xxp1;
2271 typedef union cvmx_dfa_difctl cvmx_dfa_difctl_t;
2276 * DFA_DIFRDPTR = DFA Instruction FIFO (DIF) RDPTR Register
2279 * NOTE: To write to the DFA_DIFRDPTR register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b01.
2280 * To read the DFA_DIFRDPTR register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b01.
2282 * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFRDPTR register do not take effect.
2283 * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFRDPTR register do not take effect.
2285 union cvmx_dfa_difrdptr
2288 struct cvmx_dfa_difrdptr_s
2290 #if __BYTE_ORDER == __BIG_ENDIAN
2291 uint64_t reserved_40_63 : 24;
2292 uint64_t rdptr : 35; /**< Represents the 32B-aligned address of the current
2293 instruction in the DFA Instruction FIFO in main
2294 memory. The RDPTR must be seeded by software at
2295 boot time, and is then maintained thereafter
2297 During the seed write (by SW), RDPTR[6:5]=0,
2298 since DFA instruction chunks must be 128B aligned.
2299 During a read (by SW), the 'most recent' contents
2300 of the RDPTR register are returned at the time
2301 the NCB-INB bus is driven.
2302 NOTE: Since DFA HW updates this register, its
2303 contents are unpredictable in SW (unless
2304 its guaranteed that no new DoorBell register
2305 writes have occurred and the DoorBell register is
2307 uint64_t reserved_0_4 : 5;
2309 uint64_t reserved_0_4 : 5;
2310 uint64_t rdptr : 35;
2311 uint64_t reserved_40_63 : 24;
2314 struct cvmx_dfa_difrdptr_cn31xx
2316 #if __BYTE_ORDER == __BIG_ENDIAN
2317 uint64_t reserved_36_63 : 28;
2318 uint64_t rdptr : 31; /**< Represents the 32B-aligned address of the current
2319 instruction in the DFA Instruction FIFO in main
2320 memory. The RDPTR must be seeded by software at
2321 boot time, and is then maintained thereafter
2323 During the seed write (by SW), RDPTR[6:5]=0,
2324 since DFA instruction chunks must be 128B aligned.
2325 During a read (by SW), the 'most recent' contents
2326 of the RDPTR register are returned at the time
2327 the NCB-INB bus is driven.
2328 NOTE: Since DFA HW updates this register, its
2329 contents are unpredictable in SW (unless
2330 its guaranteed that no new DoorBell register
2331 writes have occurred and the DoorBell register is
2333 uint64_t reserved_0_4 : 5;
2335 uint64_t reserved_0_4 : 5;
2336 uint64_t rdptr : 31;
2337 uint64_t reserved_36_63 : 28;
2340 struct cvmx_dfa_difrdptr_cn31xx cn38xx;
2341 struct cvmx_dfa_difrdptr_cn31xx cn38xxp2;
2342 struct cvmx_dfa_difrdptr_cn31xx cn58xx;
2343 struct cvmx_dfa_difrdptr_cn31xx cn58xxp1;
2344 struct cvmx_dfa_difrdptr_s cn63xx;
2345 struct cvmx_dfa_difrdptr_s cn63xxp1;
2347 typedef union cvmx_dfa_difrdptr cvmx_dfa_difrdptr_t;
2352 * DFA_DTCFADR = DFA DTC Failing Address Register
2354 * Description: DFA Node Cache Failing Address/Control Error Capture information
2355 * This register contains useful information to help in isolating a Node Cache RAM failure.
2356 * NOTE: The first detected PERR failure is captured in DFA_DTCFADR (locked down), until the
2357 * corresponding PERR Interrupt is cleared by writing one (W1C). (see: DFA_ERR[DC0PERR[2:0]]).
2359 union cvmx_dfa_dtcfadr
2362 struct cvmx_dfa_dtcfadr_s
2364 #if __BYTE_ORDER == __BIG_ENDIAN
2365 uint64_t reserved_44_63 : 20;
2366 uint64_t ram3fadr : 12; /**< DFA RAM3 Failing Address
2367 If DFA_ERR[DC0PERR<2>]=1, this field indicates the
2368 failing RAM3 Address. The failing address is locked
2369 down until the DC0PERR<2> W1C occurs. */
2370 uint64_t reserved_25_31 : 7;
2371 uint64_t ram2fadr : 9; /**< DFA RAM2 Failing Address
2372 If DFA_ERR[DC0PERR<1>]=1, this field indicates the
2373 failing RAM2 Address. The failing address is locked
2374 down until the DC0PERR<1> W1C occurs. */
2375 uint64_t reserved_14_15 : 2;
2376 uint64_t ram1fadr : 14; /**< DFA RAM1 Failing Address
2377 If DFA_ERR[DC0PERR<0>]=1, this field indicates the
2378 failing RAM1 Address. The failing address is locked
2379 down until the DC0PERR<0> W1C occurs. */
2381 uint64_t ram1fadr : 14;
2382 uint64_t reserved_14_15 : 2;
2383 uint64_t ram2fadr : 9;
2384 uint64_t reserved_25_31 : 7;
2385 uint64_t ram3fadr : 12;
2386 uint64_t reserved_44_63 : 20;
2389 struct cvmx_dfa_dtcfadr_s cn63xx;
2390 struct cvmx_dfa_dtcfadr_s cn63xxp1;
2392 typedef union cvmx_dfa_dtcfadr cvmx_dfa_dtcfadr_t;
2397 * Specify the RSL base addresses for the block
2399 * DFA_ECLKCFG = DFA eclk-domain Configuration Registers
2403 union cvmx_dfa_eclkcfg
2406 struct cvmx_dfa_eclkcfg_s
2408 #if __BYTE_ORDER == __BIG_ENDIAN
2409 uint64_t reserved_19_63 : 45;
2410 uint64_t sbdnum : 3; /**< SBD Debug Entry#
2411 For internal use only. (DFA Scoreboard debug)
2412 Selects which one of 8 DFA Scoreboard entries is
2413 latched into the DFA_SBD_DBG[0-3] registers. */
2414 uint64_t reserved_15_15 : 1;
2415 uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe
2416 For internal use only. (DFA Scoreboard debug)
2417 When written with a '1', the DFA Scoreboard Debug
2418 registers (DFA_SBD_DBG[0-3]) are all locked down.
2419 This allows SW to lock down the contents of the entire
2420 SBD for a single instant in time. All subsequent reads
2421 of the DFA scoreboard registers will return the data
2422 from that instant in time. */
2423 uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode
2424 DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
2425 NOTE: This should only be written to a different value
2426 during power-on SW initialization. */
2427 uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode
2428 DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
2429 NOTE: This should only be written to a different value
2430 during power-on SW initialization. */
2431 uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode
2432 (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
2433 NOTE: This should only be written to a different value
2434 during power-on SW initialization. */
2435 uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode
2436 (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
2437 NOTE: This should only be written to a different value
2438 during power-on SW initialization. */
2439 uint64_t imode : 1; /**< NCB-Inbound Arbiter
2440 (0=FP [LP=NRQ,HP=NRP], 1=RR)
2441 NOTE: This should only be written to a different value
2442 during power-on SW initialization. */
2443 uint64_t sarb : 1; /**< DFA Source Arbiter Mode
2444 Selects the arbitration mode used to select DFA requests
2445 issued from either CP2 or the DTE (NCB-CSR or DFA HW engine).
2446 - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
2448 NOTE: This should only be written to a different value
2449 during power-on SW initialization. */
2450 uint64_t reserved_3_7 : 5;
2451 uint64_t dteclkdis : 1; /**< DFA DTE Clock Disable
2452 When SET, the DFA clocks for DTE(thread engine)
2453 operation are disabled.
2454 NOTE: When SET, SW MUST NEVER issue ANY operations to
2455 the DFA via the NCB Bus. All DFA Operations must be
2456 issued solely through the CP2 interface. */
2457 uint64_t maxbnk : 1; /**< Maximum Banks per-device (used by the address mapper
2458 when extracting address bits for the memory bank#.
2460 - 1: 8 banks/device */
2461 uint64_t dfa_frstn : 1; /**< Hold this 0 until the DFA DDR PLL and DLL lock
2462 and then write a 1. A 1 on this register deasserts
2463 the internal frst_n. Refer to DFA_DDR2_PLL registers for more
2464 startup information.
2465 Startup sequence if DFA interface needs to be ON:
2466 After valid power up,
2467 Write DFA_DDR2_PLL-> PLL_RATIO & PLL_DIV2 & PLL_BYPASS
2468 to the appropriate values
2470 Write a 1 DFA_DDR2_PLL -> PLL_INIT
2471 Wait 100 microseconds
2472 Write a 1 to DFA_DDR2_PLL -> QDLL_ENA
2473 Wait 10 microseconds
2474 Write a 1 to this register DFA_FRSTN to pull DFA out of
2476 Now the DFA block is ready to be initialized (follow the
2477 DDR init sequence). */
2479 uint64_t dfa_frstn : 1;
2480 uint64_t maxbnk : 1;
2481 uint64_t dteclkdis : 1;
2482 uint64_t reserved_3_7 : 5;
2487 uint64_t dtmode : 1;
2488 uint64_t dcmode : 1;
2489 uint64_t sbdlck : 1;
2490 uint64_t reserved_15_15 : 1;
2491 uint64_t sbdnum : 3;
2492 uint64_t reserved_19_63 : 45;
2495 struct cvmx_dfa_eclkcfg_s cn31xx;
2497 typedef union cvmx_dfa_eclkcfg cvmx_dfa_eclkcfg_t;
2502 * DFA_ERR = DFA ERROR Register
2509 struct cvmx_dfa_err_s
2511 #if __BYTE_ORDER == __BIG_ENDIAN
2512 uint64_t reserved_33_63 : 31;
2513 uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit.
2514 When set, doorbell overflow conditions are reported. */
2515 uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit
2516 When set, the 20b accumulated doorbell register
2517 had overflowed (SW wrote too many doorbell requests).
2518 If the DBLINA had previously been enabled(set),
2519 an interrupt will be posted. Software can clear
2520 the interrupt by writing a 1 to this register bit.
2521 NOTE: Detection of a Doorbell Register overflow
2522 is a catastrophic error which may leave the DFA
2523 HW in an unrecoverable state. */
2524 uint64_t cp2pina : 1; /**< CP2 LW Mode Parity Error Interrupt Enable bit.
2525 When set, all PP-generated LW Mode read
2526 transactions which encounter a parity error (across
2527 the 36b of data) are reported. */
2528 uint64_t cp2perr : 1; /**< PP-CP2 Parity Error Detected - Status bit
2529 When set, a parity error had been detected for a
2530 PP-generated LW Mode read transaction.
2531 If the CP2PINA had previously been enabled(set),
2532 an interrupt will be posted. Software can clear
2533 the interrupt by writing a 1 to this register bit.
2534 See also: DFA_MEMFADR CSR which contains more data
2535 about the memory address/control to help isolate
2537 uint64_t cp2parena : 1; /**< CP2 LW Mode Parity Error Enable
2538 When set, all PP-generated LW Mode read
2539 transactions which encounter a parity error (across
2540 the 36b of data) are reported.
2541 NOTE: This signal must only be written to a different
2542 value when there are no PP-CP2 transactions
2543 (preferrably during power-on software initialization). */
2544 uint64_t dtepina : 1; /**< DTE Parity Error Interrupt Enable bit
2545 (for 18b SIMPLE mode ONLY).
2546 When set, all DTE-generated 18b SIMPLE Mode read
2547 transactions which encounter a parity error (across
2548 the 17b of data) are reported. */
2549 uint64_t dteperr : 1; /**< DTE Parity Error Detected (for 18b SIMPLE mode ONLY)
2550 When set, all DTE-generated 18b SIMPLE Mode read
2551 transactions which encounter a parity error (across
2552 the 17b of data) are reported. */
2553 uint64_t dteparena : 1; /**< DTE Parity Error Enable (for 18b SIMPLE mode ONLY)
2554 When set, all DTE-generated 18b SIMPLE Mode read
2555 transactions which encounter a parity error (across
2556 the 17b of data) are reported.
2557 NOTE: This signal must only be written to a different
2558 value when there are no DFA thread engines active
2559 (preferrably during power-on). */
2560 uint64_t dtesyn : 7; /**< DTE 29b ECC Failing 6bit Syndrome
2561 When DTESBE or DTEDBE are set, this field contains
2562 the failing 7b ECC syndrome. */
2563 uint64_t dtedbina : 1; /**< DTE 29b Double Bit Error Interrupt Enable bit
2564 When set, an interrupt is posted for any DTE-generated
2565 36b SIMPLE Mode read which encounters a double bit
2567 uint64_t dtesbina : 1; /**< DTE 29b Single Bit Error Interrupt Enable bit
2568 When set, an interrupt is posted for any DTE-generated
2569 36b SIMPLE Mode read which encounters a single bit
2570 error (which is also corrected). */
2571 uint64_t dtedbe : 1; /**< DTE 29b Double Bit Error Detected - Status bit
2572 When set, a double bit error had been detected
2573 for a DTE-generated 36b SIMPLE Mode read transaction.
2574 The DTESYN contains the failing syndrome.
2575 If the DTEDBINA had previously been enabled(set),
2576 an interrupt will be posted. Software can clear
2577 the interrupt by writing a 1 to this register bit.
2578 See also: DFA_MEMFADR CSR which contains more data
2579 about the memory address/control to help isolate
2581 NOTE: DTE-generated 18b SIMPLE Mode Read transactions
2582 do not participate in ECC check/correct). */
2583 uint64_t dtesbe : 1; /**< DTE 29b Single Bit Error Corrected - Status bit
2584 When set, a single bit error had been detected and
2585 corrected for a DTE-generated 36b SIMPLE Mode read
2587 If the DTEDBE=0, then the DTESYN contains the
2588 failing syndrome (used during correction).
2589 NOTE: DTE-generated 18b SIMPLE Mode Read
2590 transactions do not participate in ECC check/correct).
2591 If the DTESBINA had previously been enabled(set),
2592 an interrupt will be posted. Software can clear
2593 the interrupt by writing a 1 to this register bit.
2594 See also: DFA_MEMFADR CSR which contains more data
2595 about the memory address/control to help isolate
2597 uint64_t dteeccena : 1; /**< DTE 29b ECC Enable (for 36b SIMPLE mode ONLY)
2598 When set, 29b ECC is enabled on all DTE-generated
2599 36b SIMPLE Mode read transactions.
2600 NOTE: This signal must only be written to a different
2601 value when there are no DFA thread engines active
2602 (preferrably during power-on software initialization). */
2603 uint64_t cp2syn : 8; /**< PP-CP2 QW ECC Failing 8bit Syndrome
2604 When CP2SBE or CP2DBE are set, this field contains
2605 the failing ECC 8b syndrome.
2606 Refer to CP2ECCENA. */
2607 uint64_t cp2dbina : 1; /**< PP-CP2 Double Bit Error Interrupt Enable bit
2608 When set, an interrupt is posted for any PP-generated
2609 QW Mode read which encounters a double bit error.
2611 uint64_t cp2sbina : 1; /**< PP-CP2 Single Bit Error Interrupt Enable bit
2612 When set, an interrupt is posted for any PP-generated
2613 QW Mode read which encounters a single bit error
2614 (which is also corrected).
2616 uint64_t cp2dbe : 1; /**< PP-CP2 Double Bit Error Detected - Status bit
2617 When set, a double bit error had been detected
2618 for a PP-generated QW Mode read transaction.
2619 The CP2SYN contains the failing syndrome.
2620 NOTE: PP-generated LW Mode Read transactions
2621 do not participate in ECC check/correct).
2623 If the CP2DBINA had previously been enabled(set),
2624 an interrupt will be posted. Software can clear
2625 the interrupt by writing a 1 to this register bit.
2626 See also: DFA_MEMFADR CSR which contains more data
2627 about the memory address/control to help isolate
2629 uint64_t cp2sbe : 1; /**< PP-CP2 Single Bit Error Corrected - Status bit
2630 When set, a single bit error had been detected and
2631 corrected for a PP-generated QW Mode read
2633 If the CP2DBE=0, then the CP2SYN contains the
2634 failing syndrome (used during correction).
2636 If the CP2SBINA had previously been enabled(set),
2637 an interrupt will be posted. Software can clear
2638 the interrupt by writing a 1 to this register bit.
2639 See also: DFA_MEMFADR CSR which contains more data
2640 about the memory address/control to help isolate
2642 NOTE: PP-generated LW Mode Read transactions
2643 do not participate in ECC check/correct). */
2644 uint64_t cp2eccena : 1; /**< PP-CP2 QW ECC Enable (for QW Mode transactions)
2645 When set, 8bit QW ECC is enabled on all PP-generated
2646 QW Mode read transactions, CP2SBE and
2647 CP2DBE may be set, and CP2SYN may be filled.
2648 NOTE: This signal must only be written to a different
2649 value when there are no PP-CP2 transactions
2650 (preferrably during power-on software initialization).
2651 NOTE: QW refers to a 64-bit LLM Load/Store (intiated
2652 by a processor core). LW refers to a 36-bit load/store. */
2654 uint64_t cp2eccena : 1;
2655 uint64_t cp2sbe : 1;
2656 uint64_t cp2dbe : 1;
2657 uint64_t cp2sbina : 1;
2658 uint64_t cp2dbina : 1;
2659 uint64_t cp2syn : 8;
2660 uint64_t dteeccena : 1;
2661 uint64_t dtesbe : 1;
2662 uint64_t dtedbe : 1;
2663 uint64_t dtesbina : 1;
2664 uint64_t dtedbina : 1;
2665 uint64_t dtesyn : 7;
2666 uint64_t dteparena : 1;
2667 uint64_t dteperr : 1;
2668 uint64_t dtepina : 1;
2669 uint64_t cp2parena : 1;
2670 uint64_t cp2perr : 1;
2671 uint64_t cp2pina : 1;
2672 uint64_t dblovf : 1;
2673 uint64_t dblina : 1;
2674 uint64_t reserved_33_63 : 31;
2677 struct cvmx_dfa_err_s cn31xx;
2678 struct cvmx_dfa_err_s cn38xx;
2679 struct cvmx_dfa_err_s cn38xxp2;
2680 struct cvmx_dfa_err_s cn58xx;
2681 struct cvmx_dfa_err_s cn58xxp1;
2683 typedef union cvmx_dfa_err cvmx_dfa_err_t;
2688 * DFA_ERROR = DFA ERROR Register
2692 union cvmx_dfa_error
2695 struct cvmx_dfa_error_s
2697 #if __BYTE_ORDER == __BIG_ENDIAN
2698 uint64_t reserved_17_63 : 47;
2699 uint64_t cndrd : 1; /**< If DC0PERR[0]=1 indicating a RAM1 Parity error,
2700 this additional bit further specifies that the
2701 RAM1 parity error was detected during a CND-RD
2702 (Cache Node Metadata Read).
2704 For CNDRD Parity Error, the previous CNA arc fetch
2705 information is written to RWORD1+ as follows:
2706 RWORD1+[NTYPE]=MNODE
2707 RWORD1+[NDNID]=cna.ndnid
2708 RWORD1+[NHMSK]=cna.hmsk
2709 RWORD1+[NNPTR]=cna.nnptr[13:0] */
2710 uint64_t reserved_4_15 : 12;
2711 uint64_t dc0perr : 3; /**< RAM[3:1] Parity Error Detected from Node Cluster \#0
2712 See also DFA_DTCFADR register which contains the
2713 failing addresses for the internal node cache RAMs. */
2714 uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit
2715 When set, the 20b accumulated doorbell register
2716 had overflowed (SW wrote too many doorbell requests).
2717 If the DBLINA had previously been enabled(set),
2718 an interrupt will be posted. Software can clear
2719 the interrupt by writing a 1 to this register bit.
2720 NOTE: Detection of a Doorbell Register overflow
2721 is a catastrophic error which may leave the DFA
2722 HW in an unrecoverable state. */
2724 uint64_t dblovf : 1;
2725 uint64_t dc0perr : 3;
2726 uint64_t reserved_4_15 : 12;
2728 uint64_t reserved_17_63 : 47;
2731 struct cvmx_dfa_error_s cn63xx;
2732 struct cvmx_dfa_error_s cn63xxp1;
2734 typedef union cvmx_dfa_error cvmx_dfa_error_t;
2739 * DFA_INTMSK = DFA ERROR Interrupt Mask Register
2743 union cvmx_dfa_intmsk
2746 struct cvmx_dfa_intmsk_s
2748 #if __BYTE_ORDER == __BIG_ENDIAN
2749 uint64_t reserved_4_63 : 60;
2750 uint64_t dc0pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */
2751 uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit.
2752 When set, doorbell overflow conditions are reported. */
2754 uint64_t dblina : 1;
2755 uint64_t dc0pena : 3;
2756 uint64_t reserved_4_63 : 60;
2759 struct cvmx_dfa_intmsk_s cn63xx;
2760 struct cvmx_dfa_intmsk_s cn63xxp1;
2762 typedef union cvmx_dfa_intmsk cvmx_dfa_intmsk_t;
2767 * DFA_MEMCFG0 = DFA Memory Configuration
2771 union cvmx_dfa_memcfg0
2774 struct cvmx_dfa_memcfg0_s
2776 #if __BYTE_ORDER == __BIG_ENDIAN
2777 uint64_t reserved_32_63 : 32;
2778 uint64_t rldqck90_rst : 1; /**< RLDCK90 and RLDQK90 DLL SW Reset
2779 When written with a '1' the RLDCK90 and RLDQK90 DLL are
2781 uint64_t rldck_rst : 1; /**< RLDCK Zero Delay DLL(Clock Generator) SW Reset
2782 When written with a '1' the RLDCK zero delay DLL is in
2784 uint64_t clkdiv : 2; /**< RLDCLK Divisor Select
2785 - 0: RLDx_CK_H/L = Core Clock /2
2786 - 1: RESERVED (must not be used)
2787 - 2: RLDx_CK_H/L = Core Clock /3
2788 - 3: RLDx_CK_H/L = Core Clock /4
2789 The DFA LLM interface(s) are tied to the core clock
2790 frequency through this programmable clock divisor.
2792 Core Clock(MHz) | DFA-LLM Clock(MHz) | CLKDIV
2793 -----------------+--------------------+--------
2794 800 | 400/(800-DDR) | /2
2795 1000 | 333/(666-DDR) | /3
2796 800 | 200/(400-DDR) | /4
2797 NOTE: This value MUST BE programmed BEFORE doing a
2798 Hardware init sequence (see: DFA_MEMCFG0[INIT_Px] bits). */
2799 uint64_t lpp_ena : 1; /**< PP Linear Port Addressing Mode Enable
2800 When enabled, PP-core LLM accesses to the lower-512MB
2801 LLM address space are sent to the single DFA port
2802 which is enabled. NOTE: If LPP_ENA=1, only
2803 one DFA RLDRAM port may be enabled for RLDRAM accesses
2804 (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set).
2805 PP-core LLM accesses to the upper-512MB LLM address
2806 space are sent to the other 'disabled' DFA port.
2807 SW RESTRICTION: If LPP_ENA=1, then only one DFA port
2808 may be enabled for RLDRAM accesses (ie: ENA_P0 and
2809 ENA_P1 CAN NEVER BOTH be set).
2810 NOTE: This bit is used to allow PP-Core LLM accesses to a
2811 disabled port, such that each port can be sequentially
2812 addressed (ie: disable LW address interleaving).
2813 Enabling this bit allows BOTH PORTs to be active and
2814 sequentially addressable. The single port that is
2815 enabled(ENA_Px) will respond to the low-512MB LLM address
2816 space, and the other 'disabled' port will respond to the
2817 high-512MB LLM address space.
2819 - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses)
2820 - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses).
2822 If LPP_ENA=1 and SW DOES NOT initialize the disabled port
2823 (ie: INIT_Px=0->1), then refreshes and the HW init
2824 sequence WILL NOT occur for the disabled port.
2825 If LPP_ENA=1 and SW does initialize the disabled port
2826 (INIT_Px=0->1 with ENA_Px=0), then refreshes and
2827 the HW init sequence WILL occur to the disabled port. */
2828 uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization
2829 sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
2830 b) during a normal refresh sequence. If
2831 the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
2832 NOTE: This is required for DRAM used in a
2833 clamshell configuration, since the address lines
2834 carry Mode Register write data that is unique
2835 per bunk(or clam). In a clamshell configuration,
2836 The N3K A[x] pin may be tied into Clam#0's A[x]
2837 and also into Clam#1's 'mirrored' address bit A[y]
2838 (eg: Clam0 sees A[5] and Clam1 sees A[15]).
2839 To support clamshell designs, SW must initiate
2840 two separate HW init sequences for the two bunks
2841 (or clams) . Before each HW init sequence is triggered,
2842 SW must preload the DFA_MEMRLD[22:0] with the data
2843 that will be driven onto the A[22:0] wires during
2844 an MRS mode register write.
2845 NOTE: After the final HW initialization sequence has
2846 been triggered, SW must wait 64K eclks before writing
2847 the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
2848 driven during refresh sequences in normal operation.
2849 NOTE: This should only be written to a different value
2850 during power-on SW initialization. */
2851 uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'),
2852 the HW init sequence(s) for Memory Port \#0 is
2854 NOTE: To initialize memory, SW must:
2855 1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended
2857 [legal values 0: DIV2 2: DIV3 3: DIV4]
2858 2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST]
2859 and DFA_MEM_CFG0[RLDQCK90_RST] field at
2860 the SAME TIME. This step puts all three DLLs in
2861 SW reset (RLDCK, RLDCK90, RLDQK90 DLLs).
2862 3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field.
2863 This step takes the RLDCK DLL out of soft-reset so
2864 that the DLL can generate the RLDx_CK_H/L clock pins.
2865 4) Wait 1ms (for RLDCK DLL to achieve lock)
2866 5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field.
2867 This step takes the RLDCK90 DLL AND RLDQK90 DLL out
2869 6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock)
2870 7) Enable memory port(s): ENA_P0=1/ENA_P1=1
2871 8) Wait 100us (to ensure a stable clock
2872 to the RLDRAMs) - as per RLDRAM spec.
2873 - - - - - Hardware Initialization Sequence - - - - -
2874 9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s)
2875 intended to be initialized.
2876 10) Write a '1' to the corresponding INIT_Px which
2877 will initiate a hardware initialization
2878 sequence to that'specific' port.
2879 11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles.
2880 [to ensure the HW init sequence has completed
2881 before writing to ANY of the DFA_MEM* registers]
2882 - - - - - Hardware Initialization Sequence - - - - -
2883 12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable
2884 refreshes to BOTH bunks.
2885 NOTE: In some cases (where the address wires are routed
2886 differently between the front and back 'bunks'),
2887 SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to
2888 control the Hardware initialization sequence for a
2889 'specific bunk'. In these cases, SW would setup the
2890 BUNK_INIT and repeat Steps \#9-11 for each bunk/port.
2891 NOTE: This should only be written to a different value
2892 during power-on SW initialization.
2893 NOTE: DFA Memory Port#0 corresponds to the Octeon
2895 uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'),
2896 the HW init sequence(s) for Memory Port \#1 is
2898 NOTE: To initialize memory, SW must:
2899 1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended
2901 [legal values 0: DIV2 2: DIV3 3: DIV4]
2902 2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST]
2903 and DFA_MEM_CFG0[RLDQCK90_RST] field at
2904 the SAME TIME. This step puts all three DLLs in
2905 SW reset (RLDCK, RLDCK90, RLDQK90 DLLs).
2906 3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field.
2907 This step takes the RLDCK DLL out of soft-reset so
2908 that the DLL can generate the RLDx_CK_H/L clock pins.
2909 4) Wait 1ms (for RLDCK DLL to achieve lock)
2910 5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field.
2911 This step takes the RLDCK90 DLL AND RLDQK90 DLL out
2913 6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock)
2914 7) Enable memory port(s) ENA_P0=1/ENA_P1=1
2915 8) Wait 100us (to ensure a stable clock
2916 to the RLDRAMs) - as per RLDRAM spec.
2917 - - - - - Hardware Initialization Sequence - - - - -
2918 9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s)
2919 intended to be initialized.
2920 10) Write a '1' to the corresponding INIT_Px which
2921 will initiate a hardware initialization
2922 sequence to that'specific' port.
2923 11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles.
2924 [to ensure the HW init sequence has completed
2925 before writing to ANY of the DFA_MEM* registers]
2926 - - - - - Hardware Initialization Sequence - - - - -
2927 12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable
2928 refreshes to BOTH bunks.
2929 NOTE: In some cases (where the address wires are routed
2930 differently between the front and back 'bunks'),
2931 SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to
2932 control the Hardware initialization sequence for a
2933 'specific bunk'. In these cases, SW would setup the
2934 BUNK_INIT and repeat Steps \#9-11 for each bunk/port.
2935 NOTE: This should only be written to a different value
2936 during power-on SW initialization.
2937 NOTE: DFA Memory Port#1 corresponds to the Octeon
2939 uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted
2940 if back to back reads are issued to different physical
2941 bunks. This is to avoid DQ data bus collisions when
2942 references cross between physical bunks.
2943 [NOTE: the physical bunk address boundary is determined
2945 NOTE: This should only be written to a different value
2946 during power-on SW initialization. */
2947 uint64_t pbunk : 3; /**< Physical Bunk address bit pointer.
2948 Specifies which address bit within the Longword
2949 Memory address MA[23:0] is used to determine the
2951 [RLD_CS0_N corresponds to physical bunk \#0, and
2952 RLD_CS1_N corresponds to physical bunk \#1].
2953 - 000: CS0_N = MA[19]/CS1_N = !MA[19]
2954 - 001: CS0_N = MA[20]/CS1_N = !MA[20]
2955 - 010: CS0_N = MA[21]/CS1_N = !MA[21]
2956 - 011: CS0_N = MA[22]/CS1_N = !MA[22]
2957 - 100: CS0_N = MA[23]/CS1_N = !MA[23]
2958 - 101-111: CS0_N = 0 /CS1_N = 1
2960 To build out a 128MB DFA memory, 4x 32Mx9
2961 parts could be used to fill out TWO physical
2962 bunks (clamshell configuration). Each (of the
2963 two) physical bunks contains 2x 32Mx9 = 16Mx36.
2964 Each RLDRAM device also contains 8 internal banks,
2965 therefore the memory Address is 16M/8banks = 2M
2966 addresses/bunk (2^21). In this case, MA[21] would
2967 select the physical bunk.
2968 NOTE: This should only be written to a different value
2969 during power-on SW initialization.
2970 be used to determine the Chip Select(s). */
2971 uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst)
2972 NOTE: RLDRAM-II MUST USE BLEN=0(2-burst) */
2973 uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks)
2974 On reads, allows user to control the shape of the
2975 tristate disable back porch for the DQ data bus.
2976 This parameter is also very dependent on the
2977 RW_DLY and WR_DLY parameters and care must be
2978 taken when programming these parameters to avoid
2979 data bus contention. Valid range [0..2]
2980 NOTE: This should only be written to a different value
2981 during power-on SW initialization. */
2982 uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks)
2983 On reads, allows user to control the shape of the
2984 tristate disable front porch for the DQ data bus.
2985 This parameter is also very dependent on the
2986 RW_DLY and WR_DLY parameters and care must be
2987 taken when programming these parameters to avoid
2988 data bus contention. Valid range [0..2]
2989 NOTE: This should only be written to a different value
2990 during power-on SW initialization. */
2991 uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks):
2992 Determines \#mclk cycles to insert when controller
2993 switches from write to read. This allows programmer
2994 to control the data bus contention.
2995 For RLDRAM-II(BL2): (TBL=1)
2996 WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
2997 NOTE: This should only be written to a different value
2998 during power-on SW initialization.
2999 NOTE: For aggressive(performance optimal) designs,
3000 the WR_DLY 'may' be tuned down(-1) if bus fight
3001 on W->R transitions is not pronounced. */
3002 uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks):
3003 Determines \#mclk cycles to insert when controller
3004 switches from read to write. This allows programmer
3005 to control the data bus contention.
3006 For RLDRAM-II(BL2): (TBL=1)
3007 RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
3008 NOTE: This should only be written to a different value
3009 during power-on SW initialization.
3010 NOTE: For aggressive(performance optimal) designs,
3011 the RW_DLY 'may' be tuned down(-1) if bus fight
3012 on R->W transitions is not pronounced. */
3013 uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many
3014 additional dclks to wait (on top of tRL+1) before
3015 pulling data out of the padring silos used for time
3016 domain boundary crossing.
3017 NOTE: This should only be written to a different value
3018 during power-on SW initialization. */
3019 uint64_t mtype : 1; /**< FCRAM-II Memory Type
3020 *** CN58XX UNSUPPORTED *** */
3021 uint64_t reserved_2_2 : 1;
3022 uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0
3023 When enabled, this bit lets N3K be the default
3024 driver for memory port \#0.
3025 NOTE: a customer is at
3026 liberty to enable either Port#0 or Port#1 or both.
3027 NOTE: Once a port has been disabled, it MUST NEVER
3028 be re-enabled. [the only way to enable a port is
3029 through a chip reset].
3030 NOTE: DFA Memory Port#0 corresponds to the Octeon
3032 uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1
3033 When enabled, this bit lets N3K be the default
3034 driver for memory port \#1.
3035 NOTE: a customer is at
3036 liberty to enable either Port#0 or Port#1 or both.
3037 NOTE: Once a port has been disabled, it MUST NEVER
3038 be re-enabled. [the only way to enable a port is
3039 through a chip reset].
3040 NOTE: DFA Memory Port#1 corresponds to the Octeon
3043 uint64_t ena_p1 : 1;
3044 uint64_t ena_p0 : 1;
3045 uint64_t reserved_2_2 : 1;
3047 uint64_t sil_lat : 2;
3048 uint64_t rw_dly : 4;
3049 uint64_t wr_dly : 4;
3054 uint64_t r2r_pbunk : 1;
3055 uint64_t init_p1 : 1;
3056 uint64_t init_p0 : 1;
3057 uint64_t bunk_init : 2;
3058 uint64_t lpp_ena : 1;
3059 uint64_t clkdiv : 2;
3060 uint64_t rldck_rst : 1;
3061 uint64_t rldqck90_rst : 1;
3062 uint64_t reserved_32_63 : 32;
3065 struct cvmx_dfa_memcfg0_cn38xx
3067 #if __BYTE_ORDER == __BIG_ENDIAN
3068 uint64_t reserved_28_63 : 36;
3069 uint64_t lpp_ena : 1; /**< PP Linear Port Addressing Mode Enable
3070 When enabled, PP-core LLM accesses to the lower-512MB
3071 LLM address space are sent to the single DFA port
3072 which is enabled. NOTE: If LPP_ENA=1, only
3073 one DFA RLDRAM port may be enabled for RLDRAM accesses
3074 (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set).
3075 PP-core LLM accesses to the upper-512MB LLM address
3076 space are sent to the other 'disabled' DFA port.
3077 SW RESTRICTION: If LPP_ENA=1, then only one DFA port
3078 may be enabled for RLDRAM accesses (ie: ENA_P0 and
3079 ENA_P1 CAN NEVER BOTH be set).
3080 NOTE: This bit is used to allow PP-Core LLM accesses to a
3081 disabled port, such that each port can be sequentially
3082 addressed (ie: disable LW address interleaving).
3083 Enabling this bit allows BOTH PORTs to be active and
3084 sequentially addressable. The single port that is
3085 enabled(ENA_Px) will respond to the low-512MB LLM address
3086 space, and the other 'disabled' port will respond to the
3087 high-512MB LLM address space.
3089 - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses)
3090 - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses).
3092 If LPP_ENA=1 and SW DOES NOT initialize the disabled port
3093 (ie: INIT_Px=0->1), then refreshes and the HW init
3094 sequence WILL NOT occur for the disabled port.
3095 If LPP_ENA=1 and SW does initialize the disabled port
3096 (INIT_Px=0->1 with ENA_Px=0), then refreshes and
3097 the HW init sequence WILL occur to the disabled port. */
3098 uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization
3099 sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
3100 b) during a normal refresh sequence. If
3101 the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
3102 NOTE: This is required for DRAM used in a
3103 clamshell configuration, since the address lines
3104 carry Mode Register write data that is unique
3105 per bunk(or clam). In a clamshell configuration,
3106 The N3K A[x] pin may be tied into Clam#0's A[x]
3107 and also into Clam#1's 'mirrored' address bit A[y]
3108 (eg: Clam0 sees A[5] and Clam1 sees A[15]).
3109 To support clamshell designs, SW must initiate
3110 two separate HW init sequences for the two bunks
3111 (or clams) . Before each HW init sequence is triggered,
3112 SW must preload the DFA_MEMRLD[22:0] with the data
3113 that will be driven onto the A[22:0] wires during
3114 an MRS mode register write.
3115 NOTE: After the final HW initialization sequence has
3116 been triggered, SW must wait 64K eclks before writing
3117 the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
3118 driven during refresh sequences in normal operation.
3119 NOTE: This should only be written to a different value
3120 during power-on SW initialization.
3121 NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE
3122 initialized independently. In other words, a HW init
3123 must be done for Bunk#0, and then another HW init
3124 must be done for Bunk#1 at power-on. */
3125 uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'),
3126 the HW init sequence(s) for Memory Port \#0 is
3128 NOTE: To initialize memory, SW must:
3129 1) Enable memory port(s):
3130 a) ENA_P1=1 (single port in pass 1) OR
3131 b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
3132 2) Wait 100us (to ensure a stable clock
3133 to the RLDRAMs) - as per RLDRAM spec.
3134 3) Write a '1' to the corresponding INIT_Px which
3135 will initiate a hardware initialization
3137 NOTE: After writing a '1', SW must wait 64K eclk
3138 cycles to ensure the HW init sequence has completed
3139 before writing to ANY of the DFA_MEM* registers.
3140 NOTE: This should only be written to a different value
3141 during power-on SW initialization.
3142 NOTE: DFA Memory Port#0 corresponds to the Octeon
3144 uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'),
3145 the HW init sequence(s) for Memory Port \#1 is
3147 NOTE: To initialize memory, SW must:
3148 1) Enable memory port(s):
3149 a) ENA_P1=1 (single port in pass 1) OR
3150 b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
3151 2) Wait 100us (to ensure a stable clock
3152 to the RLDRAMs) - as per RLDRAM spec.
3153 3) Write a '1' to the corresponding INIT_Px which
3154 will initiate a hardware initialization
3156 NOTE: After writing a '1', SW must wait 64K eclk
3157 cycles to ensure the HW init sequence has completed
3158 before writing to ANY of the DFA_MEM* registers.
3159 NOTE: This should only be written to a different value
3160 during power-on SW initialization.
3161 NOTE: DFA Memory Port#1 corresponds to the Octeon
3163 uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted
3164 if back to back reads are issued to different physical
3165 bunks. This is to avoid DQ data bus collisions when
3166 references cross between physical bunks.
3167 [NOTE: the physical bunk address boundary is determined
3169 NOTE: This should only be written to a different value
3170 during power-on SW initialization.
3171 When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE
3172 ZERO(for optimal performance). However, if electrically,
3173 DQ-sharing becomes a power/heat issue, then R2R_PBUNK
3174 should be set (but at a cost to performance (1/2 BW). */
3175 uint64_t pbunk : 3; /**< Physical Bunk address bit pointer.
3176 Specifies which address bit within the Longword
3177 Memory address MA[23:0] is used to determine the
3179 [RLD_CS0_N corresponds to physical bunk \#0, and
3180 RLD_CS1_N corresponds to physical bunk \#1].
3181 - 000: CS0_N = MA[19]/CS1_N = !MA[19]
3182 - 001: CS0_N = MA[20]/CS1_N = !MA[20]
3183 - 010: CS0_N = MA[21]/CS1_N = !MA[21]
3184 - 011: CS0_N = MA[22]/CS1_N = !MA[22]
3185 - 100: CS0_N = MA[23]/CS1_N = !MA[23]
3186 - 101-111: CS0_N = 0 /CS1_N = 1
3188 To build out a 128MB DFA memory, 4x 32Mx9
3189 parts could be used to fill out TWO physical
3190 bunks (clamshell configuration). Each (of the
3191 two) physical bunks contains 2x 32Mx9 = 16Mx36.
3192 Each RLDRAM device also contains 8 internal banks,
3193 therefore the memory Address is 16M/8banks = 2M
3194 addresses/bunk (2^21). In this case, MA[21] would
3195 select the physical bunk.
3196 NOTE: This should only be written to a different value
3197 during power-on SW initialization.
3198 be used to determine the Chip Select(s).
3199 NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a
3200 "Redundant Bunk" scheme is employed to provide the
3201 highest overall performance (1 Req/ MCLK cycle).
3202 In this mode, it's imperative that SW set the PBUNK
3203 field +1 'above' the highest address bit. (such that
3204 the PBUNK extracted from the address will always be
3205 zero). In this mode, the CS_N[1:0] pins are driven
3206 to each redundant bunk based on a TDM scheme:
3207 [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */
3208 uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst)
3209 When BLEN=0(BL2), all QW reads/writes from CP2 are
3210 decomposed into 2 separate BL2(LW) requests to the
3212 When BLEN=1(BL4), a LW request (from CP2 or NCB) is
3213 treated as 1 BL4(QW) request to the low latency memory.
3214 NOTE: QW refers to a 64-bit LLM Load/Store (intiated
3215 by a processor core). LW refers to a 36-bit load/store.
3216 NOTE: This should only be written to a different value
3217 during power-on SW initialization before the DFA LLM
3218 (low latency memory) is used.
3219 NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst)
3220 NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a
3221 multi-bunk(clam) board design.
3222 NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4),
3223 SW SHOULD use CP2 QW read/write requests (for
3224 optimal low-latency bus performance).
3225 [LW length read/write requests(in BL4 mode) use 50%
3226 of the available bus bandwidth]
3227 NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only
3228 be used with FCRAM-II devices which support BL2 mode
3229 (see: Toshiba FCRAM-II, where DQ tristate after 2 data
3231 NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW
3232 write requests (FCRAM-II+ device specification has removed
3233 the variable write mask function from the devices).
3234 As such, if this mode is used, SW must be careful to
3235 issue only PP-CP2 QW write requests. */
3236 uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks)
3237 On reads, allows user to control the shape of the
3238 tristate disable back porch for the DQ data bus.
3239 This parameter is also very dependent on the
3240 RW_DLY and WR_DLY parameters and care must be
3241 taken when programming these parameters to avoid
3242 data bus contention. Valid range [0..2]
3243 NOTE: This should only be written to a different value
3244 during power-on SW initialization. */
3245 uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks)
3246 On reads, allows user to control the shape of the
3247 tristate disable front porch for the DQ data bus.
3248 This parameter is also very dependent on the
3249 RW_DLY and WR_DLY parameters and care must be
3250 taken when programming these parameters to avoid
3251 data bus contention. Valid range [0..2]
3252 NOTE: This should only be written to a different value
3253 during power-on SW initialization. */
3254 uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks):
3255 Determines \#mclk cycles to insert when controller
3256 switches from write to read. This allows programmer
3257 to control the data bus contention.
3258 For RLDRAM-II(BL2): (TBL=1)
3259 For FCRAM-II (BL4): (TBL=2)
3260 For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1)
3261 For FCRAM-II (BL2 grepl>=2x): (TBL=3)
3262 NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode),
3263 grepl>=2x, writes require redundant bunk writes
3264 which require an additional 2 cycles before slotting
3266 WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
3267 NOTE: This should only be written to a different value
3268 during power-on SW initialization.
3269 NOTE: For aggressive(performance optimal) designs,
3270 the WR_DLY 'may' be tuned down(-1) if bus fight
3271 on W->R transitions is not pronounced. */
3272 uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks):
3273 Determines \#mclk cycles to insert when controller
3274 switches from read to write. This allows programmer
3275 to control the data bus contention.
3276 For RLDRAM-II/FCRAM-II (BL2): (TBL=1)
3277 For FCRAM-II (BL4): (TBL=2)
3278 RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
3279 NOTE: This should only be written to a different value
3280 during power-on SW initialization.
3281 NOTE: For aggressive(performance optimal) designs,
3282 the RW_DLY 'may' be tuned down(-1) if bus fight
3283 on R->W transitions is not pronounced. */
3284 uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many
3285 additional dclks to wait (on top of tRL+1) before
3286 pulling data out of the padring silos used for time
3287 domain boundary crossing.
3288 NOTE: This should only be written to a different value
3289 during power-on SW initialization. */
3290 uint64_t mtype : 1; /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM)
3291 NOTE: N3K-P1 only supports RLDRAM-II
3292 NOTE: This should only be written to a different value
3293 during power-on SW initialization.
3294 NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the
3295 "unidirectional DS/QS" mode is supported. (see FCRAM
3296 data sheet EMRS[A6:A5]=SS(Strobe Select) register
3297 definition. [in FCRAM 2-burst mode, we use FCRAM
3298 in a clamshell configuration such that clam0 is
3299 addressed independently of clam1, and DQ is shared
3300 for optimal performance. As such it's imperative that
3301 the QS are conditionally received (and are NOT
3302 free-running), as the N3K receive data capture silos
3303 OR the clam0/1 QS strobes.
3304 NOTE: If this bit is SET, the ASX0/1
3305 ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET
3306 in order for the RLD0/1-PHY(s) to support FCRAM devices. */
3307 uint64_t reserved_2_2 : 1;
3308 uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0
3309 When enabled, this bit lets N3K be the default
3310 driver for memory port \#0.
3311 NOTE: For N3K-P1, to enable Port#0(2nd port),
3312 Port#1 MUST ALSO be enabled.
3313 NOTE: For N3K-P2, single port mode, a customer is at
3314 liberty to enable either Port#0 or Port#1.
3315 NOTE: Once a port has been disabled, it MUST NEVER
3316 be re-enabled. [the only way to enable a port is
3317 through a chip reset].
3318 NOTE: DFA Memory Port#0 corresponds to the Octeon
3320 uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1
3321 When enabled, this bit lets N3K be the default
3322 driver for memory port \#1.
3323 NOTE: For N3K-P1, If the customer wishes to use a
3324 single port, s/he must enable Port#1 (and not Port#0).
3325 NOTE: For N3K-P2, single port mode, a customer is at
3326 liberty to enable either Port#0 or Port#1.
3327 NOTE: Once a port has been disabled, it MUST NEVER
3328 be re-enabled. [the only way to enable a port is
3329 through a chip reset].
3330 NOTE: DFA Memory Port#1 corresponds to the Octeon
3333 uint64_t ena_p1 : 1;
3334 uint64_t ena_p0 : 1;
3335 uint64_t reserved_2_2 : 1;
3337 uint64_t sil_lat : 2;
3338 uint64_t rw_dly : 4;
3339 uint64_t wr_dly : 4;
3344 uint64_t r2r_pbunk : 1;
3345 uint64_t init_p1 : 1;
3346 uint64_t init_p0 : 1;
3347 uint64_t bunk_init : 2;
3348 uint64_t lpp_ena : 1;
3349 uint64_t reserved_28_63 : 36;
3352 struct cvmx_dfa_memcfg0_cn38xxp2
3354 #if __BYTE_ORDER == __BIG_ENDIAN
3355 uint64_t reserved_27_63 : 37;
3356 uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization
3357 sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
3358 b) during a normal refresh sequence. If
3359 the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
3360 NOTE: This is required for DRAM used in a
3361 clamshell configuration, since the address lines
3362 carry Mode Register write data that is unique
3363 per bunk(or clam). In a clamshell configuration,
3364 The N3K A[x] pin may be tied into Clam#0's A[x]
3365 and also into Clam#1's 'mirrored' address bit A[y]
3366 (eg: Clam0 sees A[5] and Clam1 sees A[15]).
3367 To support clamshell designs, SW must initiate
3368 two separate HW init sequences for the two bunks
3369 (or clams) . Before each HW init sequence is triggered,
3370 SW must preload the DFA_MEMRLD[22:0] with the data
3371 that will be driven onto the A[22:0] wires during
3372 an MRS mode register write.
3373 NOTE: After the final HW initialization sequence has
3374 been triggered, SW must wait 64K eclks before writing
3375 the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
3376 driven during refresh sequences in normal operation.
3377 NOTE: This should only be written to a different value
3378 during power-on SW initialization.
3379 NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE
3380 initialized independently. In other words, a HW init
3381 must be done for Bunk#0, and then another HW init
3382 must be done for Bunk#1 at power-on. */
3383 uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'),
3384 the HW init sequence(s) for Memory Port \#0 is
3386 NOTE: To initialize memory, SW must:
3387 1) Enable memory port(s):
3388 a) ENA_P1=1 (single port in pass 1) OR
3389 b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
3390 2) Wait 100us (to ensure a stable clock
3391 to the RLDRAMs) - as per RLDRAM spec.
3392 3) Write a '1' to the corresponding INIT_Px which
3393 will initiate a hardware initialization
3395 NOTE: After writing a '1', SW must wait 64K eclk
3396 cycles to ensure the HW init sequence has completed
3397 before writing to ANY of the DFA_MEM* registers.
3398 NOTE: This should only be written to a different value
3399 during power-on SW initialization.
3400 NOTE: DFA Memory Port#0 corresponds to the Octeon
3402 uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'),
3403 the HW init sequence(s) for Memory Port \#1 is
3405 NOTE: To initialize memory, SW must:
3406 1) Enable memory port(s):
3407 a) ENA_P1=1 (single port in pass 1) OR
3408 b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
3409 2) Wait 100us (to ensure a stable clock
3410 to the RLDRAMs) - as per RLDRAM spec.
3411 3) Write a '1' to the corresponding INIT_Px which
3412 will initiate a hardware initialization
3414 NOTE: After writing a '1', SW must wait 64K eclk
3415 cycles to ensure the HW init sequence has completed
3416 before writing to ANY of the DFA_MEM* registers.
3417 NOTE: This should only be written to a different value
3418 during power-on SW initialization.
3419 NOTE: DFA Memory Port#1 corresponds to the Octeon
3421 uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted
3422 if back to back reads are issued to different physical
3423 bunks. This is to avoid DQ data bus collisions when
3424 references cross between physical bunks.
3425 [NOTE: the physical bunk address boundary is determined
3427 NOTE: This should only be written to a different value
3428 during power-on SW initialization.
3429 When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE
3430 ZERO(for optimal performance). However, if electrically,
3431 DQ-sharing becomes a power/heat issue, then R2R_PBUNK
3432 should be set (but at a cost to performance (1/2 BW). */
3433 uint64_t pbunk : 3; /**< Physical Bunk address bit pointer.
3434 Specifies which address bit within the Longword
3435 Memory address MA[23:0] is used to determine the
3437 [RLD_CS0_N corresponds to physical bunk \#0, and
3438 RLD_CS1_N corresponds to physical bunk \#1].
3439 - 000: CS0_N = MA[19]/CS1_N = !MA[19]
3440 - 001: CS0_N = MA[20]/CS1_N = !MA[20]
3441 - 010: CS0_N = MA[21]/CS1_N = !MA[21]
3442 - 011: CS0_N = MA[22]/CS1_N = !MA[22]
3443 - 100: CS0_N = MA[23]/CS1_N = !MA[23]
3444 - 101-111: CS0_N = 0 /CS1_N = 1
3446 To build out a 128MB DFA memory, 4x 32Mx9
3447 parts could be used to fill out TWO physical
3448 bunks (clamshell configuration). Each (of the
3449 two) physical bunks contains 2x 32Mx9 = 16Mx36.
3450 Each RLDRAM device also contains 8 internal banks,
3451 therefore the memory Address is 16M/8banks = 2M
3452 addresses/bunk (2^21). In this case, MA[21] would
3453 select the physical bunk.
3454 NOTE: This should only be written to a different value
3455 during power-on SW initialization.
3456 be used to determine the Chip Select(s).
3457 NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a
3458 "Redundant Bunk" scheme is employed to provide the
3459 highest overall performance (1 Req/ MCLK cycle).
3460 In this mode, it's imperative that SW set the PBUNK
3461 field +1 'above' the highest address bit. (such that
3462 the PBUNK extracted from the address will always be
3463 zero). In this mode, the CS_N[1:0] pins are driven
3464 to each redundant bunk based on a TDM scheme:
3465 [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */
3466 uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst)
3467 When BLEN=0(BL2), all QW reads/writes from CP2 are
3468 decomposed into 2 separate BL2(LW) requests to the
3470 When BLEN=1(BL4), a LW request (from CP2 or NCB) is
3471 treated as 1 BL4(QW) request to the low latency memory.
3472 NOTE: QW refers to a 64-bit LLM Load/Store (intiated
3473 by a processor core). LW refers to a 36-bit load/store.
3474 NOTE: This should only be written to a different value
3475 during power-on SW initialization before the DFA LLM
3476 (low latency memory) is used.
3477 NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst)
3478 NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a
3479 multi-bunk(clam) board design.
3480 NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4),
3481 SW SHOULD use CP2 QW read/write requests (for
3482 optimal low-latency bus performance).
3483 [LW length read/write requests(in BL4 mode) use 50%
3484 of the available bus bandwidth]
3485 NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only
3486 be used with FCRAM-II devices which support BL2 mode
3487 (see: Toshiba FCRAM-II, where DQ tristate after 2 data
3489 NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW
3490 write requests (FCRAM-II+ device specification has removed
3491 the variable write mask function from the devices).
3492 As such, if this mode is used, SW must be careful to
3493 issue only PP-CP2 QW write requests. */
3494 uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks)
3495 On reads, allows user to control the shape of the
3496 tristate disable back porch for the DQ data bus.
3497 This parameter is also very dependent on the
3498 RW_DLY and WR_DLY parameters and care must be
3499 taken when programming these parameters to avoid
3500 data bus contention. Valid range [0..2]
3501 NOTE: This should only be written to a different value
3502 during power-on SW initialization. */
3503 uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks)
3504 On reads, allows user to control the shape of the
3505 tristate disable front porch for the DQ data bus.
3506 This parameter is also very dependent on the
3507 RW_DLY and WR_DLY parameters and care must be
3508 taken when programming these parameters to avoid
3509 data bus contention. Valid range [0..2]
3510 NOTE: This should only be written to a different value
3511 during power-on SW initialization. */
3512 uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks):
3513 Determines \#mclk cycles to insert when controller
3514 switches from write to read. This allows programmer
3515 to control the data bus contention.
3516 For RLDRAM-II(BL2): (TBL=1)
3517 For FCRAM-II (BL4): (TBL=2)
3518 For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1)
3519 For FCRAM-II (BL2 grepl>=2x): (TBL=3)
3520 NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode),
3521 grepl>=2x, writes require redundant bunk writes
3522 which require an additional 2 cycles before slotting
3524 WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
3525 NOTE: This should only be written to a different value
3526 during power-on SW initialization.
3527 NOTE: For aggressive(performance optimal) designs,
3528 the WR_DLY 'may' be tuned down(-1) if bus fight
3529 on W->R transitions is not pronounced. */
3530 uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks):
3531 Determines \#mclk cycles to insert when controller
3532 switches from read to write. This allows programmer
3533 to control the data bus contention.
3534 For RLDRAM-II/FCRAM-II (BL2): (TBL=1)
3535 For FCRAM-II (BL4): (TBL=2)
3536 RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
3537 NOTE: This should only be written to a different value
3538 during power-on SW initialization.
3539 NOTE: For aggressive(performance optimal) designs,
3540 the RW_DLY 'may' be tuned down(-1) if bus fight
3541 on R->W transitions is not pronounced. */
3542 uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many
3543 additional dclks to wait (on top of tRL+1) before
3544 pulling data out of the padring silos used for time
3545 domain boundary crossing.
3546 NOTE: This should only be written to a different value
3547 during power-on SW initialization. */
3548 uint64_t mtype : 1; /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM)
3549 NOTE: N3K-P1 only supports RLDRAM-II
3550 NOTE: This should only be written to a different value
3551 during power-on SW initialization.
3552 NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the
3553 "unidirectional DS/QS" mode is supported. (see FCRAM
3554 data sheet EMRS[A6:A5]=SS(Strobe Select) register
3555 definition. [in FCRAM 2-burst mode, we use FCRAM
3556 in a clamshell configuration such that clam0 is
3557 addressed independently of clam1, and DQ is shared
3558 for optimal performance. As such it's imperative that
3559 the QS are conditionally received (and are NOT
3560 free-running), as the N3K receive data capture silos
3561 OR the clam0/1 QS strobes.
3562 NOTE: If this bit is SET, the ASX0/1
3563 ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET
3564 in order for the RLD0/1-PHY(s) to support FCRAM devices. */
3565 uint64_t reserved_2_2 : 1;
3566 uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0
3567 When enabled, this bit lets N3K be the default
3568 driver for memory port \#0.
3569 NOTE: For N3K-P1, to enable Port#0(2nd port),
3570 Port#1 MUST ALSO be enabled.
3571 NOTE: For N3K-P2, single port mode, a customer is at
3572 liberty to enable either Port#0 or Port#1.
3573 NOTE: Once a port has been disabled, it MUST NEVER
3574 be re-enabled. [the only way to enable a port is
3575 through a chip reset].
3576 NOTE: DFA Memory Port#0 corresponds to the Octeon
3578 uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1
3579 When enabled, this bit lets N3K be the default
3580 driver for memory port \#1.
3581 NOTE: For N3K-P1, If the customer wishes to use a
3582 single port, s/he must enable Port#1 (and not Port#0).
3583 NOTE: For N3K-P2, single port mode, a customer is at
3584 liberty to enable either Port#0 or Port#1.
3585 NOTE: Once a port has been disabled, it MUST NEVER
3586 be re-enabled. [the only way to enable a port is
3587 through a chip reset].
3588 NOTE: DFA Memory Port#1 corresponds to the Octeon
3591 uint64_t ena_p1 : 1;
3592 uint64_t ena_p0 : 1;
3593 uint64_t reserved_2_2 : 1;
3595 uint64_t sil_lat : 2;
3596 uint64_t rw_dly : 4;
3597 uint64_t wr_dly : 4;
3602 uint64_t r2r_pbunk : 1;
3603 uint64_t init_p1 : 1;
3604 uint64_t init_p0 : 1;
3605 uint64_t bunk_init : 2;
3606 uint64_t reserved_27_63 : 37;
3609 struct cvmx_dfa_memcfg0_s cn58xx;
3610 struct cvmx_dfa_memcfg0_s cn58xxp1;
3612 typedef union cvmx_dfa_memcfg0 cvmx_dfa_memcfg0_t;
3617 * DFA_MEMCFG1 = RLDRAM Memory Timing Configuration
3621 union cvmx_dfa_memcfg1
3624 struct cvmx_dfa_memcfg1_s
3626 #if __BYTE_ORDER == __BIG_ENDIAN
3627 uint64_t reserved_34_63 : 30;
3628 uint64_t ref_intlo : 9; /**< Burst Refresh Interval[8:0] (\#dclks)
3629 For finer refresh interval granularity control.
3630 This field provides an additional level of granularity
3631 for the refresh interval. It specifies the additional
3632 \#dclks [0...511] to be added to the REF_INT[3:0] field.
3633 For RLDRAM-II: For dclk(400MHz=2.5ns):
3634 Example: 64K AREF cycles required within tREF=32ms
3635 trefint = tREF(ms)/(64K cycles/8banks)
3636 = 32ms/8K = 3.9us = 3900ns
3637 REF_INT[3:0] = ROUND_DOWN[(trefint/dclk)/512]
3638 = ROUND_DOWN[(3900/2.5)/512]
3640 REF_INTLO[8:0] = MOD[(trefint/dclk)/512]
3641 = MOD[(3900/2.5)/512]
3643 NOTE: This should only be written to a different value
3644 during power-on SW initialization. */
3645 uint64_t aref_ena : 1; /**< Auto Refresh Cycle Enable
3647 NOTE: This mode bit is ONLY intended to be used by
3648 low-level power-on initialization routines in the
3649 event that the hardware initialization routine
3650 does not work. It allows SW to create AREF
3651 commands on the RLDRAM bus directly.
3652 When this bit is set, ALL RLDRAM writes (issued by
3653 a PP through the NCB or CP2) are converted to AREF
3654 commands on the RLDRAM bus. The write-address is
3655 presented on the A[20:0]/BA[2:0] pins (for which
3656 the RLDRAM only interprets BA[2:0]).
3657 When this bit is set, only writes are allowed
3658 and MUST use grepl=0 (1x).
3659 NOTE: This should only be written to a different value
3660 during power-on SW initialization.
3661 NOTE: MRS_ENA and AREF_ENA are mutually exclusive
3662 (SW can set one or the other, but never both!)
3663 NOTE: AREF commands generated using this method target
3664 the 'addressed' bunk. */
3665 uint64_t mrs_ena : 1; /**< Mode Register Set Cycle Enable
3667 NOTE: This mode bit is ONLY intended to be used by
3668 low-level power-on initialization routines in the
3669 event that the hardware initialization routine
3670 does not work. It allows SW to create MRS
3671 commands on the RLDRAM bus directly.
3672 When this bit is set, ALL RLDRAM writes (issued by
3673 a PP through the NCB or CP2) are converted to MRS
3674 commands on the RLDRAM bus. The write-address is
3675 presented on the A[20:0]/BA[2:0] pins (for which
3676 the RLDRAM only interprets A[17:0]).
3677 When this bit is set, only writes are allowed
3678 and MUST use grepl=0 (1x).
3679 NOTE: This should only be written to a different value
3680 during power-on SW initialization.
3681 NOTE: MRS_ENA and AREF_ENA are mutually exclusive
3682 (SW can set one or the other, but never both!)
3683 NOTE: MRS commands generated using this method target
3684 the 'addressed' bunk. */
3685 uint64_t tmrsc : 3; /**< Mode Register Set Cycle Time (represented in \#mclks)
3687 - 010: tMRSC = 2 mclks
3688 - 011: tMRSC = 3 mclks
3690 - 111: tMRSC = 7 mclks
3691 NOTE: The device tMRSC parameter is a function of CL
3692 (which during HW initialization is not known. Its
3693 recommended to load tMRSC(MAX) value to avoid timing
3695 NOTE: This should only be written to a different value
3696 during power-on SW initialization. */
3697 uint64_t trc : 4; /**< Row Cycle Time (represented in \#mclks)
3698 see also: DFA_MEMRLD[RLCFG] field which must
3699 correspond with tRL/tWL parameter(s).
3700 - 0000-0010: RESERVED
3701 - 0011: tRC = 3 mclks
3702 - 0100: tRC = 4 mclks
3703 - 0101: tRC = 5 mclks
3704 - 0110: tRC = 6 mclks
3705 - 0111: tRC = 7 mclks
3706 - 1000: tRC = 8 mclks
3707 - 1001: tRC = 9 mclks
3708 - 1010-1111: RESERVED
3709 NOTE: This should only be written to a different value
3710 during power-on SW initialization. */
3711 uint64_t twl : 4; /**< Write Latency (represented in \#mclks)
3712 see also: DFA_MEMRLD[RLCFG] field which must
3713 correspond with tRL/tWL parameter(s).
3714 - 0000-0001: RESERVED
3715 - 0010: Write Latency (WL=2.0 mclk)
3716 - 0011: Write Latency (WL=3.0 mclks)
3717 - 0100: Write Latency (WL=4.0 mclks)
3718 - 0101: Write Latency (WL=5.0 mclks)
3719 - 0110: Write Latency (WL=6.0 mclks)
3720 - 0111: Write Latency (WL=7.0 mclks)
3721 - 1000: Write Latency (WL=8.0 mclks)
3722 - 1001: Write Latency (WL=9.0 mclks)
3723 - 1010: Write Latency (WL=10.0 mclks)
3724 - 1011-1111: RESERVED
3725 NOTE: This should only be written to a different value
3726 during power-on SW initialization. */
3727 uint64_t trl : 4; /**< Read Latency (represented in \#mclks)
3728 see also: DFA_MEMRLD[RLCFG] field which must
3729 correspond with tRL/tWL parameter(s).
3730 - 0000-0010: RESERVED
3731 - 0011: Read Latency = 3 mclks
3732 - 0100: Read Latency = 4 mclks
3733 - 0101: Read Latency = 5 mclks
3734 - 0110: Read Latency = 6 mclks
3735 - 0111: Read Latency = 7 mclks
3736 - 1000: Read Latency = 8 mclks
3737 - 1001: Read Latency = 9 mclks
3738 - 1010: Read Latency = 10 mclks
3739 - 1011-1111: RESERVED
3740 NOTE: This should only be written to a different value
3741 during power-on SW initialization. */
3742 uint64_t reserved_6_7 : 2;
3743 uint64_t tskw : 2; /**< Board Skew (represented in \#dclks)
3744 Represents additional board skew of DQ/DQS.
3745 - 00: board-skew = 0 dclk
3746 - 01: board-skew = 1 dclk
3747 - 10: board-skew = 2 dclk
3748 - 11: board-skew = 3 dclk
3749 NOTE: This should only be written to a different value
3750 during power-on SW initialization. */
3751 uint64_t ref_int : 4; /**< Refresh Interval (represented in \#of 512 dclk
3754 - 0001: 1 * 512 = 512 dclks
3756 - 1111: 15 * 512 = 7680 dclks
3757 NOTE: For finer level of granularity, refer to
3758 REF_INTLO[8:0] field.
3759 For RLDRAM-II, each refresh interval will
3760 generate a burst of 8 AREF commands, one to each of
3761 8 explicit banks (referenced using the RLD_BA[2:0]
3763 Example: For mclk=200MHz/dclk(400MHz=2.5ns):
3764 64K AREF cycles required within tREF=32ms
3765 trefint = tREF(ms)/(64K cycles/8banks)
3766 = 32ms/8K = 3.9us = 3900ns
3767 REF_INT = ROUND_DOWN[(trefint/dclk)/512]
3768 = ROUND_DOWN[(3900/2.5)/512]
3770 NOTE: This should only be written to a different value
3771 during power-on SW initialization. */
3773 uint64_t ref_int : 4;
3775 uint64_t reserved_6_7 : 2;
3780 uint64_t mrs_ena : 1;
3781 uint64_t aref_ena : 1;
3782 uint64_t ref_intlo : 9;
3783 uint64_t reserved_34_63 : 30;
3786 struct cvmx_dfa_memcfg1_s cn38xx;
3787 struct cvmx_dfa_memcfg1_s cn38xxp2;
3788 struct cvmx_dfa_memcfg1_s cn58xx;
3789 struct cvmx_dfa_memcfg1_s cn58xxp1;
3791 typedef union cvmx_dfa_memcfg1 cvmx_dfa_memcfg1_t;
3796 * DFA_MEMCFG2 = DFA Memory Config Register \#2
3797 * *** NOTE: Pass2 Addition
3799 * Description: Additional Memory Configuration CSRs to support FCRAM-II/II+ and Network DRAM-II
3801 union cvmx_dfa_memcfg2
3804 struct cvmx_dfa_memcfg2_s
3806 #if __BYTE_ORDER == __BIG_ENDIAN
3807 uint64_t reserved_12_63 : 52;
3808 uint64_t dteclkdis : 1; /**< DFA DTE Clock Disable
3809 When SET, the DFA clocks for DTE(thread engine)
3810 operation are disabled.
3811 NOTE: When SET, SW MUST NEVER issue ANY operations to
3812 the DFA via the NCB Bus. All DFA Operations must be
3813 issued solely through the CP2 interface.
3815 NOTE: When DTECLKDIS=1, if CP2 Errors are encountered
3816 (ie: CP2SBE, CP2DBE, CP2PERR), the DFA_MEMFADR CSR
3817 does not reflect the failing address/ctl information. */
3818 uint64_t silrst : 1; /**< LLM-PHY Silo Reset
3819 When a '1' is written (when the previous
3820 value was a '0') causes the the LLM-PHY Silo read/write
3821 pointers to be reset.
3822 NOTE: SW MUST WAIT 400 dclks after the LAST HW Init
3823 sequence was launched (ie: INIT_START 0->1 CSR write),
3824 before the SILRST can be triggered (0->1). */
3825 uint64_t trfc : 5; /**< FCRAM-II Refresh Interval
3826 *** CN58XX UNSUPPORTED *** */
3827 uint64_t refshort : 1; /**< FCRAM Short Refresh Mode
3828 *** CN58XX UNSUPPORTED *** */
3829 uint64_t ua_start : 2; /**< FCRAM-II Upper Addres Start
3830 *** CN58XX UNSUPPORTED *** */
3831 uint64_t maxbnk : 1; /**< Maximum Banks per-device (used by the address mapper
3832 when extracting address bits for the memory bank#.
3834 - 1: 8 banks/device */
3835 uint64_t fcram2p : 1; /**< FCRAM-II+ Mode Enable
3836 *** CN58XX UNSUPPORTED *** */
3838 uint64_t fcram2p : 1;
3839 uint64_t maxbnk : 1;
3840 uint64_t ua_start : 2;
3841 uint64_t refshort : 1;
3843 uint64_t silrst : 1;
3844 uint64_t dteclkdis : 1;
3845 uint64_t reserved_12_63 : 52;
3848 struct cvmx_dfa_memcfg2_s cn38xx;
3849 struct cvmx_dfa_memcfg2_s cn38xxp2;
3850 struct cvmx_dfa_memcfg2_s cn58xx;
3851 struct cvmx_dfa_memcfg2_s cn58xxp1;
3853 typedef union cvmx_dfa_memcfg2 cvmx_dfa_memcfg2_t;
3858 * DFA_MEMFADR = RLDRAM Failing Address/Control Register
3860 * Description: DFA Memory Failing Address/Control Error Capture information
3861 * This register contains useful information to help in isolating an RLDRAM memory failure.
3862 * NOTE: The first detected SEC/DED/PERR failure is captured in DFA_MEMFADR, however, a DED or PERR (which is
3863 * more severe) will always overwrite a SEC error. The user can 'infer' the source of the interrupt
3864 * via the FSRC field.
3865 * NOTE: If DFA_MEMCFG2[DTECLKDIS]=1, the contents of this register are UNDEFINED.
3867 union cvmx_dfa_memfadr
3870 struct cvmx_dfa_memfadr_s
3872 #if __BYTE_ORDER == __BIG_ENDIAN
3873 uint64_t reserved_24_63 : 40;
3874 uint64_t maddr : 24; /**< Memory Address */
3876 uint64_t maddr : 24;
3877 uint64_t reserved_24_63 : 40;
3880 struct cvmx_dfa_memfadr_cn31xx
3882 #if __BYTE_ORDER == __BIG_ENDIAN
3883 uint64_t reserved_40_63 : 24;
3884 uint64_t fdst : 9; /**< Fill-Destination
3885 FSRC[1:0] | FDST[8:0]
3886 -------------+-------------------------------------
3887 0(NCB-DTE) | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)]
3888 1(NCB-CSR) | [ncbSRC[8:0]]
3889 3(CP2-PP) | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)]
3891 DTE: DFA Thread Engine ID#
3892 PP: Packet Processor ID#
3893 FID: Fill-ID# (unique per PP)
3894 WIDX: 16b SIMPLE Mode (index)
3895 DMODE: (0=16b SIMPLE/1=32b SIMPLE)
3896 SIZE: (0=LW Mode access/1=QW Mode Access)
3897 INDEX: (0=Low LW/1=High LW)
3898 NOTE: QW refers to a 56/64-bit LLM Load/Store (intiated
3899 by a processor core). LW refers to a 32-bit load/store. */
3900 uint64_t fsrc : 2; /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */
3901 uint64_t pnum : 1; /**< Memory Port
3902 NOTE: For O2P, this bit will always return zero. */
3903 uint64_t bnum : 3; /**< Memory Bank
3904 When DFA_DDR2_ADDR[RNK_LO]=1, BNUM[2]=RANK[0].
3905 (RANK[1] can be inferred from MADDR[24:0]) */
3906 uint64_t maddr : 25; /**< Memory Address */
3908 uint64_t maddr : 25;
3913 uint64_t reserved_40_63 : 24;
3916 struct cvmx_dfa_memfadr_cn38xx
3918 #if __BYTE_ORDER == __BIG_ENDIAN
3919 uint64_t reserved_39_63 : 25;
3920 uint64_t fdst : 9; /**< Fill-Destination
3921 FSRC[1:0] | FDST[8:0]
3922 -------------+-------------------------------------
3923 0(NCB-DTE) | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)]
3924 1(NCB-CSR) | [ncbSRC[8:0]]
3925 3(CP2-PP) | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)]
3927 DTE: DFA Thread Engine ID#
3928 PP: Packet Processor ID#
3929 FID: Fill-ID# (unique per PP)
3930 WIDX: 18b SIMPLE Mode (index)
3931 DMODE: (0=18b SIMPLE/1=36b SIMPLE)
3932 SIZE: (0=LW Mode access/1=QW Mode Access)
3933 INDEX: (0=Low LW/1=High LW)
3934 NOTE: QW refers to a 64-bit LLM Load/Store (intiated
3935 by a processor core). LW refers to a 36-bit load/store. */
3936 uint64_t fsrc : 2; /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */
3937 uint64_t pnum : 1; /**< Memory Port
3938 NOTE: the port id's are reversed
3940 PNUM==1 => port#0 */
3941 uint64_t bnum : 3; /**< Memory Bank */
3942 uint64_t maddr : 24; /**< Memory Address */
3944 uint64_t maddr : 24;
3949 uint64_t reserved_39_63 : 25;
3952 struct cvmx_dfa_memfadr_cn38xx cn38xxp2;
3953 struct cvmx_dfa_memfadr_cn38xx cn58xx;
3954 struct cvmx_dfa_memfadr_cn38xx cn58xxp1;
3956 typedef union cvmx_dfa_memfadr cvmx_dfa_memfadr_t;
3961 * DFA_MEMFCR = FCRAM MRS Register(s) EMRS2[14:0], EMRS1[14:0], MRS[14:0]
3962 * *** CN58XX UNSUPPORTED ***
3965 * For FCRAM-II please consult your device's data sheet for further details:
3967 * A[13:8]=0 RESERVED
3968 * A[7]=0 TEST MODE (N3K requires test mode 0:"disabled")
3969 * A[6:4] CAS LATENCY (fully programmable - SW must ensure that the value programmed
3970 * into DFA_MEM_CFG0[TRL] corresponds with this value).
3971 * A[3]=0 BURST TYPE (N3K requires 0:"Sequential" Burst Type)
3972 * A[2:0] BURST LENGTH Burst Length [1:BL2/2:BL4] (N3K only supports BL=2,4)
3974 * In BL2 mode(for highest performance), only 1/2 the phsyical
3975 * memory is unique (ie: each bunk stores the same information).
3976 * In BL4 mode(highest capacity), all of the physical memory
3977 * is unique (ie: each bunk is uniquely addressable).
3979 * A[13:12] REFRESH MODE (N3K Supports only 0:"Conventional" and 1:"Short" auto-refresh modes)
3981 * (SW must ensure that the value programmed into DFA_MEMCFG2[REFSHORT]
3982 * is also reflected in the Refresh Mode encoding).
3983 * A[11:7]=0 RESERVED
3984 * A[6:5]=2 STROBE SELECT (N3K supports only 2:"Unidirectional DS/QS" mode - the read capture
3985 * silos rely on a conditional QS strobe)
3986 * A[4:3] DIC(QS) QS Drive Strength: fully programmable (consult your FCRAM-II data sheet)
3987 * [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive]
3988 * A[2:1] DIC(DQ) DQ Drive Strength: fully programmable (consult your FCRAM-II data sheet)
3989 * [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive]
3990 * A[0] DLL DLL Enable: Programmable [0:DLL Enable/1: DLL Disable]
3992 * EMRS2 Definition: (for FCRAM-II+)
3993 * A[13:11]=0 RESERVED
3994 * A[10:8] ODTDS On Die Termination (DS+/-)
3995 * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
3996 * A[7:6]=0 MBW Multi-Bank Write: (N3K requires use of 0:"single bank" mode only)
3997 * A[5:3] ODTin On Die Termination (input pin)
3998 * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
3999 * A[2:0] ODTDQ On Die Termination (DQ)
4000 * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
4002 union cvmx_dfa_memfcr
4005 struct cvmx_dfa_memfcr_s
4007 #if __BYTE_ORDER == __BIG_ENDIAN
4008 uint64_t reserved_47_63 : 17;
4009 uint64_t emrs2 : 15; /**< Memory Address[14:0] during EMRS2(for FCRAM-II+)
4010 *** CN58XX UNSUPPORTED *** */
4011 uint64_t reserved_31_31 : 1;
4012 uint64_t emrs : 15; /**< Memory Address[14:0] during EMRS
4013 *** CN58XX UNSUPPORTED ***
4014 A[0]=1: DLL Enabled) */
4015 uint64_t reserved_15_15 : 1;
4016 uint64_t mrs : 15; /**< FCRAM Memory Address[14:0] during MRS
4017 *** CN58XX UNSUPPORTED ***
4018 A[6:4]=4 CAS LATENCY=4(default)
4019 A[3]=0 Burst Type(must be 0:Sequential)
4020 A[2:0]=2 Burst Length=4(default) */
4023 uint64_t reserved_15_15 : 1;
4025 uint64_t reserved_31_31 : 1;
4026 uint64_t emrs2 : 15;
4027 uint64_t reserved_47_63 : 17;
4030 struct cvmx_dfa_memfcr_s cn38xx;
4031 struct cvmx_dfa_memfcr_s cn38xxp2;
4032 struct cvmx_dfa_memfcr_s cn58xx;
4033 struct cvmx_dfa_memfcr_s cn58xxp1;
4035 typedef union cvmx_dfa_memfcr cvmx_dfa_memfcr_t;
4040 * DFA_MEMHIDAT = DFA NCB-Direct CSR access to DFM Memory Space (High QW)
4043 * DFA supports NCB-Direct CSR acccesses to DFM Memory space for debug purposes. Unfortunately, NCB-Direct accesses
4044 * are limited to QW-size(64bits), whereas the minimum access granularity for DFM Memory space is OW(128bits). To
4045 * support writes to DFM Memory space, the Hi-QW of data is sourced from the DFA_MEMHIDAT register. Recall, the
4046 * OW(128b) in DDR3 memory space is fixed format:
4047 * OWDATA[127:118]: OWECC[9:0] 10bits of in-band OWECC SEC/DED codeword
4048 * This can be precomputed/written by SW OR
4049 * if DFM_FNTCTL[ECC_WENA]=1, DFM hardware will auto-compute the 10b OWECC and place in the
4050 * OWDATA[127:118] before being written to memory.
4051 * OWDATA[117:0]: Memory Data (contains fixed MNODE/MONODE arc formats for use by DTEs(thread engines).
4052 * Or, a user may choose to treat DFM Memory Space as 'scratch pad' in which case the
4053 * OWDATA[117:0] may contain user-specified information accessible via NCB-Direct CSR mode
4054 * accesses to DFA Memory Space.
4055 * NOTE: To write to the DFA_MEMHIDAT register, a device would issue an IOBST directed at the DFA with addr[34:32]=3'b111.
4056 * To read the DFA_MEMHIDAT register, a device would issue an IOBLD64 directed at the DFA with addr[34:32]=3'b111.
4058 * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_MEMHIDAT register do not take effect.
4059 * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_MEMHIDAT register do not take effect.
4061 union cvmx_dfa_memhidat
4064 struct cvmx_dfa_memhidat_s
4066 #if __BYTE_ORDER == __BIG_ENDIAN
4067 uint64_t hidat : 64; /**< DFA Hi-QW of Write data during NCB-Direct DFM DDR3
4069 All DFM DDR3 memory accesses are OW(128b) references,
4070 and since NCB-Direct Mode writes only support QW(64b),
4071 the Hi QW of data must be sourced from a CSR register.
4072 NOTE: This single register is 'shared' for ALL DFM
4073 DDR3 Memory writes. */
4075 uint64_t hidat : 64;
4078 struct cvmx_dfa_memhidat_s cn63xx;
4079 struct cvmx_dfa_memhidat_s cn63xxp1;
4081 typedef union cvmx_dfa_memhidat cvmx_dfa_memhidat_t;
4086 * DFA_MEMRLD = DFA RLDRAM MRS Register Values
4090 union cvmx_dfa_memrld
4093 struct cvmx_dfa_memrld_s
4095 #if __BYTE_ORDER == __BIG_ENDIAN
4096 uint64_t reserved_23_63 : 41;
4097 uint64_t mrsdat : 23; /**< This field represents the data driven onto the
4098 A[22:0] address lines during MRS(Mode Register Set)
4099 commands (during a HW init sequence). This field
4100 corresponds with the Mode Register Bit Map from
4101 your RLDRAM-II device specific data sheet.
4103 A[9]: ODT (on die termination)
4104 A[8]: Impedance Matching
4107 A[5]: Address Mux (for N3K: MUST BE ZERO)
4108 A[4:3]: Burst Length (for N3K: MUST BE ZERO)
4109 A[2:0]: Configuration (see data sheet for
4110 specific RLDRAM-II device).
4111 - 000-001: CFG=1 [tRC=4/tRL=4/tWL=5]
4112 - 010: CFG=2 [tRC=6/tRL=6/tWL=7]
4113 - 011: CFG=3 [tRC=8/tRL=8/tWL=9]
4115 NOTE: For additional density, the RLDRAM-II parts
4116 can be 'clamshelled' (ie: two devices mounted on
4117 different sides of the PCB board), since the BGA
4118 pinout supports 'mirroring'.
4119 To support a clamshell design, SW must preload
4120 the MRSDAT[22:0] with the proper A[22:0] pin mapping
4121 which is dependent on the 'selected' bunk/clam
4122 (see also: DFA_MEMCFG0[BUNK_INIT] field).
4123 NOTE: Care MUST BE TAKEN NOT to write to this register
4124 within 64K eclk cycles of a HW INIT (see: INIT_P0/INIT_P1).
4125 NOTE: This should only be written to a different value
4126 during power-on SW initialization. */
4128 uint64_t mrsdat : 23;
4129 uint64_t reserved_23_63 : 41;
4132 struct cvmx_dfa_memrld_s cn38xx;
4133 struct cvmx_dfa_memrld_s cn38xxp2;
4134 struct cvmx_dfa_memrld_s cn58xx;
4135 struct cvmx_dfa_memrld_s cn58xxp1;
4137 typedef union cvmx_dfa_memrld cvmx_dfa_memrld_t;
4142 * DFA_NCBCTL = DFA NCB CTL Register
4146 union cvmx_dfa_ncbctl
4149 struct cvmx_dfa_ncbctl_s
4151 #if __BYTE_ORDER == __BIG_ENDIAN
4152 uint64_t reserved_11_63 : 53;
4153 uint64_t sbdnum : 5; /**< SBD Debug Entry#
4154 For internal use only. (DFA Scoreboard debug)
4155 Selects which one of 32 DFA Scoreboard entries is
4156 latched into the DFA_SBD_DBG[0-3] registers. */
4157 uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe
4158 For internal use only. (DFA Scoreboard debug)
4159 When written with a '1', the DFA Scoreboard Debug
4160 registers (DFA_SBD_DBG[0-3]) are all locked down.
4161 This allows SW to lock down the contents of the entire
4162 SBD for a single instant in time. All subsequent reads
4163 of the DFA scoreboard registers will return the data
4164 from that instant in time. */
4165 uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode
4166 DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
4167 NOTE: This should only be written to a different value
4168 during power-on SW initialization. */
4169 uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode
4170 DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
4171 NOTE: This should only be written to a different value
4172 during power-on SW initialization. */
4173 uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode
4174 (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
4175 NOTE: This should only be written to a different value
4176 during power-on SW initialization. */
4177 uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode
4178 (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
4179 NOTE: This should only be written to a different value
4180 during power-on SW initialization. */
4181 uint64_t imode : 1; /**< NCB-Inbound Arbiter
4182 (0=FP [LP=NRQ,HP=NRP], 1=RR)
4183 NOTE: This should only be written to a different value
4184 during power-on SW initialization. */
4189 uint64_t dtmode : 1;
4190 uint64_t dcmode : 1;
4191 uint64_t sbdlck : 1;
4192 uint64_t sbdnum : 5;
4193 uint64_t reserved_11_63 : 53;
4196 struct cvmx_dfa_ncbctl_cn38xx
4198 #if __BYTE_ORDER == __BIG_ENDIAN
4199 uint64_t reserved_10_63 : 54;
4200 uint64_t sbdnum : 4; /**< SBD Debug Entry#
4201 For internal use only. (DFA Scoreboard debug)
4202 Selects which one of 16 DFA Scoreboard entries is
4203 latched into the DFA_SBD_DBG[0-3] registers. */
4204 uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe
4205 For internal use only. (DFA Scoreboard debug)
4206 When written with a '1', the DFA Scoreboard Debug
4207 registers (DFA_SBD_DBG[0-3]) are all locked down.
4208 This allows SW to lock down the contents of the entire
4209 SBD for a single instant in time. All subsequent reads
4210 of the DFA scoreboard registers will return the data
4211 from that instant in time. */
4212 uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode
4213 DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
4214 NOTE: This should only be written to a different value
4215 during power-on SW initialization. */
4216 uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode
4217 DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
4218 NOTE: This should only be written to a different value
4219 during power-on SW initialization. */
4220 uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode
4221 (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
4222 NOTE: This should only be written to a different value
4223 during power-on SW initialization. */
4224 uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode
4225 (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
4226 NOTE: This should only be written to a different value
4227 during power-on SW initialization. */
4228 uint64_t imode : 1; /**< NCB-Inbound Arbiter
4229 (0=FP [LP=NRQ,HP=NRP], 1=RR)
4230 NOTE: This should only be written to a different value
4231 during power-on SW initialization. */
4236 uint64_t dtmode : 1;
4237 uint64_t dcmode : 1;
4238 uint64_t sbdlck : 1;
4239 uint64_t sbdnum : 4;
4240 uint64_t reserved_10_63 : 54;
4243 struct cvmx_dfa_ncbctl_cn38xx cn38xxp2;
4244 struct cvmx_dfa_ncbctl_s cn58xx;
4245 struct cvmx_dfa_ncbctl_s cn58xxp1;
4247 typedef union cvmx_dfa_ncbctl cvmx_dfa_ncbctl_t;
4252 * DFA_PFC0_CNT = DFA Performance Counter \#0
4253 * *FOR INTERNAL USE ONLY*
4256 union cvmx_dfa_pfc0_cnt
4259 struct cvmx_dfa_pfc0_cnt_s
4261 #if __BYTE_ORDER == __BIG_ENDIAN
4262 uint64_t pfcnt0 : 64; /**< Performance Counter \#0
4263 When DFA_PFC_GCTL[CNT0ENA]=1, the event selected
4264 by DFA_PFC0_CTL[EVSEL] is counted.
4265 See also DFA_PFC_GCTL[CNT0WCLR] and DFA_PFC_GCTL
4266 [CNT0RCLR] for special clear count cases available
4267 for SW data collection. */
4269 uint64_t pfcnt0 : 64;
4272 struct cvmx_dfa_pfc0_cnt_s cn63xx;
4273 struct cvmx_dfa_pfc0_cnt_s cn63xxp1;
4275 typedef union cvmx_dfa_pfc0_cnt cvmx_dfa_pfc0_cnt_t;
4280 * DFA_PFC0_CTL = DFA Performance Counter#0 Control
4281 * *FOR INTERNAL USE ONLY*
4284 union cvmx_dfa_pfc0_ctl
4287 struct cvmx_dfa_pfc0_ctl_s
4289 #if __BYTE_ORDER == __BIG_ENDIAN
4290 uint64_t reserved_14_63 : 50;
4291 uint64_t evsel : 6; /**< Performance Counter#0 Event Selector
4292 // Events [0-31] are based on PMODE(0:per cluster-DTE 1:per graph)
4294 - 1: \#LDNODE visits
4295 - 2: \#SDNODE visits
4296 - 3: \#DNODE visits (LD/SD)
4297 - 4: \#LCNODE visits
4298 - 5: \#SCNODE visits
4299 - 6: \#CNODE visits (LC/SC)
4300 - 7: \#LMNODE visits
4301 - 8: \#SMNODE visits
4302 - 9: \#MNODE visits (LM/SM)
4303 - 10: \#MONODE visits
4304 - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX
4305 - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX)
4306 - 13: \#MEMORY visits (MNODE+MONODE)
4307 - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions)
4308 - 15: \#MPHIDX detected (occur for ->LMNODE transitions)
4309 - 16: \#RESCANs detected (occur when HASH collision is detected)
4310 - 17: \#GWALK iterations STALLED - Packet data/Result Buffer
4311 - 18: \#GWALK iterations NON-STALLED
4312 - 19: \#CLOAD iterations
4313 - 20: \#MLOAD iterations
4314 [NOTE: If PMODE=1(per-graph) the MLOAD IWORD0.VGID will be used to discern graph#].
4315 - 21: \#RWORD1+ writes
4316 - 22: \#cycles Cluster is busy
4317 - 23: \#GWALK Instructions
4318 - 24: \#CLOAD Instructions
4319 - 25: \#MLOAD Instructions
4320 [NOTE: If PMODE=1(per-graph) the MLOAD IWORD0.VGID will be used to discern graph#].
4321 - 26: \#GFREE Instructions
4323 - 31: \# Node Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE,EDNODE] registers
4324 //=============================================================
4325 // Events [32-63] are used ONLY FOR PMODE=0(per-cluster DTE mode):
4326 - 32: \#cycles a specific cluster-DTE remains active(valid state)
4327 - 33: \#cycles a specific cluster-DTE waits for Memory Response Data
4328 - 34: \#cycles a specific cluster-DTE waits in resource stall state
4329 (waiting for packet data or result buffer space)
4330 - 35: \#cycles a specific cluster-DTE waits in resource pending state
4332 //============================================================= */
4333 uint64_t reserved_6_7 : 2;
4334 uint64_t cldte : 4; /**< Performance Counter#0 Cluster DTE Selector
4335 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
4336 is used to select/monitor the cluster's DTE# for all events
4337 associated with Performance Counter#0. */
4338 uint64_t clnum : 2; /**< Performance Counter#0 Cluster Selector
4339 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
4340 is used to select/monitor the cluster# for all events
4341 associated with Performance Counter#0. */
4345 uint64_t reserved_6_7 : 2;
4347 uint64_t reserved_14_63 : 50;
4350 struct cvmx_dfa_pfc0_ctl_s cn63xx;
4351 struct cvmx_dfa_pfc0_ctl_s cn63xxp1;
4353 typedef union cvmx_dfa_pfc0_ctl cvmx_dfa_pfc0_ctl_t;
4358 * DFA_PFC1_CNT = DFA Performance Counter \#1
4359 * *FOR INTERNAL USE ONLY*
4362 union cvmx_dfa_pfc1_cnt
4365 struct cvmx_dfa_pfc1_cnt_s
4367 #if __BYTE_ORDER == __BIG_ENDIAN
4368 uint64_t pfcnt1 : 64; /**< Performance Counter \#1
4369 When DFA_PFC_GCTL[CNT1ENA]=1, the event selected
4370 by DFA_PFC1_CTL[EVSEL] is counted.
4371 See also DFA_PFC_GCTL[CNT1WCLR] and DFA_PFC_GCTL
4372 [CNT1RCLR] for special clear count cases available
4373 for SW data collection. */
4375 uint64_t pfcnt1 : 64;
4378 struct cvmx_dfa_pfc1_cnt_s cn63xx;
4379 struct cvmx_dfa_pfc1_cnt_s cn63xxp1;
4381 typedef union cvmx_dfa_pfc1_cnt cvmx_dfa_pfc1_cnt_t;
4386 * DFA_PFC1_CTL = DFA Performance Counter#1 Control
4387 * *FOR INTERNAL USE ONLY*
4390 union cvmx_dfa_pfc1_ctl
4393 struct cvmx_dfa_pfc1_ctl_s
4395 #if __BYTE_ORDER == __BIG_ENDIAN
4396 uint64_t reserved_14_63 : 50;
4397 uint64_t evsel : 6; /**< Performance Counter#1 Event Selector
4399 - 1: \#LDNODE visits
4400 - 2: \#SDNODE visits
4401 - 3: \#DNODE visits (LD/SD)
4402 - 4: \#LCNODE visits
4403 - 5: \#SCNODE visits
4404 - 6: \#CNODE visits (LC/SC)
4405 - 7: \#LMNODE visits
4406 - 8: \#SMNODE visits
4407 - 9: \#MNODE visits (LM/SM)
4408 - 10: \#MONODE visits
4409 - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX
4410 - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX)
4411 - 13: \#MEMORY visits (MNODE+MONODE)
4412 - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions)
4413 - 15: \#MPHIDX detected (occur for ->LMNODE transitions)
4414 - 16: \#RESCANs detected (occur when HASH collision is detected)
4415 - 17: \#GWALK STALLs detected - Packet data/Result Buffer
4416 - 18: \#GWALK DTE cycles (all DTE-GNT[3a])
4417 - 19: \#CLOAD DTE cycles
4418 - 20: \#MLOAD DTE cycles
4419 - 21: \#cycles waiting for Memory Response Data
4420 - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space)
4421 - 23: \#cycles waiting in resource pending state
4422 - 24: \#RWORD1+ writes
4423 - 25: \#DTE-VLD cycles
4424 - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers
4425 - 27: \#GWALK Instructions
4426 - 28: \#CLOAD Instructions
4427 - 29: \#MLOAD Instructions
4428 - 30: \#GFREE Instructions (== \#GFREE DTE cycles)
4430 - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */
4431 uint64_t reserved_6_7 : 2;
4432 uint64_t cldte : 4; /**< Performance Counter#1 Cluster DTE Selector
4433 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
4434 is used to select/monitor the cluster's DTE# for all events
4435 associated with Performance Counter#1. */
4436 uint64_t clnum : 2; /**< Performance Counter#1 Cluster Selector
4437 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
4438 is used to select/monitor the cluster# for all events
4439 associated with Performance Counter#1. */
4443 uint64_t reserved_6_7 : 2;
4445 uint64_t reserved_14_63 : 50;
4448 struct cvmx_dfa_pfc1_ctl_s cn63xx;
4449 struct cvmx_dfa_pfc1_ctl_s cn63xxp1;
4451 typedef union cvmx_dfa_pfc1_ctl cvmx_dfa_pfc1_ctl_t;
4456 * DFA_PFC2_CNT = DFA Performance Counter \#2
4457 * *FOR INTERNAL USE ONLY*
4460 union cvmx_dfa_pfc2_cnt
4463 struct cvmx_dfa_pfc2_cnt_s
4465 #if __BYTE_ORDER == __BIG_ENDIAN
4466 uint64_t pfcnt2 : 64; /**< Performance Counter \#2
4467 When DFA_PFC_GCTL[CNT2ENA]=1, the event selected
4468 by DFA_PFC2_CTL[EVSEL] is counted.
4469 See also DFA_PFC_GCTL[CNT2WCLR] and DFA_PFC_GCTL
4470 [CNT2RCLR] for special clear count cases available
4471 for SW data collection. */
4473 uint64_t pfcnt2 : 64;
4476 struct cvmx_dfa_pfc2_cnt_s cn63xx;
4477 struct cvmx_dfa_pfc2_cnt_s cn63xxp1;
4479 typedef union cvmx_dfa_pfc2_cnt cvmx_dfa_pfc2_cnt_t;
4484 * DFA_PFC2_CTL = DFA Performance Counter#2 Control
4485 * *FOR INTERNAL USE ONLY*
4488 union cvmx_dfa_pfc2_ctl
4491 struct cvmx_dfa_pfc2_ctl_s
4493 #if __BYTE_ORDER == __BIG_ENDIAN
4494 uint64_t reserved_14_63 : 50;
4495 uint64_t evsel : 6; /**< Performance Counter#2 Event Selector
4497 - 1: \#LDNODE visits
4498 - 2: \#SDNODE visits
4499 - 3: \#DNODE visits (LD/SD)
4500 - 4: \#LCNODE visits
4501 - 5: \#SCNODE visits
4502 - 6: \#CNODE visits (LC/SC)
4503 - 7: \#LMNODE visits
4504 - 8: \#SMNODE visits
4505 - 9: \#MNODE visits (LM/SM)
4506 - 10: \#MONODE visits
4507 - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX
4508 - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX)
4509 - 13: \#MEMORY visits (MNODE+MONODE)
4510 - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions)
4511 - 15: \#MPHIDX detected (occur for ->LMNODE transitions)
4512 - 16: \#RESCANs detected (occur when HASH collision is detected)
4513 - 17: \#GWALK STALLs detected - Packet data/Result Buffer
4514 - 18: \#GWALK DTE cycles (all DTE-GNT[3a])
4515 - 19: \#CLOAD DTE cycles
4516 - 20: \#MLOAD DTE cycles
4517 - 21: \#cycles waiting for Memory Response Data
4518 - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space)
4519 - 23: \#cycles waiting in resource pending state
4520 - 24: \#RWORD1+ writes
4521 - 25: \#DTE-VLD cycles
4522 - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers
4523 - 27: \#GWALK Instructions
4524 - 28: \#CLOAD Instructions
4525 - 29: \#MLOAD Instructions
4526 - 30: \#GFREE Instructions (== \#GFREE DTE cycles)
4528 - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */
4529 uint64_t reserved_6_7 : 2;
4530 uint64_t cldte : 4; /**< Performance Counter#2 Cluster DTE Selector
4531 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
4532 is used to select/monitor the cluster's DTE# for all events
4533 associated with Performance Counter#2. */
4534 uint64_t clnum : 2; /**< Performance Counter#2 Cluster Selector
4535 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
4536 is used to select/monitor the cluster# for all events
4537 associated with Performance Counter#2. */
4541 uint64_t reserved_6_7 : 2;
4543 uint64_t reserved_14_63 : 50;
4546 struct cvmx_dfa_pfc2_ctl_s cn63xx;
4547 struct cvmx_dfa_pfc2_ctl_s cn63xxp1;
4549 typedef union cvmx_dfa_pfc2_ctl cvmx_dfa_pfc2_ctl_t;
4554 * DFA_PFC3_CNT = DFA Performance Counter \#3
4555 * *FOR INTERNAL USE ONLY*
4558 union cvmx_dfa_pfc3_cnt
4561 struct cvmx_dfa_pfc3_cnt_s
4563 #if __BYTE_ORDER == __BIG_ENDIAN
4564 uint64_t pfcnt3 : 64; /**< Performance Counter \#3
4565 When DFA_PFC_GCTL[CNT3ENA]=1, the event selected
4566 by DFA_PFC3_CTL[EVSEL] is counted.
4567 See also DFA_PFC_GCTL[CNT3WCLR] and DFA_PFC_GCTL
4568 [CNT3RCLR] for special clear count cases available
4569 for SW data collection. */
4571 uint64_t pfcnt3 : 64;
4574 struct cvmx_dfa_pfc3_cnt_s cn63xx;
4575 struct cvmx_dfa_pfc3_cnt_s cn63xxp1;
4577 typedef union cvmx_dfa_pfc3_cnt cvmx_dfa_pfc3_cnt_t;
4582 * DFA_PFC3_CTL = DFA Performance Counter#3 Control
4583 * *FOR INTERNAL USE ONLY*
4586 union cvmx_dfa_pfc3_ctl
4589 struct cvmx_dfa_pfc3_ctl_s
4591 #if __BYTE_ORDER == __BIG_ENDIAN
4592 uint64_t reserved_14_63 : 50;
4593 uint64_t evsel : 6; /**< Performance Counter#3 Event Selector
4595 - 1: \#LDNODE visits
4596 - 2: \#SDNODE visits
4597 - 3: \#DNODE visits (LD/SD)
4598 - 4: \#LCNODE visits
4599 - 5: \#SCNODE visits
4600 - 6: \#CNODE visits (LC/SC)
4601 - 7: \#LMNODE visits
4602 - 8: \#SMNODE visits
4603 - 9: \#MNODE visits (LM/SM)
4604 - 10: \#MONODE visits
4605 - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX
4606 - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX)
4607 - 13: \#MEMORY visits (MNODE+MONODE)
4608 - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions)
4609 - 15: \#MPHIDX detected (occur for ->LMNODE transitions)
4610 - 16: \#RESCANs detected (occur when HASH collision is detected)
4611 - 17: \#GWALK STALLs detected - Packet data/Result Buffer
4612 - 18: \#GWALK DTE cycles (all DTE-GNT[3a])
4613 - 19: \#CLOAD DTE cycles
4614 - 20: \#MLOAD DTE cycles
4615 - 21: \#cycles waiting for Memory Response Data
4616 - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space)
4617 - 23: \#cycles waiting in resource pending state
4618 - 24: \#RWORD1+ writes
4619 - 25: \#DTE-VLD cycles
4620 - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers
4621 - 27: \#GWALK Instructions
4622 - 28: \#CLOAD Instructions
4623 - 29: \#MLOAD Instructions
4624 - 30: \#GFREE Instructions (== \#GFREE DTE cycles)
4626 - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */
4627 uint64_t reserved_6_7 : 2;
4628 uint64_t cldte : 4; /**< Performance Counter#3 Cluster DTE Selector
4629 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
4630 is used to select/monitor the cluster's DTE# for all events
4631 associated with Performance Counter#3. */
4632 uint64_t clnum : 2; /**< Performance Counter#3 Cluster Selector
4633 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field
4634 is used to select/monitor the cluster# for all events
4635 associated with Performance Counter#3. */
4639 uint64_t reserved_6_7 : 2;
4641 uint64_t reserved_14_63 : 50;
4644 struct cvmx_dfa_pfc3_ctl_s cn63xx;
4645 struct cvmx_dfa_pfc3_ctl_s cn63xxp1;
4647 typedef union cvmx_dfa_pfc3_ctl cvmx_dfa_pfc3_ctl_t;
4652 * DFA_PFC_GCTL = DFA Performance Counter Global Control
4653 * *FOR INTERNAL USE ONLY*
4656 union cvmx_dfa_pfc_gctl
4659 struct cvmx_dfa_pfc_gctl_s
4661 #if __BYTE_ORDER == __BIG_ENDIAN
4662 uint64_t reserved_29_63 : 35;
4663 uint64_t vgid : 8; /**< Virtual Graph Id#
4664 When PMODE=1(per-graph selector), this field is used
4665 to select/monitor only those events which are
4666 associated with this selected VGID(virtual graph ID).
4667 This field is used globally across all four performance
4669 IMPNOTE: I implemented a global VGID across all 4 performance
4670 counters to save wires/area. */
4671 uint64_t pmode : 1; /**< Select Mode
4672 - 0: Events are selected on a per-cluster DTE# (CLNUM/CLDTE)
4673 DFA_PFCx_CTL[CLNUM,CLDTE] specifies the cluster-DTE for
4674 each 1(of 4) performance counters.
4675 - 1: Events are selected on a per-graph basis (VGID=virtual Graph ID).
4676 NOTE: Only EVSEL=[0...31] can be used in conjunction with PMODE=1.
4677 DFA_PFC_GCTL[VGID] specifies the Virtual graph ID used across
4678 all four performance counters. */
4679 uint64_t ednode : 2; /**< Ending DNODE Selector
4680 When ENODE=0/1(*DNODE), this field is used to further
4681 specify the Ending DNODE transition sub-type:
4682 - 0: ALL DNODE sub-types
4683 - 1: ->D2e (explicit DNODE transition node-arc alone transitions to DNODE)
4684 - 2: ->D2i (implicit DNODE transition:arc-present triggers transition)
4685 - 3: ->D1r (rescan DNODE transition) */
4686 uint64_t enode : 3; /**< Ending Node Selector
4687 When DFA_PFCx_CTL[EVSEL]=Node Transition(31), the ENODE
4688 field is used to select Ending Node, and the SNODE
4689 field is used to select the Starting Node.
4698 uint64_t snode : 3; /**< Starting Node Selector
4699 When DFA_PFCx_CTL[EVSEL]=Node Transition(31), the SNODE
4700 field is used to select Starting Node, and the ENODE
4701 field is used to select the Ending Node.
4710 uint64_t cnt3rclr : 1; /**< Performance Counter \#3 Read Clear
4711 If this bit is set, CSR reads to the DFA_PFC3_CNT
4712 will clear the count value. This allows SW to maintain
4713 'cumulative' counters to avoid HW wraparound. */
4714 uint64_t cnt2rclr : 1; /**< Performance Counter \#2 Read Clear
4715 If this bit is set, CSR reads to the DFA_PFC2_CNT
4716 will clear the count value. This allows SW to maintain
4717 'cumulative' counters to avoid HW wraparound. */
4718 uint64_t cnt1rclr : 1; /**< Performance Counter \#1 Read Clear
4719 If this bit is set, CSR reads to the DFA_PFC1_CNT
4720 will clear the count value. This allows SW to maintain
4721 'cumulative' counters to avoid HW wraparound. */
4722 uint64_t cnt0rclr : 1; /**< Performance Counter \#0 Read Clear
4723 If this bit is set, CSR reads to the DFA_PFC0_CNT
4724 will clear the count value. This allows SW to maintain
4725 'cumulative' counters to avoid HW wraparound. */
4726 uint64_t cnt3wclr : 1; /**< Performance Counter \#3 Write Clear
4727 If this bit is set, CSR writes to the DFA_PFC3_CNT
4728 will clear the count value.
4729 If this bit is clear, CSR writes to the DFA_PFC3_CNT
4730 will continue the count from the written value. */
4731 uint64_t cnt2wclr : 1; /**< Performance Counter \#2 Write Clear
4732 If this bit is set, CSR writes to the DFA_PFC2_CNT
4733 will clear the count value.
4734 If this bit is clear, CSR writes to the DFA_PFC2_CNT
4735 will continue the count from the written value. */
4736 uint64_t cnt1wclr : 1; /**< Performance Counter \#1 Write Clear
4737 If this bit is set, CSR writes to the DFA_PFC1_CNT
4738 will clear the count value.
4739 If this bit is clear, CSR writes to the DFA_PFC1_CNT
4740 will continue the count from the written value. */
4741 uint64_t cnt0wclr : 1; /**< Performance Counter \#0 Write Clear
4742 If this bit is set, CSR writes to the DFA_PFC0_CNT
4743 will clear the count value.
4744 If this bit is clear, CSR writes to the DFA_PFC0_CNT
4745 will continue the count from the written value. */
4746 uint64_t cnt3ena : 1; /**< Performance Counter 3 Enable
4747 When this bit is set, the performance counter \#3
4749 uint64_t cnt2ena : 1; /**< Performance Counter 2 Enable
4750 When this bit is set, the performance counter \#2
4752 uint64_t cnt1ena : 1; /**< Performance Counter 1 Enable
4753 When this bit is set, the performance counter \#1
4755 uint64_t cnt0ena : 1; /**< Performance Counter 0 Enable
4756 When this bit is set, the performance counter \#0
4759 uint64_t cnt0ena : 1;
4760 uint64_t cnt1ena : 1;
4761 uint64_t cnt2ena : 1;
4762 uint64_t cnt3ena : 1;
4763 uint64_t cnt0wclr : 1;
4764 uint64_t cnt1wclr : 1;
4765 uint64_t cnt2wclr : 1;
4766 uint64_t cnt3wclr : 1;
4767 uint64_t cnt0rclr : 1;
4768 uint64_t cnt1rclr : 1;
4769 uint64_t cnt2rclr : 1;
4770 uint64_t cnt3rclr : 1;
4773 uint64_t ednode : 2;
4776 uint64_t reserved_29_63 : 35;
4779 struct cvmx_dfa_pfc_gctl_s cn63xx;
4780 struct cvmx_dfa_pfc_gctl_s cn63xxp1;
4782 typedef union cvmx_dfa_pfc_gctl cvmx_dfa_pfc_gctl_t;
4785 * cvmx_dfa_rodt_comp_ctl
4787 * DFA_RODT_COMP_CTL = DFA RLD Compensation control (For read "on die termination")
4790 union cvmx_dfa_rodt_comp_ctl
4793 struct cvmx_dfa_rodt_comp_ctl_s
4795 #if __BYTE_ORDER == __BIG_ENDIAN
4796 uint64_t reserved_17_63 : 47;
4797 uint64_t enable : 1; /**< Read On Die Termination Enable
4798 (0=disable, 1=enable) */
4799 uint64_t reserved_12_15 : 4;
4800 uint64_t nctl : 4; /**< Compensation control bits */
4801 uint64_t reserved_5_7 : 3;
4802 uint64_t pctl : 5; /**< Compensation control bits */
4805 uint64_t reserved_5_7 : 3;
4807 uint64_t reserved_12_15 : 4;
4808 uint64_t enable : 1;
4809 uint64_t reserved_17_63 : 47;
4812 struct cvmx_dfa_rodt_comp_ctl_s cn58xx;
4813 struct cvmx_dfa_rodt_comp_ctl_s cn58xxp1;
4815 typedef union cvmx_dfa_rodt_comp_ctl cvmx_dfa_rodt_comp_ctl_t;
4820 * DFA_SBD_DBG0 = DFA Scoreboard Debug \#0 Register
4822 * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
4823 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
4825 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
4826 * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
4829 union cvmx_dfa_sbd_dbg0
4832 struct cvmx_dfa_sbd_dbg0_s
4834 #if __BYTE_ORDER == __BIG_ENDIAN
4835 uint64_t sbd0 : 64; /**< DFA ScoreBoard \#0 Data
4836 For internal use only! (DFA Scoreboard Debug)
4837 [63:40] rptr[26:3]: Result Base Pointer
4838 [39:24] rwcnt[15:0] Cumulative Result Write Counter
4839 [23] lastgrdrsp: Last Gather-Rd Response
4840 [22] wtgrdrsp: Waiting Gather-Rd Response
4841 [21] wtgrdreq: Waiting for Gather-Rd Issue
4842 [20] glvld: GLPTR/GLCNT Valid
4843 [19] cmpmark: Completion Marked Node Detected
4844 [18:17] cmpcode[1:0]: Completion Code
4845 [0=PDGONE/1=PERR/2=RFULL/3=TERM]
4846 [16] cmpdet: Completion Detected
4847 [15] wthdrwrcmtrsp: Waiting for HDR RWrCmtRsp
4848 [14] wtlastwrcmtrsp: Waiting for LAST RESULT
4850 [13] hdrwrreq: Waiting for HDR RWrReq
4851 [12] wtrwrreq: Waiting for RWrReq
4852 [11] wtwqwrreq: Waiting for WQWrReq issue
4853 [10] lastprdrspeot: Last Packet-Rd Response
4854 [9] lastprdrsp: Last Packet-Rd Response
4855 [8] wtprdrsp: Waiting for PRdRsp EOT
4856 [7] wtprdreq: Waiting for PRdReq Issue
4857 [6] lastpdvld: PDPTR/PDLEN Valid
4858 [5] pdvld: Packet Data Valid
4860 [3] wqdone: WorkQueue Done condition
4861 a) WQWrReq issued(for WQPTR<>0) OR
4862 b) HDR RWrCmtRsp completed)
4863 [2] rwstf: Resultant write STF/P Mode
4864 [1] pdldt: Packet-Data LDT mode
4865 [0] gmode: Gather-Mode */
4870 struct cvmx_dfa_sbd_dbg0_s cn31xx;
4871 struct cvmx_dfa_sbd_dbg0_s cn38xx;
4872 struct cvmx_dfa_sbd_dbg0_s cn38xxp2;
4873 struct cvmx_dfa_sbd_dbg0_s cn58xx;
4874 struct cvmx_dfa_sbd_dbg0_s cn58xxp1;
4876 typedef union cvmx_dfa_sbd_dbg0 cvmx_dfa_sbd_dbg0_t;
4881 * DFA_SBD_DBG1 = DFA Scoreboard Debug \#1 Register
4883 * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
4884 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
4886 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
4887 * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
4890 union cvmx_dfa_sbd_dbg1
4893 struct cvmx_dfa_sbd_dbg1_s
4895 #if __BYTE_ORDER == __BIG_ENDIAN
4896 uint64_t sbd1 : 64; /**< DFA ScoreBoard \#1 Data
4897 For internal use only! (DFA Scoreboard Debug)
4898 [63:61] wqptr[35:33]: Work Queue Pointer
4899 [60:52] rptr[35:27]: Result Base Pointer
4900 [51:16] pdptr[35:0]: Packet Data Pointer
4901 [15:0] pdcnt[15:0]: Packet Data Counter */
4906 struct cvmx_dfa_sbd_dbg1_s cn31xx;
4907 struct cvmx_dfa_sbd_dbg1_s cn38xx;
4908 struct cvmx_dfa_sbd_dbg1_s cn38xxp2;
4909 struct cvmx_dfa_sbd_dbg1_s cn58xx;
4910 struct cvmx_dfa_sbd_dbg1_s cn58xxp1;
4912 typedef union cvmx_dfa_sbd_dbg1 cvmx_dfa_sbd_dbg1_t;
4917 * DFA_SBD_DBG2 = DFA Scoreboard Debug \#2 Register
4919 * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
4920 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
4922 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
4923 * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
4926 union cvmx_dfa_sbd_dbg2
4929 struct cvmx_dfa_sbd_dbg2_s
4931 #if __BYTE_ORDER == __BIG_ENDIAN
4932 uint64_t sbd2 : 64; /**< DFA ScoreBoard \#2 Data
4933 [63:49] wqptr[17:3]: Work Queue Pointer
4934 [48:16] rwptr[35:3]: Result Write Pointer
4935 [15:0] prwcnt[15:0]: Pending Result Write Counter */
4940 struct cvmx_dfa_sbd_dbg2_s cn31xx;
4941 struct cvmx_dfa_sbd_dbg2_s cn38xx;
4942 struct cvmx_dfa_sbd_dbg2_s cn38xxp2;
4943 struct cvmx_dfa_sbd_dbg2_s cn58xx;
4944 struct cvmx_dfa_sbd_dbg2_s cn58xxp1;
4946 typedef union cvmx_dfa_sbd_dbg2 cvmx_dfa_sbd_dbg2_t;
4951 * DFA_SBD_DBG3 = DFA Scoreboard Debug \#3 Register
4953 * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
4954 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
4956 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
4957 * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
4960 union cvmx_dfa_sbd_dbg3
4963 struct cvmx_dfa_sbd_dbg3_s
4965 #if __BYTE_ORDER == __BIG_ENDIAN
4966 uint64_t sbd3 : 64; /**< DFA ScoreBoard \#3 Data
4967 [63:49] wqptr[32:18]: Work Queue Pointer
4968 [48:16] glptr[35:3]: Gather List Pointer
4969 [15:0] glcnt[15:0]: Gather List Counter */
4974 struct cvmx_dfa_sbd_dbg3_s cn31xx;
4975 struct cvmx_dfa_sbd_dbg3_s cn38xx;
4976 struct cvmx_dfa_sbd_dbg3_s cn38xxp2;
4977 struct cvmx_dfa_sbd_dbg3_s cn58xx;
4978 struct cvmx_dfa_sbd_dbg3_s cn58xxp1;
4980 typedef union cvmx_dfa_sbd_dbg3 cvmx_dfa_sbd_dbg3_t;