1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Automatically generated error messages for cn52xx.
46 * This file is auto generated. Do not edit.
50 * <hr><h2>Error tree for CN52XX</h2>
55 * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
56 * edge [fontsize=7, font=helvitica];
57 * cvmx_root [label="ROOT|<root>root"];
58 * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
59 * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
60 * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
61 * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
62 * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
63 * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
64 * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
65 * cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
66 * cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
67 * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
68 * cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<mio>mio|<ipd>ipd|<tim>tim|<pow>pow|<usb1>usb1|<npei>npei|<rad>rad|<pko>pko|<asxpcs0>asxpcs0|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<usb>usb"];
69 * cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
70 * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
71 * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
72 * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
73 * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
74 * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
75 * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
76 * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
77 * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
78 * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
79 * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
80 * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
81 * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
82 * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
83 * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
84 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
85 * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
86 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
87 * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
88 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
89 * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
90 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
91 * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
92 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
93 * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
94 * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
95 * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
96 * cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
97 * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
98 * cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
99 * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
100 * cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
101 * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
102 * cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
103 * cvmx_usbn1_int_sum [label="USBNX_INT_SUM(1)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
104 * cvmx_npei_rsl_int_blocks:usb1:e -> cvmx_usbn1_int_sum [label="usb1"];
105 * cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
106 * cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
107 * cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
108 * cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
109 * cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
110 * cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
111 * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
112 * cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
113 * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
114 * cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
115 * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
116 * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
117 * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
118 * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
119 * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
120 * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
121 * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
122 * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
123 * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
124 * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
125 * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
126 * cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
127 * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
128 * cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
129 * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
130 * cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
131 * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
132 * cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
133 * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
134 * cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
135 * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
136 * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
137 * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
138 * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
139 * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
140 * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
141 * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
142 * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
143 * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
144 * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
145 * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
146 * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
147 * cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
151 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
152 #include <asm/octeon/cvmx.h>
153 #include <asm/octeon/cvmx-error.h>
154 #include <asm/octeon/cvmx-error-custom.h>
155 #include <asm/octeon/cvmx-csr-typedefs.h>
158 #include "cvmx-error.h"
159 #include "cvmx-error-custom.h"
162 int cvmx_error_initialize_cn52xx(void);
164 int cvmx_error_initialize_cn52xx(void)
166 cvmx_error_info_t info;
169 /* CVMX_CIU_INTX_SUM0(0) */
170 info.reg_type = CVMX_ERROR_REGISTER_IO64;
171 info.status_addr = CVMX_CIU_INTX_SUM0(0);
172 info.status_mask = 0;
173 info.enable_addr = 0;
174 info.enable_mask = 0;
176 info.group = CVMX_ERROR_GROUP_INTERNAL;
177 info.group_index = 0;
178 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
179 info.parent.status_addr = 0;
180 info.parent.status_mask = 0;
181 info.func = __cvmx_error_decode;
183 fail |= cvmx_error_add(&info);
185 /* CVMX_MIXX_ISR(0) */
186 info.reg_type = CVMX_ERROR_REGISTER_IO64;
187 info.status_addr = CVMX_MIXX_ISR(0);
188 info.status_mask = 1ull<<0 /* odblovf */;
189 info.enable_addr = CVMX_MIXX_INTENA(0);
190 info.enable_mask = 1ull<<0 /* ovfena */;
192 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
193 info.group_index = 0;
194 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
195 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
196 info.parent.status_mask = 1ull<<62 /* mii */;
197 info.func = __cvmx_error_display;
198 info.user_info = (long)
199 "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
200 " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
201 " with a value greater than the remaining #of\n"
202 " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
203 " the following occurs:\n"
204 " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
205 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
206 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
207 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
208 " and the local interrupt mask bit(OVFENA) is set, than an\n"
209 " interrupt is reported for this event.\n"
210 " SW should keep track of the #I-Ring Entries in use\n"
211 " (ie: cumulative # of ODBELL writes), and ensure that\n"
212 " future ODBELL writes don't exceed the size of the\n"
213 " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
214 " SW must reclaim O-Ring Entries by writing to the\n"
215 " MIX_ORCNT[ORCNT]. .\n"
216 " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
217 " If it occurs, it's an indication that SW has\n"
218 " overwritten the O-Ring buffer, and the only recourse\n"
220 fail |= cvmx_error_add(&info);
222 info.reg_type = CVMX_ERROR_REGISTER_IO64;
223 info.status_addr = CVMX_MIXX_ISR(0);
224 info.status_mask = 1ull<<1 /* idblovf */;
225 info.enable_addr = CVMX_MIXX_INTENA(0);
226 info.enable_mask = 1ull<<1 /* ivfena */;
228 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
229 info.group_index = 0;
230 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
231 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
232 info.parent.status_mask = 1ull<<62 /* mii */;
233 info.func = __cvmx_error_display;
234 info.user_info = (long)
235 "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
236 " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
237 " with a value greater than the remaining #of\n"
238 " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
239 " the following occurs:\n"
240 " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
241 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
242 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
243 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
244 " and the local interrupt mask bit(IVFENA) is set, than an\n"
245 " interrupt is reported for this event.\n"
246 " SW should keep track of the #I-Ring Entries in use\n"
247 " (ie: cumulative # of IDBELL writes), and ensure that\n"
248 " future IDBELL writes don't exceed the size of the\n"
249 " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
250 " SW must reclaim I-Ring Entries by keeping track of the\n"
251 " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
252 " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
253 " total #packets(not IRing Entries) and SW must further\n"
254 " keep track of the # of I-Ring Entries associated with\n"
255 " each packet as they are processed.\n"
256 " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
257 " If it occurs, it's an indication that SW has\n"
258 " overwritten the I-Ring buffer, and the only recourse\n"
260 fail |= cvmx_error_add(&info);
262 info.reg_type = CVMX_ERROR_REGISTER_IO64;
263 info.status_addr = CVMX_MIXX_ISR(0);
264 info.status_mask = 1ull<<4 /* data_drp */;
265 info.enable_addr = CVMX_MIXX_INTENA(0);
266 info.enable_mask = 1ull<<4 /* data_drpena */;
268 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
269 info.group_index = 0;
270 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
271 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
272 info.parent.status_mask = 1ull<<62 /* mii */;
273 info.func = __cvmx_error_display;
274 info.user_info = (long)
275 "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
276 " If this does occur, the DATA_DRP is set and the\n"
277 " CIU_INTx_SUM0,4[MII] bits are set.\n"
278 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
279 " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
280 " interrupt is reported for this event.\n";
281 fail |= cvmx_error_add(&info);
283 info.reg_type = CVMX_ERROR_REGISTER_IO64;
284 info.status_addr = CVMX_MIXX_ISR(0);
285 info.status_mask = 1ull<<5 /* irun */;
286 info.enable_addr = CVMX_MIXX_INTENA(0);
287 info.enable_mask = 1ull<<5 /* irunena */;
289 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
290 info.group_index = 0;
291 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
292 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
293 info.parent.status_mask = 1ull<<62 /* mii */;
294 info.func = __cvmx_error_display;
295 info.user_info = (long)
296 "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
297 " If SW writes a larger value than what is currently\n"
298 " in the MIX_IRCNT[IRCNT], then HW will report the\n"
299 " underflow condition.\n"
300 " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
301 " NOTE: If an IRUN underflow condition is detected,\n"
302 " the integrity of the MIX/AGL HW state has\n"
303 " been compromised. To recover, SW must issue a\n"
304 " software reset sequence (see: MIX_CTL[RESET]\n";
305 fail |= cvmx_error_add(&info);
307 info.reg_type = CVMX_ERROR_REGISTER_IO64;
308 info.status_addr = CVMX_MIXX_ISR(0);
309 info.status_mask = 1ull<<6 /* orun */;
310 info.enable_addr = CVMX_MIXX_INTENA(0);
311 info.enable_mask = 1ull<<6 /* orunena */;
313 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
314 info.group_index = 0;
315 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
316 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
317 info.parent.status_mask = 1ull<<62 /* mii */;
318 info.func = __cvmx_error_display;
319 info.user_info = (long)
320 "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
321 " If SW writes a larger value than what is currently\n"
322 " in the MIX_ORCNT[ORCNT], then HW will report the\n"
323 " underflow condition.\n"
324 " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
325 " NOTE: If an ORUN underflow condition is detected,\n"
326 " the integrity of the MIX/AGL HW state has\n"
327 " been compromised. To recover, SW must issue a\n"
328 " software reset sequence (see: MIX_CTL[RESET]\n";
329 fail |= cvmx_error_add(&info);
331 /* CVMX_CIU_INT_SUM1 */
332 info.reg_type = CVMX_ERROR_REGISTER_IO64;
333 info.status_addr = CVMX_CIU_INT_SUM1;
334 info.status_mask = 0;
335 info.enable_addr = 0;
336 info.enable_mask = 0;
338 info.group = CVMX_ERROR_GROUP_INTERNAL;
339 info.group_index = 0;
340 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
341 info.parent.status_addr = 0;
342 info.parent.status_mask = 0;
343 info.func = __cvmx_error_decode;
345 fail |= cvmx_error_add(&info);
347 /* CVMX_MIXX_ISR(1) */
348 info.reg_type = CVMX_ERROR_REGISTER_IO64;
349 info.status_addr = CVMX_MIXX_ISR(1);
350 info.status_mask = 1ull<<0 /* odblovf */;
351 info.enable_addr = CVMX_MIXX_INTENA(1);
352 info.enable_mask = 1ull<<0 /* ovfena */;
354 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
355 info.group_index = 1;
356 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
357 info.parent.status_addr = CVMX_CIU_INT_SUM1;
358 info.parent.status_mask = 1ull<<18 /* mii1 */;
359 info.func = __cvmx_error_display;
360 info.user_info = (long)
361 "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
362 " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
363 " with a value greater than the remaining #of\n"
364 " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
365 " the following occurs:\n"
366 " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
367 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
368 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
369 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
370 " and the local interrupt mask bit(OVFENA) is set, than an\n"
371 " interrupt is reported for this event.\n"
372 " SW should keep track of the #I-Ring Entries in use\n"
373 " (ie: cumulative # of ODBELL writes), and ensure that\n"
374 " future ODBELL writes don't exceed the size of the\n"
375 " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
376 " SW must reclaim O-Ring Entries by writing to the\n"
377 " MIX_ORCNT[ORCNT]. .\n"
378 " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
379 " If it occurs, it's an indication that SW has\n"
380 " overwritten the O-Ring buffer, and the only recourse\n"
382 fail |= cvmx_error_add(&info);
384 info.reg_type = CVMX_ERROR_REGISTER_IO64;
385 info.status_addr = CVMX_MIXX_ISR(1);
386 info.status_mask = 1ull<<1 /* idblovf */;
387 info.enable_addr = CVMX_MIXX_INTENA(1);
388 info.enable_mask = 1ull<<1 /* ivfena */;
390 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
391 info.group_index = 1;
392 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
393 info.parent.status_addr = CVMX_CIU_INT_SUM1;
394 info.parent.status_mask = 1ull<<18 /* mii1 */;
395 info.func = __cvmx_error_display;
396 info.user_info = (long)
397 "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
398 " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
399 " with a value greater than the remaining #of\n"
400 " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
401 " the following occurs:\n"
402 " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
403 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
404 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
405 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
406 " and the local interrupt mask bit(IVFENA) is set, than an\n"
407 " interrupt is reported for this event.\n"
408 " SW should keep track of the #I-Ring Entries in use\n"
409 " (ie: cumulative # of IDBELL writes), and ensure that\n"
410 " future IDBELL writes don't exceed the size of the\n"
411 " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
412 " SW must reclaim I-Ring Entries by keeping track of the\n"
413 " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
414 " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
415 " total #packets(not IRing Entries) and SW must further\n"
416 " keep track of the # of I-Ring Entries associated with\n"
417 " each packet as they are processed.\n"
418 " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
419 " If it occurs, it's an indication that SW has\n"
420 " overwritten the I-Ring buffer, and the only recourse\n"
422 fail |= cvmx_error_add(&info);
424 info.reg_type = CVMX_ERROR_REGISTER_IO64;
425 info.status_addr = CVMX_MIXX_ISR(1);
426 info.status_mask = 1ull<<4 /* data_drp */;
427 info.enable_addr = CVMX_MIXX_INTENA(1);
428 info.enable_mask = 1ull<<4 /* data_drpena */;
430 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
431 info.group_index = 1;
432 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
433 info.parent.status_addr = CVMX_CIU_INT_SUM1;
434 info.parent.status_mask = 1ull<<18 /* mii1 */;
435 info.func = __cvmx_error_display;
436 info.user_info = (long)
437 "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
438 " If this does occur, the DATA_DRP is set and the\n"
439 " CIU_INTx_SUM0,4[MII] bits are set.\n"
440 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
441 " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
442 " interrupt is reported for this event.\n";
443 fail |= cvmx_error_add(&info);
445 info.reg_type = CVMX_ERROR_REGISTER_IO64;
446 info.status_addr = CVMX_MIXX_ISR(1);
447 info.status_mask = 1ull<<5 /* irun */;
448 info.enable_addr = CVMX_MIXX_INTENA(1);
449 info.enable_mask = 1ull<<5 /* irunena */;
451 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
452 info.group_index = 1;
453 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
454 info.parent.status_addr = CVMX_CIU_INT_SUM1;
455 info.parent.status_mask = 1ull<<18 /* mii1 */;
456 info.func = __cvmx_error_display;
457 info.user_info = (long)
458 "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
459 " If SW writes a larger value than what is currently\n"
460 " in the MIX_IRCNT[IRCNT], then HW will report the\n"
461 " underflow condition.\n"
462 " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
463 " NOTE: If an IRUN underflow condition is detected,\n"
464 " the integrity of the MIX/AGL HW state has\n"
465 " been compromised. To recover, SW must issue a\n"
466 " software reset sequence (see: MIX_CTL[RESET]\n";
467 fail |= cvmx_error_add(&info);
469 info.reg_type = CVMX_ERROR_REGISTER_IO64;
470 info.status_addr = CVMX_MIXX_ISR(1);
471 info.status_mask = 1ull<<6 /* orun */;
472 info.enable_addr = CVMX_MIXX_INTENA(1);
473 info.enable_mask = 1ull<<6 /* orunena */;
475 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
476 info.group_index = 1;
477 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
478 info.parent.status_addr = CVMX_CIU_INT_SUM1;
479 info.parent.status_mask = 1ull<<18 /* mii1 */;
480 info.func = __cvmx_error_display;
481 info.user_info = (long)
482 "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
483 " If SW writes a larger value than what is currently\n"
484 " in the MIX_ORCNT[ORCNT], then HW will report the\n"
485 " underflow condition.\n"
486 " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
487 " NOTE: If an ORUN underflow condition is detected,\n"
488 " the integrity of the MIX/AGL HW state has\n"
489 " been compromised. To recover, SW must issue a\n"
490 " software reset sequence (see: MIX_CTL[RESET]\n";
491 fail |= cvmx_error_add(&info);
494 info.reg_type = CVMX_ERROR_REGISTER_IO64;
495 info.status_addr = CVMX_NDF_INT;
496 info.status_mask = 1ull<<2 /* wdog */;
497 info.enable_addr = CVMX_NDF_INT_EN;
498 info.enable_mask = 1ull<<2 /* wdog */;
500 info.group = CVMX_ERROR_GROUP_INTERNAL;
501 info.group_index = 0;
502 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
503 info.parent.status_addr = CVMX_CIU_INT_SUM1;
504 info.parent.status_mask = 1ull<<19 /* nand */;
505 info.func = __cvmx_error_display;
506 info.user_info = (long)
507 "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
508 fail |= cvmx_error_add(&info);
510 info.reg_type = CVMX_ERROR_REGISTER_IO64;
511 info.status_addr = CVMX_NDF_INT;
512 info.status_mask = 1ull<<3 /* sm_bad */;
513 info.enable_addr = CVMX_NDF_INT_EN;
514 info.enable_mask = 1ull<<3 /* sm_bad */;
516 info.group = CVMX_ERROR_GROUP_INTERNAL;
517 info.group_index = 0;
518 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
519 info.parent.status_addr = CVMX_CIU_INT_SUM1;
520 info.parent.status_mask = 1ull<<19 /* nand */;
521 info.func = __cvmx_error_display;
522 info.user_info = (long)
523 "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
524 fail |= cvmx_error_add(&info);
526 info.reg_type = CVMX_ERROR_REGISTER_IO64;
527 info.status_addr = CVMX_NDF_INT;
528 info.status_mask = 1ull<<4 /* ecc_1bit */;
529 info.enable_addr = CVMX_NDF_INT_EN;
530 info.enable_mask = 1ull<<4 /* ecc_1bit */;
532 info.group = CVMX_ERROR_GROUP_INTERNAL;
533 info.group_index = 0;
534 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
535 info.parent.status_addr = CVMX_CIU_INT_SUM1;
536 info.parent.status_mask = 1ull<<19 /* nand */;
537 info.func = __cvmx_error_display;
538 info.user_info = (long)
539 "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
540 fail |= cvmx_error_add(&info);
542 info.reg_type = CVMX_ERROR_REGISTER_IO64;
543 info.status_addr = CVMX_NDF_INT;
544 info.status_mask = 1ull<<5 /* ecc_mult */;
545 info.enable_addr = CVMX_NDF_INT_EN;
546 info.enable_mask = 1ull<<5 /* ecc_mult */;
548 info.group = CVMX_ERROR_GROUP_INTERNAL;
549 info.group_index = 0;
550 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
551 info.parent.status_addr = CVMX_CIU_INT_SUM1;
552 info.parent.status_mask = 1ull<<19 /* nand */;
553 info.func = __cvmx_error_display;
554 info.user_info = (long)
555 "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
556 fail |= cvmx_error_add(&info);
558 info.reg_type = CVMX_ERROR_REGISTER_IO64;
559 info.status_addr = CVMX_NDF_INT;
560 info.status_mask = 1ull<<6 /* ovrf */;
561 info.enable_addr = CVMX_NDF_INT_EN;
562 info.enable_mask = 1ull<<6 /* ovrf */;
564 info.group = CVMX_ERROR_GROUP_INTERNAL;
565 info.group_index = 0;
566 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
567 info.parent.status_addr = CVMX_CIU_INT_SUM1;
568 info.parent.status_mask = 1ull<<19 /* nand */;
569 info.func = __cvmx_error_display;
570 info.user_info = (long)
571 "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
573 fail |= cvmx_error_add(&info);
575 /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
576 info.reg_type = CVMX_ERROR_REGISTER_IO64;
577 info.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
578 info.status_mask = 0;
579 info.enable_addr = 0;
580 info.enable_mask = 0;
582 info.group = CVMX_ERROR_GROUP_INTERNAL;
583 info.group_index = 0;
584 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
585 info.parent.status_addr = 0;
586 info.parent.status_mask = 0;
587 info.func = __cvmx_error_decode;
589 fail |= cvmx_error_add(&info);
591 /* CVMX_L2C_INT_STAT */
592 info.reg_type = CVMX_ERROR_REGISTER_IO64;
593 info.status_addr = CVMX_L2C_INT_STAT;
594 info.status_mask = 1ull<<3 /* l2tsec */;
595 info.enable_addr = CVMX_L2C_INT_EN;
596 info.enable_mask = 1ull<<3 /* l2tsecen */;
597 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
598 info.group = CVMX_ERROR_GROUP_INTERNAL;
599 info.group_index = 0;
600 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
601 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
602 info.parent.status_mask = 1ull<<16 /* l2c */;
603 info.func = __cvmx_error_display;
604 info.user_info = (long)
605 "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
606 " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
607 " given index) are checked for single bit errors(SBEs).\n"
608 " This bit is set if ANY of the 8 sets contains an SBE.\n"
609 " SBEs are auto corrected in HW and generate an\n"
610 " interrupt(if enabled).\n"
611 " NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
612 fail |= cvmx_error_add(&info);
614 info.reg_type = CVMX_ERROR_REGISTER_IO64;
615 info.status_addr = CVMX_L2C_INT_STAT;
616 info.status_mask = 1ull<<5 /* l2dsec */;
617 info.enable_addr = CVMX_L2C_INT_EN;
618 info.enable_mask = 1ull<<5 /* l2dsecen */;
619 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
620 info.group = CVMX_ERROR_GROUP_INTERNAL;
621 info.group_index = 0;
622 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
623 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
624 info.parent.status_mask = 1ull<<16 /* l2c */;
625 info.func = __cvmx_error_display;
626 info.user_info = (long)
627 "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
628 " NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
629 fail |= cvmx_error_add(&info);
631 info.reg_type = CVMX_ERROR_REGISTER_IO64;
632 info.status_addr = CVMX_L2C_INT_STAT;
633 info.status_mask = 1ull<<0 /* oob1 */;
634 info.enable_addr = CVMX_L2C_INT_EN;
635 info.enable_mask = 1ull<<0 /* oob1en */;
637 info.group = CVMX_ERROR_GROUP_INTERNAL;
638 info.group_index = 0;
639 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
640 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
641 info.parent.status_mask = 1ull<<16 /* l2c */;
642 info.func = __cvmx_error_display;
643 info.user_info = (long)
644 "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
645 fail |= cvmx_error_add(&info);
647 info.reg_type = CVMX_ERROR_REGISTER_IO64;
648 info.status_addr = CVMX_L2C_INT_STAT;
649 info.status_mask = 1ull<<1 /* oob2 */;
650 info.enable_addr = CVMX_L2C_INT_EN;
651 info.enable_mask = 1ull<<1 /* oob2en */;
653 info.group = CVMX_ERROR_GROUP_INTERNAL;
654 info.group_index = 0;
655 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
656 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
657 info.parent.status_mask = 1ull<<16 /* l2c */;
658 info.func = __cvmx_error_display;
659 info.user_info = (long)
660 "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
661 fail |= cvmx_error_add(&info);
663 info.reg_type = CVMX_ERROR_REGISTER_IO64;
664 info.status_addr = CVMX_L2C_INT_STAT;
665 info.status_mask = 1ull<<2 /* oob3 */;
666 info.enable_addr = CVMX_L2C_INT_EN;
667 info.enable_mask = 1ull<<2 /* oob3en */;
669 info.group = CVMX_ERROR_GROUP_INTERNAL;
670 info.group_index = 0;
671 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
672 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
673 info.parent.status_mask = 1ull<<16 /* l2c */;
674 info.func = __cvmx_error_display;
675 info.user_info = (long)
676 "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
677 fail |= cvmx_error_add(&info);
679 info.reg_type = CVMX_ERROR_REGISTER_IO64;
680 info.status_addr = CVMX_L2C_INT_STAT;
681 info.status_mask = 1ull<<4 /* l2tded */;
682 info.enable_addr = CVMX_L2C_INT_EN;
683 info.enable_mask = 1ull<<4 /* l2tdeden */;
685 info.group = CVMX_ERROR_GROUP_INTERNAL;
686 info.group_index = 0;
687 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
688 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
689 info.parent.status_mask = 1ull<<16 /* l2c */;
690 info.func = __cvmx_error_display;
691 info.user_info = (long)
692 "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
693 " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
694 " given index) are checked for double bit errors(DBEs).\n"
695 " This bit is set if ANY of the 8 sets contains a DBE.\n"
696 " DBEs also generated an interrupt(if enabled).\n"
697 " NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
698 fail |= cvmx_error_add(&info);
700 info.reg_type = CVMX_ERROR_REGISTER_IO64;
701 info.status_addr = CVMX_L2C_INT_STAT;
702 info.status_mask = 1ull<<6 /* l2dded */;
703 info.enable_addr = CVMX_L2C_INT_EN;
704 info.enable_mask = 1ull<<6 /* l2ddeden */;
706 info.group = CVMX_ERROR_GROUP_INTERNAL;
707 info.group_index = 0;
708 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
709 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
710 info.parent.status_mask = 1ull<<16 /* l2c */;
711 info.func = __cvmx_error_display;
712 info.user_info = (long)
713 "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
714 " NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
715 fail |= cvmx_error_add(&info);
717 info.reg_type = CVMX_ERROR_REGISTER_IO64;
718 info.status_addr = CVMX_L2C_INT_STAT;
719 info.status_mask = 1ull<<7 /* lck */;
720 info.enable_addr = CVMX_L2C_INT_EN;
721 info.enable_mask = 1ull<<7 /* lckena */;
723 info.group = CVMX_ERROR_GROUP_INTERNAL;
724 info.group_index = 0;
725 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
726 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
727 info.parent.status_mask = 1ull<<16 /* l2c */;
728 info.func = __cvmx_error_display;
729 info.user_info = (long)
730 "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
731 " the INDEX (which is ignored by HW - but reported to SW).\n"
732 " The LDD(L1 load-miss) for the LOCK operation is completed\n"
733 " successfully, however the address is NOT locked.\n"
734 " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
735 " into account. For example, if diagnostic PPx has\n"
736 " UMSKx defined to only use SETs [1:0], and SET1 had\n"
737 " been previously LOCKED, then an attempt to LOCK the\n"
738 " last available SET0 would result in a LCKERR. (This\n"
739 " is to ensure that at least 1 SET at each INDEX is\n"
740 " not LOCKED for general use by other PPs).\n"
741 " NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
742 fail |= cvmx_error_add(&info);
744 info.reg_type = CVMX_ERROR_REGISTER_IO64;
745 info.status_addr = CVMX_L2C_INT_STAT;
746 info.status_mask = 1ull<<8 /* lck2 */;
747 info.enable_addr = CVMX_L2C_INT_EN;
748 info.enable_mask = 1ull<<8 /* lck2ena */;
750 info.group = CVMX_ERROR_GROUP_INTERNAL;
751 info.group_index = 0;
752 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
753 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
754 info.parent.status_mask = 1ull<<16 /* l2c */;
755 info.func = __cvmx_error_display;
756 info.user_info = (long)
757 "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
758 " could not find an available/unlocked set (for\n"
760 " Most likely, this is a result of SW mixing SET\n"
761 " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
762 " another PP to LOCKDOWN all SETs available to PP#n,\n"
763 " then a Rd/Wr Miss from PP#n will be unable\n"
764 " to determine a 'valid' replacement set (since LOCKED\n"
765 " addresses should NEVER be replaced).\n"
766 " If such an event occurs, the HW will select the smallest\n"
767 " available SET(specified by UMSK'x)' as the replacement\n"
768 " set, and the address is unlocked.\n"
769 " NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
770 fail |= cvmx_error_add(&info);
773 info.reg_type = CVMX_ERROR_REGISTER_IO64;
774 info.status_addr = CVMX_L2D_ERR;
775 info.status_mask = 1ull<<3 /* sec_err */;
776 info.enable_addr = CVMX_L2D_ERR;
777 info.enable_mask = 1ull<<1 /* sec_intena */;
778 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
779 info.group = CVMX_ERROR_GROUP_INTERNAL;
780 info.group_index = 0;
781 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
782 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
783 info.parent.status_mask = 1ull<<16 /* l2c */;
784 info.func = __cvmx_error_handle_l2d_err_sec_err;
785 info.user_info = (long)
786 "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
787 fail |= cvmx_error_add(&info);
789 info.reg_type = CVMX_ERROR_REGISTER_IO64;
790 info.status_addr = CVMX_L2D_ERR;
791 info.status_mask = 1ull<<4 /* ded_err */;
792 info.enable_addr = CVMX_L2D_ERR;
793 info.enable_mask = 1ull<<2 /* ded_intena */;
795 info.group = CVMX_ERROR_GROUP_INTERNAL;
796 info.group_index = 0;
797 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
798 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
799 info.parent.status_mask = 1ull<<16 /* l2c */;
800 info.func = __cvmx_error_handle_l2d_err_ded_err;
801 info.user_info = (long)
802 "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
803 fail |= cvmx_error_add(&info);
806 info.reg_type = CVMX_ERROR_REGISTER_IO64;
807 info.status_addr = CVMX_L2T_ERR;
808 info.status_mask = 1ull<<3 /* sec_err */;
809 info.enable_addr = CVMX_L2T_ERR;
810 info.enable_mask = 1ull<<1 /* sec_intena */;
811 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
812 info.group = CVMX_ERROR_GROUP_INTERNAL;
813 info.group_index = 0;
814 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
815 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
816 info.parent.status_mask = 1ull<<16 /* l2c */;
817 info.func = __cvmx_error_handle_l2t_err_sec_err;
818 info.user_info = (long)
819 "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
820 " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
821 " given index) are checked for single bit errors(SBEs).\n"
822 " This bit is set if ANY of the 8 sets contains an SBE.\n"
823 " SBEs are auto corrected in HW and generate an\n"
824 " interrupt(if enabled).\n";
825 fail |= cvmx_error_add(&info);
827 info.reg_type = CVMX_ERROR_REGISTER_IO64;
828 info.status_addr = CVMX_L2T_ERR;
829 info.status_mask = 1ull<<4 /* ded_err */;
830 info.enable_addr = CVMX_L2T_ERR;
831 info.enable_mask = 1ull<<2 /* ded_intena */;
833 info.group = CVMX_ERROR_GROUP_INTERNAL;
834 info.group_index = 0;
835 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
836 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
837 info.parent.status_mask = 1ull<<16 /* l2c */;
838 info.func = __cvmx_error_handle_l2t_err_ded_err;
839 info.user_info = (long)
840 "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
841 " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
842 " given index) are checked for double bit errors(DBEs).\n"
843 " This bit is set if ANY of the 8 sets contains a DBE.\n"
844 " DBEs also generated an interrupt(if enabled).\n";
845 fail |= cvmx_error_add(&info);
847 info.reg_type = CVMX_ERROR_REGISTER_IO64;
848 info.status_addr = CVMX_L2T_ERR;
849 info.status_mask = 1ull<<24 /* lckerr */;
850 info.enable_addr = CVMX_L2T_ERR;
851 info.enable_mask = 1ull<<25 /* lck_intena */;
853 info.group = CVMX_ERROR_GROUP_INTERNAL;
854 info.group_index = 0;
855 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
856 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
857 info.parent.status_mask = 1ull<<16 /* l2c */;
858 info.func = __cvmx_error_handle_l2t_err_lckerr;
859 info.user_info = (long)
860 "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
861 " the INDEX (which is ignored by HW - but reported to SW).\n"
862 " The LDD(L1 load-miss) for the LOCK operation is completed\n"
863 " successfully, however the address is NOT locked.\n"
864 " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
865 " into account. For example, if diagnostic PPx has\n"
866 " UMSKx defined to only use SETs [1:0], and SET1 had\n"
867 " been previously LOCKED, then an attempt to LOCK the\n"
868 " last available SET0 would result in a LCKERR. (This\n"
869 " is to ensure that at least 1 SET at each INDEX is\n"
870 " not LOCKED for general use by other PPs).\n";
871 fail |= cvmx_error_add(&info);
873 info.reg_type = CVMX_ERROR_REGISTER_IO64;
874 info.status_addr = CVMX_L2T_ERR;
875 info.status_mask = 1ull<<26 /* lckerr2 */;
876 info.enable_addr = CVMX_L2T_ERR;
877 info.enable_mask = 1ull<<27 /* lck_intena2 */;
879 info.group = CVMX_ERROR_GROUP_INTERNAL;
880 info.group_index = 0;
881 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
882 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
883 info.parent.status_mask = 1ull<<16 /* l2c */;
884 info.func = __cvmx_error_handle_l2t_err_lckerr2;
885 info.user_info = (long)
886 "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
887 " could not find an available/unlocked set (for\n"
889 " Most likely, this is a result of SW mixing SET\n"
890 " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
891 " another PP to LOCKDOWN all SETs available to PP#n,\n"
892 " then a Rd/Wr Miss from PP#n will be unable\n"
893 " to determine a 'valid' replacement set (since LOCKED\n"
894 " addresses should NEVER be replaced).\n"
895 " If such an event occurs, the HW will select the smallest\n"
896 " available SET(specified by UMSK'x)' as the replacement\n"
897 " set, and the address is unlocked.\n";
898 fail |= cvmx_error_add(&info);
900 /* CVMX_AGL_GMX_BAD_REG */
901 info.reg_type = CVMX_ERROR_REGISTER_IO64;
902 info.status_addr = CVMX_AGL_GMX_BAD_REG;
903 info.status_mask = 1ull<<32 /* ovrflw */;
904 info.enable_addr = 0;
905 info.enable_mask = 0;
907 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
908 info.group_index = 0;
909 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
910 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
911 info.parent.status_mask = 1ull<<28 /* agl */;
912 info.func = __cvmx_error_display;
913 info.user_info = (long)
914 "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
915 fail |= cvmx_error_add(&info);
917 info.reg_type = CVMX_ERROR_REGISTER_IO64;
918 info.status_addr = CVMX_AGL_GMX_BAD_REG;
919 info.status_mask = 1ull<<33 /* txpop */;
920 info.enable_addr = 0;
921 info.enable_mask = 0;
923 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
924 info.group_index = 0;
925 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
926 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
927 info.parent.status_mask = 1ull<<28 /* agl */;
928 info.func = __cvmx_error_display;
929 info.user_info = (long)
930 "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
931 fail |= cvmx_error_add(&info);
933 info.reg_type = CVMX_ERROR_REGISTER_IO64;
934 info.status_addr = CVMX_AGL_GMX_BAD_REG;
935 info.status_mask = 1ull<<34 /* txpsh */;
936 info.enable_addr = 0;
937 info.enable_mask = 0;
939 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
940 info.group_index = 0;
941 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
942 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
943 info.parent.status_mask = 1ull<<28 /* agl */;
944 info.func = __cvmx_error_display;
945 info.user_info = (long)
946 "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
947 fail |= cvmx_error_add(&info);
949 info.reg_type = CVMX_ERROR_REGISTER_IO64;
950 info.status_addr = CVMX_AGL_GMX_BAD_REG;
951 info.status_mask = 1ull<<35 /* ovrflw1 */;
952 info.enable_addr = 0;
953 info.enable_mask = 0;
955 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
956 info.group_index = 0;
957 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
958 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
959 info.parent.status_mask = 1ull<<28 /* agl */;
960 info.func = __cvmx_error_display;
961 info.user_info = (long)
962 "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
963 fail |= cvmx_error_add(&info);
965 info.reg_type = CVMX_ERROR_REGISTER_IO64;
966 info.status_addr = CVMX_AGL_GMX_BAD_REG;
967 info.status_mask = 1ull<<36 /* txpop1 */;
968 info.enable_addr = 0;
969 info.enable_mask = 0;
971 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
972 info.group_index = 0;
973 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
974 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
975 info.parent.status_mask = 1ull<<28 /* agl */;
976 info.func = __cvmx_error_display;
977 info.user_info = (long)
978 "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
979 fail |= cvmx_error_add(&info);
981 info.reg_type = CVMX_ERROR_REGISTER_IO64;
982 info.status_addr = CVMX_AGL_GMX_BAD_REG;
983 info.status_mask = 1ull<<37 /* txpsh1 */;
984 info.enable_addr = 0;
985 info.enable_mask = 0;
987 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
988 info.group_index = 0;
989 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
990 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
991 info.parent.status_mask = 1ull<<28 /* agl */;
992 info.func = __cvmx_error_display;
993 info.user_info = (long)
994 "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
995 fail |= cvmx_error_add(&info);
997 info.reg_type = CVMX_ERROR_REGISTER_IO64;
998 info.status_addr = CVMX_AGL_GMX_BAD_REG;
999 info.status_mask = 0x3ull<<2 /* out_ovr */;
1000 info.enable_addr = 0;
1001 info.enable_mask = 0;
1003 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
1004 info.group_index = 0;
1005 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1006 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1007 info.parent.status_mask = 1ull<<28 /* agl */;
1008 info.func = __cvmx_error_display;
1009 info.user_info = (long)
1010 "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
1011 fail |= cvmx_error_add(&info);
1013 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1014 info.status_addr = CVMX_AGL_GMX_BAD_REG;
1015 info.status_mask = 1ull<<22 /* loststat */;
1016 info.enable_addr = 0;
1017 info.enable_mask = 0;
1019 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
1020 info.group_index = 0;
1021 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1022 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1023 info.parent.status_mask = 1ull<<28 /* agl */;
1024 info.func = __cvmx_error_display;
1025 info.user_info = (long)
1026 "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
1027 " TX Stats are corrupted\n";
1028 fail |= cvmx_error_add(&info);
1030 /* CVMX_AGL_GMX_RXX_INT_REG(0) */
1031 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1032 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
1033 info.status_mask = 1ull<<8 /* skperr */;
1034 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
1035 info.enable_mask = 1ull<<8 /* skperr */;
1037 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
1038 info.group_index = 0;
1039 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1040 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1041 info.parent.status_mask = 1ull<<28 /* agl */;
1042 info.func = __cvmx_error_display;
1043 info.user_info = (long)
1044 "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
1045 fail |= cvmx_error_add(&info);
1047 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1048 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
1049 info.status_mask = 1ull<<10 /* ovrerr */;
1050 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
1051 info.enable_mask = 1ull<<10 /* ovrerr */;
1053 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
1054 info.group_index = 0;
1055 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1056 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1057 info.parent.status_mask = 1ull<<28 /* agl */;
1058 info.func = __cvmx_error_display;
1059 info.user_info = (long)
1060 "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
1061 " This interrupt should never assert\n";
1062 fail |= cvmx_error_add(&info);
1064 /* CVMX_AGL_GMX_RXX_INT_REG(1) */
1065 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1066 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
1067 info.status_mask = 1ull<<8 /* skperr */;
1068 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
1069 info.enable_mask = 1ull<<8 /* skperr */;
1071 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
1072 info.group_index = 1;
1073 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1074 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1075 info.parent.status_mask = 1ull<<28 /* agl */;
1076 info.func = __cvmx_error_display;
1077 info.user_info = (long)
1078 "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
1079 fail |= cvmx_error_add(&info);
1081 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1082 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
1083 info.status_mask = 1ull<<10 /* ovrerr */;
1084 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
1085 info.enable_mask = 1ull<<10 /* ovrerr */;
1087 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
1088 info.group_index = 1;
1089 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1090 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1091 info.parent.status_mask = 1ull<<28 /* agl */;
1092 info.func = __cvmx_error_display;
1093 info.user_info = (long)
1094 "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
1095 " This interrupt should never assert\n";
1096 fail |= cvmx_error_add(&info);
1098 /* CVMX_AGL_GMX_TX_INT_REG */
1099 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1100 info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
1101 info.status_mask = 1ull<<0 /* pko_nxa */;
1102 info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
1103 info.enable_mask = 1ull<<0 /* pko_nxa */;
1105 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
1106 info.group_index = 0;
1107 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1108 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1109 info.parent.status_mask = 1ull<<28 /* agl */;
1110 info.func = __cvmx_error_display;
1111 info.user_info = (long)
1112 "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
1113 fail |= cvmx_error_add(&info);
1115 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1116 info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
1117 info.status_mask = 0x3ull<<2 /* undflw */;
1118 info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
1119 info.enable_mask = 0x3ull<<2 /* undflw */;
1121 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
1122 info.group_index = 0;
1123 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1124 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1125 info.parent.status_mask = 1ull<<28 /* agl */;
1126 info.func = __cvmx_error_display;
1127 info.user_info = (long)
1128 "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
1129 fail |= cvmx_error_add(&info);
1131 /* CVMX_GMXX_BAD_REG(0) */
1132 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1133 info.status_addr = CVMX_GMXX_BAD_REG(0);
1134 info.status_mask = 0xfull<<2 /* out_ovr */;
1135 info.enable_addr = 0;
1136 info.enable_mask = 0;
1138 info.group = CVMX_ERROR_GROUP_ETHERNET;
1139 info.group_index = 0;
1140 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1141 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1142 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1143 info.func = __cvmx_error_display;
1144 info.user_info = (long)
1145 "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
1146 fail |= cvmx_error_add(&info);
1148 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1149 info.status_addr = CVMX_GMXX_BAD_REG(0);
1150 info.status_mask = 0xfull<<22 /* loststat */;
1151 info.enable_addr = 0;
1152 info.enable_mask = 0;
1154 info.group = CVMX_ERROR_GROUP_ETHERNET;
1155 info.group_index = 0;
1156 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1157 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1158 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1159 info.func = __cvmx_error_display;
1160 info.user_info = (long)
1161 "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
1162 " In SGMII, one bit per port\n"
1163 " In XAUI, only port0 is used\n"
1164 " TX Stats are corrupted\n";
1165 fail |= cvmx_error_add(&info);
1167 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1168 info.status_addr = CVMX_GMXX_BAD_REG(0);
1169 info.status_mask = 1ull<<26 /* statovr */;
1170 info.enable_addr = 0;
1171 info.enable_mask = 0;
1173 info.group = CVMX_ERROR_GROUP_ETHERNET;
1174 info.group_index = 0;
1175 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1176 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1177 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1178 info.func = __cvmx_error_display;
1179 info.user_info = (long)
1180 "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
1181 " The common FIFO to SGMII and XAUI had an overflow\n"
1182 " TX Stats are corrupted\n";
1183 fail |= cvmx_error_add(&info);
1185 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1186 info.status_addr = CVMX_GMXX_BAD_REG(0);
1187 info.status_mask = 0xfull<<27 /* inb_nxa */;
1188 info.enable_addr = 0;
1189 info.enable_mask = 0;
1191 info.group = CVMX_ERROR_GROUP_ETHERNET;
1192 info.group_index = 0;
1193 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1194 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1195 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1196 info.func = __cvmx_error_display;
1197 info.user_info = (long)
1198 "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
1199 fail |= cvmx_error_add(&info);
1201 /* CVMX_GMXX_RXX_INT_REG(0,0) */
1202 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1203 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1204 info.status_mask = 1ull<<1 /* carext */;
1205 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1206 info.enable_mask = 1ull<<1 /* carext */;
1208 info.group = CVMX_ERROR_GROUP_ETHERNET;
1209 info.group_index = 0;
1210 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1211 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1212 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1213 info.func = __cvmx_error_display;
1214 info.user_info = (long)
1215 "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
1216 " (SGMII/1000Base-X only)\n";
1217 fail |= cvmx_error_add(&info);
1219 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1220 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1221 info.status_mask = 1ull<<8 /* skperr */;
1222 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1223 info.enable_mask = 1ull<<8 /* skperr */;
1225 info.group = CVMX_ERROR_GROUP_ETHERNET;
1226 info.group_index = 0;
1227 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1228 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1229 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1230 info.func = __cvmx_error_display;
1231 info.user_info = (long)
1232 "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
1233 fail |= cvmx_error_add(&info);
1235 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1236 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1237 info.status_mask = 1ull<<10 /* ovrerr */;
1238 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1239 info.enable_mask = 1ull<<10 /* ovrerr */;
1241 info.group = CVMX_ERROR_GROUP_ETHERNET;
1242 info.group_index = 0;
1243 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1244 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1245 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1246 info.func = __cvmx_error_display;
1247 info.user_info = (long)
1248 "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1249 " This interrupt should never assert\n"
1250 " (SGMII/1000Base-X only)\n";
1251 fail |= cvmx_error_add(&info);
1253 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1254 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1255 info.status_mask = 1ull<<20 /* loc_fault */;
1256 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1257 info.enable_mask = 1ull<<20 /* loc_fault */;
1259 info.group = CVMX_ERROR_GROUP_ETHERNET;
1260 info.group_index = 0;
1261 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1262 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1263 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1264 info.func = __cvmx_error_display;
1265 info.user_info = (long)
1266 "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1267 " (XAUI Mode only)\n";
1268 fail |= cvmx_error_add(&info);
1270 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1271 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1272 info.status_mask = 1ull<<21 /* rem_fault */;
1273 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1274 info.enable_mask = 1ull<<21 /* rem_fault */;
1276 info.group = CVMX_ERROR_GROUP_ETHERNET;
1277 info.group_index = 0;
1278 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1279 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1280 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1281 info.func = __cvmx_error_display;
1282 info.user_info = (long)
1283 "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1284 " (XAUI Mode only)\n";
1285 fail |= cvmx_error_add(&info);
1287 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1288 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1289 info.status_mask = 1ull<<22 /* bad_seq */;
1290 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1291 info.enable_mask = 1ull<<22 /* bad_seq */;
1293 info.group = CVMX_ERROR_GROUP_ETHERNET;
1294 info.group_index = 0;
1295 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1296 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1297 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1298 info.func = __cvmx_error_display;
1299 info.user_info = (long)
1300 "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1301 " (XAUI Mode only)\n";
1302 fail |= cvmx_error_add(&info);
1304 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1305 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1306 info.status_mask = 1ull<<23 /* bad_term */;
1307 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1308 info.enable_mask = 1ull<<23 /* bad_term */;
1310 info.group = CVMX_ERROR_GROUP_ETHERNET;
1311 info.group_index = 0;
1312 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1313 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1314 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1315 info.func = __cvmx_error_display;
1316 info.user_info = (long)
1317 "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
1318 " than /T/. The error propagation control\n"
1319 " character /E/ will be included as part of the\n"
1320 " frame and does not cause a frame termination.\n"
1321 " (XAUI Mode only)\n";
1322 fail |= cvmx_error_add(&info);
1324 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1325 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1326 info.status_mask = 1ull<<24 /* unsop */;
1327 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1328 info.enable_mask = 1ull<<24 /* unsop */;
1330 info.group = CVMX_ERROR_GROUP_ETHERNET;
1331 info.group_index = 0;
1332 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1333 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1334 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1335 info.func = __cvmx_error_display;
1336 info.user_info = (long)
1337 "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
1338 " (XAUI Mode only)\n";
1339 fail |= cvmx_error_add(&info);
1341 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1342 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1343 info.status_mask = 1ull<<25 /* uneop */;
1344 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1345 info.enable_mask = 1ull<<25 /* uneop */;
1347 info.group = CVMX_ERROR_GROUP_ETHERNET;
1348 info.group_index = 0;
1349 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1350 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1351 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1352 info.func = __cvmx_error_display;
1353 info.user_info = (long)
1354 "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
1355 " (XAUI Mode only)\n";
1356 fail |= cvmx_error_add(&info);
1358 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1359 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1360 info.status_mask = 1ull<<26 /* undat */;
1361 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1362 info.enable_mask = 1ull<<26 /* undat */;
1364 info.group = CVMX_ERROR_GROUP_ETHERNET;
1365 info.group_index = 0;
1366 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1367 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1368 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1369 info.func = __cvmx_error_display;
1370 info.user_info = (long)
1371 "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
1372 " (XAUI Mode only)\n";
1373 fail |= cvmx_error_add(&info);
1375 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1376 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1377 info.status_mask = 1ull<<27 /* hg2fld */;
1378 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1379 info.enable_mask = 1ull<<27 /* hg2fld */;
1381 info.group = CVMX_ERROR_GROUP_ETHERNET;
1382 info.group_index = 0;
1383 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1384 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1385 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1386 info.func = __cvmx_error_display;
1387 info.user_info = (long)
1388 "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
1389 " 1) MSG_TYPE field not 6'b00_0000\n"
1390 " i.e. it is not a FLOW CONTROL message, which\n"
1391 " is the only defined type for HiGig2\n"
1392 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
1393 " which is the only defined type for HiGig2\n"
1394 " 3) FC_OBJECT field is neither 4'b0000 for\n"
1395 " Physical Link nor 4'b0010 for Logical Link.\n"
1396 " Those are the only two defined types in HiGig2\n";
1397 fail |= cvmx_error_add(&info);
1399 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1400 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
1401 info.status_mask = 1ull<<28 /* hg2cc */;
1402 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
1403 info.enable_mask = 1ull<<28 /* hg2cc */;
1405 info.group = CVMX_ERROR_GROUP_ETHERNET;
1406 info.group_index = 0;
1407 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1408 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1409 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1410 info.func = __cvmx_error_display;
1411 info.user_info = (long)
1412 "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
1413 " Set when either CRC8 error detected or when\n"
1414 " a Control Character is found in the message\n"
1415 " bytes after the K.SOM\n"
1416 " NOTE: HG2CC has higher priority than HG2FLD\n"
1417 " i.e. a HiGig2 message that results in HG2CC\n"
1418 " getting set, will never set HG2FLD.\n";
1419 fail |= cvmx_error_add(&info);
1421 /* CVMX_GMXX_RXX_INT_REG(1,0) */
1422 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1423 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1424 info.status_mask = 1ull<<1 /* carext */;
1425 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1426 info.enable_mask = 1ull<<1 /* carext */;
1428 info.group = CVMX_ERROR_GROUP_ETHERNET;
1429 info.group_index = 1;
1430 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1431 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1432 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1433 info.func = __cvmx_error_display;
1434 info.user_info = (long)
1435 "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
1436 " (SGMII/1000Base-X only)\n";
1437 fail |= cvmx_error_add(&info);
1439 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1440 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1441 info.status_mask = 1ull<<8 /* skperr */;
1442 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1443 info.enable_mask = 1ull<<8 /* skperr */;
1445 info.group = CVMX_ERROR_GROUP_ETHERNET;
1446 info.group_index = 1;
1447 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1448 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1449 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1450 info.func = __cvmx_error_display;
1451 info.user_info = (long)
1452 "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
1453 fail |= cvmx_error_add(&info);
1455 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1456 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1457 info.status_mask = 1ull<<10 /* ovrerr */;
1458 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1459 info.enable_mask = 1ull<<10 /* ovrerr */;
1461 info.group = CVMX_ERROR_GROUP_ETHERNET;
1462 info.group_index = 1;
1463 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1464 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1465 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1466 info.func = __cvmx_error_display;
1467 info.user_info = (long)
1468 "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1469 " This interrupt should never assert\n"
1470 " (SGMII/1000Base-X only)\n";
1471 fail |= cvmx_error_add(&info);
1473 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1474 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1475 info.status_mask = 1ull<<20 /* loc_fault */;
1476 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1477 info.enable_mask = 1ull<<20 /* loc_fault */;
1479 info.group = CVMX_ERROR_GROUP_ETHERNET;
1480 info.group_index = 1;
1481 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1482 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1483 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1484 info.func = __cvmx_error_display;
1485 info.user_info = (long)
1486 "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1487 " (XAUI Mode only)\n";
1488 fail |= cvmx_error_add(&info);
1490 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1491 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1492 info.status_mask = 1ull<<21 /* rem_fault */;
1493 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1494 info.enable_mask = 1ull<<21 /* rem_fault */;
1496 info.group = CVMX_ERROR_GROUP_ETHERNET;
1497 info.group_index = 1;
1498 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1499 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1500 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1501 info.func = __cvmx_error_display;
1502 info.user_info = (long)
1503 "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1504 " (XAUI Mode only)\n";
1505 fail |= cvmx_error_add(&info);
1507 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1508 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1509 info.status_mask = 1ull<<22 /* bad_seq */;
1510 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1511 info.enable_mask = 1ull<<22 /* bad_seq */;
1513 info.group = CVMX_ERROR_GROUP_ETHERNET;
1514 info.group_index = 1;
1515 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1516 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1517 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1518 info.func = __cvmx_error_display;
1519 info.user_info = (long)
1520 "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1521 " (XAUI Mode only)\n";
1522 fail |= cvmx_error_add(&info);
1524 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1525 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1526 info.status_mask = 1ull<<23 /* bad_term */;
1527 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1528 info.enable_mask = 1ull<<23 /* bad_term */;
1530 info.group = CVMX_ERROR_GROUP_ETHERNET;
1531 info.group_index = 1;
1532 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1533 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1534 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1535 info.func = __cvmx_error_display;
1536 info.user_info = (long)
1537 "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
1538 " than /T/. The error propagation control\n"
1539 " character /E/ will be included as part of the\n"
1540 " frame and does not cause a frame termination.\n"
1541 " (XAUI Mode only)\n";
1542 fail |= cvmx_error_add(&info);
1544 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1545 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1546 info.status_mask = 1ull<<24 /* unsop */;
1547 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1548 info.enable_mask = 1ull<<24 /* unsop */;
1550 info.group = CVMX_ERROR_GROUP_ETHERNET;
1551 info.group_index = 1;
1552 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1553 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1554 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1555 info.func = __cvmx_error_display;
1556 info.user_info = (long)
1557 "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
1558 " (XAUI Mode only)\n";
1559 fail |= cvmx_error_add(&info);
1561 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1562 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1563 info.status_mask = 1ull<<25 /* uneop */;
1564 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1565 info.enable_mask = 1ull<<25 /* uneop */;
1567 info.group = CVMX_ERROR_GROUP_ETHERNET;
1568 info.group_index = 1;
1569 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1570 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1571 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1572 info.func = __cvmx_error_display;
1573 info.user_info = (long)
1574 "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
1575 " (XAUI Mode only)\n";
1576 fail |= cvmx_error_add(&info);
1578 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1579 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1580 info.status_mask = 1ull<<26 /* undat */;
1581 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1582 info.enable_mask = 1ull<<26 /* undat */;
1584 info.group = CVMX_ERROR_GROUP_ETHERNET;
1585 info.group_index = 1;
1586 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1587 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1588 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1589 info.func = __cvmx_error_display;
1590 info.user_info = (long)
1591 "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
1592 " (XAUI Mode only)\n";
1593 fail |= cvmx_error_add(&info);
1595 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1596 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1597 info.status_mask = 1ull<<27 /* hg2fld */;
1598 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1599 info.enable_mask = 1ull<<27 /* hg2fld */;
1601 info.group = CVMX_ERROR_GROUP_ETHERNET;
1602 info.group_index = 1;
1603 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1604 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1605 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1606 info.func = __cvmx_error_display;
1607 info.user_info = (long)
1608 "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
1609 " 1) MSG_TYPE field not 6'b00_0000\n"
1610 " i.e. it is not a FLOW CONTROL message, which\n"
1611 " is the only defined type for HiGig2\n"
1612 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
1613 " which is the only defined type for HiGig2\n"
1614 " 3) FC_OBJECT field is neither 4'b0000 for\n"
1615 " Physical Link nor 4'b0010 for Logical Link.\n"
1616 " Those are the only two defined types in HiGig2\n";
1617 fail |= cvmx_error_add(&info);
1619 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1620 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
1621 info.status_mask = 1ull<<28 /* hg2cc */;
1622 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
1623 info.enable_mask = 1ull<<28 /* hg2cc */;
1625 info.group = CVMX_ERROR_GROUP_ETHERNET;
1626 info.group_index = 1;
1627 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1628 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1629 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1630 info.func = __cvmx_error_display;
1631 info.user_info = (long)
1632 "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
1633 " Set when either CRC8 error detected or when\n"
1634 " a Control Character is found in the message\n"
1635 " bytes after the K.SOM\n"
1636 " NOTE: HG2CC has higher priority than HG2FLD\n"
1637 " i.e. a HiGig2 message that results in HG2CC\n"
1638 " getting set, will never set HG2FLD.\n";
1639 fail |= cvmx_error_add(&info);
1641 /* CVMX_GMXX_RXX_INT_REG(2,0) */
1642 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1643 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1644 info.status_mask = 1ull<<1 /* carext */;
1645 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1646 info.enable_mask = 1ull<<1 /* carext */;
1648 info.group = CVMX_ERROR_GROUP_ETHERNET;
1649 info.group_index = 2;
1650 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1651 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1652 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1653 info.func = __cvmx_error_display;
1654 info.user_info = (long)
1655 "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
1656 " (SGMII/1000Base-X only)\n";
1657 fail |= cvmx_error_add(&info);
1659 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1660 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1661 info.status_mask = 1ull<<8 /* skperr */;
1662 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1663 info.enable_mask = 1ull<<8 /* skperr */;
1665 info.group = CVMX_ERROR_GROUP_ETHERNET;
1666 info.group_index = 2;
1667 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1668 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1669 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1670 info.func = __cvmx_error_display;
1671 info.user_info = (long)
1672 "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
1673 fail |= cvmx_error_add(&info);
1675 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1676 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1677 info.status_mask = 1ull<<10 /* ovrerr */;
1678 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1679 info.enable_mask = 1ull<<10 /* ovrerr */;
1681 info.group = CVMX_ERROR_GROUP_ETHERNET;
1682 info.group_index = 2;
1683 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1684 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1685 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1686 info.func = __cvmx_error_display;
1687 info.user_info = (long)
1688 "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1689 " This interrupt should never assert\n"
1690 " (SGMII/1000Base-X only)\n";
1691 fail |= cvmx_error_add(&info);
1693 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1694 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1695 info.status_mask = 1ull<<20 /* loc_fault */;
1696 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1697 info.enable_mask = 1ull<<20 /* loc_fault */;
1699 info.group = CVMX_ERROR_GROUP_ETHERNET;
1700 info.group_index = 2;
1701 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1702 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1703 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1704 info.func = __cvmx_error_display;
1705 info.user_info = (long)
1706 "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1707 " (XAUI Mode only)\n";
1708 fail |= cvmx_error_add(&info);
1710 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1711 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1712 info.status_mask = 1ull<<21 /* rem_fault */;
1713 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1714 info.enable_mask = 1ull<<21 /* rem_fault */;
1716 info.group = CVMX_ERROR_GROUP_ETHERNET;
1717 info.group_index = 2;
1718 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1719 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1720 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1721 info.func = __cvmx_error_display;
1722 info.user_info = (long)
1723 "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1724 " (XAUI Mode only)\n";
1725 fail |= cvmx_error_add(&info);
1727 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1728 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1729 info.status_mask = 1ull<<22 /* bad_seq */;
1730 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1731 info.enable_mask = 1ull<<22 /* bad_seq */;
1733 info.group = CVMX_ERROR_GROUP_ETHERNET;
1734 info.group_index = 2;
1735 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1736 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1737 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1738 info.func = __cvmx_error_display;
1739 info.user_info = (long)
1740 "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1741 " (XAUI Mode only)\n";
1742 fail |= cvmx_error_add(&info);
1744 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1745 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1746 info.status_mask = 1ull<<23 /* bad_term */;
1747 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1748 info.enable_mask = 1ull<<23 /* bad_term */;
1750 info.group = CVMX_ERROR_GROUP_ETHERNET;
1751 info.group_index = 2;
1752 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1753 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1754 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1755 info.func = __cvmx_error_display;
1756 info.user_info = (long)
1757 "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
1758 " than /T/. The error propagation control\n"
1759 " character /E/ will be included as part of the\n"
1760 " frame and does not cause a frame termination.\n"
1761 " (XAUI Mode only)\n";
1762 fail |= cvmx_error_add(&info);
1764 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1765 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1766 info.status_mask = 1ull<<24 /* unsop */;
1767 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1768 info.enable_mask = 1ull<<24 /* unsop */;
1770 info.group = CVMX_ERROR_GROUP_ETHERNET;
1771 info.group_index = 2;
1772 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1773 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1774 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1775 info.func = __cvmx_error_display;
1776 info.user_info = (long)
1777 "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
1778 " (XAUI Mode only)\n";
1779 fail |= cvmx_error_add(&info);
1781 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1782 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1783 info.status_mask = 1ull<<25 /* uneop */;
1784 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1785 info.enable_mask = 1ull<<25 /* uneop */;
1787 info.group = CVMX_ERROR_GROUP_ETHERNET;
1788 info.group_index = 2;
1789 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1790 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1791 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1792 info.func = __cvmx_error_display;
1793 info.user_info = (long)
1794 "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
1795 " (XAUI Mode only)\n";
1796 fail |= cvmx_error_add(&info);
1798 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1799 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1800 info.status_mask = 1ull<<26 /* undat */;
1801 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1802 info.enable_mask = 1ull<<26 /* undat */;
1804 info.group = CVMX_ERROR_GROUP_ETHERNET;
1805 info.group_index = 2;
1806 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1807 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1808 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1809 info.func = __cvmx_error_display;
1810 info.user_info = (long)
1811 "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
1812 " (XAUI Mode only)\n";
1813 fail |= cvmx_error_add(&info);
1815 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1816 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1817 info.status_mask = 1ull<<27 /* hg2fld */;
1818 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1819 info.enable_mask = 1ull<<27 /* hg2fld */;
1821 info.group = CVMX_ERROR_GROUP_ETHERNET;
1822 info.group_index = 2;
1823 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1824 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1825 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1826 info.func = __cvmx_error_display;
1827 info.user_info = (long)
1828 "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
1829 " 1) MSG_TYPE field not 6'b00_0000\n"
1830 " i.e. it is not a FLOW CONTROL message, which\n"
1831 " is the only defined type for HiGig2\n"
1832 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
1833 " which is the only defined type for HiGig2\n"
1834 " 3) FC_OBJECT field is neither 4'b0000 for\n"
1835 " Physical Link nor 4'b0010 for Logical Link.\n"
1836 " Those are the only two defined types in HiGig2\n";
1837 fail |= cvmx_error_add(&info);
1839 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1840 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
1841 info.status_mask = 1ull<<28 /* hg2cc */;
1842 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
1843 info.enable_mask = 1ull<<28 /* hg2cc */;
1845 info.group = CVMX_ERROR_GROUP_ETHERNET;
1846 info.group_index = 2;
1847 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1848 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1849 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1850 info.func = __cvmx_error_display;
1851 info.user_info = (long)
1852 "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
1853 " Set when either CRC8 error detected or when\n"
1854 " a Control Character is found in the message\n"
1855 " bytes after the K.SOM\n"
1856 " NOTE: HG2CC has higher priority than HG2FLD\n"
1857 " i.e. a HiGig2 message that results in HG2CC\n"
1858 " getting set, will never set HG2FLD.\n";
1859 fail |= cvmx_error_add(&info);
1861 /* CVMX_GMXX_RXX_INT_REG(3,0) */
1862 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1863 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1864 info.status_mask = 1ull<<1 /* carext */;
1865 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1866 info.enable_mask = 1ull<<1 /* carext */;
1868 info.group = CVMX_ERROR_GROUP_ETHERNET;
1869 info.group_index = 3;
1870 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1871 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1872 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1873 info.func = __cvmx_error_display;
1874 info.user_info = (long)
1875 "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
1876 " (SGMII/1000Base-X only)\n";
1877 fail |= cvmx_error_add(&info);
1879 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1880 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1881 info.status_mask = 1ull<<8 /* skperr */;
1882 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1883 info.enable_mask = 1ull<<8 /* skperr */;
1885 info.group = CVMX_ERROR_GROUP_ETHERNET;
1886 info.group_index = 3;
1887 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1888 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1889 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1890 info.func = __cvmx_error_display;
1891 info.user_info = (long)
1892 "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
1893 fail |= cvmx_error_add(&info);
1895 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1896 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1897 info.status_mask = 1ull<<10 /* ovrerr */;
1898 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1899 info.enable_mask = 1ull<<10 /* ovrerr */;
1901 info.group = CVMX_ERROR_GROUP_ETHERNET;
1902 info.group_index = 3;
1903 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1904 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1905 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1906 info.func = __cvmx_error_display;
1907 info.user_info = (long)
1908 "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
1909 " This interrupt should never assert\n"
1910 " (SGMII/1000Base-X only)\n";
1911 fail |= cvmx_error_add(&info);
1913 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1914 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1915 info.status_mask = 1ull<<20 /* loc_fault */;
1916 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1917 info.enable_mask = 1ull<<20 /* loc_fault */;
1919 info.group = CVMX_ERROR_GROUP_ETHERNET;
1920 info.group_index = 3;
1921 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1922 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1923 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1924 info.func = __cvmx_error_display;
1925 info.user_info = (long)
1926 "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
1927 " (XAUI Mode only)\n";
1928 fail |= cvmx_error_add(&info);
1930 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1931 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1932 info.status_mask = 1ull<<21 /* rem_fault */;
1933 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1934 info.enable_mask = 1ull<<21 /* rem_fault */;
1936 info.group = CVMX_ERROR_GROUP_ETHERNET;
1937 info.group_index = 3;
1938 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1939 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1940 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1941 info.func = __cvmx_error_display;
1942 info.user_info = (long)
1943 "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
1944 " (XAUI Mode only)\n";
1945 fail |= cvmx_error_add(&info);
1947 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1948 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1949 info.status_mask = 1ull<<22 /* bad_seq */;
1950 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1951 info.enable_mask = 1ull<<22 /* bad_seq */;
1953 info.group = CVMX_ERROR_GROUP_ETHERNET;
1954 info.group_index = 3;
1955 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1956 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1957 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1958 info.func = __cvmx_error_display;
1959 info.user_info = (long)
1960 "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
1961 " (XAUI Mode only)\n";
1962 fail |= cvmx_error_add(&info);
1964 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1965 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1966 info.status_mask = 1ull<<23 /* bad_term */;
1967 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1968 info.enable_mask = 1ull<<23 /* bad_term */;
1970 info.group = CVMX_ERROR_GROUP_ETHERNET;
1971 info.group_index = 3;
1972 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1973 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1974 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1975 info.func = __cvmx_error_display;
1976 info.user_info = (long)
1977 "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
1978 " than /T/. The error propagation control\n"
1979 " character /E/ will be included as part of the\n"
1980 " frame and does not cause a frame termination.\n"
1981 " (XAUI Mode only)\n";
1982 fail |= cvmx_error_add(&info);
1984 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1985 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
1986 info.status_mask = 1ull<<24 /* unsop */;
1987 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
1988 info.enable_mask = 1ull<<24 /* unsop */;
1990 info.group = CVMX_ERROR_GROUP_ETHERNET;
1991 info.group_index = 3;
1992 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1993 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
1994 info.parent.status_mask = 1ull<<1 /* gmx0 */;
1995 info.func = __cvmx_error_display;
1996 info.user_info = (long)
1997 "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
1998 " (XAUI Mode only)\n";
1999 fail |= cvmx_error_add(&info);
2001 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2002 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
2003 info.status_mask = 1ull<<25 /* uneop */;
2004 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
2005 info.enable_mask = 1ull<<25 /* uneop */;
2007 info.group = CVMX_ERROR_GROUP_ETHERNET;
2008 info.group_index = 3;
2009 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2010 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2011 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2012 info.func = __cvmx_error_display;
2013 info.user_info = (long)
2014 "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
2015 " (XAUI Mode only)\n";
2016 fail |= cvmx_error_add(&info);
2018 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2019 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
2020 info.status_mask = 1ull<<26 /* undat */;
2021 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
2022 info.enable_mask = 1ull<<26 /* undat */;
2024 info.group = CVMX_ERROR_GROUP_ETHERNET;
2025 info.group_index = 3;
2026 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2027 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2028 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2029 info.func = __cvmx_error_display;
2030 info.user_info = (long)
2031 "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
2032 " (XAUI Mode only)\n";
2033 fail |= cvmx_error_add(&info);
2035 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2036 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
2037 info.status_mask = 1ull<<27 /* hg2fld */;
2038 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
2039 info.enable_mask = 1ull<<27 /* hg2fld */;
2041 info.group = CVMX_ERROR_GROUP_ETHERNET;
2042 info.group_index = 3;
2043 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2044 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2045 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2046 info.func = __cvmx_error_display;
2047 info.user_info = (long)
2048 "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
2049 " 1) MSG_TYPE field not 6'b00_0000\n"
2050 " i.e. it is not a FLOW CONTROL message, which\n"
2051 " is the only defined type for HiGig2\n"
2052 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
2053 " which is the only defined type for HiGig2\n"
2054 " 3) FC_OBJECT field is neither 4'b0000 for\n"
2055 " Physical Link nor 4'b0010 for Logical Link.\n"
2056 " Those are the only two defined types in HiGig2\n";
2057 fail |= cvmx_error_add(&info);
2059 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2060 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
2061 info.status_mask = 1ull<<28 /* hg2cc */;
2062 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
2063 info.enable_mask = 1ull<<28 /* hg2cc */;
2065 info.group = CVMX_ERROR_GROUP_ETHERNET;
2066 info.group_index = 3;
2067 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2068 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2069 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2070 info.func = __cvmx_error_display;
2071 info.user_info = (long)
2072 "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
2073 " Set when either CRC8 error detected or when\n"
2074 " a Control Character is found in the message\n"
2075 " bytes after the K.SOM\n"
2076 " NOTE: HG2CC has higher priority than HG2FLD\n"
2077 " i.e. a HiGig2 message that results in HG2CC\n"
2078 " getting set, will never set HG2FLD.\n";
2079 fail |= cvmx_error_add(&info);
2081 /* CVMX_GMXX_TX_INT_REG(0) */
2082 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2083 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
2084 info.status_mask = 1ull<<0 /* pko_nxa */;
2085 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
2086 info.enable_mask = 1ull<<0 /* pko_nxa */;
2088 info.group = CVMX_ERROR_GROUP_ETHERNET;
2089 info.group_index = 0;
2090 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2091 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2092 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2093 info.func = __cvmx_error_display;
2094 info.user_info = (long)
2095 "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
2096 fail |= cvmx_error_add(&info);
2098 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2099 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
2100 info.status_mask = 0xfull<<2 /* undflw */;
2101 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
2102 info.enable_mask = 0xfull<<2 /* undflw */;
2104 info.group = CVMX_ERROR_GROUP_ETHERNET;
2105 info.group_index = 0;
2106 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2107 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2108 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2109 info.func = __cvmx_error_display;
2110 info.user_info = (long)
2111 "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
2112 fail |= cvmx_error_add(&info);
2114 /* CVMX_MIO_BOOT_ERR */
2115 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2116 info.status_addr = CVMX_MIO_BOOT_ERR;
2117 info.status_mask = 1ull<<0 /* adr_err */;
2118 info.enable_addr = CVMX_MIO_BOOT_INT;
2119 info.enable_mask = 1ull<<0 /* adr_int */;
2121 info.group = CVMX_ERROR_GROUP_INTERNAL;
2122 info.group_index = 0;
2123 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2124 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2125 info.parent.status_mask = 1ull<<0 /* mio */;
2126 info.func = __cvmx_error_display;
2127 info.user_info = (long)
2128 "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
2129 fail |= cvmx_error_add(&info);
2131 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2132 info.status_addr = CVMX_MIO_BOOT_ERR;
2133 info.status_mask = 1ull<<1 /* wait_err */;
2134 info.enable_addr = CVMX_MIO_BOOT_INT;
2135 info.enable_mask = 1ull<<1 /* wait_int */;
2137 info.group = CVMX_ERROR_GROUP_INTERNAL;
2138 info.group_index = 0;
2139 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2140 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2141 info.parent.status_mask = 1ull<<0 /* mio */;
2142 info.func = __cvmx_error_display;
2143 info.user_info = (long)
2144 "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
2145 fail |= cvmx_error_add(&info);
2147 /* CVMX_IPD_INT_SUM */
2148 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2149 info.status_addr = CVMX_IPD_INT_SUM;
2150 info.status_mask = 1ull<<0 /* prc_par0 */;
2151 info.enable_addr = CVMX_IPD_INT_ENB;
2152 info.enable_mask = 1ull<<0 /* prc_par0 */;
2154 info.group = CVMX_ERROR_GROUP_INTERNAL;
2155 info.group_index = 0;
2156 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2157 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2158 info.parent.status_mask = 1ull<<9 /* ipd */;
2159 info.func = __cvmx_error_display;
2160 info.user_info = (long)
2161 "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
2162 " [31:0] of the PBM memory.\n";
2163 fail |= cvmx_error_add(&info);
2165 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2166 info.status_addr = CVMX_IPD_INT_SUM;
2167 info.status_mask = 1ull<<1 /* prc_par1 */;
2168 info.enable_addr = CVMX_IPD_INT_ENB;
2169 info.enable_mask = 1ull<<1 /* prc_par1 */;
2171 info.group = CVMX_ERROR_GROUP_INTERNAL;
2172 info.group_index = 0;
2173 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2174 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2175 info.parent.status_mask = 1ull<<9 /* ipd */;
2176 info.func = __cvmx_error_display;
2177 info.user_info = (long)
2178 "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
2179 " [63:32] of the PBM memory.\n";
2180 fail |= cvmx_error_add(&info);
2182 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2183 info.status_addr = CVMX_IPD_INT_SUM;
2184 info.status_mask = 1ull<<2 /* prc_par2 */;
2185 info.enable_addr = CVMX_IPD_INT_ENB;
2186 info.enable_mask = 1ull<<2 /* prc_par2 */;
2188 info.group = CVMX_ERROR_GROUP_INTERNAL;
2189 info.group_index = 0;
2190 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2191 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2192 info.parent.status_mask = 1ull<<9 /* ipd */;
2193 info.func = __cvmx_error_display;
2194 info.user_info = (long)
2195 "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
2196 " [95:64] of the PBM memory.\n";
2197 fail |= cvmx_error_add(&info);
2199 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2200 info.status_addr = CVMX_IPD_INT_SUM;
2201 info.status_mask = 1ull<<3 /* prc_par3 */;
2202 info.enable_addr = CVMX_IPD_INT_ENB;
2203 info.enable_mask = 1ull<<3 /* prc_par3 */;
2205 info.group = CVMX_ERROR_GROUP_INTERNAL;
2206 info.group_index = 0;
2207 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2208 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2209 info.parent.status_mask = 1ull<<9 /* ipd */;
2210 info.func = __cvmx_error_display;
2211 info.user_info = (long)
2212 "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
2213 " [127:96] of the PBM memory.\n";
2214 fail |= cvmx_error_add(&info);
2216 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2217 info.status_addr = CVMX_IPD_INT_SUM;
2218 info.status_mask = 1ull<<4 /* bp_sub */;
2219 info.enable_addr = CVMX_IPD_INT_ENB;
2220 info.enable_mask = 1ull<<4 /* bp_sub */;
2222 info.group = CVMX_ERROR_GROUP_INTERNAL;
2223 info.group_index = 0;
2224 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2225 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2226 info.parent.status_mask = 1ull<<9 /* ipd */;
2227 info.func = __cvmx_error_display;
2228 info.user_info = (long)
2229 "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
2230 " supplied illegal value.\n";
2231 fail |= cvmx_error_add(&info);
2233 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2234 info.status_addr = CVMX_IPD_INT_SUM;
2235 info.status_mask = 1ull<<5 /* dc_ovr */;
2236 info.enable_addr = CVMX_IPD_INT_ENB;
2237 info.enable_mask = 1ull<<5 /* dc_ovr */;
2239 info.group = CVMX_ERROR_GROUP_INTERNAL;
2240 info.group_index = 0;
2241 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2242 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2243 info.parent.status_mask = 1ull<<9 /* ipd */;
2244 info.func = __cvmx_error_display;
2245 info.user_info = (long)
2246 "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
2247 fail |= cvmx_error_add(&info);
2249 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2250 info.status_addr = CVMX_IPD_INT_SUM;
2251 info.status_mask = 1ull<<6 /* cc_ovr */;
2252 info.enable_addr = CVMX_IPD_INT_ENB;
2253 info.enable_mask = 1ull<<6 /* cc_ovr */;
2255 info.group = CVMX_ERROR_GROUP_INTERNAL;
2256 info.group_index = 0;
2257 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2258 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2259 info.parent.status_mask = 1ull<<9 /* ipd */;
2260 info.func = __cvmx_error_display;
2261 info.user_info = (long)
2262 "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
2263 fail |= cvmx_error_add(&info);
2265 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2266 info.status_addr = CVMX_IPD_INT_SUM;
2267 info.status_mask = 1ull<<7 /* c_coll */;
2268 info.enable_addr = CVMX_IPD_INT_ENB;
2269 info.enable_mask = 1ull<<7 /* c_coll */;
2271 info.group = CVMX_ERROR_GROUP_INTERNAL;
2272 info.group_index = 0;
2273 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2274 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2275 info.parent.status_mask = 1ull<<9 /* ipd */;
2276 info.func = __cvmx_error_display;
2277 info.user_info = (long)
2278 "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
2280 fail |= cvmx_error_add(&info);
2282 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2283 info.status_addr = CVMX_IPD_INT_SUM;
2284 info.status_mask = 1ull<<8 /* d_coll */;
2285 info.enable_addr = CVMX_IPD_INT_ENB;
2286 info.enable_mask = 1ull<<8 /* d_coll */;
2288 info.group = CVMX_ERROR_GROUP_INTERNAL;
2289 info.group_index = 0;
2290 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2291 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2292 info.parent.status_mask = 1ull<<9 /* ipd */;
2293 info.func = __cvmx_error_display;
2294 info.user_info = (long)
2295 "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
2297 fail |= cvmx_error_add(&info);
2299 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2300 info.status_addr = CVMX_IPD_INT_SUM;
2301 info.status_mask = 1ull<<9 /* bc_ovr */;
2302 info.enable_addr = CVMX_IPD_INT_ENB;
2303 info.enable_mask = 1ull<<9 /* bc_ovr */;
2305 info.group = CVMX_ERROR_GROUP_INTERNAL;
2306 info.group_index = 0;
2307 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2308 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2309 info.parent.status_mask = 1ull<<9 /* ipd */;
2310 info.func = __cvmx_error_display;
2311 info.user_info = (long)
2312 "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
2313 fail |= cvmx_error_add(&info);
2315 /* CVMX_TIM_REG_ERROR */
2316 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2317 info.status_addr = CVMX_TIM_REG_ERROR;
2318 info.status_mask = 0xffffull<<0 /* mask */;
2319 info.enable_addr = CVMX_TIM_REG_INT_MASK;
2320 info.enable_mask = 0xffffull<<0 /* mask */;
2322 info.group = CVMX_ERROR_GROUP_INTERNAL;
2323 info.group_index = 0;
2324 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2325 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2326 info.parent.status_mask = 1ull<<11 /* tim */;
2327 info.func = __cvmx_error_display;
2328 info.user_info = (long)
2329 "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
2330 fail |= cvmx_error_add(&info);
2332 /* CVMX_POW_ECC_ERR */
2333 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2334 info.status_addr = CVMX_POW_ECC_ERR;
2335 info.status_mask = 1ull<<0 /* sbe */;
2336 info.enable_addr = CVMX_POW_ECC_ERR;
2337 info.enable_mask = 1ull<<2 /* sbe_ie */;
2338 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
2339 info.group = CVMX_ERROR_GROUP_INTERNAL;
2340 info.group_index = 0;
2341 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2342 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2343 info.parent.status_mask = 1ull<<12 /* pow */;
2344 info.func = __cvmx_error_handle_pow_ecc_err_sbe;
2345 info.user_info = (long)
2346 "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
2347 fail |= cvmx_error_add(&info);
2349 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2350 info.status_addr = CVMX_POW_ECC_ERR;
2351 info.status_mask = 1ull<<1 /* dbe */;
2352 info.enable_addr = CVMX_POW_ECC_ERR;
2353 info.enable_mask = 1ull<<3 /* dbe_ie */;
2355 info.group = CVMX_ERROR_GROUP_INTERNAL;
2356 info.group_index = 0;
2357 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2358 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2359 info.parent.status_mask = 1ull<<12 /* pow */;
2360 info.func = __cvmx_error_handle_pow_ecc_err_dbe;
2361 info.user_info = (long)
2362 "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
2363 fail |= cvmx_error_add(&info);
2365 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2366 info.status_addr = CVMX_POW_ECC_ERR;
2367 info.status_mask = 1ull<<12 /* rpe */;
2368 info.enable_addr = CVMX_POW_ECC_ERR;
2369 info.enable_mask = 1ull<<13 /* rpe_ie */;
2371 info.group = CVMX_ERROR_GROUP_INTERNAL;
2372 info.group_index = 0;
2373 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2374 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2375 info.parent.status_mask = 1ull<<12 /* pow */;
2376 info.func = __cvmx_error_handle_pow_ecc_err_rpe;
2377 info.user_info = (long)
2378 "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
2379 fail |= cvmx_error_add(&info);
2381 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2382 info.status_addr = CVMX_POW_ECC_ERR;
2383 info.status_mask = 0x1fffull<<16 /* iop */;
2384 info.enable_addr = CVMX_POW_ECC_ERR;
2385 info.enable_mask = 0x1fffull<<32 /* iop_ie */;
2387 info.group = CVMX_ERROR_GROUP_INTERNAL;
2388 info.group_index = 0;
2389 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2390 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2391 info.parent.status_mask = 1ull<<12 /* pow */;
2392 info.func = __cvmx_error_handle_pow_ecc_err_iop;
2393 info.user_info = (long)
2394 "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
2395 fail |= cvmx_error_add(&info);
2397 /* CVMX_USBNX_INT_SUM(1) */
2398 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2399 info.status_addr = CVMX_USBNX_INT_SUM(1);
2400 info.status_mask = 1ull<<0 /* pr_po_e */;
2401 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2402 info.enable_mask = 1ull<<0 /* pr_po_e */;
2404 info.group = CVMX_ERROR_GROUP_USB;
2405 info.group_index = 1;
2406 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2407 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2408 info.parent.status_mask = 1ull<<15 /* usb1 */;
2409 info.func = __cvmx_error_display;
2410 info.user_info = (long)
2411 "ERROR USBNX_INT_SUM(1)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
2412 fail |= cvmx_error_add(&info);
2414 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2415 info.status_addr = CVMX_USBNX_INT_SUM(1);
2416 info.status_mask = 1ull<<1 /* pr_pu_f */;
2417 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2418 info.enable_mask = 1ull<<1 /* pr_pu_f */;
2420 info.group = CVMX_ERROR_GROUP_USB;
2421 info.group_index = 1;
2422 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2423 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2424 info.parent.status_mask = 1ull<<15 /* usb1 */;
2425 info.func = __cvmx_error_display;
2426 info.user_info = (long)
2427 "ERROR USBNX_INT_SUM(1)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
2428 fail |= cvmx_error_add(&info);
2430 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2431 info.status_addr = CVMX_USBNX_INT_SUM(1);
2432 info.status_mask = 1ull<<2 /* nr_po_e */;
2433 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2434 info.enable_mask = 1ull<<2 /* nr_po_e */;
2436 info.group = CVMX_ERROR_GROUP_USB;
2437 info.group_index = 1;
2438 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2439 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2440 info.parent.status_mask = 1ull<<15 /* usb1 */;
2441 info.func = __cvmx_error_display;
2442 info.user_info = (long)
2443 "ERROR USBNX_INT_SUM(1)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
2444 fail |= cvmx_error_add(&info);
2446 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2447 info.status_addr = CVMX_USBNX_INT_SUM(1);
2448 info.status_mask = 1ull<<3 /* nr_pu_f */;
2449 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2450 info.enable_mask = 1ull<<3 /* nr_pu_f */;
2452 info.group = CVMX_ERROR_GROUP_USB;
2453 info.group_index = 1;
2454 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2455 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2456 info.parent.status_mask = 1ull<<15 /* usb1 */;
2457 info.func = __cvmx_error_display;
2458 info.user_info = (long)
2459 "ERROR USBNX_INT_SUM(1)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
2460 fail |= cvmx_error_add(&info);
2462 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2463 info.status_addr = CVMX_USBNX_INT_SUM(1);
2464 info.status_mask = 1ull<<4 /* lr_po_e */;
2465 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2466 info.enable_mask = 1ull<<4 /* lr_po_e */;
2468 info.group = CVMX_ERROR_GROUP_USB;
2469 info.group_index = 1;
2470 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2471 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2472 info.parent.status_mask = 1ull<<15 /* usb1 */;
2473 info.func = __cvmx_error_display;
2474 info.user_info = (long)
2475 "ERROR USBNX_INT_SUM(1)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
2476 fail |= cvmx_error_add(&info);
2478 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2479 info.status_addr = CVMX_USBNX_INT_SUM(1);
2480 info.status_mask = 1ull<<5 /* lr_pu_f */;
2481 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2482 info.enable_mask = 1ull<<5 /* lr_pu_f */;
2484 info.group = CVMX_ERROR_GROUP_USB;
2485 info.group_index = 1;
2486 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2487 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2488 info.parent.status_mask = 1ull<<15 /* usb1 */;
2489 info.func = __cvmx_error_display;
2490 info.user_info = (long)
2491 "ERROR USBNX_INT_SUM(1)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
2492 fail |= cvmx_error_add(&info);
2494 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2495 info.status_addr = CVMX_USBNX_INT_SUM(1);
2496 info.status_mask = 1ull<<6 /* pt_po_e */;
2497 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2498 info.enable_mask = 1ull<<6 /* pt_po_e */;
2500 info.group = CVMX_ERROR_GROUP_USB;
2501 info.group_index = 1;
2502 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2503 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2504 info.parent.status_mask = 1ull<<15 /* usb1 */;
2505 info.func = __cvmx_error_display;
2506 info.user_info = (long)
2507 "ERROR USBNX_INT_SUM(1)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
2508 fail |= cvmx_error_add(&info);
2510 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2511 info.status_addr = CVMX_USBNX_INT_SUM(1);
2512 info.status_mask = 1ull<<7 /* pt_pu_f */;
2513 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2514 info.enable_mask = 1ull<<7 /* pt_pu_f */;
2516 info.group = CVMX_ERROR_GROUP_USB;
2517 info.group_index = 1;
2518 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2519 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2520 info.parent.status_mask = 1ull<<15 /* usb1 */;
2521 info.func = __cvmx_error_display;
2522 info.user_info = (long)
2523 "ERROR USBNX_INT_SUM(1)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
2524 fail |= cvmx_error_add(&info);
2526 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2527 info.status_addr = CVMX_USBNX_INT_SUM(1);
2528 info.status_mask = 1ull<<8 /* nt_po_e */;
2529 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2530 info.enable_mask = 1ull<<8 /* nt_po_e */;
2532 info.group = CVMX_ERROR_GROUP_USB;
2533 info.group_index = 1;
2534 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2535 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2536 info.parent.status_mask = 1ull<<15 /* usb1 */;
2537 info.func = __cvmx_error_display;
2538 info.user_info = (long)
2539 "ERROR USBNX_INT_SUM(1)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
2540 fail |= cvmx_error_add(&info);
2542 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2543 info.status_addr = CVMX_USBNX_INT_SUM(1);
2544 info.status_mask = 1ull<<9 /* nt_pu_f */;
2545 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2546 info.enable_mask = 1ull<<9 /* nt_pu_f */;
2548 info.group = CVMX_ERROR_GROUP_USB;
2549 info.group_index = 1;
2550 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2551 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2552 info.parent.status_mask = 1ull<<15 /* usb1 */;
2553 info.func = __cvmx_error_display;
2554 info.user_info = (long)
2555 "ERROR USBNX_INT_SUM(1)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
2556 fail |= cvmx_error_add(&info);
2558 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2559 info.status_addr = CVMX_USBNX_INT_SUM(1);
2560 info.status_mask = 1ull<<10 /* lt_po_e */;
2561 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2562 info.enable_mask = 1ull<<10 /* lt_po_e */;
2564 info.group = CVMX_ERROR_GROUP_USB;
2565 info.group_index = 1;
2566 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2567 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2568 info.parent.status_mask = 1ull<<15 /* usb1 */;
2569 info.func = __cvmx_error_display;
2570 info.user_info = (long)
2571 "ERROR USBNX_INT_SUM(1)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
2572 fail |= cvmx_error_add(&info);
2574 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2575 info.status_addr = CVMX_USBNX_INT_SUM(1);
2576 info.status_mask = 1ull<<11 /* lt_pu_f */;
2577 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2578 info.enable_mask = 1ull<<11 /* lt_pu_f */;
2580 info.group = CVMX_ERROR_GROUP_USB;
2581 info.group_index = 1;
2582 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2583 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2584 info.parent.status_mask = 1ull<<15 /* usb1 */;
2585 info.func = __cvmx_error_display;
2586 info.user_info = (long)
2587 "ERROR USBNX_INT_SUM(1)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
2588 fail |= cvmx_error_add(&info);
2590 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2591 info.status_addr = CVMX_USBNX_INT_SUM(1);
2592 info.status_mask = 1ull<<12 /* dcred_e */;
2593 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2594 info.enable_mask = 1ull<<12 /* dcred_e */;
2596 info.group = CVMX_ERROR_GROUP_USB;
2597 info.group_index = 1;
2598 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2599 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2600 info.parent.status_mask = 1ull<<15 /* usb1 */;
2601 info.func = __cvmx_error_display;
2602 info.user_info = (long)
2603 "ERROR USBNX_INT_SUM(1)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
2604 fail |= cvmx_error_add(&info);
2606 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2607 info.status_addr = CVMX_USBNX_INT_SUM(1);
2608 info.status_mask = 1ull<<13 /* dcred_f */;
2609 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2610 info.enable_mask = 1ull<<13 /* dcred_f */;
2612 info.group = CVMX_ERROR_GROUP_USB;
2613 info.group_index = 1;
2614 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2615 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2616 info.parent.status_mask = 1ull<<15 /* usb1 */;
2617 info.func = __cvmx_error_display;
2618 info.user_info = (long)
2619 "ERROR USBNX_INT_SUM(1)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
2620 fail |= cvmx_error_add(&info);
2622 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2623 info.status_addr = CVMX_USBNX_INT_SUM(1);
2624 info.status_mask = 1ull<<14 /* l2c_s_e */;
2625 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2626 info.enable_mask = 1ull<<14 /* l2c_s_e */;
2628 info.group = CVMX_ERROR_GROUP_USB;
2629 info.group_index = 1;
2630 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2631 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2632 info.parent.status_mask = 1ull<<15 /* usb1 */;
2633 info.func = __cvmx_error_display;
2634 info.user_info = (long)
2635 "ERROR USBNX_INT_SUM(1)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
2636 fail |= cvmx_error_add(&info);
2638 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2639 info.status_addr = CVMX_USBNX_INT_SUM(1);
2640 info.status_mask = 1ull<<15 /* l2c_a_f */;
2641 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2642 info.enable_mask = 1ull<<15 /* l2c_a_f */;
2644 info.group = CVMX_ERROR_GROUP_USB;
2645 info.group_index = 1;
2646 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2647 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2648 info.parent.status_mask = 1ull<<15 /* usb1 */;
2649 info.func = __cvmx_error_display;
2650 info.user_info = (long)
2651 "ERROR USBNX_INT_SUM(1)[L2C_A_F]: L2C Credit Count Added When Full.\n";
2652 fail |= cvmx_error_add(&info);
2654 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2655 info.status_addr = CVMX_USBNX_INT_SUM(1);
2656 info.status_mask = 1ull<<16 /* lt_fi_e */;
2657 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2658 info.enable_mask = 1ull<<16 /* l2_fi_e */;
2660 info.group = CVMX_ERROR_GROUP_USB;
2661 info.group_index = 1;
2662 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2663 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2664 info.parent.status_mask = 1ull<<15 /* usb1 */;
2665 info.func = __cvmx_error_display;
2666 info.user_info = (long)
2667 "ERROR USBNX_INT_SUM(1)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
2668 fail |= cvmx_error_add(&info);
2670 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2671 info.status_addr = CVMX_USBNX_INT_SUM(1);
2672 info.status_mask = 1ull<<17 /* lt_fi_f */;
2673 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2674 info.enable_mask = 1ull<<17 /* l2_fi_f */;
2676 info.group = CVMX_ERROR_GROUP_USB;
2677 info.group_index = 1;
2678 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2679 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2680 info.parent.status_mask = 1ull<<15 /* usb1 */;
2681 info.func = __cvmx_error_display;
2682 info.user_info = (long)
2683 "ERROR USBNX_INT_SUM(1)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
2684 fail |= cvmx_error_add(&info);
2686 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2687 info.status_addr = CVMX_USBNX_INT_SUM(1);
2688 info.status_mask = 1ull<<18 /* rg_fi_e */;
2689 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2690 info.enable_mask = 1ull<<18 /* rg_fi_e */;
2692 info.group = CVMX_ERROR_GROUP_USB;
2693 info.group_index = 1;
2694 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2695 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2696 info.parent.status_mask = 1ull<<15 /* usb1 */;
2697 info.func = __cvmx_error_display;
2698 info.user_info = (long)
2699 "ERROR USBNX_INT_SUM(1)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
2700 fail |= cvmx_error_add(&info);
2702 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2703 info.status_addr = CVMX_USBNX_INT_SUM(1);
2704 info.status_mask = 1ull<<19 /* rg_fi_f */;
2705 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2706 info.enable_mask = 1ull<<19 /* rg_fi_f */;
2708 info.group = CVMX_ERROR_GROUP_USB;
2709 info.group_index = 1;
2710 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2711 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2712 info.parent.status_mask = 1ull<<15 /* usb1 */;
2713 info.func = __cvmx_error_display;
2714 info.user_info = (long)
2715 "ERROR USBNX_INT_SUM(1)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
2716 fail |= cvmx_error_add(&info);
2718 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2719 info.status_addr = CVMX_USBNX_INT_SUM(1);
2720 info.status_mask = 1ull<<20 /* rq_q2_f */;
2721 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2722 info.enable_mask = 1ull<<20 /* rq_q2_f */;
2724 info.group = CVMX_ERROR_GROUP_USB;
2725 info.group_index = 1;
2726 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2727 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2728 info.parent.status_mask = 1ull<<15 /* usb1 */;
2729 info.func = __cvmx_error_display;
2730 info.user_info = (long)
2731 "ERROR USBNX_INT_SUM(1)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
2732 fail |= cvmx_error_add(&info);
2734 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2735 info.status_addr = CVMX_USBNX_INT_SUM(1);
2736 info.status_mask = 1ull<<21 /* rq_q2_e */;
2737 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2738 info.enable_mask = 1ull<<21 /* rq_q2_e */;
2740 info.group = CVMX_ERROR_GROUP_USB;
2741 info.group_index = 1;
2742 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2743 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2744 info.parent.status_mask = 1ull<<15 /* usb1 */;
2745 info.func = __cvmx_error_display;
2746 info.user_info = (long)
2747 "ERROR USBNX_INT_SUM(1)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
2748 fail |= cvmx_error_add(&info);
2750 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2751 info.status_addr = CVMX_USBNX_INT_SUM(1);
2752 info.status_mask = 1ull<<22 /* rq_q3_f */;
2753 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2754 info.enable_mask = 1ull<<22 /* rq_q3_f */;
2756 info.group = CVMX_ERROR_GROUP_USB;
2757 info.group_index = 1;
2758 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2759 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2760 info.parent.status_mask = 1ull<<15 /* usb1 */;
2761 info.func = __cvmx_error_display;
2762 info.user_info = (long)
2763 "ERROR USBNX_INT_SUM(1)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
2764 fail |= cvmx_error_add(&info);
2766 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2767 info.status_addr = CVMX_USBNX_INT_SUM(1);
2768 info.status_mask = 1ull<<23 /* rq_q3_e */;
2769 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2770 info.enable_mask = 1ull<<23 /* rq_q3_e */;
2772 info.group = CVMX_ERROR_GROUP_USB;
2773 info.group_index = 1;
2774 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2775 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2776 info.parent.status_mask = 1ull<<15 /* usb1 */;
2777 info.func = __cvmx_error_display;
2778 info.user_info = (long)
2779 "ERROR USBNX_INT_SUM(1)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
2780 fail |= cvmx_error_add(&info);
2782 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2783 info.status_addr = CVMX_USBNX_INT_SUM(1);
2784 info.status_mask = 1ull<<24 /* uod_pe */;
2785 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2786 info.enable_mask = 1ull<<24 /* uod_pe */;
2788 info.group = CVMX_ERROR_GROUP_USB;
2789 info.group_index = 1;
2790 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2791 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2792 info.parent.status_mask = 1ull<<15 /* usb1 */;
2793 info.func = __cvmx_error_display;
2794 info.user_info = (long)
2795 "ERROR USBNX_INT_SUM(1)[UOD_PE]: UOD Fifo Pop Empty.\n";
2796 fail |= cvmx_error_add(&info);
2798 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2799 info.status_addr = CVMX_USBNX_INT_SUM(1);
2800 info.status_mask = 1ull<<25 /* uod_pf */;
2801 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2802 info.enable_mask = 1ull<<25 /* uod_pf */;
2804 info.group = CVMX_ERROR_GROUP_USB;
2805 info.group_index = 1;
2806 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2807 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2808 info.parent.status_mask = 1ull<<15 /* usb1 */;
2809 info.func = __cvmx_error_display;
2810 info.user_info = (long)
2811 "ERROR USBNX_INT_SUM(1)[UOD_PF]: UOD Fifo Push Full.\n";
2812 fail |= cvmx_error_add(&info);
2814 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2815 info.status_addr = CVMX_USBNX_INT_SUM(1);
2816 info.status_mask = 1ull<<32 /* ltl_f_pe */;
2817 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2818 info.enable_mask = 1ull<<32 /* ltl_f_pe */;
2820 info.group = CVMX_ERROR_GROUP_USB;
2821 info.group_index = 1;
2822 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2823 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2824 info.parent.status_mask = 1ull<<15 /* usb1 */;
2825 info.func = __cvmx_error_display;
2826 info.user_info = (long)
2827 "ERROR USBNX_INT_SUM(1)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
2828 fail |= cvmx_error_add(&info);
2830 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2831 info.status_addr = CVMX_USBNX_INT_SUM(1);
2832 info.status_mask = 1ull<<33 /* ltl_f_pf */;
2833 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2834 info.enable_mask = 1ull<<33 /* ltl_f_pf */;
2836 info.group = CVMX_ERROR_GROUP_USB;
2837 info.group_index = 1;
2838 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2839 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2840 info.parent.status_mask = 1ull<<15 /* usb1 */;
2841 info.func = __cvmx_error_display;
2842 info.user_info = (long)
2843 "ERROR USBNX_INT_SUM(1)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
2844 fail |= cvmx_error_add(&info);
2846 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2847 info.status_addr = CVMX_USBNX_INT_SUM(1);
2848 info.status_mask = 1ull<<34 /* nd4o_rpe */;
2849 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2850 info.enable_mask = 1ull<<34 /* nd4o_rpe */;
2852 info.group = CVMX_ERROR_GROUP_USB;
2853 info.group_index = 1;
2854 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2855 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2856 info.parent.status_mask = 1ull<<15 /* usb1 */;
2857 info.func = __cvmx_error_display;
2858 info.user_info = (long)
2859 "ERROR USBNX_INT_SUM(1)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
2860 fail |= cvmx_error_add(&info);
2862 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2863 info.status_addr = CVMX_USBNX_INT_SUM(1);
2864 info.status_mask = 1ull<<35 /* nd4o_rpf */;
2865 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2866 info.enable_mask = 1ull<<35 /* nd4o_rpf */;
2868 info.group = CVMX_ERROR_GROUP_USB;
2869 info.group_index = 1;
2870 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2871 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2872 info.parent.status_mask = 1ull<<15 /* usb1 */;
2873 info.func = __cvmx_error_display;
2874 info.user_info = (long)
2875 "ERROR USBNX_INT_SUM(1)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
2876 fail |= cvmx_error_add(&info);
2878 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2879 info.status_addr = CVMX_USBNX_INT_SUM(1);
2880 info.status_mask = 1ull<<36 /* nd4o_dpe */;
2881 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2882 info.enable_mask = 1ull<<36 /* nd4o_dpe */;
2884 info.group = CVMX_ERROR_GROUP_USB;
2885 info.group_index = 1;
2886 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2887 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2888 info.parent.status_mask = 1ull<<15 /* usb1 */;
2889 info.func = __cvmx_error_display;
2890 info.user_info = (long)
2891 "ERROR USBNX_INT_SUM(1)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
2892 fail |= cvmx_error_add(&info);
2894 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2895 info.status_addr = CVMX_USBNX_INT_SUM(1);
2896 info.status_mask = 1ull<<37 /* nd4o_dpf */;
2897 info.enable_addr = CVMX_USBNX_INT_ENB(1);
2898 info.enable_mask = 1ull<<37 /* nd4o_dpf */;
2900 info.group = CVMX_ERROR_GROUP_USB;
2901 info.group_index = 1;
2902 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2903 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2904 info.parent.status_mask = 1ull<<15 /* usb1 */;
2905 info.func = __cvmx_error_display;
2906 info.user_info = (long)
2907 "ERROR USBNX_INT_SUM(1)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
2908 fail |= cvmx_error_add(&info);
2910 /* CVMX_PEXP_NPEI_INT_SUM */
2911 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2912 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2913 info.status_mask = 1ull<<59 /* c0_ldwn */;
2914 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2915 info.enable_mask = 1ull<<59 /* c0_ldwn */;
2917 info.group = CVMX_ERROR_GROUP_PCI;
2918 info.group_index = 0;
2919 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2920 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2921 info.parent.status_mask = 1ull<<3 /* npei */;
2922 info.func = __cvmx_error_display;
2923 info.user_info = (long)
2924 "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
2925 fail |= cvmx_error_add(&info);
2927 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2928 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2929 info.status_mask = 1ull<<21 /* c0_se */;
2930 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2931 info.enable_mask = 1ull<<21 /* c0_se */;
2933 info.group = CVMX_ERROR_GROUP_PCI;
2934 info.group_index = 0;
2935 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2936 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2937 info.parent.status_mask = 1ull<<3 /* npei */;
2938 info.func = __cvmx_error_display;
2939 info.user_info = (long)
2940 "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
2941 " Pcie Core 0. (cfg_sys_err_rc)\n";
2942 fail |= cvmx_error_add(&info);
2944 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2945 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2946 info.status_mask = 1ull<<38 /* c0_un_b0 */;
2947 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2948 info.enable_mask = 1ull<<38 /* c0_un_b0 */;
2950 info.group = CVMX_ERROR_GROUP_PCI;
2951 info.group_index = 0;
2952 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2953 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2954 info.parent.status_mask = 1ull<<3 /* npei */;
2955 info.func = __cvmx_error_display;
2956 info.user_info = (long)
2957 "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
2959 fail |= cvmx_error_add(&info);
2961 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2962 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2963 info.status_mask = 1ull<<39 /* c0_un_b1 */;
2964 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2965 info.enable_mask = 1ull<<39 /* c0_un_b1 */;
2967 info.group = CVMX_ERROR_GROUP_PCI;
2968 info.group_index = 0;
2969 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2970 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2971 info.parent.status_mask = 1ull<<3 /* npei */;
2972 info.func = __cvmx_error_display;
2973 info.user_info = (long)
2974 "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
2976 fail |= cvmx_error_add(&info);
2978 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2979 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2980 info.status_mask = 1ull<<40 /* c0_un_b2 */;
2981 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2982 info.enable_mask = 1ull<<40 /* c0_un_b2 */;
2984 info.group = CVMX_ERROR_GROUP_PCI;
2985 info.group_index = 0;
2986 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2987 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
2988 info.parent.status_mask = 1ull<<3 /* npei */;
2989 info.func = __cvmx_error_display;
2990 info.user_info = (long)
2991 "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
2993 fail |= cvmx_error_add(&info);
2995 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2996 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
2997 info.status_mask = 1ull<<42 /* c0_un_bx */;
2998 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
2999 info.enable_mask = 1ull<<42 /* c0_un_bx */;
3001 info.group = CVMX_ERROR_GROUP_PCI;
3002 info.group_index = 0;
3003 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3004 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3005 info.parent.status_mask = 1ull<<3 /* npei */;
3006 info.func = __cvmx_error_display;
3007 info.user_info = (long)
3008 "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
3010 fail |= cvmx_error_add(&info);
3012 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3013 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3014 info.status_mask = 1ull<<53 /* c0_un_wf */;
3015 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3016 info.enable_mask = 1ull<<53 /* c0_un_wf */;
3018 info.group = CVMX_ERROR_GROUP_PCI;
3019 info.group_index = 0;
3020 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3021 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3022 info.parent.status_mask = 1ull<<3 /* npei */;
3023 info.func = __cvmx_error_display;
3024 info.user_info = (long)
3025 "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
3026 " register. Core0.\n";
3027 fail |= cvmx_error_add(&info);
3029 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3030 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3031 info.status_mask = 1ull<<41 /* c0_un_wi */;
3032 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3033 info.enable_mask = 1ull<<41 /* c0_un_wi */;
3035 info.group = CVMX_ERROR_GROUP_PCI;
3036 info.group_index = 0;
3037 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3038 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3039 info.parent.status_mask = 1ull<<3 /* npei */;
3040 info.func = __cvmx_error_display;
3041 info.user_info = (long)
3042 "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
3044 fail |= cvmx_error_add(&info);
3046 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3047 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3048 info.status_mask = 1ull<<33 /* c0_up_b0 */;
3049 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3050 info.enable_mask = 1ull<<33 /* c0_up_b0 */;
3052 info.group = CVMX_ERROR_GROUP_PCI;
3053 info.group_index = 0;
3054 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3055 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3056 info.parent.status_mask = 1ull<<3 /* npei */;
3057 info.func = __cvmx_error_display;
3058 info.user_info = (long)
3059 "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
3061 fail |= cvmx_error_add(&info);
3063 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3064 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3065 info.status_mask = 1ull<<34 /* c0_up_b1 */;
3066 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3067 info.enable_mask = 1ull<<34 /* c0_up_b1 */;
3069 info.group = CVMX_ERROR_GROUP_PCI;
3070 info.group_index = 0;
3071 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3072 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3073 info.parent.status_mask = 1ull<<3 /* npei */;
3074 info.func = __cvmx_error_display;
3075 info.user_info = (long)
3076 "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
3078 fail |= cvmx_error_add(&info);
3080 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3081 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3082 info.status_mask = 1ull<<35 /* c0_up_b2 */;
3083 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3084 info.enable_mask = 1ull<<35 /* c0_up_b2 */;
3086 info.group = CVMX_ERROR_GROUP_PCI;
3087 info.group_index = 0;
3088 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3089 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3090 info.parent.status_mask = 1ull<<3 /* npei */;
3091 info.func = __cvmx_error_display;
3092 info.user_info = (long)
3093 "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
3095 fail |= cvmx_error_add(&info);
3097 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3098 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3099 info.status_mask = 1ull<<37 /* c0_up_bx */;
3100 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3101 info.enable_mask = 1ull<<37 /* c0_up_bx */;
3103 info.group = CVMX_ERROR_GROUP_PCI;
3104 info.group_index = 0;
3105 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3106 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3107 info.parent.status_mask = 1ull<<3 /* npei */;
3108 info.func = __cvmx_error_display;
3109 info.user_info = (long)
3110 "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
3112 fail |= cvmx_error_add(&info);
3114 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3115 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3116 info.status_mask = 1ull<<55 /* c0_up_wf */;
3117 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3118 info.enable_mask = 1ull<<55 /* c0_up_wf */;
3120 info.group = CVMX_ERROR_GROUP_PCI;
3121 info.group_index = 0;
3122 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3123 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3124 info.parent.status_mask = 1ull<<3 /* npei */;
3125 info.func = __cvmx_error_display;
3126 info.user_info = (long)
3127 "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
3128 " register. Core0.\n";
3129 fail |= cvmx_error_add(&info);
3131 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3132 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3133 info.status_mask = 1ull<<36 /* c0_up_wi */;
3134 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3135 info.enable_mask = 1ull<<36 /* c0_up_wi */;
3137 info.group = CVMX_ERROR_GROUP_PCI;
3138 info.group_index = 0;
3139 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3140 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3141 info.parent.status_mask = 1ull<<3 /* npei */;
3142 info.func = __cvmx_error_display;
3143 info.user_info = (long)
3144 "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
3146 fail |= cvmx_error_add(&info);
3148 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3149 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3150 info.status_mask = 1ull<<23 /* c0_wake */;
3151 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3152 info.enable_mask = 1ull<<23 /* c0_wake */;
3154 info.group = CVMX_ERROR_GROUP_PCI;
3155 info.group_index = 0;
3156 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3157 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3158 info.parent.status_mask = 1ull<<3 /* npei */;
3159 info.func = __cvmx_error_display;
3160 info.user_info = (long)
3161 "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
3162 " Pcie Core 0. (wake_n)\n"
3163 " Octeon will never generate this interrupt.\n";
3164 fail |= cvmx_error_add(&info);
3166 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3167 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3168 info.status_mask = 1ull<<22 /* crs0_dr */;
3169 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3170 info.enable_mask = 1ull<<22 /* crs0_dr */;
3172 info.group = CVMX_ERROR_GROUP_PCI;
3173 info.group_index = 0;
3174 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3175 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3176 info.parent.status_mask = 1ull<<3 /* npei */;
3177 info.func = __cvmx_error_display;
3178 info.user_info = (long)
3179 "ERROR PEXP_NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n";
3180 fail |= cvmx_error_add(&info);
3182 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3183 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3184 info.status_mask = 1ull<<20 /* crs0_er */;
3185 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3186 info.enable_mask = 1ull<<20 /* crs0_er */;
3188 info.group = CVMX_ERROR_GROUP_PCI;
3189 info.group_index = 0;
3190 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3191 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3192 info.parent.status_mask = 1ull<<3 /* npei */;
3193 info.func = __cvmx_error_display;
3194 info.user_info = (long)
3195 "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n";
3196 fail |= cvmx_error_add(&info);
3198 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3199 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3200 info.status_mask = 1ull<<60 /* c1_ldwn */;
3201 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3202 info.enable_mask = 1ull<<60 /* c1_ldwn */;
3204 info.group = CVMX_ERROR_GROUP_PCI;
3205 info.group_index = 1;
3206 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3207 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3208 info.parent.status_mask = 1ull<<3 /* npei */;
3209 info.func = __cvmx_error_display;
3210 info.user_info = (long)
3211 "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
3212 fail |= cvmx_error_add(&info);
3214 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3215 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3216 info.status_mask = 1ull<<28 /* c1_se */;
3217 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3218 info.enable_mask = 1ull<<28 /* c1_se */;
3220 info.group = CVMX_ERROR_GROUP_PCI;
3221 info.group_index = 1;
3222 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3223 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3224 info.parent.status_mask = 1ull<<3 /* npei */;
3225 info.func = __cvmx_error_display;
3226 info.user_info = (long)
3227 "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
3228 " Pcie Core 1. (cfg_sys_err_rc)\n";
3229 fail |= cvmx_error_add(&info);
3231 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3232 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3233 info.status_mask = 1ull<<48 /* c1_un_b0 */;
3234 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3235 info.enable_mask = 1ull<<48 /* c1_un_b0 */;
3237 info.group = CVMX_ERROR_GROUP_PCI;
3238 info.group_index = 1;
3239 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3240 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3241 info.parent.status_mask = 1ull<<3 /* npei */;
3242 info.func = __cvmx_error_display;
3243 info.user_info = (long)
3244 "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
3246 fail |= cvmx_error_add(&info);
3248 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3249 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3250 info.status_mask = 1ull<<49 /* c1_un_b1 */;
3251 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3252 info.enable_mask = 1ull<<49 /* c1_un_b1 */;
3254 info.group = CVMX_ERROR_GROUP_PCI;
3255 info.group_index = 1;
3256 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3257 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3258 info.parent.status_mask = 1ull<<3 /* npei */;
3259 info.func = __cvmx_error_display;
3260 info.user_info = (long)
3261 "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
3263 fail |= cvmx_error_add(&info);
3265 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3266 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3267 info.status_mask = 1ull<<50 /* c1_un_b2 */;
3268 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3269 info.enable_mask = 1ull<<50 /* c1_un_b2 */;
3271 info.group = CVMX_ERROR_GROUP_PCI;
3272 info.group_index = 1;
3273 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3274 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3275 info.parent.status_mask = 1ull<<3 /* npei */;
3276 info.func = __cvmx_error_display;
3277 info.user_info = (long)
3278 "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
3280 fail |= cvmx_error_add(&info);
3282 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3283 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3284 info.status_mask = 1ull<<52 /* c1_un_bx */;
3285 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3286 info.enable_mask = 1ull<<52 /* c1_un_bx */;
3288 info.group = CVMX_ERROR_GROUP_PCI;
3289 info.group_index = 1;
3290 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3291 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3292 info.parent.status_mask = 1ull<<3 /* npei */;
3293 info.func = __cvmx_error_display;
3294 info.user_info = (long)
3295 "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
3297 fail |= cvmx_error_add(&info);
3299 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3300 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3301 info.status_mask = 1ull<<54 /* c1_un_wf */;
3302 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3303 info.enable_mask = 1ull<<54 /* c1_un_wf */;
3305 info.group = CVMX_ERROR_GROUP_PCI;
3306 info.group_index = 1;
3307 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3308 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3309 info.parent.status_mask = 1ull<<3 /* npei */;
3310 info.func = __cvmx_error_display;
3311 info.user_info = (long)
3312 "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
3313 " register. Core1.\n";
3314 fail |= cvmx_error_add(&info);
3316 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3317 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3318 info.status_mask = 1ull<<51 /* c1_un_wi */;
3319 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3320 info.enable_mask = 1ull<<51 /* c1_un_wi */;
3322 info.group = CVMX_ERROR_GROUP_PCI;
3323 info.group_index = 1;
3324 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3325 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3326 info.parent.status_mask = 1ull<<3 /* npei */;
3327 info.func = __cvmx_error_display;
3328 info.user_info = (long)
3329 "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
3331 fail |= cvmx_error_add(&info);
3333 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3334 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3335 info.status_mask = 1ull<<43 /* c1_up_b0 */;
3336 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3337 info.enable_mask = 1ull<<43 /* c1_up_b0 */;
3339 info.group = CVMX_ERROR_GROUP_PCI;
3340 info.group_index = 1;
3341 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3342 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3343 info.parent.status_mask = 1ull<<3 /* npei */;
3344 info.func = __cvmx_error_display;
3345 info.user_info = (long)
3346 "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
3348 fail |= cvmx_error_add(&info);
3350 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3351 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3352 info.status_mask = 1ull<<44 /* c1_up_b1 */;
3353 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3354 info.enable_mask = 1ull<<44 /* c1_up_b1 */;
3356 info.group = CVMX_ERROR_GROUP_PCI;
3357 info.group_index = 1;
3358 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3359 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3360 info.parent.status_mask = 1ull<<3 /* npei */;
3361 info.func = __cvmx_error_display;
3362 info.user_info = (long)
3363 "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsuppored P-TLP for Bar1.\n"
3365 fail |= cvmx_error_add(&info);
3367 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3368 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3369 info.status_mask = 1ull<<45 /* c1_up_b2 */;
3370 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3371 info.enable_mask = 1ull<<45 /* c1_up_b2 */;
3373 info.group = CVMX_ERROR_GROUP_PCI;
3374 info.group_index = 1;
3375 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3376 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3377 info.parent.status_mask = 1ull<<3 /* npei */;
3378 info.func = __cvmx_error_display;
3379 info.user_info = (long)
3380 "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
3382 fail |= cvmx_error_add(&info);
3384 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3385 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3386 info.status_mask = 1ull<<47 /* c1_up_bx */;
3387 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3388 info.enable_mask = 1ull<<47 /* c1_up_bx */;
3390 info.group = CVMX_ERROR_GROUP_PCI;
3391 info.group_index = 1;
3392 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3393 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3394 info.parent.status_mask = 1ull<<3 /* npei */;
3395 info.func = __cvmx_error_display;
3396 info.user_info = (long)
3397 "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
3399 fail |= cvmx_error_add(&info);
3401 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3402 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3403 info.status_mask = 1ull<<56 /* c1_up_wf */;
3404 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3405 info.enable_mask = 1ull<<56 /* c1_up_wf */;
3407 info.group = CVMX_ERROR_GROUP_PCI;
3408 info.group_index = 1;
3409 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3410 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3411 info.parent.status_mask = 1ull<<3 /* npei */;
3412 info.func = __cvmx_error_display;
3413 info.user_info = (long)
3414 "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
3415 " register. Core1.\n";
3416 fail |= cvmx_error_add(&info);
3418 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3419 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3420 info.status_mask = 1ull<<46 /* c1_up_wi */;
3421 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3422 info.enable_mask = 1ull<<46 /* c1_up_wi */;
3424 info.group = CVMX_ERROR_GROUP_PCI;
3425 info.group_index = 1;
3426 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3427 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3428 info.parent.status_mask = 1ull<<3 /* npei */;
3429 info.func = __cvmx_error_display;
3430 info.user_info = (long)
3431 "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
3433 fail |= cvmx_error_add(&info);
3435 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3436 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3437 info.status_mask = 1ull<<30 /* c1_wake */;
3438 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3439 info.enable_mask = 1ull<<30 /* c1_wake */;
3441 info.group = CVMX_ERROR_GROUP_PCI;
3442 info.group_index = 1;
3443 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3444 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3445 info.parent.status_mask = 1ull<<3 /* npei */;
3446 info.func = __cvmx_error_display;
3447 info.user_info = (long)
3448 "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
3449 " Pcie Core 1. (wake_n)\n"
3450 " Octeon will never generate this interrupt.\n";
3451 fail |= cvmx_error_add(&info);
3453 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3454 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3455 info.status_mask = 1ull<<29 /* crs1_dr */;
3456 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3457 info.enable_mask = 1ull<<29 /* crs1_dr */;
3459 info.group = CVMX_ERROR_GROUP_PCI;
3460 info.group_index = 1;
3461 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3462 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3463 info.parent.status_mask = 1ull<<3 /* npei */;
3464 info.func = __cvmx_error_display;
3465 info.user_info = (long)
3466 "ERROR PEXP_NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n";
3467 fail |= cvmx_error_add(&info);
3469 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3470 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3471 info.status_mask = 1ull<<27 /* crs1_er */;
3472 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3473 info.enable_mask = 1ull<<27 /* crs1_er */;
3475 info.group = CVMX_ERROR_GROUP_PCI;
3476 info.group_index = 1;
3477 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3478 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3479 info.parent.status_mask = 1ull<<3 /* npei */;
3480 info.func = __cvmx_error_display;
3481 info.user_info = (long)
3482 "ERROR PEXP_NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n";
3483 fail |= cvmx_error_add(&info);
3485 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3486 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3487 info.status_mask = 1ull<<2 /* bar0_to */;
3488 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3489 info.enable_mask = 1ull<<2 /* bar0_to */;
3491 info.group = CVMX_ERROR_GROUP_INTERNAL;
3492 info.group_index = 0;
3493 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3494 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3495 info.parent.status_mask = 1ull<<3 /* npei */;
3496 info.func = __cvmx_error_display;
3497 info.user_info = (long)
3498 "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
3499 " read-data/commit in 0xffff core clocks.\n";
3500 fail |= cvmx_error_add(&info);
3502 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3503 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3504 info.status_mask = 1ull<<4 /* dma0dbo */;
3505 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3506 info.enable_mask = 1ull<<4 /* dma0dbo */;
3508 info.group = CVMX_ERROR_GROUP_INTERNAL;
3509 info.group_index = 0;
3510 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3511 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3512 info.parent.status_mask = 1ull<<3 /* npei */;
3513 info.func = __cvmx_error_display;
3514 info.user_info = (long)
3515 "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
3516 " Bit[32] of the doorbell count was set.\n";
3517 fail |= cvmx_error_add(&info);
3519 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3520 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3521 info.status_mask = 1ull<<5 /* dma1dbo */;
3522 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3523 info.enable_mask = 1ull<<5 /* dma1dbo */;
3525 info.group = CVMX_ERROR_GROUP_INTERNAL;
3526 info.group_index = 0;
3527 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3528 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3529 info.parent.status_mask = 1ull<<3 /* npei */;
3530 info.func = __cvmx_error_display;
3531 info.user_info = (long)
3532 "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
3533 " Bit[32] of the doorbell count was set.\n";
3534 fail |= cvmx_error_add(&info);
3536 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3537 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3538 info.status_mask = 1ull<<6 /* dma2dbo */;
3539 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3540 info.enable_mask = 1ull<<6 /* dma2dbo */;
3542 info.group = CVMX_ERROR_GROUP_INTERNAL;
3543 info.group_index = 0;
3544 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3545 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3546 info.parent.status_mask = 1ull<<3 /* npei */;
3547 info.func = __cvmx_error_display;
3548 info.user_info = (long)
3549 "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
3550 " Bit[32] of the doorbell count was set.\n";
3551 fail |= cvmx_error_add(&info);
3553 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3554 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3555 info.status_mask = 1ull<<7 /* dma3dbo */;
3556 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3557 info.enable_mask = 1ull<<7 /* dma3dbo */;
3559 info.group = CVMX_ERROR_GROUP_INTERNAL;
3560 info.group_index = 0;
3561 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3562 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3563 info.parent.status_mask = 1ull<<3 /* npei */;
3564 info.func = __cvmx_error_display;
3565 info.user_info = (long)
3566 "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
3567 " Bit[32] of the doorbell count was set.\n";
3568 fail |= cvmx_error_add(&info);
3570 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3571 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3572 info.status_mask = 1ull<<3 /* iob2big */;
3573 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3574 info.enable_mask = 1ull<<3 /* iob2big */;
3576 info.group = CVMX_ERROR_GROUP_INTERNAL;
3577 info.group_index = 0;
3578 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3579 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3580 info.parent.status_mask = 1ull<<3 /* npei */;
3581 info.func = __cvmx_error_display;
3582 info.user_info = (long)
3583 "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
3584 fail |= cvmx_error_add(&info);
3586 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3587 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3588 info.status_mask = 1ull<<0 /* rml_rto */;
3589 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3590 info.enable_mask = 1ull<<0 /* rml_rto */;
3592 info.group = CVMX_ERROR_GROUP_INTERNAL;
3593 info.group_index = 0;
3594 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3595 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3596 info.parent.status_mask = 1ull<<3 /* npei */;
3597 info.func = __cvmx_error_display;
3598 info.user_info = (long)
3599 "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
3600 fail |= cvmx_error_add(&info);
3602 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3603 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3604 info.status_mask = 1ull<<1 /* rml_wto */;
3605 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3606 info.enable_mask = 1ull<<1 /* rml_wto */;
3608 info.group = CVMX_ERROR_GROUP_INTERNAL;
3609 info.group_index = 0;
3610 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3611 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3612 info.parent.status_mask = 1ull<<3 /* npei */;
3613 info.func = __cvmx_error_display;
3614 info.user_info = (long)
3615 "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
3616 fail |= cvmx_error_add(&info);
3618 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3619 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3620 info.status_mask = 1ull<<8 /* dma4dbo */;
3621 info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
3622 info.enable_mask = 1ull<<8 /* dma4dbo */;
3624 info.group = CVMX_ERROR_GROUP_INTERNAL;
3625 info.group_index = 0;
3626 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3627 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3628 info.parent.status_mask = 1ull<<3 /* npei */;
3629 info.func = __cvmx_error_display;
3630 info.user_info = (long)
3631 "ERROR PEXP_NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
3632 " Bit[32] of the doorbell count was set.\n";
3633 fail |= cvmx_error_add(&info);
3635 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3636 info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3637 info.status_mask = 0;
3638 info.enable_addr = 0;
3639 info.enable_mask = 0;
3641 info.group = CVMX_ERROR_GROUP_INTERNAL;
3642 info.group_index = 0;
3643 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3644 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
3645 info.parent.status_mask = 1ull<<3 /* npei */;
3646 info.func = __cvmx_error_decode;
3648 fail |= cvmx_error_add(&info);
3650 /* CVMX_PESCX_DBG_INFO(0) */
3651 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3652 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3653 info.status_mask = 1ull<<0 /* spoison */;
3654 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3655 info.enable_mask = 1ull<<0 /* spoison */;
3657 info.group = CVMX_ERROR_GROUP_PCI;
3658 info.group_index = 0;
3659 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3660 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3661 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3662 info.func = __cvmx_error_display;
3663 info.user_info = (long)
3664 "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
3665 " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
3666 fail |= cvmx_error_add(&info);
3668 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3669 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3670 info.status_mask = 1ull<<2 /* rtlplle */;
3671 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3672 info.enable_mask = 1ull<<2 /* rtlplle */;
3674 info.group = CVMX_ERROR_GROUP_PCI;
3675 info.group_index = 0;
3676 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3677 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3678 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3679 info.func = __cvmx_error_display;
3680 info.user_info = (long)
3681 "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
3682 " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
3683 fail |= cvmx_error_add(&info);
3685 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3686 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3687 info.status_mask = 1ull<<3 /* recrce */;
3688 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3689 info.enable_mask = 1ull<<3 /* recrce */;
3691 info.group = CVMX_ERROR_GROUP_PCI;
3692 info.group_index = 0;
3693 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3694 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3695 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3696 info.func = __cvmx_error_display;
3697 info.user_info = (long)
3698 "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
3699 " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
3700 fail |= cvmx_error_add(&info);
3702 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3703 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3704 info.status_mask = 1ull<<4 /* rpoison */;
3705 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3706 info.enable_mask = 1ull<<4 /* rpoison */;
3708 info.group = CVMX_ERROR_GROUP_PCI;
3709 info.group_index = 0;
3710 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3711 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3712 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3713 info.func = __cvmx_error_display;
3714 info.user_info = (long)
3715 "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
3716 " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
3717 fail |= cvmx_error_add(&info);
3719 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3720 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3721 info.status_mask = 1ull<<5 /* rcemrc */;
3722 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3723 info.enable_mask = 1ull<<5 /* rcemrc */;
3725 info.group = CVMX_ERROR_GROUP_PCI;
3726 info.group_index = 0;
3727 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3728 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3729 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3730 info.func = __cvmx_error_display;
3731 info.user_info = (long)
3732 "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
3733 " pedc_radm_correctable_err\n";
3734 fail |= cvmx_error_add(&info);
3736 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3737 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3738 info.status_mask = 1ull<<6 /* rnfemrc */;
3739 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3740 info.enable_mask = 1ull<<6 /* rnfemrc */;
3742 info.group = CVMX_ERROR_GROUP_PCI;
3743 info.group_index = 0;
3744 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3745 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3746 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3747 info.func = __cvmx_error_display;
3748 info.user_info = (long)
3749 "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
3750 " pedc_radm_nonfatal_err\n";
3751 fail |= cvmx_error_add(&info);
3753 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3754 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3755 info.status_mask = 1ull<<7 /* rfemrc */;
3756 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3757 info.enable_mask = 1ull<<7 /* rfemrc */;
3759 info.group = CVMX_ERROR_GROUP_PCI;
3760 info.group_index = 0;
3761 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3762 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3763 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3764 info.func = __cvmx_error_display;
3765 info.user_info = (long)
3766 "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
3767 " pedc_radm_fatal_err\n"
3768 " Bit set when a message with ERR_FATAL is set.\n";
3769 fail |= cvmx_error_add(&info);
3771 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3772 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3773 info.status_mask = 1ull<<8 /* rpmerc */;
3774 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3775 info.enable_mask = 1ull<<8 /* rpmerc */;
3777 info.group = CVMX_ERROR_GROUP_PCI;
3778 info.group_index = 0;
3779 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3780 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3781 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3782 info.func = __cvmx_error_display;
3783 info.user_info = (long)
3784 "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
3785 " pedc_radm_pm_pme\n";
3786 fail |= cvmx_error_add(&info);
3788 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3789 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3790 info.status_mask = 1ull<<9 /* rptamrc */;
3791 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3792 info.enable_mask = 1ull<<9 /* rptamrc */;
3794 info.group = CVMX_ERROR_GROUP_PCI;
3795 info.group_index = 0;
3796 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3797 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3798 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3799 info.func = __cvmx_error_display;
3800 info.user_info = (long)
3801 "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
3803 " pedc_radm_pm_to_ack\n";
3804 fail |= cvmx_error_add(&info);
3806 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3807 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3808 info.status_mask = 1ull<<10 /* rumep */;
3809 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3810 info.enable_mask = 1ull<<10 /* rumep */;
3812 info.group = CVMX_ERROR_GROUP_PCI;
3813 info.group_index = 0;
3814 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3815 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3816 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3817 info.func = __cvmx_error_display;
3818 info.user_info = (long)
3819 "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
3820 " pedc_radm_msg_unlock\n";
3821 fail |= cvmx_error_add(&info);
3823 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3824 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3825 info.status_mask = 1ull<<11 /* rvdm */;
3826 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3827 info.enable_mask = 1ull<<11 /* rvdm */;
3829 info.group = CVMX_ERROR_GROUP_PCI;
3830 info.group_index = 0;
3831 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3832 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3833 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3834 info.func = __cvmx_error_display;
3835 info.user_info = (long)
3836 "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
3837 " pedc_radm_vendor_msg\n";
3838 fail |= cvmx_error_add(&info);
3840 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3841 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3842 info.status_mask = 1ull<<12 /* acto */;
3843 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3844 info.enable_mask = 1ull<<12 /* acto */;
3846 info.group = CVMX_ERROR_GROUP_PCI;
3847 info.group_index = 0;
3848 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3849 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3850 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3851 info.func = __cvmx_error_display;
3852 info.user_info = (long)
3853 "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
3854 " pedc_radm_cpl_timeout\n";
3855 fail |= cvmx_error_add(&info);
3857 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3858 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3859 info.status_mask = 1ull<<13 /* rte */;
3860 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3861 info.enable_mask = 1ull<<13 /* rte */;
3863 info.group = CVMX_ERROR_GROUP_PCI;
3864 info.group_index = 0;
3865 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3866 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3867 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3868 info.func = __cvmx_error_display;
3869 info.user_info = (long)
3870 "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
3871 " xdlh_replay_timeout_err\n"
3872 " This bit is set when the REPLAY_TIMER expires in\n"
3873 " the PCIE core. The probability of this bit being\n"
3874 " set will increase with the traffic load.\n";
3875 fail |= cvmx_error_add(&info);
3877 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3878 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3879 info.status_mask = 1ull<<14 /* mre */;
3880 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3881 info.enable_mask = 1ull<<14 /* mre */;
3883 info.group = CVMX_ERROR_GROUP_PCI;
3884 info.group_index = 0;
3885 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3886 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3887 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3888 info.func = __cvmx_error_display;
3889 info.user_info = (long)
3890 "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
3891 " xdlh_replay_num_rlover_err\n";
3892 fail |= cvmx_error_add(&info);
3894 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3895 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3896 info.status_mask = 1ull<<15 /* rdwdle */;
3897 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3898 info.enable_mask = 1ull<<15 /* rdwdle */;
3900 info.group = CVMX_ERROR_GROUP_PCI;
3901 info.group_index = 0;
3902 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3903 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3904 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3905 info.func = __cvmx_error_display;
3906 info.user_info = (long)
3907 "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
3908 " rdlh_bad_dllp_err\n";
3909 fail |= cvmx_error_add(&info);
3911 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3912 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3913 info.status_mask = 1ull<<16 /* rtwdle */;
3914 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3915 info.enable_mask = 1ull<<16 /* rtwdle */;
3917 info.group = CVMX_ERROR_GROUP_PCI;
3918 info.group_index = 0;
3919 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3920 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3921 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3922 info.func = __cvmx_error_display;
3923 info.user_info = (long)
3924 "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
3925 " rdlh_bad_tlp_err\n";
3926 fail |= cvmx_error_add(&info);
3928 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3929 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3930 info.status_mask = 1ull<<17 /* dpeoosd */;
3931 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3932 info.enable_mask = 1ull<<17 /* dpeoosd */;
3934 info.group = CVMX_ERROR_GROUP_PCI;
3935 info.group_index = 0;
3936 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3937 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3938 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3939 info.func = __cvmx_error_display;
3940 info.user_info = (long)
3941 "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
3943 fail |= cvmx_error_add(&info);
3945 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3946 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3947 info.status_mask = 1ull<<18 /* fcpvwt */;
3948 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3949 info.enable_mask = 1ull<<18 /* fcpvwt */;
3951 info.group = CVMX_ERROR_GROUP_PCI;
3952 info.group_index = 0;
3953 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3954 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3955 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3956 info.func = __cvmx_error_display;
3957 info.user_info = (long)
3958 "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
3959 " rtlh_fc_prot_err\n";
3960 fail |= cvmx_error_add(&info);
3962 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3963 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3964 info.status_mask = 1ull<<19 /* rpe */;
3965 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3966 info.enable_mask = 1ull<<19 /* rpe */;
3968 info.group = CVMX_ERROR_GROUP_PCI;
3969 info.group_index = 0;
3970 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3971 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3972 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3973 info.func = __cvmx_error_display;
3974 info.user_info = (long)
3975 "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
3976 " (RxStatus = 3b100) or disparity error\n"
3977 " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
3980 fail |= cvmx_error_add(&info);
3982 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3983 info.status_addr = CVMX_PESCX_DBG_INFO(0);
3984 info.status_mask = 1ull<<20 /* fcuv */;
3985 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
3986 info.enable_mask = 1ull<<20 /* fcuv */;
3988 info.group = CVMX_ERROR_GROUP_PCI;
3989 info.group_index = 0;
3990 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3991 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
3992 info.parent.status_mask = 1ull<<57 /* c0_exc */;
3993 info.func = __cvmx_error_display;
3994 info.user_info = (long)
3995 "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
3996 " int_xadm_fc_prot_err\n";
3997 fail |= cvmx_error_add(&info);
3999 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4000 info.status_addr = CVMX_PESCX_DBG_INFO(0);
4001 info.status_mask = 1ull<<21 /* rqo */;
4002 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
4003 info.enable_mask = 1ull<<21 /* rqo */;
4005 info.group = CVMX_ERROR_GROUP_PCI;
4006 info.group_index = 0;
4007 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4008 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4009 info.parent.status_mask = 1ull<<57 /* c0_exc */;
4010 info.func = __cvmx_error_display;
4011 info.user_info = (long)
4012 "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
4013 " flow control advertisements are ignored\n"
4014 " radm_qoverflow\n";
4015 fail |= cvmx_error_add(&info);
4017 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4018 info.status_addr = CVMX_PESCX_DBG_INFO(0);
4019 info.status_mask = 1ull<<22 /* rauc */;
4020 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
4021 info.enable_mask = 1ull<<22 /* rauc */;
4023 info.group = CVMX_ERROR_GROUP_PCI;
4024 info.group_index = 0;
4025 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4026 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4027 info.parent.status_mask = 1ull<<57 /* c0_exc */;
4028 info.func = __cvmx_error_display;
4029 info.user_info = (long)
4030 "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
4031 " radm_unexp_cpl_err\n";
4032 fail |= cvmx_error_add(&info);
4034 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4035 info.status_addr = CVMX_PESCX_DBG_INFO(0);
4036 info.status_mask = 1ull<<23 /* racur */;
4037 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
4038 info.enable_mask = 1ull<<23 /* racur */;
4040 info.group = CVMX_ERROR_GROUP_PCI;
4041 info.group_index = 0;
4042 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4043 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4044 info.parent.status_mask = 1ull<<57 /* c0_exc */;
4045 info.func = __cvmx_error_display;
4046 info.user_info = (long)
4047 "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
4048 " radm_rcvd_cpl_ur\n";
4049 fail |= cvmx_error_add(&info);
4051 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4052 info.status_addr = CVMX_PESCX_DBG_INFO(0);
4053 info.status_mask = 1ull<<24 /* racca */;
4054 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
4055 info.enable_mask = 1ull<<24 /* racca */;
4057 info.group = CVMX_ERROR_GROUP_PCI;
4058 info.group_index = 0;
4059 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4060 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4061 info.parent.status_mask = 1ull<<57 /* c0_exc */;
4062 info.func = __cvmx_error_display;
4063 info.user_info = (long)
4064 "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
4065 " radm_rcvd_cpl_ca\n";
4066 fail |= cvmx_error_add(&info);
4068 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4069 info.status_addr = CVMX_PESCX_DBG_INFO(0);
4070 info.status_mask = 1ull<<25 /* caar */;
4071 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
4072 info.enable_mask = 1ull<<25 /* caar */;
4074 info.group = CVMX_ERROR_GROUP_PCI;
4075 info.group_index = 0;
4076 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4077 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4078 info.parent.status_mask = 1ull<<57 /* c0_exc */;
4079 info.func = __cvmx_error_display;
4080 info.user_info = (long)
4081 "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
4082 " radm_rcvd_ca_req\n"
4083 " This bit will never be set because Octeon does\n"
4084 " not generate Completer Aborts.\n";
4085 fail |= cvmx_error_add(&info);
4087 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4088 info.status_addr = CVMX_PESCX_DBG_INFO(0);
4089 info.status_mask = 1ull<<26 /* rarwdns */;
4090 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
4091 info.enable_mask = 1ull<<26 /* rarwdns */;
4093 info.group = CVMX_ERROR_GROUP_PCI;
4094 info.group_index = 0;
4095 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4096 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4097 info.parent.status_mask = 1ull<<57 /* c0_exc */;
4098 info.func = __cvmx_error_display;
4099 info.user_info = (long)
4100 "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
4101 " radm_rcvd_ur_req\n";
4102 fail |= cvmx_error_add(&info);
4104 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4105 info.status_addr = CVMX_PESCX_DBG_INFO(0);
4106 info.status_mask = 1ull<<27 /* ramtlp */;
4107 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
4108 info.enable_mask = 1ull<<27 /* ramtlp */;
4110 info.group = CVMX_ERROR_GROUP_PCI;
4111 info.group_index = 0;
4112 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4113 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4114 info.parent.status_mask = 1ull<<57 /* c0_exc */;
4115 info.func = __cvmx_error_display;
4116 info.user_info = (long)
4117 "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
4118 " radm_mlf_tlp_err\n";
4119 fail |= cvmx_error_add(&info);
4121 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4122 info.status_addr = CVMX_PESCX_DBG_INFO(0);
4123 info.status_mask = 1ull<<28 /* racpp */;
4124 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
4125 info.enable_mask = 1ull<<28 /* racpp */;
4127 info.group = CVMX_ERROR_GROUP_PCI;
4128 info.group_index = 0;
4129 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4130 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4131 info.parent.status_mask = 1ull<<57 /* c0_exc */;
4132 info.func = __cvmx_error_display;
4133 info.user_info = (long)
4134 "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
4135 " radm_rcvd_cpl_poisoned\n";
4136 fail |= cvmx_error_add(&info);
4138 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4139 info.status_addr = CVMX_PESCX_DBG_INFO(0);
4140 info.status_mask = 1ull<<29 /* rawwpp */;
4141 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
4142 info.enable_mask = 1ull<<29 /* rawwpp */;
4144 info.group = CVMX_ERROR_GROUP_PCI;
4145 info.group_index = 0;
4146 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4147 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4148 info.parent.status_mask = 1ull<<57 /* c0_exc */;
4149 info.func = __cvmx_error_display;
4150 info.user_info = (long)
4151 "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
4152 " radm_rcvd_wreq_poisoned\n";
4153 fail |= cvmx_error_add(&info);
4155 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4156 info.status_addr = CVMX_PESCX_DBG_INFO(0);
4157 info.status_mask = 1ull<<30 /* ecrc_e */;
4158 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
4159 info.enable_mask = 1ull<<30 /* ecrc_e */;
4161 info.group = CVMX_ERROR_GROUP_PCI;
4162 info.group_index = 0;
4163 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4164 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4165 info.parent.status_mask = 1ull<<57 /* c0_exc */;
4166 info.func = __cvmx_error_display;
4167 info.user_info = (long)
4168 "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
4170 fail |= cvmx_error_add(&info);
4172 /* CVMX_PESCX_DBG_INFO(1) */
4173 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4174 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4175 info.status_mask = 1ull<<0 /* spoison */;
4176 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4177 info.enable_mask = 1ull<<0 /* spoison */;
4179 info.group = CVMX_ERROR_GROUP_PCI;
4180 info.group_index = 1;
4181 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4182 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4183 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4184 info.func = __cvmx_error_display;
4185 info.user_info = (long)
4186 "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
4187 " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
4188 fail |= cvmx_error_add(&info);
4190 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4191 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4192 info.status_mask = 1ull<<2 /* rtlplle */;
4193 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4194 info.enable_mask = 1ull<<2 /* rtlplle */;
4196 info.group = CVMX_ERROR_GROUP_PCI;
4197 info.group_index = 1;
4198 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4199 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4200 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4201 info.func = __cvmx_error_display;
4202 info.user_info = (long)
4203 "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
4204 " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
4205 fail |= cvmx_error_add(&info);
4207 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4208 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4209 info.status_mask = 1ull<<3 /* recrce */;
4210 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4211 info.enable_mask = 1ull<<3 /* recrce */;
4213 info.group = CVMX_ERROR_GROUP_PCI;
4214 info.group_index = 1;
4215 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4216 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4217 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4218 info.func = __cvmx_error_display;
4219 info.user_info = (long)
4220 "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
4221 " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
4222 fail |= cvmx_error_add(&info);
4224 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4225 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4226 info.status_mask = 1ull<<4 /* rpoison */;
4227 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4228 info.enable_mask = 1ull<<4 /* rpoison */;
4230 info.group = CVMX_ERROR_GROUP_PCI;
4231 info.group_index = 1;
4232 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4233 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4234 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4235 info.func = __cvmx_error_display;
4236 info.user_info = (long)
4237 "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
4238 " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
4239 fail |= cvmx_error_add(&info);
4241 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4242 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4243 info.status_mask = 1ull<<5 /* rcemrc */;
4244 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4245 info.enable_mask = 1ull<<5 /* rcemrc */;
4247 info.group = CVMX_ERROR_GROUP_PCI;
4248 info.group_index = 1;
4249 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4250 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4251 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4252 info.func = __cvmx_error_display;
4253 info.user_info = (long)
4254 "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
4255 " pedc_radm_correctable_err\n";
4256 fail |= cvmx_error_add(&info);
4258 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4259 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4260 info.status_mask = 1ull<<6 /* rnfemrc */;
4261 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4262 info.enable_mask = 1ull<<6 /* rnfemrc */;
4264 info.group = CVMX_ERROR_GROUP_PCI;
4265 info.group_index = 1;
4266 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4267 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4268 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4269 info.func = __cvmx_error_display;
4270 info.user_info = (long)
4271 "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
4272 " pedc_radm_nonfatal_err\n";
4273 fail |= cvmx_error_add(&info);
4275 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4276 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4277 info.status_mask = 1ull<<7 /* rfemrc */;
4278 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4279 info.enable_mask = 1ull<<7 /* rfemrc */;
4281 info.group = CVMX_ERROR_GROUP_PCI;
4282 info.group_index = 1;
4283 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4284 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4285 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4286 info.func = __cvmx_error_display;
4287 info.user_info = (long)
4288 "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
4289 " pedc_radm_fatal_err\n"
4290 " Bit set when a message with ERR_FATAL is set.\n";
4291 fail |= cvmx_error_add(&info);
4293 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4294 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4295 info.status_mask = 1ull<<8 /* rpmerc */;
4296 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4297 info.enable_mask = 1ull<<8 /* rpmerc */;
4299 info.group = CVMX_ERROR_GROUP_PCI;
4300 info.group_index = 1;
4301 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4302 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4303 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4304 info.func = __cvmx_error_display;
4305 info.user_info = (long)
4306 "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
4307 " pedc_radm_pm_pme\n";
4308 fail |= cvmx_error_add(&info);
4310 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4311 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4312 info.status_mask = 1ull<<9 /* rptamrc */;
4313 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4314 info.enable_mask = 1ull<<9 /* rptamrc */;
4316 info.group = CVMX_ERROR_GROUP_PCI;
4317 info.group_index = 1;
4318 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4319 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4320 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4321 info.func = __cvmx_error_display;
4322 info.user_info = (long)
4323 "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
4325 " pedc_radm_pm_to_ack\n";
4326 fail |= cvmx_error_add(&info);
4328 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4329 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4330 info.status_mask = 1ull<<10 /* rumep */;
4331 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4332 info.enable_mask = 1ull<<10 /* rumep */;
4334 info.group = CVMX_ERROR_GROUP_PCI;
4335 info.group_index = 1;
4336 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4337 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4338 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4339 info.func = __cvmx_error_display;
4340 info.user_info = (long)
4341 "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
4342 " pedc_radm_msg_unlock\n";
4343 fail |= cvmx_error_add(&info);
4345 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4346 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4347 info.status_mask = 1ull<<11 /* rvdm */;
4348 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4349 info.enable_mask = 1ull<<11 /* rvdm */;
4351 info.group = CVMX_ERROR_GROUP_PCI;
4352 info.group_index = 1;
4353 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4354 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4355 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4356 info.func = __cvmx_error_display;
4357 info.user_info = (long)
4358 "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
4359 " pedc_radm_vendor_msg\n";
4360 fail |= cvmx_error_add(&info);
4362 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4363 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4364 info.status_mask = 1ull<<12 /* acto */;
4365 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4366 info.enable_mask = 1ull<<12 /* acto */;
4368 info.group = CVMX_ERROR_GROUP_PCI;
4369 info.group_index = 1;
4370 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4371 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4372 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4373 info.func = __cvmx_error_display;
4374 info.user_info = (long)
4375 "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
4376 " pedc_radm_cpl_timeout\n";
4377 fail |= cvmx_error_add(&info);
4379 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4380 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4381 info.status_mask = 1ull<<13 /* rte */;
4382 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4383 info.enable_mask = 1ull<<13 /* rte */;
4385 info.group = CVMX_ERROR_GROUP_PCI;
4386 info.group_index = 1;
4387 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4388 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4389 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4390 info.func = __cvmx_error_display;
4391 info.user_info = (long)
4392 "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
4393 " xdlh_replay_timeout_err\n"
4394 " This bit is set when the REPLAY_TIMER expires in\n"
4395 " the PCIE core. The probability of this bit being\n"
4396 " set will increase with the traffic load.\n";
4397 fail |= cvmx_error_add(&info);
4399 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4400 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4401 info.status_mask = 1ull<<14 /* mre */;
4402 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4403 info.enable_mask = 1ull<<14 /* mre */;
4405 info.group = CVMX_ERROR_GROUP_PCI;
4406 info.group_index = 1;
4407 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4408 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4409 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4410 info.func = __cvmx_error_display;
4411 info.user_info = (long)
4412 "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
4413 " xdlh_replay_num_rlover_err\n";
4414 fail |= cvmx_error_add(&info);
4416 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4417 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4418 info.status_mask = 1ull<<15 /* rdwdle */;
4419 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4420 info.enable_mask = 1ull<<15 /* rdwdle */;
4422 info.group = CVMX_ERROR_GROUP_PCI;
4423 info.group_index = 1;
4424 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4425 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4426 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4427 info.func = __cvmx_error_display;
4428 info.user_info = (long)
4429 "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
4430 " rdlh_bad_dllp_err\n";
4431 fail |= cvmx_error_add(&info);
4433 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4434 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4435 info.status_mask = 1ull<<16 /* rtwdle */;
4436 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4437 info.enable_mask = 1ull<<16 /* rtwdle */;
4439 info.group = CVMX_ERROR_GROUP_PCI;
4440 info.group_index = 1;
4441 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4442 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4443 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4444 info.func = __cvmx_error_display;
4445 info.user_info = (long)
4446 "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
4447 " rdlh_bad_tlp_err\n";
4448 fail |= cvmx_error_add(&info);
4450 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4451 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4452 info.status_mask = 1ull<<17 /* dpeoosd */;
4453 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4454 info.enable_mask = 1ull<<17 /* dpeoosd */;
4456 info.group = CVMX_ERROR_GROUP_PCI;
4457 info.group_index = 1;
4458 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4459 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4460 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4461 info.func = __cvmx_error_display;
4462 info.user_info = (long)
4463 "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
4465 fail |= cvmx_error_add(&info);
4467 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4468 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4469 info.status_mask = 1ull<<18 /* fcpvwt */;
4470 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4471 info.enable_mask = 1ull<<18 /* fcpvwt */;
4473 info.group = CVMX_ERROR_GROUP_PCI;
4474 info.group_index = 1;
4475 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4476 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4477 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4478 info.func = __cvmx_error_display;
4479 info.user_info = (long)
4480 "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
4481 " rtlh_fc_prot_err\n";
4482 fail |= cvmx_error_add(&info);
4484 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4485 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4486 info.status_mask = 1ull<<19 /* rpe */;
4487 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4488 info.enable_mask = 1ull<<19 /* rpe */;
4490 info.group = CVMX_ERROR_GROUP_PCI;
4491 info.group_index = 1;
4492 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4493 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4494 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4495 info.func = __cvmx_error_display;
4496 info.user_info = (long)
4497 "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
4498 " (RxStatus = 3b100) or disparity error\n"
4499 " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
4502 fail |= cvmx_error_add(&info);
4504 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4505 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4506 info.status_mask = 1ull<<20 /* fcuv */;
4507 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4508 info.enable_mask = 1ull<<20 /* fcuv */;
4510 info.group = CVMX_ERROR_GROUP_PCI;
4511 info.group_index = 1;
4512 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4513 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4514 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4515 info.func = __cvmx_error_display;
4516 info.user_info = (long)
4517 "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
4518 " int_xadm_fc_prot_err\n";
4519 fail |= cvmx_error_add(&info);
4521 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4522 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4523 info.status_mask = 1ull<<21 /* rqo */;
4524 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4525 info.enable_mask = 1ull<<21 /* rqo */;
4527 info.group = CVMX_ERROR_GROUP_PCI;
4528 info.group_index = 1;
4529 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4530 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4531 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4532 info.func = __cvmx_error_display;
4533 info.user_info = (long)
4534 "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
4535 " flow control advertisements are ignored\n"
4536 " radm_qoverflow\n";
4537 fail |= cvmx_error_add(&info);
4539 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4540 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4541 info.status_mask = 1ull<<22 /* rauc */;
4542 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4543 info.enable_mask = 1ull<<22 /* rauc */;
4545 info.group = CVMX_ERROR_GROUP_PCI;
4546 info.group_index = 1;
4547 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4548 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4549 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4550 info.func = __cvmx_error_display;
4551 info.user_info = (long)
4552 "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
4553 " radm_unexp_cpl_err\n";
4554 fail |= cvmx_error_add(&info);
4556 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4557 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4558 info.status_mask = 1ull<<23 /* racur */;
4559 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4560 info.enable_mask = 1ull<<23 /* racur */;
4562 info.group = CVMX_ERROR_GROUP_PCI;
4563 info.group_index = 1;
4564 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4565 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4566 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4567 info.func = __cvmx_error_display;
4568 info.user_info = (long)
4569 "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
4570 " radm_rcvd_cpl_ur\n";
4571 fail |= cvmx_error_add(&info);
4573 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4574 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4575 info.status_mask = 1ull<<24 /* racca */;
4576 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4577 info.enable_mask = 1ull<<24 /* racca */;
4579 info.group = CVMX_ERROR_GROUP_PCI;
4580 info.group_index = 1;
4581 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4582 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4583 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4584 info.func = __cvmx_error_display;
4585 info.user_info = (long)
4586 "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
4587 " radm_rcvd_cpl_ca\n";
4588 fail |= cvmx_error_add(&info);
4590 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4591 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4592 info.status_mask = 1ull<<25 /* caar */;
4593 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4594 info.enable_mask = 1ull<<25 /* caar */;
4596 info.group = CVMX_ERROR_GROUP_PCI;
4597 info.group_index = 1;
4598 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4599 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4600 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4601 info.func = __cvmx_error_display;
4602 info.user_info = (long)
4603 "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
4604 " radm_rcvd_ca_req\n"
4605 " This bit will never be set because Octeon does\n"
4606 " not generate Completer Aborts.\n";
4607 fail |= cvmx_error_add(&info);
4609 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4610 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4611 info.status_mask = 1ull<<26 /* rarwdns */;
4612 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4613 info.enable_mask = 1ull<<26 /* rarwdns */;
4615 info.group = CVMX_ERROR_GROUP_PCI;
4616 info.group_index = 1;
4617 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4618 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4619 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4620 info.func = __cvmx_error_display;
4621 info.user_info = (long)
4622 "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
4623 " radm_rcvd_ur_req\n";
4624 fail |= cvmx_error_add(&info);
4626 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4627 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4628 info.status_mask = 1ull<<27 /* ramtlp */;
4629 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4630 info.enable_mask = 1ull<<27 /* ramtlp */;
4632 info.group = CVMX_ERROR_GROUP_PCI;
4633 info.group_index = 1;
4634 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4635 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4636 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4637 info.func = __cvmx_error_display;
4638 info.user_info = (long)
4639 "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
4640 " radm_mlf_tlp_err\n";
4641 fail |= cvmx_error_add(&info);
4643 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4644 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4645 info.status_mask = 1ull<<28 /* racpp */;
4646 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4647 info.enable_mask = 1ull<<28 /* racpp */;
4649 info.group = CVMX_ERROR_GROUP_PCI;
4650 info.group_index = 1;
4651 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4652 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4653 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4654 info.func = __cvmx_error_display;
4655 info.user_info = (long)
4656 "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
4657 " radm_rcvd_cpl_poisoned\n";
4658 fail |= cvmx_error_add(&info);
4660 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4661 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4662 info.status_mask = 1ull<<29 /* rawwpp */;
4663 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4664 info.enable_mask = 1ull<<29 /* rawwpp */;
4666 info.group = CVMX_ERROR_GROUP_PCI;
4667 info.group_index = 1;
4668 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4669 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4670 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4671 info.func = __cvmx_error_display;
4672 info.user_info = (long)
4673 "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
4674 " radm_rcvd_wreq_poisoned\n";
4675 fail |= cvmx_error_add(&info);
4677 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4678 info.status_addr = CVMX_PESCX_DBG_INFO(1);
4679 info.status_mask = 1ull<<30 /* ecrc_e */;
4680 info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
4681 info.enable_mask = 1ull<<30 /* ecrc_e */;
4683 info.group = CVMX_ERROR_GROUP_PCI;
4684 info.group_index = 1;
4685 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4686 info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
4687 info.parent.status_mask = 1ull<<58 /* c1_exc */;
4688 info.func = __cvmx_error_display;
4689 info.user_info = (long)
4690 "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
4692 fail |= cvmx_error_add(&info);
4694 /* CVMX_RAD_REG_ERROR */
4695 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4696 info.status_addr = CVMX_RAD_REG_ERROR;
4697 info.status_mask = 1ull<<0 /* doorbell */;
4698 info.enable_addr = CVMX_RAD_REG_INT_MASK;
4699 info.enable_mask = 1ull<<0 /* doorbell */;
4701 info.group = CVMX_ERROR_GROUP_INTERNAL;
4702 info.group_index = 0;
4703 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4704 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4705 info.parent.status_mask = 1ull<<14 /* rad */;
4706 info.func = __cvmx_error_display;
4707 info.user_info = (long)
4708 "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
4709 fail |= cvmx_error_add(&info);
4711 /* CVMX_PKO_REG_ERROR */
4712 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4713 info.status_addr = CVMX_PKO_REG_ERROR;
4714 info.status_mask = 1ull<<0 /* parity */;
4715 info.enable_addr = CVMX_PKO_REG_INT_MASK;
4716 info.enable_mask = 1ull<<0 /* parity */;
4718 info.group = CVMX_ERROR_GROUP_INTERNAL;
4719 info.group_index = 0;
4720 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4721 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4722 info.parent.status_mask = 1ull<<10 /* pko */;
4723 info.func = __cvmx_error_display;
4724 info.user_info = (long)
4725 "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
4726 fail |= cvmx_error_add(&info);
4728 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4729 info.status_addr = CVMX_PKO_REG_ERROR;
4730 info.status_mask = 1ull<<1 /* doorbell */;
4731 info.enable_addr = CVMX_PKO_REG_INT_MASK;
4732 info.enable_mask = 1ull<<1 /* doorbell */;
4734 info.group = CVMX_ERROR_GROUP_INTERNAL;
4735 info.group_index = 0;
4736 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4737 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4738 info.parent.status_mask = 1ull<<10 /* pko */;
4739 info.func = __cvmx_error_display;
4740 info.user_info = (long)
4741 "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
4742 fail |= cvmx_error_add(&info);
4744 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4745 info.status_addr = CVMX_PKO_REG_ERROR;
4746 info.status_mask = 1ull<<2 /* currzero */;
4747 info.enable_addr = CVMX_PKO_REG_INT_MASK;
4748 info.enable_mask = 1ull<<2 /* currzero */;
4750 info.group = CVMX_ERROR_GROUP_INTERNAL;
4751 info.group_index = 0;
4752 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4753 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4754 info.parent.status_mask = 1ull<<10 /* pko */;
4755 info.func = __cvmx_error_display;
4756 info.user_info = (long)
4757 "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
4758 fail |= cvmx_error_add(&info);
4760 /* CVMX_PCSX_INTX_REG(0,0) */
4761 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4762 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
4763 info.status_mask = 1ull<<2 /* an_err */;
4764 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
4765 info.enable_mask = 1ull<<2 /* an_err_en */;
4767 info.group = CVMX_ERROR_GROUP_ETHERNET;
4768 info.group_index = 0;
4769 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4770 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4771 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4772 info.func = __cvmx_error_display;
4773 info.user_info = (long)
4774 "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
4775 fail |= cvmx_error_add(&info);
4777 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4778 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
4779 info.status_mask = 1ull<<3 /* txfifu */;
4780 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
4781 info.enable_mask = 1ull<<3 /* txfifu_en */;
4783 info.group = CVMX_ERROR_GROUP_ETHERNET;
4784 info.group_index = 0;
4785 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4786 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4787 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4788 info.func = __cvmx_error_display;
4789 info.user_info = (long)
4790 "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
4792 fail |= cvmx_error_add(&info);
4794 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4795 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
4796 info.status_mask = 1ull<<4 /* txfifo */;
4797 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
4798 info.enable_mask = 1ull<<4 /* txfifo_en */;
4800 info.group = CVMX_ERROR_GROUP_ETHERNET;
4801 info.group_index = 0;
4802 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4803 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4804 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4805 info.func = __cvmx_error_display;
4806 info.user_info = (long)
4807 "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
4809 fail |= cvmx_error_add(&info);
4811 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4812 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
4813 info.status_mask = 1ull<<5 /* txbad */;
4814 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
4815 info.enable_mask = 1ull<<5 /* txbad_en */;
4817 info.group = CVMX_ERROR_GROUP_ETHERNET;
4818 info.group_index = 0;
4819 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4820 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4821 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4822 info.func = __cvmx_error_display;
4823 info.user_info = (long)
4824 "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
4825 " state. Should never be set during normal operation\n";
4826 fail |= cvmx_error_add(&info);
4828 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4829 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
4830 info.status_mask = 1ull<<7 /* rxbad */;
4831 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
4832 info.enable_mask = 1ull<<7 /* rxbad_en */;
4834 info.group = CVMX_ERROR_GROUP_ETHERNET;
4835 info.group_index = 0;
4836 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4837 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4838 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4839 info.func = __cvmx_error_display;
4840 info.user_info = (long)
4841 "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
4842 " state. Should never be set during normal operation\n";
4843 fail |= cvmx_error_add(&info);
4845 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4846 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
4847 info.status_mask = 1ull<<8 /* rxlock */;
4848 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
4849 info.enable_mask = 1ull<<8 /* rxlock_en */;
4851 info.group = CVMX_ERROR_GROUP_ETHERNET;
4852 info.group_index = 0;
4853 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4854 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4855 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4856 info.func = __cvmx_error_display;
4857 info.user_info = (long)
4858 "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
4860 " Cannot fire in loopback1 mode\n";
4861 fail |= cvmx_error_add(&info);
4863 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4864 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
4865 info.status_mask = 1ull<<9 /* an_bad */;
4866 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
4867 info.enable_mask = 1ull<<9 /* an_bad_en */;
4869 info.group = CVMX_ERROR_GROUP_ETHERNET;
4870 info.group_index = 0;
4871 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4872 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4873 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4874 info.func = __cvmx_error_display;
4875 info.user_info = (long)
4876 "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
4877 " state. Should never be set during normal operation\n";
4878 fail |= cvmx_error_add(&info);
4880 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4881 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
4882 info.status_mask = 1ull<<10 /* sync_bad */;
4883 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
4884 info.enable_mask = 1ull<<10 /* sync_bad_en */;
4886 info.group = CVMX_ERROR_GROUP_ETHERNET;
4887 info.group_index = 0;
4888 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4889 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4890 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4891 info.func = __cvmx_error_display;
4892 info.user_info = (long)
4893 "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
4894 " state. Should never be set during normal operation\n";
4895 fail |= cvmx_error_add(&info);
4897 /* CVMX_PCSX_INTX_REG(1,0) */
4898 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4899 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
4900 info.status_mask = 1ull<<2 /* an_err */;
4901 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
4902 info.enable_mask = 1ull<<2 /* an_err_en */;
4904 info.group = CVMX_ERROR_GROUP_ETHERNET;
4905 info.group_index = 1;
4906 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4907 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4908 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4909 info.func = __cvmx_error_display;
4910 info.user_info = (long)
4911 "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
4912 fail |= cvmx_error_add(&info);
4914 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4915 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
4916 info.status_mask = 1ull<<3 /* txfifu */;
4917 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
4918 info.enable_mask = 1ull<<3 /* txfifu_en */;
4920 info.group = CVMX_ERROR_GROUP_ETHERNET;
4921 info.group_index = 1;
4922 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4923 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4924 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4925 info.func = __cvmx_error_display;
4926 info.user_info = (long)
4927 "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
4929 fail |= cvmx_error_add(&info);
4931 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4932 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
4933 info.status_mask = 1ull<<4 /* txfifo */;
4934 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
4935 info.enable_mask = 1ull<<4 /* txfifo_en */;
4937 info.group = CVMX_ERROR_GROUP_ETHERNET;
4938 info.group_index = 1;
4939 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4940 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4941 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4942 info.func = __cvmx_error_display;
4943 info.user_info = (long)
4944 "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
4946 fail |= cvmx_error_add(&info);
4948 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4949 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
4950 info.status_mask = 1ull<<5 /* txbad */;
4951 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
4952 info.enable_mask = 1ull<<5 /* txbad_en */;
4954 info.group = CVMX_ERROR_GROUP_ETHERNET;
4955 info.group_index = 1;
4956 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4957 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4958 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4959 info.func = __cvmx_error_display;
4960 info.user_info = (long)
4961 "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
4962 " state. Should never be set during normal operation\n";
4963 fail |= cvmx_error_add(&info);
4965 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4966 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
4967 info.status_mask = 1ull<<7 /* rxbad */;
4968 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
4969 info.enable_mask = 1ull<<7 /* rxbad_en */;
4971 info.group = CVMX_ERROR_GROUP_ETHERNET;
4972 info.group_index = 1;
4973 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4974 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4975 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4976 info.func = __cvmx_error_display;
4977 info.user_info = (long)
4978 "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
4979 " state. Should never be set during normal operation\n";
4980 fail |= cvmx_error_add(&info);
4982 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4983 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
4984 info.status_mask = 1ull<<8 /* rxlock */;
4985 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
4986 info.enable_mask = 1ull<<8 /* rxlock_en */;
4988 info.group = CVMX_ERROR_GROUP_ETHERNET;
4989 info.group_index = 1;
4990 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4991 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
4992 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
4993 info.func = __cvmx_error_display;
4994 info.user_info = (long)
4995 "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
4997 " Cannot fire in loopback1 mode\n";
4998 fail |= cvmx_error_add(&info);
5000 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5001 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
5002 info.status_mask = 1ull<<9 /* an_bad */;
5003 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
5004 info.enable_mask = 1ull<<9 /* an_bad_en */;
5006 info.group = CVMX_ERROR_GROUP_ETHERNET;
5007 info.group_index = 1;
5008 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5009 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5010 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5011 info.func = __cvmx_error_display;
5012 info.user_info = (long)
5013 "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5014 " state. Should never be set during normal operation\n";
5015 fail |= cvmx_error_add(&info);
5017 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5018 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
5019 info.status_mask = 1ull<<10 /* sync_bad */;
5020 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
5021 info.enable_mask = 1ull<<10 /* sync_bad_en */;
5023 info.group = CVMX_ERROR_GROUP_ETHERNET;
5024 info.group_index = 1;
5025 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5026 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5027 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5028 info.func = __cvmx_error_display;
5029 info.user_info = (long)
5030 "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5031 " state. Should never be set during normal operation\n";
5032 fail |= cvmx_error_add(&info);
5034 /* CVMX_PCSX_INTX_REG(2,0) */
5035 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5036 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5037 info.status_mask = 1ull<<2 /* an_err */;
5038 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5039 info.enable_mask = 1ull<<2 /* an_err_en */;
5041 info.group = CVMX_ERROR_GROUP_ETHERNET;
5042 info.group_index = 2;
5043 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5044 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5045 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5046 info.func = __cvmx_error_display;
5047 info.user_info = (long)
5048 "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
5049 fail |= cvmx_error_add(&info);
5051 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5052 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5053 info.status_mask = 1ull<<3 /* txfifu */;
5054 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5055 info.enable_mask = 1ull<<3 /* txfifu_en */;
5057 info.group = CVMX_ERROR_GROUP_ETHERNET;
5058 info.group_index = 2;
5059 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5060 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5061 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5062 info.func = __cvmx_error_display;
5063 info.user_info = (long)
5064 "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5066 fail |= cvmx_error_add(&info);
5068 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5069 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5070 info.status_mask = 1ull<<4 /* txfifo */;
5071 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5072 info.enable_mask = 1ull<<4 /* txfifo_en */;
5074 info.group = CVMX_ERROR_GROUP_ETHERNET;
5075 info.group_index = 2;
5076 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5077 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5078 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5079 info.func = __cvmx_error_display;
5080 info.user_info = (long)
5081 "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5083 fail |= cvmx_error_add(&info);
5085 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5086 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5087 info.status_mask = 1ull<<5 /* txbad */;
5088 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5089 info.enable_mask = 1ull<<5 /* txbad_en */;
5091 info.group = CVMX_ERROR_GROUP_ETHERNET;
5092 info.group_index = 2;
5093 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5094 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5095 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5096 info.func = __cvmx_error_display;
5097 info.user_info = (long)
5098 "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5099 " state. Should never be set during normal operation\n";
5100 fail |= cvmx_error_add(&info);
5102 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5103 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5104 info.status_mask = 1ull<<7 /* rxbad */;
5105 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5106 info.enable_mask = 1ull<<7 /* rxbad_en */;
5108 info.group = CVMX_ERROR_GROUP_ETHERNET;
5109 info.group_index = 2;
5110 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5111 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5112 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5113 info.func = __cvmx_error_display;
5114 info.user_info = (long)
5115 "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
5116 " state. Should never be set during normal operation\n";
5117 fail |= cvmx_error_add(&info);
5119 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5120 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5121 info.status_mask = 1ull<<8 /* rxlock */;
5122 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5123 info.enable_mask = 1ull<<8 /* rxlock_en */;
5125 info.group = CVMX_ERROR_GROUP_ETHERNET;
5126 info.group_index = 2;
5127 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5128 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5129 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5130 info.func = __cvmx_error_display;
5131 info.user_info = (long)
5132 "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5134 " Cannot fire in loopback1 mode\n";
5135 fail |= cvmx_error_add(&info);
5137 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5138 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5139 info.status_mask = 1ull<<9 /* an_bad */;
5140 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5141 info.enable_mask = 1ull<<9 /* an_bad_en */;
5143 info.group = CVMX_ERROR_GROUP_ETHERNET;
5144 info.group_index = 2;
5145 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5146 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5147 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5148 info.func = __cvmx_error_display;
5149 info.user_info = (long)
5150 "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5151 " state. Should never be set during normal operation\n";
5152 fail |= cvmx_error_add(&info);
5154 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5155 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
5156 info.status_mask = 1ull<<10 /* sync_bad */;
5157 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
5158 info.enable_mask = 1ull<<10 /* sync_bad_en */;
5160 info.group = CVMX_ERROR_GROUP_ETHERNET;
5161 info.group_index = 2;
5162 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5163 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5164 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5165 info.func = __cvmx_error_display;
5166 info.user_info = (long)
5167 "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5168 " state. Should never be set during normal operation\n";
5169 fail |= cvmx_error_add(&info);
5171 /* CVMX_PCSX_INTX_REG(3,0) */
5172 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5173 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5174 info.status_mask = 1ull<<2 /* an_err */;
5175 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5176 info.enable_mask = 1ull<<2 /* an_err_en */;
5178 info.group = CVMX_ERROR_GROUP_ETHERNET;
5179 info.group_index = 3;
5180 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5181 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5182 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5183 info.func = __cvmx_error_display;
5184 info.user_info = (long)
5185 "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
5186 fail |= cvmx_error_add(&info);
5188 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5189 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5190 info.status_mask = 1ull<<3 /* txfifu */;
5191 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5192 info.enable_mask = 1ull<<3 /* txfifu_en */;
5194 info.group = CVMX_ERROR_GROUP_ETHERNET;
5195 info.group_index = 3;
5196 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5197 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5198 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5199 info.func = __cvmx_error_display;
5200 info.user_info = (long)
5201 "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
5203 fail |= cvmx_error_add(&info);
5205 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5206 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5207 info.status_mask = 1ull<<4 /* txfifo */;
5208 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5209 info.enable_mask = 1ull<<4 /* txfifo_en */;
5211 info.group = CVMX_ERROR_GROUP_ETHERNET;
5212 info.group_index = 3;
5213 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5214 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5215 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5216 info.func = __cvmx_error_display;
5217 info.user_info = (long)
5218 "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
5220 fail |= cvmx_error_add(&info);
5222 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5223 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5224 info.status_mask = 1ull<<5 /* txbad */;
5225 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5226 info.enable_mask = 1ull<<5 /* txbad_en */;
5228 info.group = CVMX_ERROR_GROUP_ETHERNET;
5229 info.group_index = 3;
5230 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5231 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5232 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5233 info.func = __cvmx_error_display;
5234 info.user_info = (long)
5235 "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
5236 " state. Should never be set during normal operation\n";
5237 fail |= cvmx_error_add(&info);
5239 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5240 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5241 info.status_mask = 1ull<<7 /* rxbad */;
5242 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5243 info.enable_mask = 1ull<<7 /* rxbad_en */;
5245 info.group = CVMX_ERROR_GROUP_ETHERNET;
5246 info.group_index = 3;
5247 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5248 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5249 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5250 info.func = __cvmx_error_display;
5251 info.user_info = (long)
5252 "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
5253 " state. Should never be set during normal operation\n";
5254 fail |= cvmx_error_add(&info);
5256 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5257 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5258 info.status_mask = 1ull<<8 /* rxlock */;
5259 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5260 info.enable_mask = 1ull<<8 /* rxlock_en */;
5262 info.group = CVMX_ERROR_GROUP_ETHERNET;
5263 info.group_index = 3;
5264 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5265 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5266 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5267 info.func = __cvmx_error_display;
5268 info.user_info = (long)
5269 "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
5271 " Cannot fire in loopback1 mode\n";
5272 fail |= cvmx_error_add(&info);
5274 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5275 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5276 info.status_mask = 1ull<<9 /* an_bad */;
5277 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5278 info.enable_mask = 1ull<<9 /* an_bad_en */;
5280 info.group = CVMX_ERROR_GROUP_ETHERNET;
5281 info.group_index = 3;
5282 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5283 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5284 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5285 info.func = __cvmx_error_display;
5286 info.user_info = (long)
5287 "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
5288 " state. Should never be set during normal operation\n";
5289 fail |= cvmx_error_add(&info);
5291 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5292 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
5293 info.status_mask = 1ull<<10 /* sync_bad */;
5294 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
5295 info.enable_mask = 1ull<<10 /* sync_bad_en */;
5297 info.group = CVMX_ERROR_GROUP_ETHERNET;
5298 info.group_index = 3;
5299 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5300 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5301 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5302 info.func = __cvmx_error_display;
5303 info.user_info = (long)
5304 "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
5305 " state. Should never be set during normal operation\n";
5306 fail |= cvmx_error_add(&info);
5308 /* CVMX_PCSXX_INT_REG(0) */
5309 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5310 info.status_addr = CVMX_PCSXX_INT_REG(0);
5311 info.status_mask = 1ull<<0 /* txflt */;
5312 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
5313 info.enable_mask = 1ull<<0 /* txflt_en */;
5315 info.group = CVMX_ERROR_GROUP_ETHERNET;
5316 info.group_index = 0;
5317 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5318 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5319 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5320 info.func = __cvmx_error_display;
5321 info.user_info = (long)
5322 "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
5323 fail |= cvmx_error_add(&info);
5325 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5326 info.status_addr = CVMX_PCSXX_INT_REG(0);
5327 info.status_mask = 1ull<<1 /* rxbad */;
5328 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
5329 info.enable_mask = 1ull<<1 /* rxbad_en */;
5331 info.group = CVMX_ERROR_GROUP_ETHERNET;
5332 info.group_index = 0;
5333 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5334 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5335 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5336 info.func = __cvmx_error_display;
5337 info.user_info = (long)
5338 "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
5339 fail |= cvmx_error_add(&info);
5341 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5342 info.status_addr = CVMX_PCSXX_INT_REG(0);
5343 info.status_mask = 1ull<<2 /* rxsynbad */;
5344 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
5345 info.enable_mask = 1ull<<2 /* rxsynbad_en */;
5347 info.group = CVMX_ERROR_GROUP_ETHERNET;
5348 info.group_index = 0;
5349 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5350 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5351 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5352 info.func = __cvmx_error_display;
5353 info.user_info = (long)
5354 "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
5355 " in one of the 4 xaui lanes\n";
5356 fail |= cvmx_error_add(&info);
5358 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5359 info.status_addr = CVMX_PCSXX_INT_REG(0);
5360 info.status_mask = 1ull<<4 /* synlos */;
5361 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
5362 info.enable_mask = 1ull<<4 /* synlos_en */;
5364 info.group = CVMX_ERROR_GROUP_ETHERNET;
5365 info.group_index = 0;
5366 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5367 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5368 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5369 info.func = __cvmx_error_display;
5370 info.user_info = (long)
5371 "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
5372 fail |= cvmx_error_add(&info);
5374 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5375 info.status_addr = CVMX_PCSXX_INT_REG(0);
5376 info.status_mask = 1ull<<5 /* algnlos */;
5377 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
5378 info.enable_mask = 1ull<<5 /* algnlos_en */;
5380 info.group = CVMX_ERROR_GROUP_ETHERNET;
5381 info.group_index = 0;
5382 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5383 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5384 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
5385 info.func = __cvmx_error_display;
5386 info.user_info = (long)
5387 "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
5388 fail |= cvmx_error_add(&info);
5390 /* CVMX_PIP_INT_REG */
5391 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5392 info.status_addr = CVMX_PIP_INT_REG;
5393 info.status_mask = 1ull<<3 /* prtnxa */;
5394 info.enable_addr = CVMX_PIP_INT_EN;
5395 info.enable_mask = 1ull<<3 /* prtnxa */;
5397 info.group = CVMX_ERROR_GROUP_INTERNAL;
5398 info.group_index = 0;
5399 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5400 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5401 info.parent.status_mask = 1ull<<20 /* pip */;
5402 info.func = __cvmx_error_display;
5403 info.user_info = (long)
5404 "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
5405 fail |= cvmx_error_add(&info);
5407 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5408 info.status_addr = CVMX_PIP_INT_REG;
5409 info.status_mask = 1ull<<4 /* badtag */;
5410 info.enable_addr = CVMX_PIP_INT_EN;
5411 info.enable_mask = 1ull<<4 /* badtag */;
5413 info.group = CVMX_ERROR_GROUP_INTERNAL;
5414 info.group_index = 0;
5415 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5416 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5417 info.parent.status_mask = 1ull<<20 /* pip */;
5418 info.func = __cvmx_error_display;
5419 info.user_info = (long)
5420 "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
5421 fail |= cvmx_error_add(&info);
5423 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5424 info.status_addr = CVMX_PIP_INT_REG;
5425 info.status_mask = 1ull<<5 /* skprunt */;
5426 info.enable_addr = CVMX_PIP_INT_EN;
5427 info.enable_mask = 1ull<<5 /* skprunt */;
5429 info.group = CVMX_ERROR_GROUP_INTERNAL;
5430 info.group_index = 0;
5431 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5432 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5433 info.parent.status_mask = 1ull<<20 /* pip */;
5434 info.func = __cvmx_error_display;
5435 info.user_info = (long)
5436 "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
5437 " This interrupt can occur with received PARTIAL\n"
5438 " packets that are truncated to SKIP bytes or\n"
5440 fail |= cvmx_error_add(&info);
5442 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5443 info.status_addr = CVMX_PIP_INT_REG;
5444 info.status_mask = 1ull<<6 /* todoovr */;
5445 info.enable_addr = CVMX_PIP_INT_EN;
5446 info.enable_mask = 1ull<<6 /* todoovr */;
5448 info.group = CVMX_ERROR_GROUP_INTERNAL;
5449 info.group_index = 0;
5450 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5451 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5452 info.parent.status_mask = 1ull<<20 /* pip */;
5453 info.func = __cvmx_error_display;
5454 info.user_info = (long)
5455 "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n";
5456 fail |= cvmx_error_add(&info);
5458 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5459 info.status_addr = CVMX_PIP_INT_REG;
5460 info.status_mask = 1ull<<7 /* feperr */;
5461 info.enable_addr = CVMX_PIP_INT_EN;
5462 info.enable_mask = 1ull<<7 /* feperr */;
5464 info.group = CVMX_ERROR_GROUP_INTERNAL;
5465 info.group_index = 0;
5466 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5467 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5468 info.parent.status_mask = 1ull<<20 /* pip */;
5469 info.func = __cvmx_error_display;
5470 info.user_info = (long)
5471 "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
5472 fail |= cvmx_error_add(&info);
5474 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5475 info.status_addr = CVMX_PIP_INT_REG;
5476 info.status_mask = 1ull<<8 /* beperr */;
5477 info.enable_addr = CVMX_PIP_INT_EN;
5478 info.enable_mask = 1ull<<8 /* beperr */;
5480 info.group = CVMX_ERROR_GROUP_INTERNAL;
5481 info.group_index = 0;
5482 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5483 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5484 info.parent.status_mask = 1ull<<20 /* pip */;
5485 info.func = __cvmx_error_display;
5486 info.user_info = (long)
5487 "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
5488 fail |= cvmx_error_add(&info);
5490 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5491 info.status_addr = CVMX_PIP_INT_REG;
5492 info.status_mask = 1ull<<12 /* punyerr */;
5493 info.enable_addr = CVMX_PIP_INT_EN;
5494 info.enable_mask = 1ull<<12 /* punyerr */;
5496 info.group = CVMX_ERROR_GROUP_INTERNAL;
5497 info.group_index = 0;
5498 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5499 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5500 info.parent.status_mask = 1ull<<20 /* pip */;
5501 info.func = __cvmx_error_display;
5502 info.user_info = (long)
5503 "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
5504 " stripping in IPD is enable\n";
5505 fail |= cvmx_error_add(&info);
5507 /* CVMX_FPA_INT_SUM */
5508 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5509 info.status_addr = CVMX_FPA_INT_SUM;
5510 info.status_mask = 1ull<<0 /* fed0_sbe */;
5511 info.enable_addr = CVMX_FPA_INT_ENB;
5512 info.enable_mask = 1ull<<0 /* fed0_sbe */;
5514 info.group = CVMX_ERROR_GROUP_INTERNAL;
5515 info.group_index = 0;
5516 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5517 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5518 info.parent.status_mask = 1ull<<5 /* fpa */;
5519 info.func = __cvmx_error_display;
5520 info.user_info = (long)
5521 "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
5522 fail |= cvmx_error_add(&info);
5524 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5525 info.status_addr = CVMX_FPA_INT_SUM;
5526 info.status_mask = 1ull<<1 /* fed0_dbe */;
5527 info.enable_addr = CVMX_FPA_INT_ENB;
5528 info.enable_mask = 1ull<<1 /* fed0_dbe */;
5530 info.group = CVMX_ERROR_GROUP_INTERNAL;
5531 info.group_index = 0;
5532 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5533 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5534 info.parent.status_mask = 1ull<<5 /* fpa */;
5535 info.func = __cvmx_error_display;
5536 info.user_info = (long)
5537 "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
5538 fail |= cvmx_error_add(&info);
5540 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5541 info.status_addr = CVMX_FPA_INT_SUM;
5542 info.status_mask = 1ull<<2 /* fed1_sbe */;
5543 info.enable_addr = CVMX_FPA_INT_ENB;
5544 info.enable_mask = 1ull<<2 /* fed1_sbe */;
5546 info.group = CVMX_ERROR_GROUP_INTERNAL;
5547 info.group_index = 0;
5548 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5549 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5550 info.parent.status_mask = 1ull<<5 /* fpa */;
5551 info.func = __cvmx_error_display;
5552 info.user_info = (long)
5553 "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
5554 fail |= cvmx_error_add(&info);
5556 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5557 info.status_addr = CVMX_FPA_INT_SUM;
5558 info.status_mask = 1ull<<3 /* fed1_dbe */;
5559 info.enable_addr = CVMX_FPA_INT_ENB;
5560 info.enable_mask = 1ull<<3 /* fed1_dbe */;
5562 info.group = CVMX_ERROR_GROUP_INTERNAL;
5563 info.group_index = 0;
5564 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5565 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5566 info.parent.status_mask = 1ull<<5 /* fpa */;
5567 info.func = __cvmx_error_display;
5568 info.user_info = (long)
5569 "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
5570 fail |= cvmx_error_add(&info);
5572 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5573 info.status_addr = CVMX_FPA_INT_SUM;
5574 info.status_mask = 1ull<<4 /* q0_und */;
5575 info.enable_addr = CVMX_FPA_INT_ENB;
5576 info.enable_mask = 1ull<<4 /* q0_und */;
5578 info.group = CVMX_ERROR_GROUP_INTERNAL;
5579 info.group_index = 0;
5580 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5581 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5582 info.parent.status_mask = 1ull<<5 /* fpa */;
5583 info.func = __cvmx_error_display;
5584 info.user_info = (long)
5585 "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
5587 fail |= cvmx_error_add(&info);
5589 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5590 info.status_addr = CVMX_FPA_INT_SUM;
5591 info.status_mask = 1ull<<5 /* q0_coff */;
5592 info.enable_addr = CVMX_FPA_INT_ENB;
5593 info.enable_mask = 1ull<<5 /* q0_coff */;
5595 info.group = CVMX_ERROR_GROUP_INTERNAL;
5596 info.group_index = 0;
5597 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5598 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5599 info.parent.status_mask = 1ull<<5 /* fpa */;
5600 info.func = __cvmx_error_display;
5601 info.user_info = (long)
5602 "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
5603 " the count available is greater than pointers\n"
5604 " present in the FPA.\n";
5605 fail |= cvmx_error_add(&info);
5607 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5608 info.status_addr = CVMX_FPA_INT_SUM;
5609 info.status_mask = 1ull<<6 /* q0_perr */;
5610 info.enable_addr = CVMX_FPA_INT_ENB;
5611 info.enable_mask = 1ull<<6 /* q0_perr */;
5613 info.group = CVMX_ERROR_GROUP_INTERNAL;
5614 info.group_index = 0;
5615 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5616 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5617 info.parent.status_mask = 1ull<<5 /* fpa */;
5618 info.func = __cvmx_error_display;
5619 info.user_info = (long)
5620 "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
5621 " the L2C does not have the FPA owner ship bit set.\n";
5622 fail |= cvmx_error_add(&info);
5624 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5625 info.status_addr = CVMX_FPA_INT_SUM;
5626 info.status_mask = 1ull<<7 /* q1_und */;
5627 info.enable_addr = CVMX_FPA_INT_ENB;
5628 info.enable_mask = 1ull<<7 /* q1_und */;
5630 info.group = CVMX_ERROR_GROUP_INTERNAL;
5631 info.group_index = 0;
5632 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5633 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5634 info.parent.status_mask = 1ull<<5 /* fpa */;
5635 info.func = __cvmx_error_display;
5636 info.user_info = (long)
5637 "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
5639 fail |= cvmx_error_add(&info);
5641 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5642 info.status_addr = CVMX_FPA_INT_SUM;
5643 info.status_mask = 1ull<<8 /* q1_coff */;
5644 info.enable_addr = CVMX_FPA_INT_ENB;
5645 info.enable_mask = 1ull<<8 /* q1_coff */;
5647 info.group = CVMX_ERROR_GROUP_INTERNAL;
5648 info.group_index = 0;
5649 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5650 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5651 info.parent.status_mask = 1ull<<5 /* fpa */;
5652 info.func = __cvmx_error_display;
5653 info.user_info = (long)
5654 "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
5655 " the count available is greater than pointers\n"
5656 " present in the FPA.\n";
5657 fail |= cvmx_error_add(&info);
5659 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5660 info.status_addr = CVMX_FPA_INT_SUM;
5661 info.status_mask = 1ull<<9 /* q1_perr */;
5662 info.enable_addr = CVMX_FPA_INT_ENB;
5663 info.enable_mask = 1ull<<9 /* q1_perr */;
5665 info.group = CVMX_ERROR_GROUP_INTERNAL;
5666 info.group_index = 0;
5667 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5668 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5669 info.parent.status_mask = 1ull<<5 /* fpa */;
5670 info.func = __cvmx_error_display;
5671 info.user_info = (long)
5672 "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
5673 " the L2C does not have the FPA owner ship bit set.\n";
5674 fail |= cvmx_error_add(&info);
5676 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5677 info.status_addr = CVMX_FPA_INT_SUM;
5678 info.status_mask = 1ull<<10 /* q2_und */;
5679 info.enable_addr = CVMX_FPA_INT_ENB;
5680 info.enable_mask = 1ull<<10 /* q2_und */;
5682 info.group = CVMX_ERROR_GROUP_INTERNAL;
5683 info.group_index = 0;
5684 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5685 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5686 info.parent.status_mask = 1ull<<5 /* fpa */;
5687 info.func = __cvmx_error_display;
5688 info.user_info = (long)
5689 "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
5691 fail |= cvmx_error_add(&info);
5693 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5694 info.status_addr = CVMX_FPA_INT_SUM;
5695 info.status_mask = 1ull<<11 /* q2_coff */;
5696 info.enable_addr = CVMX_FPA_INT_ENB;
5697 info.enable_mask = 1ull<<11 /* q2_coff */;
5699 info.group = CVMX_ERROR_GROUP_INTERNAL;
5700 info.group_index = 0;
5701 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5702 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5703 info.parent.status_mask = 1ull<<5 /* fpa */;
5704 info.func = __cvmx_error_display;
5705 info.user_info = (long)
5706 "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
5707 " the count available is greater than than pointers\n"
5708 " present in the FPA.\n";
5709 fail |= cvmx_error_add(&info);
5711 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5712 info.status_addr = CVMX_FPA_INT_SUM;
5713 info.status_mask = 1ull<<12 /* q2_perr */;
5714 info.enable_addr = CVMX_FPA_INT_ENB;
5715 info.enable_mask = 1ull<<12 /* q2_perr */;
5717 info.group = CVMX_ERROR_GROUP_INTERNAL;
5718 info.group_index = 0;
5719 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5720 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5721 info.parent.status_mask = 1ull<<5 /* fpa */;
5722 info.func = __cvmx_error_display;
5723 info.user_info = (long)
5724 "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
5725 " the L2C does not have the FPA owner ship bit set.\n";
5726 fail |= cvmx_error_add(&info);
5728 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5729 info.status_addr = CVMX_FPA_INT_SUM;
5730 info.status_mask = 1ull<<13 /* q3_und */;
5731 info.enable_addr = CVMX_FPA_INT_ENB;
5732 info.enable_mask = 1ull<<13 /* q3_und */;
5734 info.group = CVMX_ERROR_GROUP_INTERNAL;
5735 info.group_index = 0;
5736 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5737 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5738 info.parent.status_mask = 1ull<<5 /* fpa */;
5739 info.func = __cvmx_error_display;
5740 info.user_info = (long)
5741 "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
5743 fail |= cvmx_error_add(&info);
5745 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5746 info.status_addr = CVMX_FPA_INT_SUM;
5747 info.status_mask = 1ull<<14 /* q3_coff */;
5748 info.enable_addr = CVMX_FPA_INT_ENB;
5749 info.enable_mask = 1ull<<14 /* q3_coff */;
5751 info.group = CVMX_ERROR_GROUP_INTERNAL;
5752 info.group_index = 0;
5753 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5754 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5755 info.parent.status_mask = 1ull<<5 /* fpa */;
5756 info.func = __cvmx_error_display;
5757 info.user_info = (long)
5758 "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
5759 " the count available is greater than than pointers\n"
5760 " present in the FPA.\n";
5761 fail |= cvmx_error_add(&info);
5763 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5764 info.status_addr = CVMX_FPA_INT_SUM;
5765 info.status_mask = 1ull<<15 /* q3_perr */;
5766 info.enable_addr = CVMX_FPA_INT_ENB;
5767 info.enable_mask = 1ull<<15 /* q3_perr */;
5769 info.group = CVMX_ERROR_GROUP_INTERNAL;
5770 info.group_index = 0;
5771 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5772 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5773 info.parent.status_mask = 1ull<<5 /* fpa */;
5774 info.func = __cvmx_error_display;
5775 info.user_info = (long)
5776 "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
5777 " the L2C does not have the FPA owner ship bit set.\n";
5778 fail |= cvmx_error_add(&info);
5780 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5781 info.status_addr = CVMX_FPA_INT_SUM;
5782 info.status_mask = 1ull<<16 /* q4_und */;
5783 info.enable_addr = CVMX_FPA_INT_ENB;
5784 info.enable_mask = 1ull<<16 /* q4_und */;
5786 info.group = CVMX_ERROR_GROUP_INTERNAL;
5787 info.group_index = 0;
5788 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5789 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5790 info.parent.status_mask = 1ull<<5 /* fpa */;
5791 info.func = __cvmx_error_display;
5792 info.user_info = (long)
5793 "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
5795 fail |= cvmx_error_add(&info);
5797 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5798 info.status_addr = CVMX_FPA_INT_SUM;
5799 info.status_mask = 1ull<<17 /* q4_coff */;
5800 info.enable_addr = CVMX_FPA_INT_ENB;
5801 info.enable_mask = 1ull<<17 /* q4_coff */;
5803 info.group = CVMX_ERROR_GROUP_INTERNAL;
5804 info.group_index = 0;
5805 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5806 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5807 info.parent.status_mask = 1ull<<5 /* fpa */;
5808 info.func = __cvmx_error_display;
5809 info.user_info = (long)
5810 "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
5811 " the count available is greater than than pointers\n"
5812 " present in the FPA.\n";
5813 fail |= cvmx_error_add(&info);
5815 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5816 info.status_addr = CVMX_FPA_INT_SUM;
5817 info.status_mask = 1ull<<18 /* q4_perr */;
5818 info.enable_addr = CVMX_FPA_INT_ENB;
5819 info.enable_mask = 1ull<<18 /* q4_perr */;
5821 info.group = CVMX_ERROR_GROUP_INTERNAL;
5822 info.group_index = 0;
5823 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5824 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5825 info.parent.status_mask = 1ull<<5 /* fpa */;
5826 info.func = __cvmx_error_display;
5827 info.user_info = (long)
5828 "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
5829 " the L2C does not have the FPA owner ship bit set.\n";
5830 fail |= cvmx_error_add(&info);
5832 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5833 info.status_addr = CVMX_FPA_INT_SUM;
5834 info.status_mask = 1ull<<19 /* q5_und */;
5835 info.enable_addr = CVMX_FPA_INT_ENB;
5836 info.enable_mask = 1ull<<19 /* q5_und */;
5838 info.group = CVMX_ERROR_GROUP_INTERNAL;
5839 info.group_index = 0;
5840 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5841 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5842 info.parent.status_mask = 1ull<<5 /* fpa */;
5843 info.func = __cvmx_error_display;
5844 info.user_info = (long)
5845 "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
5847 fail |= cvmx_error_add(&info);
5849 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5850 info.status_addr = CVMX_FPA_INT_SUM;
5851 info.status_mask = 1ull<<20 /* q5_coff */;
5852 info.enable_addr = CVMX_FPA_INT_ENB;
5853 info.enable_mask = 1ull<<20 /* q5_coff */;
5855 info.group = CVMX_ERROR_GROUP_INTERNAL;
5856 info.group_index = 0;
5857 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5858 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5859 info.parent.status_mask = 1ull<<5 /* fpa */;
5860 info.func = __cvmx_error_display;
5861 info.user_info = (long)
5862 "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
5863 " the count available is greater than than pointers\n"
5864 " present in the FPA.\n";
5865 fail |= cvmx_error_add(&info);
5867 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5868 info.status_addr = CVMX_FPA_INT_SUM;
5869 info.status_mask = 1ull<<21 /* q5_perr */;
5870 info.enable_addr = CVMX_FPA_INT_ENB;
5871 info.enable_mask = 1ull<<21 /* q5_perr */;
5873 info.group = CVMX_ERROR_GROUP_INTERNAL;
5874 info.group_index = 0;
5875 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5876 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5877 info.parent.status_mask = 1ull<<5 /* fpa */;
5878 info.func = __cvmx_error_display;
5879 info.user_info = (long)
5880 "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
5881 " the L2C does not have the FPA owner ship bit set.\n";
5882 fail |= cvmx_error_add(&info);
5884 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5885 info.status_addr = CVMX_FPA_INT_SUM;
5886 info.status_mask = 1ull<<22 /* q6_und */;
5887 info.enable_addr = CVMX_FPA_INT_ENB;
5888 info.enable_mask = 1ull<<22 /* q6_und */;
5890 info.group = CVMX_ERROR_GROUP_INTERNAL;
5891 info.group_index = 0;
5892 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5893 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5894 info.parent.status_mask = 1ull<<5 /* fpa */;
5895 info.func = __cvmx_error_display;
5896 info.user_info = (long)
5897 "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
5899 fail |= cvmx_error_add(&info);
5901 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5902 info.status_addr = CVMX_FPA_INT_SUM;
5903 info.status_mask = 1ull<<23 /* q6_coff */;
5904 info.enable_addr = CVMX_FPA_INT_ENB;
5905 info.enable_mask = 1ull<<23 /* q6_coff */;
5907 info.group = CVMX_ERROR_GROUP_INTERNAL;
5908 info.group_index = 0;
5909 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5910 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5911 info.parent.status_mask = 1ull<<5 /* fpa */;
5912 info.func = __cvmx_error_display;
5913 info.user_info = (long)
5914 "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
5915 " the count available is greater than than pointers\n"
5916 " present in the FPA.\n";
5917 fail |= cvmx_error_add(&info);
5919 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5920 info.status_addr = CVMX_FPA_INT_SUM;
5921 info.status_mask = 1ull<<24 /* q6_perr */;
5922 info.enable_addr = CVMX_FPA_INT_ENB;
5923 info.enable_mask = 1ull<<24 /* q6_perr */;
5925 info.group = CVMX_ERROR_GROUP_INTERNAL;
5926 info.group_index = 0;
5927 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5928 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5929 info.parent.status_mask = 1ull<<5 /* fpa */;
5930 info.func = __cvmx_error_display;
5931 info.user_info = (long)
5932 "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
5933 " the L2C does not have the FPA owner ship bit set.\n";
5934 fail |= cvmx_error_add(&info);
5936 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5937 info.status_addr = CVMX_FPA_INT_SUM;
5938 info.status_mask = 1ull<<25 /* q7_und */;
5939 info.enable_addr = CVMX_FPA_INT_ENB;
5940 info.enable_mask = 1ull<<25 /* q7_und */;
5942 info.group = CVMX_ERROR_GROUP_INTERNAL;
5943 info.group_index = 0;
5944 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5945 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5946 info.parent.status_mask = 1ull<<5 /* fpa */;
5947 info.func = __cvmx_error_display;
5948 info.user_info = (long)
5949 "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
5951 fail |= cvmx_error_add(&info);
5953 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5954 info.status_addr = CVMX_FPA_INT_SUM;
5955 info.status_mask = 1ull<<26 /* q7_coff */;
5956 info.enable_addr = CVMX_FPA_INT_ENB;
5957 info.enable_mask = 1ull<<26 /* q7_coff */;
5959 info.group = CVMX_ERROR_GROUP_INTERNAL;
5960 info.group_index = 0;
5961 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5962 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5963 info.parent.status_mask = 1ull<<5 /* fpa */;
5964 info.func = __cvmx_error_display;
5965 info.user_info = (long)
5966 "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
5967 " the count available is greater than than pointers\n"
5968 " present in the FPA.\n";
5969 fail |= cvmx_error_add(&info);
5971 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5972 info.status_addr = CVMX_FPA_INT_SUM;
5973 info.status_mask = 1ull<<27 /* q7_perr */;
5974 info.enable_addr = CVMX_FPA_INT_ENB;
5975 info.enable_mask = 1ull<<27 /* q7_perr */;
5977 info.group = CVMX_ERROR_GROUP_INTERNAL;
5978 info.group_index = 0;
5979 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5980 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5981 info.parent.status_mask = 1ull<<5 /* fpa */;
5982 info.func = __cvmx_error_display;
5983 info.user_info = (long)
5984 "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
5985 " the L2C does not have the FPA owner ship bit set.\n";
5986 fail |= cvmx_error_add(&info);
5988 /* CVMX_LMCX_MEM_CFG0(0) */
5989 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5990 info.status_addr = CVMX_LMCX_MEM_CFG0(0);
5991 info.status_mask = 0xfull<<21 /* sec_err */;
5992 info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
5993 info.enable_mask = 1ull<<19 /* intr_sec_ena */;
5994 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
5995 info.group = CVMX_ERROR_GROUP_LMC;
5996 info.group_index = 0;
5997 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5998 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
5999 info.parent.status_mask = 1ull<<17 /* lmc0 */;
6000 info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
6001 info.user_info = (long)
6002 "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
6003 " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
6004 " [0] corresponds to DQ[63:0]_c0_p0\n"
6005 " [1] corresponds to DQ[63:0]_c0_p1\n"
6006 " [2] corresponds to DQ[63:0]_c1_p0\n"
6007 " [3] corresponds to DQ[63:0]_c1_p1\n"
6008 " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
6009 " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
6010 " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
6011 " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
6012 " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
6013 " where _cC_pP denotes cycle C and phase P\n"
6014 " Write of 1 will clear the corresponding error bit\n";
6015 fail |= cvmx_error_add(&info);
6017 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6018 info.status_addr = CVMX_LMCX_MEM_CFG0(0);
6019 info.status_mask = 0xfull<<25 /* ded_err */;
6020 info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
6021 info.enable_mask = 1ull<<20 /* intr_ded_ena */;
6023 info.group = CVMX_ERROR_GROUP_LMC;
6024 info.group_index = 0;
6025 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6026 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6027 info.parent.status_mask = 1ull<<17 /* lmc0 */;
6028 info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
6029 info.user_info = (long)
6030 "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
6031 " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
6032 " [0] corresponds to DQ[63:0]_c0_p0\n"
6033 " [1] corresponds to DQ[63:0]_c0_p1\n"
6034 " [2] corresponds to DQ[63:0]_c1_p0\n"
6035 " [3] corresponds to DQ[63:0]_c1_p1\n"
6036 " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
6037 " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
6038 " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
6039 " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
6040 " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
6041 " where _cC_pP denotes cycle C and phase P\n"
6042 " Write of 1 will clear the corresponding error bit\n";
6043 fail |= cvmx_error_add(&info);
6045 /* CVMX_IOB_INT_SUM */
6046 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6047 info.status_addr = CVMX_IOB_INT_SUM;
6048 info.status_mask = 1ull<<0 /* np_sop */;
6049 info.enable_addr = CVMX_IOB_INT_ENB;
6050 info.enable_mask = 1ull<<0 /* np_sop */;
6052 info.group = CVMX_ERROR_GROUP_INTERNAL;
6053 info.group_index = 0;
6054 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6055 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6056 info.parent.status_mask = 1ull<<30 /* iob */;
6057 info.func = __cvmx_error_display;
6058 info.user_info = (long)
6059 "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
6060 " port for a non-passthrough packet.\n"
6061 " The first detected error associated with bits [5:0]\n"
6062 " of this register will only be set here. A new bit\n"
6063 " can be set when the previous reported bit is cleared.\n";
6064 fail |= cvmx_error_add(&info);
6066 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6067 info.status_addr = CVMX_IOB_INT_SUM;
6068 info.status_mask = 1ull<<1 /* np_eop */;
6069 info.enable_addr = CVMX_IOB_INT_ENB;
6070 info.enable_mask = 1ull<<1 /* np_eop */;
6072 info.group = CVMX_ERROR_GROUP_INTERNAL;
6073 info.group_index = 0;
6074 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6075 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6076 info.parent.status_mask = 1ull<<30 /* iob */;
6077 info.func = __cvmx_error_display;
6078 info.user_info = (long)
6079 "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
6080 " port for a non-passthrough packet.\n"
6081 " The first detected error associated with bits [5:0]\n"
6082 " of this register will only be set here. A new bit\n"
6083 " can be set when the previous reported bit is cleared.\n";
6084 fail |= cvmx_error_add(&info);
6086 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6087 info.status_addr = CVMX_IOB_INT_SUM;
6088 info.status_mask = 1ull<<2 /* p_sop */;
6089 info.enable_addr = CVMX_IOB_INT_ENB;
6090 info.enable_mask = 1ull<<2 /* p_sop */;
6092 info.group = CVMX_ERROR_GROUP_INTERNAL;
6093 info.group_index = 0;
6094 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6095 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6096 info.parent.status_mask = 1ull<<30 /* iob */;
6097 info.func = __cvmx_error_display;
6098 info.user_info = (long)
6099 "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
6100 " port for a passthrough packet.\n"
6101 " The first detected error associated with bits [5:0]\n"
6102 " of this register will only be set here. A new bit\n"
6103 " can be set when the previous reported bit is cleared.\n";
6104 fail |= cvmx_error_add(&info);
6106 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6107 info.status_addr = CVMX_IOB_INT_SUM;
6108 info.status_mask = 1ull<<3 /* p_eop */;
6109 info.enable_addr = CVMX_IOB_INT_ENB;
6110 info.enable_mask = 1ull<<3 /* p_eop */;
6112 info.group = CVMX_ERROR_GROUP_INTERNAL;
6113 info.group_index = 0;
6114 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6115 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6116 info.parent.status_mask = 1ull<<30 /* iob */;
6117 info.func = __cvmx_error_display;
6118 info.user_info = (long)
6119 "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
6120 " port for a passthrough packet.\n"
6121 " The first detected error associated with bits [5:0]\n"
6122 " of this register will only be set here. A new bit\n"
6123 " can be set when the previous reported bit is cleared.\n";
6124 fail |= cvmx_error_add(&info);
6126 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6127 info.status_addr = CVMX_IOB_INT_SUM;
6128 info.status_mask = 1ull<<4 /* np_dat */;
6129 info.enable_addr = CVMX_IOB_INT_ENB;
6130 info.enable_mask = 1ull<<4 /* np_dat */;
6132 info.group = CVMX_ERROR_GROUP_INTERNAL;
6133 info.group_index = 0;
6134 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6135 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6136 info.parent.status_mask = 1ull<<30 /* iob */;
6137 info.func = __cvmx_error_display;
6138 info.user_info = (long)
6139 "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
6140 " port for a non-passthrough packet.\n"
6141 " The first detected error associated with bits [5:0]\n"
6142 " of this register will only be set here. A new bit\n"
6143 " can be set when the previous reported bit is cleared.\n";
6144 fail |= cvmx_error_add(&info);
6146 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6147 info.status_addr = CVMX_IOB_INT_SUM;
6148 info.status_mask = 1ull<<5 /* p_dat */;
6149 info.enable_addr = CVMX_IOB_INT_ENB;
6150 info.enable_mask = 1ull<<5 /* p_dat */;
6152 info.group = CVMX_ERROR_GROUP_INTERNAL;
6153 info.group_index = 0;
6154 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6155 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6156 info.parent.status_mask = 1ull<<30 /* iob */;
6157 info.func = __cvmx_error_display;
6158 info.user_info = (long)
6159 "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
6160 " port for a passthrough packet.\n"
6161 " The first detected error associated with bits [5:0]\n"
6162 " of this register will only be set here. A new bit\n"
6163 " can be set when the previous reported bit is cleared.\n";
6164 fail |= cvmx_error_add(&info);
6166 /* CVMX_USBNX_INT_SUM(0) */
6167 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6168 info.status_addr = CVMX_USBNX_INT_SUM(0);
6169 info.status_mask = 1ull<<0 /* pr_po_e */;
6170 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6171 info.enable_mask = 1ull<<0 /* pr_po_e */;
6173 info.group = CVMX_ERROR_GROUP_USB;
6174 info.group_index = 0;
6175 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6176 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6177 info.parent.status_mask = 1ull<<13 /* usb */;
6178 info.func = __cvmx_error_display;
6179 info.user_info = (long)
6180 "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
6181 fail |= cvmx_error_add(&info);
6183 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6184 info.status_addr = CVMX_USBNX_INT_SUM(0);
6185 info.status_mask = 1ull<<1 /* pr_pu_f */;
6186 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6187 info.enable_mask = 1ull<<1 /* pr_pu_f */;
6189 info.group = CVMX_ERROR_GROUP_USB;
6190 info.group_index = 0;
6191 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6192 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6193 info.parent.status_mask = 1ull<<13 /* usb */;
6194 info.func = __cvmx_error_display;
6195 info.user_info = (long)
6196 "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
6197 fail |= cvmx_error_add(&info);
6199 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6200 info.status_addr = CVMX_USBNX_INT_SUM(0);
6201 info.status_mask = 1ull<<2 /* nr_po_e */;
6202 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6203 info.enable_mask = 1ull<<2 /* nr_po_e */;
6205 info.group = CVMX_ERROR_GROUP_USB;
6206 info.group_index = 0;
6207 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6208 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6209 info.parent.status_mask = 1ull<<13 /* usb */;
6210 info.func = __cvmx_error_display;
6211 info.user_info = (long)
6212 "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
6213 fail |= cvmx_error_add(&info);
6215 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6216 info.status_addr = CVMX_USBNX_INT_SUM(0);
6217 info.status_mask = 1ull<<3 /* nr_pu_f */;
6218 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6219 info.enable_mask = 1ull<<3 /* nr_pu_f */;
6221 info.group = CVMX_ERROR_GROUP_USB;
6222 info.group_index = 0;
6223 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6224 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6225 info.parent.status_mask = 1ull<<13 /* usb */;
6226 info.func = __cvmx_error_display;
6227 info.user_info = (long)
6228 "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
6229 fail |= cvmx_error_add(&info);
6231 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6232 info.status_addr = CVMX_USBNX_INT_SUM(0);
6233 info.status_mask = 1ull<<4 /* lr_po_e */;
6234 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6235 info.enable_mask = 1ull<<4 /* lr_po_e */;
6237 info.group = CVMX_ERROR_GROUP_USB;
6238 info.group_index = 0;
6239 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6240 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6241 info.parent.status_mask = 1ull<<13 /* usb */;
6242 info.func = __cvmx_error_display;
6243 info.user_info = (long)
6244 "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
6245 fail |= cvmx_error_add(&info);
6247 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6248 info.status_addr = CVMX_USBNX_INT_SUM(0);
6249 info.status_mask = 1ull<<5 /* lr_pu_f */;
6250 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6251 info.enable_mask = 1ull<<5 /* lr_pu_f */;
6253 info.group = CVMX_ERROR_GROUP_USB;
6254 info.group_index = 0;
6255 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6256 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6257 info.parent.status_mask = 1ull<<13 /* usb */;
6258 info.func = __cvmx_error_display;
6259 info.user_info = (long)
6260 "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
6261 fail |= cvmx_error_add(&info);
6263 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6264 info.status_addr = CVMX_USBNX_INT_SUM(0);
6265 info.status_mask = 1ull<<6 /* pt_po_e */;
6266 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6267 info.enable_mask = 1ull<<6 /* pt_po_e */;
6269 info.group = CVMX_ERROR_GROUP_USB;
6270 info.group_index = 0;
6271 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6272 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6273 info.parent.status_mask = 1ull<<13 /* usb */;
6274 info.func = __cvmx_error_display;
6275 info.user_info = (long)
6276 "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
6277 fail |= cvmx_error_add(&info);
6279 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6280 info.status_addr = CVMX_USBNX_INT_SUM(0);
6281 info.status_mask = 1ull<<7 /* pt_pu_f */;
6282 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6283 info.enable_mask = 1ull<<7 /* pt_pu_f */;
6285 info.group = CVMX_ERROR_GROUP_USB;
6286 info.group_index = 0;
6287 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6288 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6289 info.parent.status_mask = 1ull<<13 /* usb */;
6290 info.func = __cvmx_error_display;
6291 info.user_info = (long)
6292 "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
6293 fail |= cvmx_error_add(&info);
6295 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6296 info.status_addr = CVMX_USBNX_INT_SUM(0);
6297 info.status_mask = 1ull<<8 /* nt_po_e */;
6298 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6299 info.enable_mask = 1ull<<8 /* nt_po_e */;
6301 info.group = CVMX_ERROR_GROUP_USB;
6302 info.group_index = 0;
6303 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6304 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6305 info.parent.status_mask = 1ull<<13 /* usb */;
6306 info.func = __cvmx_error_display;
6307 info.user_info = (long)
6308 "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
6309 fail |= cvmx_error_add(&info);
6311 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6312 info.status_addr = CVMX_USBNX_INT_SUM(0);
6313 info.status_mask = 1ull<<9 /* nt_pu_f */;
6314 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6315 info.enable_mask = 1ull<<9 /* nt_pu_f */;
6317 info.group = CVMX_ERROR_GROUP_USB;
6318 info.group_index = 0;
6319 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6320 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6321 info.parent.status_mask = 1ull<<13 /* usb */;
6322 info.func = __cvmx_error_display;
6323 info.user_info = (long)
6324 "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
6325 fail |= cvmx_error_add(&info);
6327 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6328 info.status_addr = CVMX_USBNX_INT_SUM(0);
6329 info.status_mask = 1ull<<10 /* lt_po_e */;
6330 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6331 info.enable_mask = 1ull<<10 /* lt_po_e */;
6333 info.group = CVMX_ERROR_GROUP_USB;
6334 info.group_index = 0;
6335 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6336 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6337 info.parent.status_mask = 1ull<<13 /* usb */;
6338 info.func = __cvmx_error_display;
6339 info.user_info = (long)
6340 "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
6341 fail |= cvmx_error_add(&info);
6343 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6344 info.status_addr = CVMX_USBNX_INT_SUM(0);
6345 info.status_mask = 1ull<<11 /* lt_pu_f */;
6346 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6347 info.enable_mask = 1ull<<11 /* lt_pu_f */;
6349 info.group = CVMX_ERROR_GROUP_USB;
6350 info.group_index = 0;
6351 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6352 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6353 info.parent.status_mask = 1ull<<13 /* usb */;
6354 info.func = __cvmx_error_display;
6355 info.user_info = (long)
6356 "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
6357 fail |= cvmx_error_add(&info);
6359 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6360 info.status_addr = CVMX_USBNX_INT_SUM(0);
6361 info.status_mask = 1ull<<12 /* dcred_e */;
6362 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6363 info.enable_mask = 1ull<<12 /* dcred_e */;
6365 info.group = CVMX_ERROR_GROUP_USB;
6366 info.group_index = 0;
6367 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6368 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6369 info.parent.status_mask = 1ull<<13 /* usb */;
6370 info.func = __cvmx_error_display;
6371 info.user_info = (long)
6372 "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
6373 fail |= cvmx_error_add(&info);
6375 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6376 info.status_addr = CVMX_USBNX_INT_SUM(0);
6377 info.status_mask = 1ull<<13 /* dcred_f */;
6378 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6379 info.enable_mask = 1ull<<13 /* dcred_f */;
6381 info.group = CVMX_ERROR_GROUP_USB;
6382 info.group_index = 0;
6383 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6384 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6385 info.parent.status_mask = 1ull<<13 /* usb */;
6386 info.func = __cvmx_error_display;
6387 info.user_info = (long)
6388 "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
6389 fail |= cvmx_error_add(&info);
6391 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6392 info.status_addr = CVMX_USBNX_INT_SUM(0);
6393 info.status_mask = 1ull<<14 /* l2c_s_e */;
6394 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6395 info.enable_mask = 1ull<<14 /* l2c_s_e */;
6397 info.group = CVMX_ERROR_GROUP_USB;
6398 info.group_index = 0;
6399 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6400 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6401 info.parent.status_mask = 1ull<<13 /* usb */;
6402 info.func = __cvmx_error_display;
6403 info.user_info = (long)
6404 "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
6405 fail |= cvmx_error_add(&info);
6407 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6408 info.status_addr = CVMX_USBNX_INT_SUM(0);
6409 info.status_mask = 1ull<<15 /* l2c_a_f */;
6410 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6411 info.enable_mask = 1ull<<15 /* l2c_a_f */;
6413 info.group = CVMX_ERROR_GROUP_USB;
6414 info.group_index = 0;
6415 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6416 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6417 info.parent.status_mask = 1ull<<13 /* usb */;
6418 info.func = __cvmx_error_display;
6419 info.user_info = (long)
6420 "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
6421 fail |= cvmx_error_add(&info);
6423 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6424 info.status_addr = CVMX_USBNX_INT_SUM(0);
6425 info.status_mask = 1ull<<16 /* lt_fi_e */;
6426 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6427 info.enable_mask = 1ull<<16 /* l2_fi_e */;
6429 info.group = CVMX_ERROR_GROUP_USB;
6430 info.group_index = 0;
6431 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6432 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6433 info.parent.status_mask = 1ull<<13 /* usb */;
6434 info.func = __cvmx_error_display;
6435 info.user_info = (long)
6436 "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
6437 fail |= cvmx_error_add(&info);
6439 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6440 info.status_addr = CVMX_USBNX_INT_SUM(0);
6441 info.status_mask = 1ull<<17 /* lt_fi_f */;
6442 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6443 info.enable_mask = 1ull<<17 /* l2_fi_f */;
6445 info.group = CVMX_ERROR_GROUP_USB;
6446 info.group_index = 0;
6447 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6448 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6449 info.parent.status_mask = 1ull<<13 /* usb */;
6450 info.func = __cvmx_error_display;
6451 info.user_info = (long)
6452 "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
6453 fail |= cvmx_error_add(&info);
6455 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6456 info.status_addr = CVMX_USBNX_INT_SUM(0);
6457 info.status_mask = 1ull<<18 /* rg_fi_e */;
6458 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6459 info.enable_mask = 1ull<<18 /* rg_fi_e */;
6461 info.group = CVMX_ERROR_GROUP_USB;
6462 info.group_index = 0;
6463 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6464 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6465 info.parent.status_mask = 1ull<<13 /* usb */;
6466 info.func = __cvmx_error_display;
6467 info.user_info = (long)
6468 "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
6469 fail |= cvmx_error_add(&info);
6471 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6472 info.status_addr = CVMX_USBNX_INT_SUM(0);
6473 info.status_mask = 1ull<<19 /* rg_fi_f */;
6474 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6475 info.enable_mask = 1ull<<19 /* rg_fi_f */;
6477 info.group = CVMX_ERROR_GROUP_USB;
6478 info.group_index = 0;
6479 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6480 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6481 info.parent.status_mask = 1ull<<13 /* usb */;
6482 info.func = __cvmx_error_display;
6483 info.user_info = (long)
6484 "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
6485 fail |= cvmx_error_add(&info);
6487 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6488 info.status_addr = CVMX_USBNX_INT_SUM(0);
6489 info.status_mask = 1ull<<20 /* rq_q2_f */;
6490 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6491 info.enable_mask = 1ull<<20 /* rq_q2_f */;
6493 info.group = CVMX_ERROR_GROUP_USB;
6494 info.group_index = 0;
6495 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6496 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6497 info.parent.status_mask = 1ull<<13 /* usb */;
6498 info.func = __cvmx_error_display;
6499 info.user_info = (long)
6500 "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
6501 fail |= cvmx_error_add(&info);
6503 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6504 info.status_addr = CVMX_USBNX_INT_SUM(0);
6505 info.status_mask = 1ull<<21 /* rq_q2_e */;
6506 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6507 info.enable_mask = 1ull<<21 /* rq_q2_e */;
6509 info.group = CVMX_ERROR_GROUP_USB;
6510 info.group_index = 0;
6511 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6512 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6513 info.parent.status_mask = 1ull<<13 /* usb */;
6514 info.func = __cvmx_error_display;
6515 info.user_info = (long)
6516 "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
6517 fail |= cvmx_error_add(&info);
6519 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6520 info.status_addr = CVMX_USBNX_INT_SUM(0);
6521 info.status_mask = 1ull<<22 /* rq_q3_f */;
6522 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6523 info.enable_mask = 1ull<<22 /* rq_q3_f */;
6525 info.group = CVMX_ERROR_GROUP_USB;
6526 info.group_index = 0;
6527 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6528 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6529 info.parent.status_mask = 1ull<<13 /* usb */;
6530 info.func = __cvmx_error_display;
6531 info.user_info = (long)
6532 "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
6533 fail |= cvmx_error_add(&info);
6535 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6536 info.status_addr = CVMX_USBNX_INT_SUM(0);
6537 info.status_mask = 1ull<<23 /* rq_q3_e */;
6538 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6539 info.enable_mask = 1ull<<23 /* rq_q3_e */;
6541 info.group = CVMX_ERROR_GROUP_USB;
6542 info.group_index = 0;
6543 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6544 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6545 info.parent.status_mask = 1ull<<13 /* usb */;
6546 info.func = __cvmx_error_display;
6547 info.user_info = (long)
6548 "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
6549 fail |= cvmx_error_add(&info);
6551 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6552 info.status_addr = CVMX_USBNX_INT_SUM(0);
6553 info.status_mask = 1ull<<24 /* uod_pe */;
6554 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6555 info.enable_mask = 1ull<<24 /* uod_pe */;
6557 info.group = CVMX_ERROR_GROUP_USB;
6558 info.group_index = 0;
6559 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6560 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6561 info.parent.status_mask = 1ull<<13 /* usb */;
6562 info.func = __cvmx_error_display;
6563 info.user_info = (long)
6564 "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
6565 fail |= cvmx_error_add(&info);
6567 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6568 info.status_addr = CVMX_USBNX_INT_SUM(0);
6569 info.status_mask = 1ull<<25 /* uod_pf */;
6570 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6571 info.enable_mask = 1ull<<25 /* uod_pf */;
6573 info.group = CVMX_ERROR_GROUP_USB;
6574 info.group_index = 0;
6575 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6576 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6577 info.parent.status_mask = 1ull<<13 /* usb */;
6578 info.func = __cvmx_error_display;
6579 info.user_info = (long)
6580 "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
6581 fail |= cvmx_error_add(&info);
6583 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6584 info.status_addr = CVMX_USBNX_INT_SUM(0);
6585 info.status_mask = 1ull<<32 /* ltl_f_pe */;
6586 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6587 info.enable_mask = 1ull<<32 /* ltl_f_pe */;
6589 info.group = CVMX_ERROR_GROUP_USB;
6590 info.group_index = 0;
6591 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6592 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6593 info.parent.status_mask = 1ull<<13 /* usb */;
6594 info.func = __cvmx_error_display;
6595 info.user_info = (long)
6596 "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
6597 fail |= cvmx_error_add(&info);
6599 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6600 info.status_addr = CVMX_USBNX_INT_SUM(0);
6601 info.status_mask = 1ull<<33 /* ltl_f_pf */;
6602 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6603 info.enable_mask = 1ull<<33 /* ltl_f_pf */;
6605 info.group = CVMX_ERROR_GROUP_USB;
6606 info.group_index = 0;
6607 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6608 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6609 info.parent.status_mask = 1ull<<13 /* usb */;
6610 info.func = __cvmx_error_display;
6611 info.user_info = (long)
6612 "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
6613 fail |= cvmx_error_add(&info);
6615 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6616 info.status_addr = CVMX_USBNX_INT_SUM(0);
6617 info.status_mask = 1ull<<34 /* nd4o_rpe */;
6618 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6619 info.enable_mask = 1ull<<34 /* nd4o_rpe */;
6621 info.group = CVMX_ERROR_GROUP_USB;
6622 info.group_index = 0;
6623 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6624 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6625 info.parent.status_mask = 1ull<<13 /* usb */;
6626 info.func = __cvmx_error_display;
6627 info.user_info = (long)
6628 "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
6629 fail |= cvmx_error_add(&info);
6631 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6632 info.status_addr = CVMX_USBNX_INT_SUM(0);
6633 info.status_mask = 1ull<<35 /* nd4o_rpf */;
6634 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6635 info.enable_mask = 1ull<<35 /* nd4o_rpf */;
6637 info.group = CVMX_ERROR_GROUP_USB;
6638 info.group_index = 0;
6639 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6640 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6641 info.parent.status_mask = 1ull<<13 /* usb */;
6642 info.func = __cvmx_error_display;
6643 info.user_info = (long)
6644 "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
6645 fail |= cvmx_error_add(&info);
6647 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6648 info.status_addr = CVMX_USBNX_INT_SUM(0);
6649 info.status_mask = 1ull<<36 /* nd4o_dpe */;
6650 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6651 info.enable_mask = 1ull<<36 /* nd4o_dpe */;
6653 info.group = CVMX_ERROR_GROUP_USB;
6654 info.group_index = 0;
6655 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6656 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6657 info.parent.status_mask = 1ull<<13 /* usb */;
6658 info.func = __cvmx_error_display;
6659 info.user_info = (long)
6660 "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
6661 fail |= cvmx_error_add(&info);
6663 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6664 info.status_addr = CVMX_USBNX_INT_SUM(0);
6665 info.status_mask = 1ull<<37 /* nd4o_dpf */;
6666 info.enable_addr = CVMX_USBNX_INT_ENB(0);
6667 info.enable_mask = 1ull<<37 /* nd4o_dpf */;
6669 info.group = CVMX_ERROR_GROUP_USB;
6670 info.group_index = 0;
6671 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6672 info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
6673 info.parent.status_mask = 1ull<<13 /* usb */;
6674 info.func = __cvmx_error_display;
6675 info.user_info = (long)
6676 "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
6677 fail |= cvmx_error_add(&info);