1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Automatically generated error messages for cn63xx.
46 * This file is auto generated. Do not edit.
50 * <hr><h2>Error tree for CN63XX</h2>
55 * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
56 * edge [fontsize=7, font=helvitica];
57 * cvmx_root [label="ROOT|<root>root"];
58 * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
59 * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
60 * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
61 * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
62 * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
63 * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
64 * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
65 * cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
66 * cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
67 * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
68 * cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<usb>usb|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<srio1>srio1|<sli>sli|<dpi>dpi"];
69 * cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
70 * cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
71 * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
72 * cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
73 * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
74 * cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
75 * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
76 * cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
77 * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
78 * cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
79 * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
80 * cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
81 * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
82 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
83 * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
84 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
85 * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
86 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
87 * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
88 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
89 * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
90 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
91 * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
92 * cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
93 * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
94 * cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
95 * cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
96 * cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
97 * cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
98 * cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
99 * cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
100 * cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
101 * cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
102 * cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
103 * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7"];
104 * cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
105 * cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
106 * cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
107 * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
108 * cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
109 * cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
110 * cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
111 * cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"];
112 * cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"];
113 * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
114 * cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
115 * cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
116 * cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
117 * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
118 * cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
119 * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
120 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
121 * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
122 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
123 * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
124 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
125 * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
126 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
127 * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
128 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
129 * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
130 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
131 * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
132 * cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
133 * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
134 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
135 * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
136 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
137 * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
138 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
139 * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
140 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
141 * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
142 * cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
143 * cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
144 * cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
145 * cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout"];
146 * cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
147 * cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout"];
148 * cvmx_ciu_block_int:srio1:e -> cvmx_srio1_int_reg [label="srio1"];
149 * cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad"];
150 * cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
151 * cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
152 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
153 * cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
154 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
155 * cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
156 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
157 * cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
158 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
159 * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
160 * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
161 * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
162 * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
163 * cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
164 * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
165 * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
166 * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
167 * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
168 * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
169 * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
170 * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
171 * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
172 * cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
173 * cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
174 * cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
175 * cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
179 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
180 #include <asm/octeon/cvmx.h>
181 #include <asm/octeon/cvmx-error.h>
182 #include <asm/octeon/cvmx-error-custom.h>
183 #include <asm/octeon/cvmx-csr-typedefs.h>
186 #include "cvmx-error.h"
187 #include "cvmx-error-custom.h"
190 int cvmx_error_initialize_cn63xx(void);
192 int cvmx_error_initialize_cn63xx(void)
194 cvmx_error_info_t info;
197 /* CVMX_CIU_INTX_SUM0(0) */
198 info.reg_type = CVMX_ERROR_REGISTER_IO64;
199 info.status_addr = CVMX_CIU_INTX_SUM0(0);
200 info.status_mask = 0;
201 info.enable_addr = 0;
202 info.enable_mask = 0;
204 info.group = CVMX_ERROR_GROUP_INTERNAL;
205 info.group_index = 0;
206 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
207 info.parent.status_addr = 0;
208 info.parent.status_mask = 0;
209 info.func = __cvmx_error_decode;
211 fail |= cvmx_error_add(&info);
213 /* CVMX_MIXX_ISR(0) */
214 info.reg_type = CVMX_ERROR_REGISTER_IO64;
215 info.status_addr = CVMX_MIXX_ISR(0);
216 info.status_mask = 1ull<<0 /* odblovf */;
217 info.enable_addr = CVMX_MIXX_INTENA(0);
218 info.enable_mask = 1ull<<0 /* ovfena */;
220 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
221 info.group_index = 0;
222 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
223 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
224 info.parent.status_mask = 1ull<<62 /* mii */;
225 info.func = __cvmx_error_display;
226 info.user_info = (long)
227 "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
228 " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
229 " with a value greater than the remaining #of\n"
230 " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
231 " the following occurs:\n"
232 " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
233 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
234 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
235 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
236 " and the local interrupt mask bit(OVFENA) is set, than an\n"
237 " interrupt is reported for this event.\n"
238 " SW should keep track of the #I-Ring Entries in use\n"
239 " (ie: cumulative # of ODBELL writes), and ensure that\n"
240 " future ODBELL writes don't exceed the size of the\n"
241 " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
242 " SW must reclaim O-Ring Entries by writing to the\n"
243 " MIX_ORCNT[ORCNT]. .\n"
244 " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
245 " If it occurs, it's an indication that SW has\n"
246 " overwritten the O-Ring buffer, and the only recourse\n"
248 fail |= cvmx_error_add(&info);
250 info.reg_type = CVMX_ERROR_REGISTER_IO64;
251 info.status_addr = CVMX_MIXX_ISR(0);
252 info.status_mask = 1ull<<1 /* idblovf */;
253 info.enable_addr = CVMX_MIXX_INTENA(0);
254 info.enable_mask = 1ull<<1 /* ivfena */;
256 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
257 info.group_index = 0;
258 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
259 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
260 info.parent.status_mask = 1ull<<62 /* mii */;
261 info.func = __cvmx_error_display;
262 info.user_info = (long)
263 "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
264 " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
265 " with a value greater than the remaining #of\n"
266 " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
267 " the following occurs:\n"
268 " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
269 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
270 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
271 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
272 " and the local interrupt mask bit(IVFENA) is set, than an\n"
273 " interrupt is reported for this event.\n"
274 " SW should keep track of the #I-Ring Entries in use\n"
275 " (ie: cumulative # of IDBELL writes), and ensure that\n"
276 " future IDBELL writes don't exceed the size of the\n"
277 " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
278 " SW must reclaim I-Ring Entries by keeping track of the\n"
279 " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
280 " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
281 " total #packets(not IRing Entries) and SW must further\n"
282 " keep track of the # of I-Ring Entries associated with\n"
283 " each packet as they are processed.\n"
284 " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
285 " If it occurs, it's an indication that SW has\n"
286 " overwritten the I-Ring buffer, and the only recourse\n"
288 fail |= cvmx_error_add(&info);
290 info.reg_type = CVMX_ERROR_REGISTER_IO64;
291 info.status_addr = CVMX_MIXX_ISR(0);
292 info.status_mask = 1ull<<4 /* data_drp */;
293 info.enable_addr = CVMX_MIXX_INTENA(0);
294 info.enable_mask = 1ull<<4 /* data_drpena */;
296 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
297 info.group_index = 0;
298 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
299 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
300 info.parent.status_mask = 1ull<<62 /* mii */;
301 info.func = __cvmx_error_display;
302 info.user_info = (long)
303 "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
304 " If this does occur, the DATA_DRP is set and the\n"
305 " CIU_INTx_SUM0,4[MII] bits are set.\n"
306 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
307 " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
308 " interrupt is reported for this event.\n";
309 fail |= cvmx_error_add(&info);
311 info.reg_type = CVMX_ERROR_REGISTER_IO64;
312 info.status_addr = CVMX_MIXX_ISR(0);
313 info.status_mask = 1ull<<5 /* irun */;
314 info.enable_addr = CVMX_MIXX_INTENA(0);
315 info.enable_mask = 1ull<<5 /* irunena */;
317 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
318 info.group_index = 0;
319 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
320 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
321 info.parent.status_mask = 1ull<<62 /* mii */;
322 info.func = __cvmx_error_display;
323 info.user_info = (long)
324 "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
325 " If SW writes a larger value than what is currently\n"
326 " in the MIX_IRCNT[IRCNT], then HW will report the\n"
327 " underflow condition.\n"
328 " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
329 " NOTE: If an IRUN underflow condition is detected,\n"
330 " the integrity of the MIX/AGL HW state has\n"
331 " been compromised. To recover, SW must issue a\n"
332 " software reset sequence (see: MIX_CTL[RESET]\n";
333 fail |= cvmx_error_add(&info);
335 info.reg_type = CVMX_ERROR_REGISTER_IO64;
336 info.status_addr = CVMX_MIXX_ISR(0);
337 info.status_mask = 1ull<<6 /* orun */;
338 info.enable_addr = CVMX_MIXX_INTENA(0);
339 info.enable_mask = 1ull<<6 /* orunena */;
341 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
342 info.group_index = 0;
343 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
344 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
345 info.parent.status_mask = 1ull<<62 /* mii */;
346 info.func = __cvmx_error_display;
347 info.user_info = (long)
348 "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
349 " If SW writes a larger value than what is currently\n"
350 " in the MIX_ORCNT[ORCNT], then HW will report the\n"
351 " underflow condition.\n"
352 " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
353 " NOTE: If an ORUN underflow condition is detected,\n"
354 " the integrity of the MIX/AGL HW state has\n"
355 " been compromised. To recover, SW must issue a\n"
356 " software reset sequence (see: MIX_CTL[RESET]\n";
357 fail |= cvmx_error_add(&info);
359 /* CVMX_CIU_INT_SUM1 */
360 info.reg_type = CVMX_ERROR_REGISTER_IO64;
361 info.status_addr = CVMX_CIU_INT_SUM1;
362 info.status_mask = 0;
363 info.enable_addr = 0;
364 info.enable_mask = 0;
366 info.group = CVMX_ERROR_GROUP_INTERNAL;
367 info.group_index = 0;
368 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
369 info.parent.status_addr = 0;
370 info.parent.status_mask = 0;
371 info.func = __cvmx_error_decode;
373 fail |= cvmx_error_add(&info);
375 /* CVMX_MIXX_ISR(1) */
376 info.reg_type = CVMX_ERROR_REGISTER_IO64;
377 info.status_addr = CVMX_MIXX_ISR(1);
378 info.status_mask = 1ull<<0 /* odblovf */;
379 info.enable_addr = CVMX_MIXX_INTENA(1);
380 info.enable_mask = 1ull<<0 /* ovfena */;
382 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
383 info.group_index = 1;
384 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
385 info.parent.status_addr = CVMX_CIU_INT_SUM1;
386 info.parent.status_mask = 1ull<<18 /* mii1 */;
387 info.func = __cvmx_error_display;
388 info.user_info = (long)
389 "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
390 " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
391 " with a value greater than the remaining #of\n"
392 " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
393 " the following occurs:\n"
394 " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
395 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
396 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
397 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
398 " and the local interrupt mask bit(OVFENA) is set, than an\n"
399 " interrupt is reported for this event.\n"
400 " SW should keep track of the #I-Ring Entries in use\n"
401 " (ie: cumulative # of ODBELL writes), and ensure that\n"
402 " future ODBELL writes don't exceed the size of the\n"
403 " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
404 " SW must reclaim O-Ring Entries by writing to the\n"
405 " MIX_ORCNT[ORCNT]. .\n"
406 " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
407 " If it occurs, it's an indication that SW has\n"
408 " overwritten the O-Ring buffer, and the only recourse\n"
410 fail |= cvmx_error_add(&info);
412 info.reg_type = CVMX_ERROR_REGISTER_IO64;
413 info.status_addr = CVMX_MIXX_ISR(1);
414 info.status_mask = 1ull<<1 /* idblovf */;
415 info.enable_addr = CVMX_MIXX_INTENA(1);
416 info.enable_mask = 1ull<<1 /* ivfena */;
418 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
419 info.group_index = 1;
420 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
421 info.parent.status_addr = CVMX_CIU_INT_SUM1;
422 info.parent.status_mask = 1ull<<18 /* mii1 */;
423 info.func = __cvmx_error_display;
424 info.user_info = (long)
425 "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
426 " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
427 " with a value greater than the remaining #of\n"
428 " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
429 " the following occurs:\n"
430 " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
431 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
432 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
433 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
434 " and the local interrupt mask bit(IVFENA) is set, than an\n"
435 " interrupt is reported for this event.\n"
436 " SW should keep track of the #I-Ring Entries in use\n"
437 " (ie: cumulative # of IDBELL writes), and ensure that\n"
438 " future IDBELL writes don't exceed the size of the\n"
439 " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
440 " SW must reclaim I-Ring Entries by keeping track of the\n"
441 " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
442 " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
443 " total #packets(not IRing Entries) and SW must further\n"
444 " keep track of the # of I-Ring Entries associated with\n"
445 " each packet as they are processed.\n"
446 " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
447 " If it occurs, it's an indication that SW has\n"
448 " overwritten the I-Ring buffer, and the only recourse\n"
450 fail |= cvmx_error_add(&info);
452 info.reg_type = CVMX_ERROR_REGISTER_IO64;
453 info.status_addr = CVMX_MIXX_ISR(1);
454 info.status_mask = 1ull<<4 /* data_drp */;
455 info.enable_addr = CVMX_MIXX_INTENA(1);
456 info.enable_mask = 1ull<<4 /* data_drpena */;
458 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
459 info.group_index = 1;
460 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
461 info.parent.status_addr = CVMX_CIU_INT_SUM1;
462 info.parent.status_mask = 1ull<<18 /* mii1 */;
463 info.func = __cvmx_error_display;
464 info.user_info = (long)
465 "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
466 " If this does occur, the DATA_DRP is set and the\n"
467 " CIU_INTx_SUM0,4[MII] bits are set.\n"
468 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
469 " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
470 " interrupt is reported for this event.\n";
471 fail |= cvmx_error_add(&info);
473 info.reg_type = CVMX_ERROR_REGISTER_IO64;
474 info.status_addr = CVMX_MIXX_ISR(1);
475 info.status_mask = 1ull<<5 /* irun */;
476 info.enable_addr = CVMX_MIXX_INTENA(1);
477 info.enable_mask = 1ull<<5 /* irunena */;
479 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
480 info.group_index = 1;
481 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
482 info.parent.status_addr = CVMX_CIU_INT_SUM1;
483 info.parent.status_mask = 1ull<<18 /* mii1 */;
484 info.func = __cvmx_error_display;
485 info.user_info = (long)
486 "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
487 " If SW writes a larger value than what is currently\n"
488 " in the MIX_IRCNT[IRCNT], then HW will report the\n"
489 " underflow condition.\n"
490 " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
491 " NOTE: If an IRUN underflow condition is detected,\n"
492 " the integrity of the MIX/AGL HW state has\n"
493 " been compromised. To recover, SW must issue a\n"
494 " software reset sequence (see: MIX_CTL[RESET]\n";
495 fail |= cvmx_error_add(&info);
497 info.reg_type = CVMX_ERROR_REGISTER_IO64;
498 info.status_addr = CVMX_MIXX_ISR(1);
499 info.status_mask = 1ull<<6 /* orun */;
500 info.enable_addr = CVMX_MIXX_INTENA(1);
501 info.enable_mask = 1ull<<6 /* orunena */;
503 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
504 info.group_index = 1;
505 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
506 info.parent.status_addr = CVMX_CIU_INT_SUM1;
507 info.parent.status_mask = 1ull<<18 /* mii1 */;
508 info.func = __cvmx_error_display;
509 info.user_info = (long)
510 "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
511 " If SW writes a larger value than what is currently\n"
512 " in the MIX_ORCNT[ORCNT], then HW will report the\n"
513 " underflow condition.\n"
514 " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
515 " NOTE: If an ORUN underflow condition is detected,\n"
516 " the integrity of the MIX/AGL HW state has\n"
517 " been compromised. To recover, SW must issue a\n"
518 " software reset sequence (see: MIX_CTL[RESET]\n";
519 fail |= cvmx_error_add(&info);
522 info.reg_type = CVMX_ERROR_REGISTER_IO64;
523 info.status_addr = CVMX_NDF_INT;
524 info.status_mask = 1ull<<2 /* wdog */;
525 info.enable_addr = CVMX_NDF_INT_EN;
526 info.enable_mask = 1ull<<2 /* wdog */;
528 info.group = CVMX_ERROR_GROUP_INTERNAL;
529 info.group_index = 0;
530 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
531 info.parent.status_addr = CVMX_CIU_INT_SUM1;
532 info.parent.status_mask = 1ull<<19 /* nand */;
533 info.func = __cvmx_error_display;
534 info.user_info = (long)
535 "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
536 fail |= cvmx_error_add(&info);
538 info.reg_type = CVMX_ERROR_REGISTER_IO64;
539 info.status_addr = CVMX_NDF_INT;
540 info.status_mask = 1ull<<3 /* sm_bad */;
541 info.enable_addr = CVMX_NDF_INT_EN;
542 info.enable_mask = 1ull<<3 /* sm_bad */;
544 info.group = CVMX_ERROR_GROUP_INTERNAL;
545 info.group_index = 0;
546 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
547 info.parent.status_addr = CVMX_CIU_INT_SUM1;
548 info.parent.status_mask = 1ull<<19 /* nand */;
549 info.func = __cvmx_error_display;
550 info.user_info = (long)
551 "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
552 fail |= cvmx_error_add(&info);
554 info.reg_type = CVMX_ERROR_REGISTER_IO64;
555 info.status_addr = CVMX_NDF_INT;
556 info.status_mask = 1ull<<4 /* ecc_1bit */;
557 info.enable_addr = CVMX_NDF_INT_EN;
558 info.enable_mask = 1ull<<4 /* ecc_1bit */;
560 info.group = CVMX_ERROR_GROUP_INTERNAL;
561 info.group_index = 0;
562 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
563 info.parent.status_addr = CVMX_CIU_INT_SUM1;
564 info.parent.status_mask = 1ull<<19 /* nand */;
565 info.func = __cvmx_error_display;
566 info.user_info = (long)
567 "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
568 fail |= cvmx_error_add(&info);
570 info.reg_type = CVMX_ERROR_REGISTER_IO64;
571 info.status_addr = CVMX_NDF_INT;
572 info.status_mask = 1ull<<5 /* ecc_mult */;
573 info.enable_addr = CVMX_NDF_INT_EN;
574 info.enable_mask = 1ull<<5 /* ecc_mult */;
576 info.group = CVMX_ERROR_GROUP_INTERNAL;
577 info.group_index = 0;
578 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
579 info.parent.status_addr = CVMX_CIU_INT_SUM1;
580 info.parent.status_mask = 1ull<<19 /* nand */;
581 info.func = __cvmx_error_display;
582 info.user_info = (long)
583 "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
584 fail |= cvmx_error_add(&info);
586 info.reg_type = CVMX_ERROR_REGISTER_IO64;
587 info.status_addr = CVMX_NDF_INT;
588 info.status_mask = 1ull<<6 /* ovrf */;
589 info.enable_addr = CVMX_NDF_INT_EN;
590 info.enable_mask = 1ull<<6 /* ovrf */;
592 info.group = CVMX_ERROR_GROUP_INTERNAL;
593 info.group_index = 0;
594 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
595 info.parent.status_addr = CVMX_CIU_INT_SUM1;
596 info.parent.status_mask = 1ull<<19 /* nand */;
597 info.func = __cvmx_error_display;
598 info.user_info = (long)
599 "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
601 fail |= cvmx_error_add(&info);
603 /* CVMX_CIU_BLOCK_INT */
604 info.reg_type = CVMX_ERROR_REGISTER_IO64;
605 info.status_addr = CVMX_CIU_BLOCK_INT;
606 info.status_mask = 0;
607 info.enable_addr = 0;
608 info.enable_mask = 0;
610 info.group = CVMX_ERROR_GROUP_INTERNAL;
611 info.group_index = 0;
612 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
613 info.parent.status_addr = 0;
614 info.parent.status_mask = 0;
615 info.func = __cvmx_error_decode;
617 fail |= cvmx_error_add(&info);
619 /* CVMX_L2C_INT_REG */
620 info.reg_type = CVMX_ERROR_REGISTER_IO64;
621 info.status_addr = CVMX_L2C_INT_REG;
622 info.status_mask = 1ull<<0 /* holerd */;
623 info.enable_addr = CVMX_L2C_INT_ENA;
624 info.enable_mask = 1ull<<0 /* holerd */;
626 info.group = CVMX_ERROR_GROUP_INTERNAL;
627 info.group_index = 0;
628 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
629 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
630 info.parent.status_mask = 1ull<<16 /* l2c */;
631 info.func = __cvmx_error_display;
632 info.user_info = (long)
633 "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
634 fail |= cvmx_error_add(&info);
636 info.reg_type = CVMX_ERROR_REGISTER_IO64;
637 info.status_addr = CVMX_L2C_INT_REG;
638 info.status_mask = 1ull<<1 /* holewr */;
639 info.enable_addr = CVMX_L2C_INT_ENA;
640 info.enable_mask = 1ull<<1 /* holewr */;
642 info.group = CVMX_ERROR_GROUP_INTERNAL;
643 info.group_index = 0;
644 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
645 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
646 info.parent.status_mask = 1ull<<16 /* l2c */;
647 info.func = __cvmx_error_display;
648 info.user_info = (long)
649 "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
650 fail |= cvmx_error_add(&info);
652 info.reg_type = CVMX_ERROR_REGISTER_IO64;
653 info.status_addr = CVMX_L2C_INT_REG;
654 info.status_mask = 1ull<<2 /* vrtwr */;
655 info.enable_addr = CVMX_L2C_INT_ENA;
656 info.enable_mask = 1ull<<2 /* vrtwr */;
658 info.group = CVMX_ERROR_GROUP_INTERNAL;
659 info.group_index = 0;
660 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
661 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
662 info.parent.status_mask = 1ull<<16 /* l2c */;
663 info.func = __cvmx_error_display;
664 info.user_info = (long)
665 "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
666 " Set when L2C_VRT_MEM blocked a store.\n";
667 fail |= cvmx_error_add(&info);
669 info.reg_type = CVMX_ERROR_REGISTER_IO64;
670 info.status_addr = CVMX_L2C_INT_REG;
671 info.status_mask = 1ull<<3 /* vrtidrng */;
672 info.enable_addr = CVMX_L2C_INT_ENA;
673 info.enable_mask = 1ull<<3 /* vrtidrng */;
675 info.group = CVMX_ERROR_GROUP_INTERNAL;
676 info.group_index = 0;
677 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
678 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
679 info.parent.status_mask = 1ull<<16 /* l2c */;
680 info.func = __cvmx_error_display;
681 info.user_info = (long)
682 "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
683 " Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
685 fail |= cvmx_error_add(&info);
687 info.reg_type = CVMX_ERROR_REGISTER_IO64;
688 info.status_addr = CVMX_L2C_INT_REG;
689 info.status_mask = 1ull<<4 /* vrtadrng */;
690 info.enable_addr = CVMX_L2C_INT_ENA;
691 info.enable_mask = 1ull<<4 /* vrtadrng */;
693 info.group = CVMX_ERROR_GROUP_INTERNAL;
694 info.group_index = 0;
695 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
696 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
697 info.parent.status_mask = 1ull<<16 /* l2c */;
698 info.func = __cvmx_error_display;
699 info.user_info = (long)
700 "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
701 " Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
703 " L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
704 fail |= cvmx_error_add(&info);
706 info.reg_type = CVMX_ERROR_REGISTER_IO64;
707 info.status_addr = CVMX_L2C_INT_REG;
708 info.status_mask = 1ull<<5 /* vrtpe */;
709 info.enable_addr = CVMX_L2C_INT_ENA;
710 info.enable_mask = 1ull<<5 /* vrtpe */;
712 info.group = CVMX_ERROR_GROUP_INTERNAL;
713 info.group_index = 0;
714 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
715 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
716 info.parent.status_mask = 1ull<<16 /* l2c */;
717 info.func = __cvmx_error_display;
718 info.user_info = (long)
719 "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
720 " Whenever an L2C_VRT_MEM read finds a parity error,\n"
721 " that L2C_VRT_MEM cannot cause stores to be blocked.\n"
722 " Software should correct the error.\n";
723 fail |= cvmx_error_add(&info);
725 info.reg_type = CVMX_ERROR_REGISTER_IO64;
726 info.status_addr = CVMX_L2C_INT_REG;
727 info.status_mask = 1ull<<6 /* bigwr */;
728 info.enable_addr = CVMX_L2C_INT_ENA;
729 info.enable_mask = 1ull<<6 /* bigwr */;
731 info.group = CVMX_ERROR_GROUP_INTERNAL;
732 info.group_index = 0;
733 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
734 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
735 info.parent.status_mask = 1ull<<16 /* l2c */;
736 info.func = __cvmx_error_display;
737 info.user_info = (long)
738 "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
739 fail |= cvmx_error_add(&info);
741 info.reg_type = CVMX_ERROR_REGISTER_IO64;
742 info.status_addr = CVMX_L2C_INT_REG;
743 info.status_mask = 1ull<<7 /* bigrd */;
744 info.enable_addr = CVMX_L2C_INT_ENA;
745 info.enable_mask = 1ull<<7 /* bigrd */;
747 info.group = CVMX_ERROR_GROUP_INTERNAL;
748 info.group_index = 0;
749 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
750 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
751 info.parent.status_mask = 1ull<<16 /* l2c */;
752 info.func = __cvmx_error_display;
753 info.user_info = (long)
754 "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
755 fail |= cvmx_error_add(&info);
757 info.reg_type = CVMX_ERROR_REGISTER_IO64;
758 info.status_addr = CVMX_L2C_INT_REG;
759 info.status_mask = 0;
760 info.enable_addr = 0;
761 info.enable_mask = 0;
763 info.group = CVMX_ERROR_GROUP_INTERNAL;
764 info.group_index = 0;
765 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
766 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
767 info.parent.status_mask = 1ull<<16 /* l2c */;
768 info.func = __cvmx_error_decode;
770 fail |= cvmx_error_add(&info);
772 /* CVMX_L2C_ERR_TDTX(0) */
773 info.reg_type = CVMX_ERROR_REGISTER_IO64;
774 info.status_addr = CVMX_L2C_ERR_TDTX(0);
775 info.status_mask = 1ull<<60 /* vsbe */;
776 info.enable_addr = 0;
777 info.enable_mask = 0;
779 info.group = CVMX_ERROR_GROUP_INTERNAL;
780 info.group_index = 0;
781 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
782 info.parent.status_addr = CVMX_L2C_INT_REG;
783 info.parent.status_mask = 1ull<<16 /* tad0 */;
784 info.func = __cvmx_error_display;
785 info.user_info = (long)
786 "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
787 fail |= cvmx_error_add(&info);
789 info.reg_type = CVMX_ERROR_REGISTER_IO64;
790 info.status_addr = CVMX_L2C_ERR_TDTX(0);
791 info.status_mask = 1ull<<61 /* vdbe */;
792 info.enable_addr = 0;
793 info.enable_mask = 0;
795 info.group = CVMX_ERROR_GROUP_INTERNAL;
796 info.group_index = 0;
797 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
798 info.parent.status_addr = CVMX_L2C_INT_REG;
799 info.parent.status_mask = 1ull<<16 /* tad0 */;
800 info.func = __cvmx_error_display;
801 info.user_info = (long)
802 "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
803 fail |= cvmx_error_add(&info);
805 info.reg_type = CVMX_ERROR_REGISTER_IO64;
806 info.status_addr = CVMX_L2C_ERR_TDTX(0);
807 info.status_mask = 1ull<<62 /* sbe */;
808 info.enable_addr = 0;
809 info.enable_mask = 0;
811 info.group = CVMX_ERROR_GROUP_INTERNAL;
812 info.group_index = 0;
813 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
814 info.parent.status_addr = CVMX_L2C_INT_REG;
815 info.parent.status_mask = 1ull<<16 /* tad0 */;
816 info.func = __cvmx_error_display;
817 info.user_info = (long)
818 "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
819 fail |= cvmx_error_add(&info);
821 info.reg_type = CVMX_ERROR_REGISTER_IO64;
822 info.status_addr = CVMX_L2C_ERR_TDTX(0);
823 info.status_mask = 1ull<<63 /* dbe */;
824 info.enable_addr = 0;
825 info.enable_mask = 0;
827 info.group = CVMX_ERROR_GROUP_INTERNAL;
828 info.group_index = 0;
829 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
830 info.parent.status_addr = CVMX_L2C_INT_REG;
831 info.parent.status_mask = 1ull<<16 /* tad0 */;
832 info.func = __cvmx_error_display;
833 info.user_info = (long)
834 "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
835 fail |= cvmx_error_add(&info);
837 /* CVMX_L2C_ERR_TTGX(0) */
838 info.reg_type = CVMX_ERROR_REGISTER_IO64;
839 info.status_addr = CVMX_L2C_ERR_TTGX(0);
840 info.status_mask = 1ull<<61 /* noway */;
841 info.enable_addr = 0;
842 info.enable_mask = 0;
844 info.group = CVMX_ERROR_GROUP_INTERNAL;
845 info.group_index = 0;
846 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
847 info.parent.status_addr = CVMX_L2C_INT_REG;
848 info.parent.status_mask = 1ull<<16 /* tad0 */;
849 info.func = __cvmx_error_display;
850 info.user_info = (long)
851 "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
852 " L2C sets NOWAY during its processing of a\n"
853 " transaction whenever it needed/wanted to allocate\n"
854 " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
855 " is (generally) not an indication that L2C failed to\n"
856 " complete transactions. Rather, it is a hint of\n"
857 " possible performance degradation. (For example, L2C\n"
858 " must read-modify-write DRAM for every transaction\n"
859 " that updates some, but not all, of the bytes in a\n"
860 " cache block, misses in the L2 cache, and cannot\n"
861 " allocate a WAY.) There is one \"failure\" case where\n"
862 " L2C will set NOWAY: when it cannot leave a block\n"
863 " locked in the L2 cache as part of a LCKL2\n"
865 fail |= cvmx_error_add(&info);
867 info.reg_type = CVMX_ERROR_REGISTER_IO64;
868 info.status_addr = CVMX_L2C_ERR_TTGX(0);
869 info.status_mask = 1ull<<62 /* sbe */;
870 info.enable_addr = 0;
871 info.enable_mask = 0;
873 info.group = CVMX_ERROR_GROUP_INTERNAL;
874 info.group_index = 0;
875 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
876 info.parent.status_addr = CVMX_L2C_INT_REG;
877 info.parent.status_mask = 1ull<<16 /* tad0 */;
878 info.func = __cvmx_error_display;
879 info.user_info = (long)
880 "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
881 fail |= cvmx_error_add(&info);
883 info.reg_type = CVMX_ERROR_REGISTER_IO64;
884 info.status_addr = CVMX_L2C_ERR_TTGX(0);
885 info.status_mask = 1ull<<63 /* dbe */;
886 info.enable_addr = 0;
887 info.enable_mask = 0;
889 info.group = CVMX_ERROR_GROUP_INTERNAL;
890 info.group_index = 0;
891 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
892 info.parent.status_addr = CVMX_L2C_INT_REG;
893 info.parent.status_mask = 1ull<<16 /* tad0 */;
894 info.func = __cvmx_error_display;
895 info.user_info = (long)
896 "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
897 fail |= cvmx_error_add(&info);
899 /* CVMX_IPD_INT_SUM */
900 info.reg_type = CVMX_ERROR_REGISTER_IO64;
901 info.status_addr = CVMX_IPD_INT_SUM;
902 info.status_mask = 1ull<<0 /* prc_par0 */;
903 info.enable_addr = CVMX_IPD_INT_ENB;
904 info.enable_mask = 1ull<<0 /* prc_par0 */;
906 info.group = CVMX_ERROR_GROUP_INTERNAL;
907 info.group_index = 0;
908 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
909 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
910 info.parent.status_mask = 1ull<<9 /* ipd */;
911 info.func = __cvmx_error_display;
912 info.user_info = (long)
913 "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
914 " [31:0] of the PBM memory.\n";
915 fail |= cvmx_error_add(&info);
917 info.reg_type = CVMX_ERROR_REGISTER_IO64;
918 info.status_addr = CVMX_IPD_INT_SUM;
919 info.status_mask = 1ull<<1 /* prc_par1 */;
920 info.enable_addr = CVMX_IPD_INT_ENB;
921 info.enable_mask = 1ull<<1 /* prc_par1 */;
923 info.group = CVMX_ERROR_GROUP_INTERNAL;
924 info.group_index = 0;
925 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
926 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
927 info.parent.status_mask = 1ull<<9 /* ipd */;
928 info.func = __cvmx_error_display;
929 info.user_info = (long)
930 "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
931 " [63:32] of the PBM memory.\n";
932 fail |= cvmx_error_add(&info);
934 info.reg_type = CVMX_ERROR_REGISTER_IO64;
935 info.status_addr = CVMX_IPD_INT_SUM;
936 info.status_mask = 1ull<<2 /* prc_par2 */;
937 info.enable_addr = CVMX_IPD_INT_ENB;
938 info.enable_mask = 1ull<<2 /* prc_par2 */;
940 info.group = CVMX_ERROR_GROUP_INTERNAL;
941 info.group_index = 0;
942 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
943 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
944 info.parent.status_mask = 1ull<<9 /* ipd */;
945 info.func = __cvmx_error_display;
946 info.user_info = (long)
947 "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
948 " [95:64] of the PBM memory.\n";
949 fail |= cvmx_error_add(&info);
951 info.reg_type = CVMX_ERROR_REGISTER_IO64;
952 info.status_addr = CVMX_IPD_INT_SUM;
953 info.status_mask = 1ull<<3 /* prc_par3 */;
954 info.enable_addr = CVMX_IPD_INT_ENB;
955 info.enable_mask = 1ull<<3 /* prc_par3 */;
957 info.group = CVMX_ERROR_GROUP_INTERNAL;
958 info.group_index = 0;
959 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
960 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
961 info.parent.status_mask = 1ull<<9 /* ipd */;
962 info.func = __cvmx_error_display;
963 info.user_info = (long)
964 "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
965 " [127:96] of the PBM memory.\n";
966 fail |= cvmx_error_add(&info);
968 info.reg_type = CVMX_ERROR_REGISTER_IO64;
969 info.status_addr = CVMX_IPD_INT_SUM;
970 info.status_mask = 1ull<<4 /* bp_sub */;
971 info.enable_addr = CVMX_IPD_INT_ENB;
972 info.enable_mask = 1ull<<4 /* bp_sub */;
974 info.group = CVMX_ERROR_GROUP_INTERNAL;
975 info.group_index = 0;
976 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
977 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
978 info.parent.status_mask = 1ull<<9 /* ipd */;
979 info.func = __cvmx_error_display;
980 info.user_info = (long)
981 "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
982 " supplied illegal value.\n";
983 fail |= cvmx_error_add(&info);
985 info.reg_type = CVMX_ERROR_REGISTER_IO64;
986 info.status_addr = CVMX_IPD_INT_SUM;
987 info.status_mask = 1ull<<5 /* dc_ovr */;
988 info.enable_addr = CVMX_IPD_INT_ENB;
989 info.enable_mask = 1ull<<5 /* dc_ovr */;
991 info.group = CVMX_ERROR_GROUP_INTERNAL;
992 info.group_index = 0;
993 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
994 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
995 info.parent.status_mask = 1ull<<9 /* ipd */;
996 info.func = __cvmx_error_display;
997 info.user_info = (long)
998 "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
999 fail |= cvmx_error_add(&info);
1001 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1002 info.status_addr = CVMX_IPD_INT_SUM;
1003 info.status_mask = 1ull<<6 /* cc_ovr */;
1004 info.enable_addr = CVMX_IPD_INT_ENB;
1005 info.enable_mask = 1ull<<6 /* cc_ovr */;
1007 info.group = CVMX_ERROR_GROUP_INTERNAL;
1008 info.group_index = 0;
1009 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1010 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1011 info.parent.status_mask = 1ull<<9 /* ipd */;
1012 info.func = __cvmx_error_display;
1013 info.user_info = (long)
1014 "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
1015 fail |= cvmx_error_add(&info);
1017 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1018 info.status_addr = CVMX_IPD_INT_SUM;
1019 info.status_mask = 1ull<<7 /* c_coll */;
1020 info.enable_addr = CVMX_IPD_INT_ENB;
1021 info.enable_mask = 1ull<<7 /* c_coll */;
1023 info.group = CVMX_ERROR_GROUP_INTERNAL;
1024 info.group_index = 0;
1025 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1026 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1027 info.parent.status_mask = 1ull<<9 /* ipd */;
1028 info.func = __cvmx_error_display;
1029 info.user_info = (long)
1030 "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
1032 fail |= cvmx_error_add(&info);
1034 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1035 info.status_addr = CVMX_IPD_INT_SUM;
1036 info.status_mask = 1ull<<8 /* d_coll */;
1037 info.enable_addr = CVMX_IPD_INT_ENB;
1038 info.enable_mask = 1ull<<8 /* d_coll */;
1040 info.group = CVMX_ERROR_GROUP_INTERNAL;
1041 info.group_index = 0;
1042 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1043 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1044 info.parent.status_mask = 1ull<<9 /* ipd */;
1045 info.func = __cvmx_error_display;
1046 info.user_info = (long)
1047 "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
1049 fail |= cvmx_error_add(&info);
1051 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1052 info.status_addr = CVMX_IPD_INT_SUM;
1053 info.status_mask = 1ull<<9 /* bc_ovr */;
1054 info.enable_addr = CVMX_IPD_INT_ENB;
1055 info.enable_mask = 1ull<<9 /* bc_ovr */;
1057 info.group = CVMX_ERROR_GROUP_INTERNAL;
1058 info.group_index = 0;
1059 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1060 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1061 info.parent.status_mask = 1ull<<9 /* ipd */;
1062 info.func = __cvmx_error_display;
1063 info.user_info = (long)
1064 "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
1065 fail |= cvmx_error_add(&info);
1067 /* CVMX_POW_ECC_ERR */
1068 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1069 info.status_addr = CVMX_POW_ECC_ERR;
1070 info.status_mask = 1ull<<0 /* sbe */;
1071 info.enable_addr = CVMX_POW_ECC_ERR;
1072 info.enable_mask = 1ull<<2 /* sbe_ie */;
1073 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
1074 info.group = CVMX_ERROR_GROUP_INTERNAL;
1075 info.group_index = 0;
1076 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1077 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1078 info.parent.status_mask = 1ull<<12 /* pow */;
1079 info.func = __cvmx_error_handle_pow_ecc_err_sbe;
1080 info.user_info = (long)
1081 "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
1082 fail |= cvmx_error_add(&info);
1084 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1085 info.status_addr = CVMX_POW_ECC_ERR;
1086 info.status_mask = 1ull<<1 /* dbe */;
1087 info.enable_addr = CVMX_POW_ECC_ERR;
1088 info.enable_mask = 1ull<<3 /* dbe_ie */;
1090 info.group = CVMX_ERROR_GROUP_INTERNAL;
1091 info.group_index = 0;
1092 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1093 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1094 info.parent.status_mask = 1ull<<12 /* pow */;
1095 info.func = __cvmx_error_handle_pow_ecc_err_dbe;
1096 info.user_info = (long)
1097 "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
1098 fail |= cvmx_error_add(&info);
1100 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1101 info.status_addr = CVMX_POW_ECC_ERR;
1102 info.status_mask = 1ull<<12 /* rpe */;
1103 info.enable_addr = CVMX_POW_ECC_ERR;
1104 info.enable_mask = 1ull<<13 /* rpe_ie */;
1106 info.group = CVMX_ERROR_GROUP_INTERNAL;
1107 info.group_index = 0;
1108 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1109 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1110 info.parent.status_mask = 1ull<<12 /* pow */;
1111 info.func = __cvmx_error_handle_pow_ecc_err_rpe;
1112 info.user_info = (long)
1113 "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
1114 fail |= cvmx_error_add(&info);
1116 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1117 info.status_addr = CVMX_POW_ECC_ERR;
1118 info.status_mask = 0x1fffull<<16 /* iop */;
1119 info.enable_addr = CVMX_POW_ECC_ERR;
1120 info.enable_mask = 0x1fffull<<32 /* iop_ie */;
1122 info.group = CVMX_ERROR_GROUP_INTERNAL;
1123 info.group_index = 0;
1124 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1125 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1126 info.parent.status_mask = 1ull<<12 /* pow */;
1127 info.func = __cvmx_error_handle_pow_ecc_err_iop;
1128 info.user_info = (long)
1129 "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
1130 fail |= cvmx_error_add(&info);
1132 /* CVMX_RAD_REG_ERROR */
1133 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1134 info.status_addr = CVMX_RAD_REG_ERROR;
1135 info.status_mask = 1ull<<0 /* doorbell */;
1136 info.enable_addr = CVMX_RAD_REG_INT_MASK;
1137 info.enable_mask = 1ull<<0 /* doorbell */;
1139 info.group = CVMX_ERROR_GROUP_INTERNAL;
1140 info.group_index = 0;
1141 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1142 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1143 info.parent.status_mask = 1ull<<14 /* rad */;
1144 info.func = __cvmx_error_display;
1145 info.user_info = (long)
1146 "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
1147 fail |= cvmx_error_add(&info);
1149 /* CVMX_PCSX_INTX_REG(0,0) */
1150 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1151 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1152 info.status_mask = 1ull<<2 /* an_err */;
1153 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1154 info.enable_mask = 1ull<<2 /* an_err_en */;
1156 info.group = CVMX_ERROR_GROUP_ETHERNET;
1157 info.group_index = 0;
1158 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1159 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1160 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1161 info.func = __cvmx_error_display;
1162 info.user_info = (long)
1163 "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1164 fail |= cvmx_error_add(&info);
1166 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1167 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1168 info.status_mask = 1ull<<3 /* txfifu */;
1169 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1170 info.enable_mask = 1ull<<3 /* txfifu_en */;
1172 info.group = CVMX_ERROR_GROUP_ETHERNET;
1173 info.group_index = 0;
1174 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1175 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1176 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1177 info.func = __cvmx_error_display;
1178 info.user_info = (long)
1179 "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1181 fail |= cvmx_error_add(&info);
1183 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1184 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1185 info.status_mask = 1ull<<4 /* txfifo */;
1186 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1187 info.enable_mask = 1ull<<4 /* txfifo_en */;
1189 info.group = CVMX_ERROR_GROUP_ETHERNET;
1190 info.group_index = 0;
1191 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1192 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1193 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1194 info.func = __cvmx_error_display;
1195 info.user_info = (long)
1196 "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1198 fail |= cvmx_error_add(&info);
1200 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1201 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1202 info.status_mask = 1ull<<5 /* txbad */;
1203 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1204 info.enable_mask = 1ull<<5 /* txbad_en */;
1206 info.group = CVMX_ERROR_GROUP_ETHERNET;
1207 info.group_index = 0;
1208 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1209 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1210 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1211 info.func = __cvmx_error_display;
1212 info.user_info = (long)
1213 "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1214 " state. Should never be set during normal operation\n";
1215 fail |= cvmx_error_add(&info);
1217 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1218 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1219 info.status_mask = 1ull<<7 /* rxbad */;
1220 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1221 info.enable_mask = 1ull<<7 /* rxbad_en */;
1223 info.group = CVMX_ERROR_GROUP_ETHERNET;
1224 info.group_index = 0;
1225 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1226 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1227 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1228 info.func = __cvmx_error_display;
1229 info.user_info = (long)
1230 "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1231 " state. Should never be set during normal operation\n";
1232 fail |= cvmx_error_add(&info);
1234 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1235 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1236 info.status_mask = 1ull<<8 /* rxlock */;
1237 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1238 info.enable_mask = 1ull<<8 /* rxlock_en */;
1240 info.group = CVMX_ERROR_GROUP_ETHERNET;
1241 info.group_index = 0;
1242 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1243 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1244 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1245 info.func = __cvmx_error_display;
1246 info.user_info = (long)
1247 "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1249 " Cannot fire in loopback1 mode\n";
1250 fail |= cvmx_error_add(&info);
1252 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1253 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1254 info.status_mask = 1ull<<9 /* an_bad */;
1255 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1256 info.enable_mask = 1ull<<9 /* an_bad_en */;
1258 info.group = CVMX_ERROR_GROUP_ETHERNET;
1259 info.group_index = 0;
1260 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1261 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1262 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1263 info.func = __cvmx_error_display;
1264 info.user_info = (long)
1265 "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1266 " state. Should never be set during normal operation\n";
1267 fail |= cvmx_error_add(&info);
1269 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1270 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1271 info.status_mask = 1ull<<10 /* sync_bad */;
1272 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1273 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1275 info.group = CVMX_ERROR_GROUP_ETHERNET;
1276 info.group_index = 0;
1277 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1278 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1279 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1280 info.func = __cvmx_error_display;
1281 info.user_info = (long)
1282 "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1283 " state. Should never be set during normal operation\n";
1284 fail |= cvmx_error_add(&info);
1286 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1287 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1288 info.status_mask = 1ull<<12 /* dbg_sync */;
1289 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1290 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1292 info.group = CVMX_ERROR_GROUP_ETHERNET;
1293 info.group_index = 0;
1294 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1295 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1296 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1297 info.func = __cvmx_error_display;
1298 info.user_info = (long)
1299 "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1300 fail |= cvmx_error_add(&info);
1302 /* CVMX_PCSX_INTX_REG(1,0) */
1303 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1304 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1305 info.status_mask = 1ull<<2 /* an_err */;
1306 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1307 info.enable_mask = 1ull<<2 /* an_err_en */;
1309 info.group = CVMX_ERROR_GROUP_ETHERNET;
1310 info.group_index = 1;
1311 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1312 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1313 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1314 info.func = __cvmx_error_display;
1315 info.user_info = (long)
1316 "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1317 fail |= cvmx_error_add(&info);
1319 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1320 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1321 info.status_mask = 1ull<<3 /* txfifu */;
1322 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1323 info.enable_mask = 1ull<<3 /* txfifu_en */;
1325 info.group = CVMX_ERROR_GROUP_ETHERNET;
1326 info.group_index = 1;
1327 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1328 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1329 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1330 info.func = __cvmx_error_display;
1331 info.user_info = (long)
1332 "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1334 fail |= cvmx_error_add(&info);
1336 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1337 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1338 info.status_mask = 1ull<<4 /* txfifo */;
1339 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1340 info.enable_mask = 1ull<<4 /* txfifo_en */;
1342 info.group = CVMX_ERROR_GROUP_ETHERNET;
1343 info.group_index = 1;
1344 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1345 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1346 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1347 info.func = __cvmx_error_display;
1348 info.user_info = (long)
1349 "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1351 fail |= cvmx_error_add(&info);
1353 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1354 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1355 info.status_mask = 1ull<<5 /* txbad */;
1356 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1357 info.enable_mask = 1ull<<5 /* txbad_en */;
1359 info.group = CVMX_ERROR_GROUP_ETHERNET;
1360 info.group_index = 1;
1361 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1362 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1363 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1364 info.func = __cvmx_error_display;
1365 info.user_info = (long)
1366 "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1367 " state. Should never be set during normal operation\n";
1368 fail |= cvmx_error_add(&info);
1370 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1371 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1372 info.status_mask = 1ull<<7 /* rxbad */;
1373 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1374 info.enable_mask = 1ull<<7 /* rxbad_en */;
1376 info.group = CVMX_ERROR_GROUP_ETHERNET;
1377 info.group_index = 1;
1378 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1379 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1380 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1381 info.func = __cvmx_error_display;
1382 info.user_info = (long)
1383 "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1384 " state. Should never be set during normal operation\n";
1385 fail |= cvmx_error_add(&info);
1387 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1388 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1389 info.status_mask = 1ull<<8 /* rxlock */;
1390 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1391 info.enable_mask = 1ull<<8 /* rxlock_en */;
1393 info.group = CVMX_ERROR_GROUP_ETHERNET;
1394 info.group_index = 1;
1395 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1396 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1397 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1398 info.func = __cvmx_error_display;
1399 info.user_info = (long)
1400 "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1402 " Cannot fire in loopback1 mode\n";
1403 fail |= cvmx_error_add(&info);
1405 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1406 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1407 info.status_mask = 1ull<<9 /* an_bad */;
1408 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1409 info.enable_mask = 1ull<<9 /* an_bad_en */;
1411 info.group = CVMX_ERROR_GROUP_ETHERNET;
1412 info.group_index = 1;
1413 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1414 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1415 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1416 info.func = __cvmx_error_display;
1417 info.user_info = (long)
1418 "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1419 " state. Should never be set during normal operation\n";
1420 fail |= cvmx_error_add(&info);
1422 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1423 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1424 info.status_mask = 1ull<<10 /* sync_bad */;
1425 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1426 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1428 info.group = CVMX_ERROR_GROUP_ETHERNET;
1429 info.group_index = 1;
1430 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1431 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1432 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1433 info.func = __cvmx_error_display;
1434 info.user_info = (long)
1435 "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1436 " state. Should never be set during normal operation\n";
1437 fail |= cvmx_error_add(&info);
1439 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1440 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1441 info.status_mask = 1ull<<12 /* dbg_sync */;
1442 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1443 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1445 info.group = CVMX_ERROR_GROUP_ETHERNET;
1446 info.group_index = 1;
1447 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1448 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1449 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1450 info.func = __cvmx_error_display;
1451 info.user_info = (long)
1452 "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1453 fail |= cvmx_error_add(&info);
1455 /* CVMX_PCSX_INTX_REG(2,0) */
1456 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1457 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1458 info.status_mask = 1ull<<2 /* an_err */;
1459 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1460 info.enable_mask = 1ull<<2 /* an_err_en */;
1462 info.group = CVMX_ERROR_GROUP_ETHERNET;
1463 info.group_index = 2;
1464 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1465 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1466 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1467 info.func = __cvmx_error_display;
1468 info.user_info = (long)
1469 "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1470 fail |= cvmx_error_add(&info);
1472 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1473 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1474 info.status_mask = 1ull<<3 /* txfifu */;
1475 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1476 info.enable_mask = 1ull<<3 /* txfifu_en */;
1478 info.group = CVMX_ERROR_GROUP_ETHERNET;
1479 info.group_index = 2;
1480 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1481 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1482 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1483 info.func = __cvmx_error_display;
1484 info.user_info = (long)
1485 "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1487 fail |= cvmx_error_add(&info);
1489 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1490 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1491 info.status_mask = 1ull<<4 /* txfifo */;
1492 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1493 info.enable_mask = 1ull<<4 /* txfifo_en */;
1495 info.group = CVMX_ERROR_GROUP_ETHERNET;
1496 info.group_index = 2;
1497 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1498 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1499 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1500 info.func = __cvmx_error_display;
1501 info.user_info = (long)
1502 "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1504 fail |= cvmx_error_add(&info);
1506 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1507 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1508 info.status_mask = 1ull<<5 /* txbad */;
1509 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1510 info.enable_mask = 1ull<<5 /* txbad_en */;
1512 info.group = CVMX_ERROR_GROUP_ETHERNET;
1513 info.group_index = 2;
1514 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1515 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1516 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1517 info.func = __cvmx_error_display;
1518 info.user_info = (long)
1519 "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1520 " state. Should never be set during normal operation\n";
1521 fail |= cvmx_error_add(&info);
1523 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1524 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1525 info.status_mask = 1ull<<7 /* rxbad */;
1526 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1527 info.enable_mask = 1ull<<7 /* rxbad_en */;
1529 info.group = CVMX_ERROR_GROUP_ETHERNET;
1530 info.group_index = 2;
1531 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1532 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1533 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1534 info.func = __cvmx_error_display;
1535 info.user_info = (long)
1536 "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1537 " state. Should never be set during normal operation\n";
1538 fail |= cvmx_error_add(&info);
1540 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1541 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1542 info.status_mask = 1ull<<8 /* rxlock */;
1543 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1544 info.enable_mask = 1ull<<8 /* rxlock_en */;
1546 info.group = CVMX_ERROR_GROUP_ETHERNET;
1547 info.group_index = 2;
1548 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1549 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1550 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1551 info.func = __cvmx_error_display;
1552 info.user_info = (long)
1553 "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1555 " Cannot fire in loopback1 mode\n";
1556 fail |= cvmx_error_add(&info);
1558 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1559 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1560 info.status_mask = 1ull<<9 /* an_bad */;
1561 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1562 info.enable_mask = 1ull<<9 /* an_bad_en */;
1564 info.group = CVMX_ERROR_GROUP_ETHERNET;
1565 info.group_index = 2;
1566 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1567 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1568 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1569 info.func = __cvmx_error_display;
1570 info.user_info = (long)
1571 "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1572 " state. Should never be set during normal operation\n";
1573 fail |= cvmx_error_add(&info);
1575 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1576 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1577 info.status_mask = 1ull<<10 /* sync_bad */;
1578 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1579 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1581 info.group = CVMX_ERROR_GROUP_ETHERNET;
1582 info.group_index = 2;
1583 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1584 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1585 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1586 info.func = __cvmx_error_display;
1587 info.user_info = (long)
1588 "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1589 " state. Should never be set during normal operation\n";
1590 fail |= cvmx_error_add(&info);
1592 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1593 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1594 info.status_mask = 1ull<<12 /* dbg_sync */;
1595 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1596 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1598 info.group = CVMX_ERROR_GROUP_ETHERNET;
1599 info.group_index = 2;
1600 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1601 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1602 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1603 info.func = __cvmx_error_display;
1604 info.user_info = (long)
1605 "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1606 fail |= cvmx_error_add(&info);
1608 /* CVMX_PCSX_INTX_REG(3,0) */
1609 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1610 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1611 info.status_mask = 1ull<<2 /* an_err */;
1612 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1613 info.enable_mask = 1ull<<2 /* an_err_en */;
1615 info.group = CVMX_ERROR_GROUP_ETHERNET;
1616 info.group_index = 3;
1617 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1618 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1619 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1620 info.func = __cvmx_error_display;
1621 info.user_info = (long)
1622 "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1623 fail |= cvmx_error_add(&info);
1625 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1626 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1627 info.status_mask = 1ull<<3 /* txfifu */;
1628 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1629 info.enable_mask = 1ull<<3 /* txfifu_en */;
1631 info.group = CVMX_ERROR_GROUP_ETHERNET;
1632 info.group_index = 3;
1633 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1634 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1635 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1636 info.func = __cvmx_error_display;
1637 info.user_info = (long)
1638 "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1640 fail |= cvmx_error_add(&info);
1642 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1643 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1644 info.status_mask = 1ull<<4 /* txfifo */;
1645 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1646 info.enable_mask = 1ull<<4 /* txfifo_en */;
1648 info.group = CVMX_ERROR_GROUP_ETHERNET;
1649 info.group_index = 3;
1650 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1651 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1652 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1653 info.func = __cvmx_error_display;
1654 info.user_info = (long)
1655 "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1657 fail |= cvmx_error_add(&info);
1659 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1660 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1661 info.status_mask = 1ull<<5 /* txbad */;
1662 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1663 info.enable_mask = 1ull<<5 /* txbad_en */;
1665 info.group = CVMX_ERROR_GROUP_ETHERNET;
1666 info.group_index = 3;
1667 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1668 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1669 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1670 info.func = __cvmx_error_display;
1671 info.user_info = (long)
1672 "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1673 " state. Should never be set during normal operation\n";
1674 fail |= cvmx_error_add(&info);
1676 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1677 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1678 info.status_mask = 1ull<<7 /* rxbad */;
1679 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1680 info.enable_mask = 1ull<<7 /* rxbad_en */;
1682 info.group = CVMX_ERROR_GROUP_ETHERNET;
1683 info.group_index = 3;
1684 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1685 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1686 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1687 info.func = __cvmx_error_display;
1688 info.user_info = (long)
1689 "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1690 " state. Should never be set during normal operation\n";
1691 fail |= cvmx_error_add(&info);
1693 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1694 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1695 info.status_mask = 1ull<<8 /* rxlock */;
1696 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1697 info.enable_mask = 1ull<<8 /* rxlock_en */;
1699 info.group = CVMX_ERROR_GROUP_ETHERNET;
1700 info.group_index = 3;
1701 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1702 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1703 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1704 info.func = __cvmx_error_display;
1705 info.user_info = (long)
1706 "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1708 " Cannot fire in loopback1 mode\n";
1709 fail |= cvmx_error_add(&info);
1711 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1712 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1713 info.status_mask = 1ull<<9 /* an_bad */;
1714 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1715 info.enable_mask = 1ull<<9 /* an_bad_en */;
1717 info.group = CVMX_ERROR_GROUP_ETHERNET;
1718 info.group_index = 3;
1719 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1720 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1721 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1722 info.func = __cvmx_error_display;
1723 info.user_info = (long)
1724 "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1725 " state. Should never be set during normal operation\n";
1726 fail |= cvmx_error_add(&info);
1728 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1729 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1730 info.status_mask = 1ull<<10 /* sync_bad */;
1731 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1732 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1734 info.group = CVMX_ERROR_GROUP_ETHERNET;
1735 info.group_index = 3;
1736 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1737 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1738 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1739 info.func = __cvmx_error_display;
1740 info.user_info = (long)
1741 "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1742 " state. Should never be set during normal operation\n";
1743 fail |= cvmx_error_add(&info);
1745 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1746 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1747 info.status_mask = 1ull<<12 /* dbg_sync */;
1748 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1749 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1751 info.group = CVMX_ERROR_GROUP_ETHERNET;
1752 info.group_index = 3;
1753 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1754 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1755 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1756 info.func = __cvmx_error_display;
1757 info.user_info = (long)
1758 "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1759 fail |= cvmx_error_add(&info);
1761 /* CVMX_PCSXX_INT_REG(0) */
1762 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1763 info.status_addr = CVMX_PCSXX_INT_REG(0);
1764 info.status_mask = 1ull<<0 /* txflt */;
1765 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1766 info.enable_mask = 1ull<<0 /* txflt_en */;
1768 info.group = CVMX_ERROR_GROUP_ETHERNET;
1769 info.group_index = 0;
1770 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1771 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1772 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1773 info.func = __cvmx_error_display;
1774 info.user_info = (long)
1775 "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
1776 fail |= cvmx_error_add(&info);
1778 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1779 info.status_addr = CVMX_PCSXX_INT_REG(0);
1780 info.status_mask = 1ull<<1 /* rxbad */;
1781 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1782 info.enable_mask = 1ull<<1 /* rxbad_en */;
1784 info.group = CVMX_ERROR_GROUP_ETHERNET;
1785 info.group_index = 0;
1786 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1787 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1788 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1789 info.func = __cvmx_error_display;
1790 info.user_info = (long)
1791 "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
1792 fail |= cvmx_error_add(&info);
1794 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1795 info.status_addr = CVMX_PCSXX_INT_REG(0);
1796 info.status_mask = 1ull<<2 /* rxsynbad */;
1797 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1798 info.enable_mask = 1ull<<2 /* rxsynbad_en */;
1800 info.group = CVMX_ERROR_GROUP_ETHERNET;
1801 info.group_index = 0;
1802 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1803 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1804 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1805 info.func = __cvmx_error_display;
1806 info.user_info = (long)
1807 "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
1808 " in one of the 4 xaui lanes\n";
1809 fail |= cvmx_error_add(&info);
1811 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1812 info.status_addr = CVMX_PCSXX_INT_REG(0);
1813 info.status_mask = 1ull<<4 /* synlos */;
1814 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1815 info.enable_mask = 1ull<<4 /* synlos_en */;
1817 info.group = CVMX_ERROR_GROUP_ETHERNET;
1818 info.group_index = 0;
1819 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1820 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1821 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1822 info.func = __cvmx_error_display;
1823 info.user_info = (long)
1824 "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
1825 fail |= cvmx_error_add(&info);
1827 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1828 info.status_addr = CVMX_PCSXX_INT_REG(0);
1829 info.status_mask = 1ull<<5 /* algnlos */;
1830 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1831 info.enable_mask = 1ull<<5 /* algnlos_en */;
1833 info.group = CVMX_ERROR_GROUP_ETHERNET;
1834 info.group_index = 0;
1835 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1836 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1837 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1838 info.func = __cvmx_error_display;
1839 info.user_info = (long)
1840 "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
1841 fail |= cvmx_error_add(&info);
1843 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1844 info.status_addr = CVMX_PCSXX_INT_REG(0);
1845 info.status_mask = 1ull<<6 /* dbg_sync */;
1846 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1847 info.enable_mask = 1ull<<6 /* dbg_sync_en */;
1849 info.group = CVMX_ERROR_GROUP_ETHERNET;
1850 info.group_index = 0;
1851 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1852 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1853 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1854 info.func = __cvmx_error_display;
1855 info.user_info = (long)
1856 "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
1857 fail |= cvmx_error_add(&info);
1859 /* CVMX_PIP_INT_REG */
1860 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1861 info.status_addr = CVMX_PIP_INT_REG;
1862 info.status_mask = 1ull<<3 /* prtnxa */;
1863 info.enable_addr = CVMX_PIP_INT_EN;
1864 info.enable_mask = 1ull<<3 /* prtnxa */;
1866 info.group = CVMX_ERROR_GROUP_INTERNAL;
1867 info.group_index = 0;
1868 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1869 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1870 info.parent.status_mask = 1ull<<20 /* pip */;
1871 info.func = __cvmx_error_display;
1872 info.user_info = (long)
1873 "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
1874 fail |= cvmx_error_add(&info);
1876 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1877 info.status_addr = CVMX_PIP_INT_REG;
1878 info.status_mask = 1ull<<4 /* badtag */;
1879 info.enable_addr = CVMX_PIP_INT_EN;
1880 info.enable_mask = 1ull<<4 /* badtag */;
1882 info.group = CVMX_ERROR_GROUP_INTERNAL;
1883 info.group_index = 0;
1884 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1885 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1886 info.parent.status_mask = 1ull<<20 /* pip */;
1887 info.func = __cvmx_error_display;
1888 info.user_info = (long)
1889 "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
1890 fail |= cvmx_error_add(&info);
1892 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1893 info.status_addr = CVMX_PIP_INT_REG;
1894 info.status_mask = 1ull<<5 /* skprunt */;
1895 info.enable_addr = CVMX_PIP_INT_EN;
1896 info.enable_mask = 1ull<<5 /* skprunt */;
1898 info.group = CVMX_ERROR_GROUP_INTERNAL;
1899 info.group_index = 0;
1900 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1901 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1902 info.parent.status_mask = 1ull<<20 /* pip */;
1903 info.func = __cvmx_error_display;
1904 info.user_info = (long)
1905 "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
1906 " This interrupt can occur with received PARTIAL\n"
1907 " packets that are truncated to SKIP bytes or\n"
1909 fail |= cvmx_error_add(&info);
1911 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1912 info.status_addr = CVMX_PIP_INT_REG;
1913 info.status_mask = 1ull<<6 /* todoovr */;
1914 info.enable_addr = CVMX_PIP_INT_EN;
1915 info.enable_mask = 1ull<<6 /* todoovr */;
1917 info.group = CVMX_ERROR_GROUP_INTERNAL;
1918 info.group_index = 0;
1919 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1920 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1921 info.parent.status_mask = 1ull<<20 /* pip */;
1922 info.func = __cvmx_error_display;
1923 info.user_info = (long)
1924 "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
1925 fail |= cvmx_error_add(&info);
1927 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1928 info.status_addr = CVMX_PIP_INT_REG;
1929 info.status_mask = 1ull<<7 /* feperr */;
1930 info.enable_addr = CVMX_PIP_INT_EN;
1931 info.enable_mask = 1ull<<7 /* feperr */;
1933 info.group = CVMX_ERROR_GROUP_INTERNAL;
1934 info.group_index = 0;
1935 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1936 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1937 info.parent.status_mask = 1ull<<20 /* pip */;
1938 info.func = __cvmx_error_display;
1939 info.user_info = (long)
1940 "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
1941 fail |= cvmx_error_add(&info);
1943 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1944 info.status_addr = CVMX_PIP_INT_REG;
1945 info.status_mask = 1ull<<8 /* beperr */;
1946 info.enable_addr = CVMX_PIP_INT_EN;
1947 info.enable_mask = 1ull<<8 /* beperr */;
1949 info.group = CVMX_ERROR_GROUP_INTERNAL;
1950 info.group_index = 0;
1951 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1952 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1953 info.parent.status_mask = 1ull<<20 /* pip */;
1954 info.func = __cvmx_error_display;
1955 info.user_info = (long)
1956 "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
1957 fail |= cvmx_error_add(&info);
1959 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1960 info.status_addr = CVMX_PIP_INT_REG;
1961 info.status_mask = 1ull<<12 /* punyerr */;
1962 info.enable_addr = CVMX_PIP_INT_EN;
1963 info.enable_mask = 1ull<<12 /* punyerr */;
1965 info.group = CVMX_ERROR_GROUP_INTERNAL;
1966 info.group_index = 0;
1967 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1968 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1969 info.parent.status_mask = 1ull<<20 /* pip */;
1970 info.func = __cvmx_error_display;
1971 info.user_info = (long)
1972 "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
1973 " stripping in IPD is enable\n";
1974 fail |= cvmx_error_add(&info);
1976 /* CVMX_PKO_REG_ERROR */
1977 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1978 info.status_addr = CVMX_PKO_REG_ERROR;
1979 info.status_mask = 1ull<<0 /* parity */;
1980 info.enable_addr = CVMX_PKO_REG_INT_MASK;
1981 info.enable_mask = 1ull<<0 /* parity */;
1983 info.group = CVMX_ERROR_GROUP_INTERNAL;
1984 info.group_index = 0;
1985 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1986 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1987 info.parent.status_mask = 1ull<<10 /* pko */;
1988 info.func = __cvmx_error_display;
1989 info.user_info = (long)
1990 "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
1991 fail |= cvmx_error_add(&info);
1993 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1994 info.status_addr = CVMX_PKO_REG_ERROR;
1995 info.status_mask = 1ull<<1 /* doorbell */;
1996 info.enable_addr = CVMX_PKO_REG_INT_MASK;
1997 info.enable_mask = 1ull<<1 /* doorbell */;
1999 info.group = CVMX_ERROR_GROUP_INTERNAL;
2000 info.group_index = 0;
2001 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2002 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2003 info.parent.status_mask = 1ull<<10 /* pko */;
2004 info.func = __cvmx_error_display;
2005 info.user_info = (long)
2006 "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
2007 fail |= cvmx_error_add(&info);
2009 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2010 info.status_addr = CVMX_PKO_REG_ERROR;
2011 info.status_mask = 1ull<<2 /* currzero */;
2012 info.enable_addr = CVMX_PKO_REG_INT_MASK;
2013 info.enable_mask = 1ull<<2 /* currzero */;
2015 info.group = CVMX_ERROR_GROUP_INTERNAL;
2016 info.group_index = 0;
2017 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2018 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2019 info.parent.status_mask = 1ull<<10 /* pko */;
2020 info.func = __cvmx_error_display;
2021 info.user_info = (long)
2022 "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
2023 fail |= cvmx_error_add(&info);
2025 /* CVMX_PEMX_INT_SUM(0) */
2026 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2027 info.status_addr = CVMX_PEMX_INT_SUM(0);
2028 info.status_mask = 1ull<<1 /* se */;
2029 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2030 info.enable_mask = 1ull<<1 /* se */;
2032 info.group = CVMX_ERROR_GROUP_PCI;
2033 info.group_index = 0;
2034 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2035 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2036 info.parent.status_mask = 1ull<<25 /* pem0 */;
2037 info.func = __cvmx_error_display;
2038 info.user_info = (long)
2039 "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
2040 " (cfg_sys_err_rc)\n";
2041 fail |= cvmx_error_add(&info);
2043 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2044 info.status_addr = CVMX_PEMX_INT_SUM(0);
2045 info.status_mask = 1ull<<4 /* up_b1 */;
2046 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2047 info.enable_mask = 1ull<<4 /* up_b1 */;
2049 info.group = CVMX_ERROR_GROUP_PCI;
2050 info.group_index = 0;
2051 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2052 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2053 info.parent.status_mask = 1ull<<25 /* pem0 */;
2054 info.func = __cvmx_error_display;
2055 info.user_info = (long)
2056 "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
2058 fail |= cvmx_error_add(&info);
2060 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2061 info.status_addr = CVMX_PEMX_INT_SUM(0);
2062 info.status_mask = 1ull<<5 /* up_b2 */;
2063 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2064 info.enable_mask = 1ull<<5 /* up_b2 */;
2066 info.group = CVMX_ERROR_GROUP_PCI;
2067 info.group_index = 0;
2068 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2069 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2070 info.parent.status_mask = 1ull<<25 /* pem0 */;
2071 info.func = __cvmx_error_display;
2072 info.user_info = (long)
2073 "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
2074 fail |= cvmx_error_add(&info);
2076 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2077 info.status_addr = CVMX_PEMX_INT_SUM(0);
2078 info.status_mask = 1ull<<6 /* up_bx */;
2079 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2080 info.enable_mask = 1ull<<6 /* up_bx */;
2082 info.group = CVMX_ERROR_GROUP_PCI;
2083 info.group_index = 0;
2084 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2085 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2086 info.parent.status_mask = 1ull<<25 /* pem0 */;
2087 info.func = __cvmx_error_display;
2088 info.user_info = (long)
2089 "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
2090 fail |= cvmx_error_add(&info);
2092 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2093 info.status_addr = CVMX_PEMX_INT_SUM(0);
2094 info.status_mask = 1ull<<7 /* un_b1 */;
2095 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2096 info.enable_mask = 1ull<<7 /* un_b1 */;
2098 info.group = CVMX_ERROR_GROUP_PCI;
2099 info.group_index = 0;
2100 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2101 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2102 info.parent.status_mask = 1ull<<25 /* pem0 */;
2103 info.func = __cvmx_error_display;
2104 info.user_info = (long)
2105 "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
2107 fail |= cvmx_error_add(&info);
2109 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2110 info.status_addr = CVMX_PEMX_INT_SUM(0);
2111 info.status_mask = 1ull<<8 /* un_b2 */;
2112 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2113 info.enable_mask = 1ull<<8 /* un_b2 */;
2115 info.group = CVMX_ERROR_GROUP_PCI;
2116 info.group_index = 0;
2117 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2118 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2119 info.parent.status_mask = 1ull<<25 /* pem0 */;
2120 info.func = __cvmx_error_display;
2121 info.user_info = (long)
2122 "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
2123 fail |= cvmx_error_add(&info);
2125 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2126 info.status_addr = CVMX_PEMX_INT_SUM(0);
2127 info.status_mask = 1ull<<9 /* un_bx */;
2128 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2129 info.enable_mask = 1ull<<9 /* un_bx */;
2131 info.group = CVMX_ERROR_GROUP_PCI;
2132 info.group_index = 0;
2133 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2134 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2135 info.parent.status_mask = 1ull<<25 /* pem0 */;
2136 info.func = __cvmx_error_display;
2137 info.user_info = (long)
2138 "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
2139 fail |= cvmx_error_add(&info);
2141 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2142 info.status_addr = CVMX_PEMX_INT_SUM(0);
2143 info.status_mask = 1ull<<11 /* rdlk */;
2144 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2145 info.enable_mask = 1ull<<11 /* rdlk */;
2147 info.group = CVMX_ERROR_GROUP_PCI;
2148 info.group_index = 0;
2149 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2150 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2151 info.parent.status_mask = 1ull<<25 /* pem0 */;
2152 info.func = __cvmx_error_display;
2153 info.user_info = (long)
2154 "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
2155 fail |= cvmx_error_add(&info);
2157 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2158 info.status_addr = CVMX_PEMX_INT_SUM(0);
2159 info.status_mask = 1ull<<12 /* crs_er */;
2160 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2161 info.enable_mask = 1ull<<12 /* crs_er */;
2163 info.group = CVMX_ERROR_GROUP_PCI;
2164 info.group_index = 0;
2165 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2166 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2167 info.parent.status_mask = 1ull<<25 /* pem0 */;
2168 info.func = __cvmx_error_display;
2169 info.user_info = (long)
2170 "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
2171 fail |= cvmx_error_add(&info);
2173 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2174 info.status_addr = CVMX_PEMX_INT_SUM(0);
2175 info.status_mask = 1ull<<13 /* crs_dr */;
2176 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2177 info.enable_mask = 1ull<<13 /* crs_dr */;
2179 info.group = CVMX_ERROR_GROUP_PCI;
2180 info.group_index = 0;
2181 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2182 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2183 info.parent.status_mask = 1ull<<25 /* pem0 */;
2184 info.func = __cvmx_error_display;
2185 info.user_info = (long)
2186 "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
2187 fail |= cvmx_error_add(&info);
2189 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2190 info.status_addr = CVMX_PEMX_INT_SUM(0);
2191 info.status_mask = 0;
2192 info.enable_addr = 0;
2193 info.enable_mask = 0;
2195 info.group = CVMX_ERROR_GROUP_INTERNAL;
2196 info.group_index = 0;
2197 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2198 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2199 info.parent.status_mask = 1ull<<25 /* pem0 */;
2200 info.func = __cvmx_error_decode;
2202 fail |= cvmx_error_add(&info);
2204 /* CVMX_PEMX_DBG_INFO(0) */
2205 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2206 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2207 info.status_mask = 1ull<<0 /* spoison */;
2208 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2209 info.enable_mask = 1ull<<0 /* spoison */;
2211 info.group = CVMX_ERROR_GROUP_PCI;
2212 info.group_index = 0;
2213 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2214 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2215 info.parent.status_mask = 1ull<<10 /* exc */;
2216 info.func = __cvmx_error_display;
2217 info.user_info = (long)
2218 "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
2219 " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
2220 fail |= cvmx_error_add(&info);
2222 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2223 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2224 info.status_mask = 1ull<<2 /* rtlplle */;
2225 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2226 info.enable_mask = 1ull<<2 /* rtlplle */;
2228 info.group = CVMX_ERROR_GROUP_PCI;
2229 info.group_index = 0;
2230 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2231 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2232 info.parent.status_mask = 1ull<<10 /* exc */;
2233 info.func = __cvmx_error_display;
2234 info.user_info = (long)
2235 "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
2236 " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
2237 fail |= cvmx_error_add(&info);
2239 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2240 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2241 info.status_mask = 1ull<<3 /* recrce */;
2242 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2243 info.enable_mask = 1ull<<3 /* recrce */;
2245 info.group = CVMX_ERROR_GROUP_PCI;
2246 info.group_index = 0;
2247 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2248 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2249 info.parent.status_mask = 1ull<<10 /* exc */;
2250 info.func = __cvmx_error_display;
2251 info.user_info = (long)
2252 "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
2253 " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
2254 fail |= cvmx_error_add(&info);
2256 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2257 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2258 info.status_mask = 1ull<<4 /* rpoison */;
2259 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2260 info.enable_mask = 1ull<<4 /* rpoison */;
2262 info.group = CVMX_ERROR_GROUP_PCI;
2263 info.group_index = 0;
2264 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2265 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2266 info.parent.status_mask = 1ull<<10 /* exc */;
2267 info.func = __cvmx_error_display;
2268 info.user_info = (long)
2269 "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
2270 " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
2271 fail |= cvmx_error_add(&info);
2273 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2274 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2275 info.status_mask = 1ull<<5 /* rcemrc */;
2276 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2277 info.enable_mask = 1ull<<5 /* rcemrc */;
2279 info.group = CVMX_ERROR_GROUP_PCI;
2280 info.group_index = 0;
2281 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2282 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2283 info.parent.status_mask = 1ull<<10 /* exc */;
2284 info.func = __cvmx_error_display;
2285 info.user_info = (long)
2286 "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
2287 " pedc_radm_correctable_err\n";
2288 fail |= cvmx_error_add(&info);
2290 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2291 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2292 info.status_mask = 1ull<<6 /* rnfemrc */;
2293 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2294 info.enable_mask = 1ull<<6 /* rnfemrc */;
2296 info.group = CVMX_ERROR_GROUP_PCI;
2297 info.group_index = 0;
2298 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2299 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2300 info.parent.status_mask = 1ull<<10 /* exc */;
2301 info.func = __cvmx_error_display;
2302 info.user_info = (long)
2303 "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
2304 " pedc_radm_nonfatal_err\n";
2305 fail |= cvmx_error_add(&info);
2307 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2308 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2309 info.status_mask = 1ull<<7 /* rfemrc */;
2310 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2311 info.enable_mask = 1ull<<7 /* rfemrc */;
2313 info.group = CVMX_ERROR_GROUP_PCI;
2314 info.group_index = 0;
2315 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2316 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2317 info.parent.status_mask = 1ull<<10 /* exc */;
2318 info.func = __cvmx_error_display;
2319 info.user_info = (long)
2320 "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
2321 " pedc_radm_fatal_err\n"
2322 " Bit set when a message with ERR_FATAL is set.\n";
2323 fail |= cvmx_error_add(&info);
2325 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2326 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2327 info.status_mask = 1ull<<8 /* rpmerc */;
2328 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2329 info.enable_mask = 1ull<<8 /* rpmerc */;
2331 info.group = CVMX_ERROR_GROUP_PCI;
2332 info.group_index = 0;
2333 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2334 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2335 info.parent.status_mask = 1ull<<10 /* exc */;
2336 info.func = __cvmx_error_display;
2337 info.user_info = (long)
2338 "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
2339 " pedc_radm_pm_pme\n";
2340 fail |= cvmx_error_add(&info);
2342 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2343 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2344 info.status_mask = 1ull<<9 /* rptamrc */;
2345 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2346 info.enable_mask = 1ull<<9 /* rptamrc */;
2348 info.group = CVMX_ERROR_GROUP_PCI;
2349 info.group_index = 0;
2350 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2351 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2352 info.parent.status_mask = 1ull<<10 /* exc */;
2353 info.func = __cvmx_error_display;
2354 info.user_info = (long)
2355 "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
2357 " pedc_radm_pm_to_ack\n";
2358 fail |= cvmx_error_add(&info);
2360 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2361 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2362 info.status_mask = 1ull<<10 /* rumep */;
2363 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2364 info.enable_mask = 1ull<<10 /* rumep */;
2366 info.group = CVMX_ERROR_GROUP_PCI;
2367 info.group_index = 0;
2368 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2369 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2370 info.parent.status_mask = 1ull<<10 /* exc */;
2371 info.func = __cvmx_error_display;
2372 info.user_info = (long)
2373 "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
2374 " pedc_radm_msg_unlock\n";
2375 fail |= cvmx_error_add(&info);
2377 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2378 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2379 info.status_mask = 1ull<<11 /* rvdm */;
2380 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2381 info.enable_mask = 1ull<<11 /* rvdm */;
2383 info.group = CVMX_ERROR_GROUP_PCI;
2384 info.group_index = 0;
2385 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2386 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2387 info.parent.status_mask = 1ull<<10 /* exc */;
2388 info.func = __cvmx_error_display;
2389 info.user_info = (long)
2390 "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
2391 " pedc_radm_vendor_msg\n";
2392 fail |= cvmx_error_add(&info);
2394 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2395 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2396 info.status_mask = 1ull<<12 /* acto */;
2397 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2398 info.enable_mask = 1ull<<12 /* acto */;
2400 info.group = CVMX_ERROR_GROUP_PCI;
2401 info.group_index = 0;
2402 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2403 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2404 info.parent.status_mask = 1ull<<10 /* exc */;
2405 info.func = __cvmx_error_display;
2406 info.user_info = (long)
2407 "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
2408 " pedc_radm_cpl_timeout\n";
2409 fail |= cvmx_error_add(&info);
2411 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2412 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2413 info.status_mask = 1ull<<13 /* rte */;
2414 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2415 info.enable_mask = 1ull<<13 /* rte */;
2417 info.group = CVMX_ERROR_GROUP_PCI;
2418 info.group_index = 0;
2419 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2420 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2421 info.parent.status_mask = 1ull<<10 /* exc */;
2422 info.func = __cvmx_error_display;
2423 info.user_info = (long)
2424 "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
2425 " xdlh_replay_timeout_err\n"
2426 " This bit is set when the REPLAY_TIMER expires in\n"
2427 " the PCIE core. The probability of this bit being\n"
2428 " set will increase with the traffic load.\n";
2429 fail |= cvmx_error_add(&info);
2431 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2432 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2433 info.status_mask = 1ull<<14 /* mre */;
2434 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2435 info.enable_mask = 1ull<<14 /* mre */;
2437 info.group = CVMX_ERROR_GROUP_PCI;
2438 info.group_index = 0;
2439 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2440 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2441 info.parent.status_mask = 1ull<<10 /* exc */;
2442 info.func = __cvmx_error_display;
2443 info.user_info = (long)
2444 "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
2445 " xdlh_replay_num_rlover_err\n";
2446 fail |= cvmx_error_add(&info);
2448 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2449 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2450 info.status_mask = 1ull<<15 /* rdwdle */;
2451 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2452 info.enable_mask = 1ull<<15 /* rdwdle */;
2454 info.group = CVMX_ERROR_GROUP_PCI;
2455 info.group_index = 0;
2456 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2457 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2458 info.parent.status_mask = 1ull<<10 /* exc */;
2459 info.func = __cvmx_error_display;
2460 info.user_info = (long)
2461 "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
2462 " rdlh_bad_dllp_err\n";
2463 fail |= cvmx_error_add(&info);
2465 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2466 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2467 info.status_mask = 1ull<<16 /* rtwdle */;
2468 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2469 info.enable_mask = 1ull<<16 /* rtwdle */;
2471 info.group = CVMX_ERROR_GROUP_PCI;
2472 info.group_index = 0;
2473 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2474 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2475 info.parent.status_mask = 1ull<<10 /* exc */;
2476 info.func = __cvmx_error_display;
2477 info.user_info = (long)
2478 "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
2479 " rdlh_bad_tlp_err\n";
2480 fail |= cvmx_error_add(&info);
2482 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2483 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2484 info.status_mask = 1ull<<17 /* dpeoosd */;
2485 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2486 info.enable_mask = 1ull<<17 /* dpeoosd */;
2488 info.group = CVMX_ERROR_GROUP_PCI;
2489 info.group_index = 0;
2490 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2491 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2492 info.parent.status_mask = 1ull<<10 /* exc */;
2493 info.func = __cvmx_error_display;
2494 info.user_info = (long)
2495 "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
2497 fail |= cvmx_error_add(&info);
2499 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2500 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2501 info.status_mask = 1ull<<18 /* fcpvwt */;
2502 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2503 info.enable_mask = 1ull<<18 /* fcpvwt */;
2505 info.group = CVMX_ERROR_GROUP_PCI;
2506 info.group_index = 0;
2507 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2508 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2509 info.parent.status_mask = 1ull<<10 /* exc */;
2510 info.func = __cvmx_error_display;
2511 info.user_info = (long)
2512 "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
2513 " rtlh_fc_prot_err\n";
2514 fail |= cvmx_error_add(&info);
2516 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2517 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2518 info.status_mask = 1ull<<19 /* rpe */;
2519 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2520 info.enable_mask = 1ull<<19 /* rpe */;
2522 info.group = CVMX_ERROR_GROUP_PCI;
2523 info.group_index = 0;
2524 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2525 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2526 info.parent.status_mask = 1ull<<10 /* exc */;
2527 info.func = __cvmx_error_display;
2528 info.user_info = (long)
2529 "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
2530 " (RxStatus = 3b100) or disparity error\n"
2531 " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
2534 fail |= cvmx_error_add(&info);
2536 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2537 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2538 info.status_mask = 1ull<<20 /* fcuv */;
2539 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2540 info.enable_mask = 1ull<<20 /* fcuv */;
2542 info.group = CVMX_ERROR_GROUP_PCI;
2543 info.group_index = 0;
2544 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2545 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2546 info.parent.status_mask = 1ull<<10 /* exc */;
2547 info.func = __cvmx_error_display;
2548 info.user_info = (long)
2549 "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
2550 " int_xadm_fc_prot_err\n";
2551 fail |= cvmx_error_add(&info);
2553 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2554 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2555 info.status_mask = 1ull<<21 /* rqo */;
2556 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2557 info.enable_mask = 1ull<<21 /* rqo */;
2559 info.group = CVMX_ERROR_GROUP_PCI;
2560 info.group_index = 0;
2561 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2562 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2563 info.parent.status_mask = 1ull<<10 /* exc */;
2564 info.func = __cvmx_error_display;
2565 info.user_info = (long)
2566 "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
2567 " flow control advertisements are ignored\n"
2568 " radm_qoverflow\n";
2569 fail |= cvmx_error_add(&info);
2571 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2572 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2573 info.status_mask = 1ull<<22 /* rauc */;
2574 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2575 info.enable_mask = 1ull<<22 /* rauc */;
2577 info.group = CVMX_ERROR_GROUP_PCI;
2578 info.group_index = 0;
2579 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2580 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2581 info.parent.status_mask = 1ull<<10 /* exc */;
2582 info.func = __cvmx_error_display;
2583 info.user_info = (long)
2584 "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
2585 " radm_unexp_cpl_err\n";
2586 fail |= cvmx_error_add(&info);
2588 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2589 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2590 info.status_mask = 1ull<<23 /* racur */;
2591 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2592 info.enable_mask = 1ull<<23 /* racur */;
2594 info.group = CVMX_ERROR_GROUP_PCI;
2595 info.group_index = 0;
2596 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2597 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2598 info.parent.status_mask = 1ull<<10 /* exc */;
2599 info.func = __cvmx_error_display;
2600 info.user_info = (long)
2601 "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
2602 " radm_rcvd_cpl_ur\n";
2603 fail |= cvmx_error_add(&info);
2605 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2606 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2607 info.status_mask = 1ull<<24 /* racca */;
2608 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2609 info.enable_mask = 1ull<<24 /* racca */;
2611 info.group = CVMX_ERROR_GROUP_PCI;
2612 info.group_index = 0;
2613 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2614 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2615 info.parent.status_mask = 1ull<<10 /* exc */;
2616 info.func = __cvmx_error_display;
2617 info.user_info = (long)
2618 "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
2619 " radm_rcvd_cpl_ca\n";
2620 fail |= cvmx_error_add(&info);
2622 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2623 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2624 info.status_mask = 1ull<<25 /* caar */;
2625 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2626 info.enable_mask = 1ull<<25 /* caar */;
2628 info.group = CVMX_ERROR_GROUP_PCI;
2629 info.group_index = 0;
2630 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2631 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2632 info.parent.status_mask = 1ull<<10 /* exc */;
2633 info.func = __cvmx_error_display;
2634 info.user_info = (long)
2635 "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
2636 " radm_rcvd_ca_req\n"
2637 " This bit will never be set because Octeon does\n"
2638 " not generate Completer Aborts.\n";
2639 fail |= cvmx_error_add(&info);
2641 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2642 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2643 info.status_mask = 1ull<<26 /* rarwdns */;
2644 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2645 info.enable_mask = 1ull<<26 /* rarwdns */;
2647 info.group = CVMX_ERROR_GROUP_PCI;
2648 info.group_index = 0;
2649 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2650 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2651 info.parent.status_mask = 1ull<<10 /* exc */;
2652 info.func = __cvmx_error_display;
2653 info.user_info = (long)
2654 "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
2655 " radm_rcvd_ur_req\n";
2656 fail |= cvmx_error_add(&info);
2658 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2659 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2660 info.status_mask = 1ull<<27 /* ramtlp */;
2661 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2662 info.enable_mask = 1ull<<27 /* ramtlp */;
2664 info.group = CVMX_ERROR_GROUP_PCI;
2665 info.group_index = 0;
2666 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2667 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2668 info.parent.status_mask = 1ull<<10 /* exc */;
2669 info.func = __cvmx_error_display;
2670 info.user_info = (long)
2671 "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
2672 " radm_mlf_tlp_err\n";
2673 fail |= cvmx_error_add(&info);
2675 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2676 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2677 info.status_mask = 1ull<<28 /* racpp */;
2678 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2679 info.enable_mask = 1ull<<28 /* racpp */;
2681 info.group = CVMX_ERROR_GROUP_PCI;
2682 info.group_index = 0;
2683 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2684 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2685 info.parent.status_mask = 1ull<<10 /* exc */;
2686 info.func = __cvmx_error_display;
2687 info.user_info = (long)
2688 "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
2689 " radm_rcvd_cpl_poisoned\n";
2690 fail |= cvmx_error_add(&info);
2692 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2693 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2694 info.status_mask = 1ull<<29 /* rawwpp */;
2695 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2696 info.enable_mask = 1ull<<29 /* rawwpp */;
2698 info.group = CVMX_ERROR_GROUP_PCI;
2699 info.group_index = 0;
2700 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2701 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2702 info.parent.status_mask = 1ull<<10 /* exc */;
2703 info.func = __cvmx_error_display;
2704 info.user_info = (long)
2705 "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
2706 " radm_rcvd_wreq_poisoned\n";
2707 fail |= cvmx_error_add(&info);
2709 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2710 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2711 info.status_mask = 1ull<<30 /* ecrc_e */;
2712 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2713 info.enable_mask = 1ull<<30 /* ecrc_e */;
2715 info.group = CVMX_ERROR_GROUP_PCI;
2716 info.group_index = 0;
2717 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2718 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2719 info.parent.status_mask = 1ull<<10 /* exc */;
2720 info.func = __cvmx_error_display;
2721 info.user_info = (long)
2722 "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
2724 fail |= cvmx_error_add(&info);
2726 /* CVMX_PEMX_INT_SUM(1) */
2727 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2728 info.status_addr = CVMX_PEMX_INT_SUM(1);
2729 info.status_mask = 1ull<<1 /* se */;
2730 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2731 info.enable_mask = 1ull<<1 /* se */;
2733 info.group = CVMX_ERROR_GROUP_PCI;
2734 info.group_index = 1;
2735 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2736 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2737 info.parent.status_mask = 1ull<<26 /* pem1 */;
2738 info.func = __cvmx_error_display;
2739 info.user_info = (long)
2740 "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
2741 " (cfg_sys_err_rc)\n";
2742 fail |= cvmx_error_add(&info);
2744 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2745 info.status_addr = CVMX_PEMX_INT_SUM(1);
2746 info.status_mask = 1ull<<4 /* up_b1 */;
2747 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2748 info.enable_mask = 1ull<<4 /* up_b1 */;
2750 info.group = CVMX_ERROR_GROUP_PCI;
2751 info.group_index = 1;
2752 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2753 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2754 info.parent.status_mask = 1ull<<26 /* pem1 */;
2755 info.func = __cvmx_error_display;
2756 info.user_info = (long)
2757 "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
2759 fail |= cvmx_error_add(&info);
2761 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2762 info.status_addr = CVMX_PEMX_INT_SUM(1);
2763 info.status_mask = 1ull<<5 /* up_b2 */;
2764 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2765 info.enable_mask = 1ull<<5 /* up_b2 */;
2767 info.group = CVMX_ERROR_GROUP_PCI;
2768 info.group_index = 1;
2769 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2770 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2771 info.parent.status_mask = 1ull<<26 /* pem1 */;
2772 info.func = __cvmx_error_display;
2773 info.user_info = (long)
2774 "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
2775 fail |= cvmx_error_add(&info);
2777 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2778 info.status_addr = CVMX_PEMX_INT_SUM(1);
2779 info.status_mask = 1ull<<6 /* up_bx */;
2780 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2781 info.enable_mask = 1ull<<6 /* up_bx */;
2783 info.group = CVMX_ERROR_GROUP_PCI;
2784 info.group_index = 1;
2785 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2786 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2787 info.parent.status_mask = 1ull<<26 /* pem1 */;
2788 info.func = __cvmx_error_display;
2789 info.user_info = (long)
2790 "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
2791 fail |= cvmx_error_add(&info);
2793 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2794 info.status_addr = CVMX_PEMX_INT_SUM(1);
2795 info.status_mask = 1ull<<7 /* un_b1 */;
2796 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2797 info.enable_mask = 1ull<<7 /* un_b1 */;
2799 info.group = CVMX_ERROR_GROUP_PCI;
2800 info.group_index = 1;
2801 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2802 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2803 info.parent.status_mask = 1ull<<26 /* pem1 */;
2804 info.func = __cvmx_error_display;
2805 info.user_info = (long)
2806 "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
2808 fail |= cvmx_error_add(&info);
2810 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2811 info.status_addr = CVMX_PEMX_INT_SUM(1);
2812 info.status_mask = 1ull<<8 /* un_b2 */;
2813 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2814 info.enable_mask = 1ull<<8 /* un_b2 */;
2816 info.group = CVMX_ERROR_GROUP_PCI;
2817 info.group_index = 1;
2818 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2819 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2820 info.parent.status_mask = 1ull<<26 /* pem1 */;
2821 info.func = __cvmx_error_display;
2822 info.user_info = (long)
2823 "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
2824 fail |= cvmx_error_add(&info);
2826 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2827 info.status_addr = CVMX_PEMX_INT_SUM(1);
2828 info.status_mask = 1ull<<9 /* un_bx */;
2829 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2830 info.enable_mask = 1ull<<9 /* un_bx */;
2832 info.group = CVMX_ERROR_GROUP_PCI;
2833 info.group_index = 1;
2834 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2835 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2836 info.parent.status_mask = 1ull<<26 /* pem1 */;
2837 info.func = __cvmx_error_display;
2838 info.user_info = (long)
2839 "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
2840 fail |= cvmx_error_add(&info);
2842 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2843 info.status_addr = CVMX_PEMX_INT_SUM(1);
2844 info.status_mask = 1ull<<11 /* rdlk */;
2845 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2846 info.enable_mask = 1ull<<11 /* rdlk */;
2848 info.group = CVMX_ERROR_GROUP_PCI;
2849 info.group_index = 1;
2850 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2851 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2852 info.parent.status_mask = 1ull<<26 /* pem1 */;
2853 info.func = __cvmx_error_display;
2854 info.user_info = (long)
2855 "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
2856 fail |= cvmx_error_add(&info);
2858 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2859 info.status_addr = CVMX_PEMX_INT_SUM(1);
2860 info.status_mask = 1ull<<12 /* crs_er */;
2861 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2862 info.enable_mask = 1ull<<12 /* crs_er */;
2864 info.group = CVMX_ERROR_GROUP_PCI;
2865 info.group_index = 1;
2866 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2867 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2868 info.parent.status_mask = 1ull<<26 /* pem1 */;
2869 info.func = __cvmx_error_display;
2870 info.user_info = (long)
2871 "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
2872 fail |= cvmx_error_add(&info);
2874 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2875 info.status_addr = CVMX_PEMX_INT_SUM(1);
2876 info.status_mask = 1ull<<13 /* crs_dr */;
2877 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2878 info.enable_mask = 1ull<<13 /* crs_dr */;
2880 info.group = CVMX_ERROR_GROUP_PCI;
2881 info.group_index = 1;
2882 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2883 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2884 info.parent.status_mask = 1ull<<26 /* pem1 */;
2885 info.func = __cvmx_error_display;
2886 info.user_info = (long)
2887 "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
2888 fail |= cvmx_error_add(&info);
2890 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2891 info.status_addr = CVMX_PEMX_INT_SUM(1);
2892 info.status_mask = 0;
2893 info.enable_addr = 0;
2894 info.enable_mask = 0;
2896 info.group = CVMX_ERROR_GROUP_INTERNAL;
2897 info.group_index = 0;
2898 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2899 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2900 info.parent.status_mask = 1ull<<26 /* pem1 */;
2901 info.func = __cvmx_error_decode;
2903 fail |= cvmx_error_add(&info);
2905 /* CVMX_PEMX_DBG_INFO(1) */
2906 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2907 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2908 info.status_mask = 1ull<<0 /* spoison */;
2909 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2910 info.enable_mask = 1ull<<0 /* spoison */;
2912 info.group = CVMX_ERROR_GROUP_PCI;
2913 info.group_index = 1;
2914 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2915 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2916 info.parent.status_mask = 1ull<<10 /* exc */;
2917 info.func = __cvmx_error_display;
2918 info.user_info = (long)
2919 "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
2920 " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
2921 fail |= cvmx_error_add(&info);
2923 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2924 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2925 info.status_mask = 1ull<<2 /* rtlplle */;
2926 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2927 info.enable_mask = 1ull<<2 /* rtlplle */;
2929 info.group = CVMX_ERROR_GROUP_PCI;
2930 info.group_index = 1;
2931 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2932 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2933 info.parent.status_mask = 1ull<<10 /* exc */;
2934 info.func = __cvmx_error_display;
2935 info.user_info = (long)
2936 "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
2937 " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
2938 fail |= cvmx_error_add(&info);
2940 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2941 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2942 info.status_mask = 1ull<<3 /* recrce */;
2943 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2944 info.enable_mask = 1ull<<3 /* recrce */;
2946 info.group = CVMX_ERROR_GROUP_PCI;
2947 info.group_index = 1;
2948 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2949 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2950 info.parent.status_mask = 1ull<<10 /* exc */;
2951 info.func = __cvmx_error_display;
2952 info.user_info = (long)
2953 "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
2954 " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
2955 fail |= cvmx_error_add(&info);
2957 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2958 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2959 info.status_mask = 1ull<<4 /* rpoison */;
2960 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2961 info.enable_mask = 1ull<<4 /* rpoison */;
2963 info.group = CVMX_ERROR_GROUP_PCI;
2964 info.group_index = 1;
2965 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2966 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2967 info.parent.status_mask = 1ull<<10 /* exc */;
2968 info.func = __cvmx_error_display;
2969 info.user_info = (long)
2970 "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
2971 " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
2972 fail |= cvmx_error_add(&info);
2974 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2975 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2976 info.status_mask = 1ull<<5 /* rcemrc */;
2977 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2978 info.enable_mask = 1ull<<5 /* rcemrc */;
2980 info.group = CVMX_ERROR_GROUP_PCI;
2981 info.group_index = 1;
2982 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2983 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2984 info.parent.status_mask = 1ull<<10 /* exc */;
2985 info.func = __cvmx_error_display;
2986 info.user_info = (long)
2987 "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
2988 " pedc_radm_correctable_err\n";
2989 fail |= cvmx_error_add(&info);
2991 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2992 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2993 info.status_mask = 1ull<<6 /* rnfemrc */;
2994 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2995 info.enable_mask = 1ull<<6 /* rnfemrc */;
2997 info.group = CVMX_ERROR_GROUP_PCI;
2998 info.group_index = 1;
2999 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3000 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3001 info.parent.status_mask = 1ull<<10 /* exc */;
3002 info.func = __cvmx_error_display;
3003 info.user_info = (long)
3004 "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
3005 " pedc_radm_nonfatal_err\n";
3006 fail |= cvmx_error_add(&info);
3008 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3009 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3010 info.status_mask = 1ull<<7 /* rfemrc */;
3011 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3012 info.enable_mask = 1ull<<7 /* rfemrc */;
3014 info.group = CVMX_ERROR_GROUP_PCI;
3015 info.group_index = 1;
3016 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3017 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3018 info.parent.status_mask = 1ull<<10 /* exc */;
3019 info.func = __cvmx_error_display;
3020 info.user_info = (long)
3021 "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
3022 " pedc_radm_fatal_err\n"
3023 " Bit set when a message with ERR_FATAL is set.\n";
3024 fail |= cvmx_error_add(&info);
3026 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3027 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3028 info.status_mask = 1ull<<8 /* rpmerc */;
3029 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3030 info.enable_mask = 1ull<<8 /* rpmerc */;
3032 info.group = CVMX_ERROR_GROUP_PCI;
3033 info.group_index = 1;
3034 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3035 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3036 info.parent.status_mask = 1ull<<10 /* exc */;
3037 info.func = __cvmx_error_display;
3038 info.user_info = (long)
3039 "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
3040 " pedc_radm_pm_pme\n";
3041 fail |= cvmx_error_add(&info);
3043 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3044 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3045 info.status_mask = 1ull<<9 /* rptamrc */;
3046 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3047 info.enable_mask = 1ull<<9 /* rptamrc */;
3049 info.group = CVMX_ERROR_GROUP_PCI;
3050 info.group_index = 1;
3051 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3052 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3053 info.parent.status_mask = 1ull<<10 /* exc */;
3054 info.func = __cvmx_error_display;
3055 info.user_info = (long)
3056 "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
3058 " pedc_radm_pm_to_ack\n";
3059 fail |= cvmx_error_add(&info);
3061 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3062 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3063 info.status_mask = 1ull<<10 /* rumep */;
3064 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3065 info.enable_mask = 1ull<<10 /* rumep */;
3067 info.group = CVMX_ERROR_GROUP_PCI;
3068 info.group_index = 1;
3069 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3070 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3071 info.parent.status_mask = 1ull<<10 /* exc */;
3072 info.func = __cvmx_error_display;
3073 info.user_info = (long)
3074 "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
3075 " pedc_radm_msg_unlock\n";
3076 fail |= cvmx_error_add(&info);
3078 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3079 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3080 info.status_mask = 1ull<<11 /* rvdm */;
3081 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3082 info.enable_mask = 1ull<<11 /* rvdm */;
3084 info.group = CVMX_ERROR_GROUP_PCI;
3085 info.group_index = 1;
3086 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3087 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3088 info.parent.status_mask = 1ull<<10 /* exc */;
3089 info.func = __cvmx_error_display;
3090 info.user_info = (long)
3091 "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
3092 " pedc_radm_vendor_msg\n";
3093 fail |= cvmx_error_add(&info);
3095 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3096 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3097 info.status_mask = 1ull<<12 /* acto */;
3098 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3099 info.enable_mask = 1ull<<12 /* acto */;
3101 info.group = CVMX_ERROR_GROUP_PCI;
3102 info.group_index = 1;
3103 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3104 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3105 info.parent.status_mask = 1ull<<10 /* exc */;
3106 info.func = __cvmx_error_display;
3107 info.user_info = (long)
3108 "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
3109 " pedc_radm_cpl_timeout\n";
3110 fail |= cvmx_error_add(&info);
3112 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3113 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3114 info.status_mask = 1ull<<13 /* rte */;
3115 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3116 info.enable_mask = 1ull<<13 /* rte */;
3118 info.group = CVMX_ERROR_GROUP_PCI;
3119 info.group_index = 1;
3120 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3121 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3122 info.parent.status_mask = 1ull<<10 /* exc */;
3123 info.func = __cvmx_error_display;
3124 info.user_info = (long)
3125 "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
3126 " xdlh_replay_timeout_err\n"
3127 " This bit is set when the REPLAY_TIMER expires in\n"
3128 " the PCIE core. The probability of this bit being\n"
3129 " set will increase with the traffic load.\n";
3130 fail |= cvmx_error_add(&info);
3132 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3133 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3134 info.status_mask = 1ull<<14 /* mre */;
3135 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3136 info.enable_mask = 1ull<<14 /* mre */;
3138 info.group = CVMX_ERROR_GROUP_PCI;
3139 info.group_index = 1;
3140 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3141 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3142 info.parent.status_mask = 1ull<<10 /* exc */;
3143 info.func = __cvmx_error_display;
3144 info.user_info = (long)
3145 "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
3146 " xdlh_replay_num_rlover_err\n";
3147 fail |= cvmx_error_add(&info);
3149 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3150 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3151 info.status_mask = 1ull<<15 /* rdwdle */;
3152 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3153 info.enable_mask = 1ull<<15 /* rdwdle */;
3155 info.group = CVMX_ERROR_GROUP_PCI;
3156 info.group_index = 1;
3157 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3158 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3159 info.parent.status_mask = 1ull<<10 /* exc */;
3160 info.func = __cvmx_error_display;
3161 info.user_info = (long)
3162 "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
3163 " rdlh_bad_dllp_err\n";
3164 fail |= cvmx_error_add(&info);
3166 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3167 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3168 info.status_mask = 1ull<<16 /* rtwdle */;
3169 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3170 info.enable_mask = 1ull<<16 /* rtwdle */;
3172 info.group = CVMX_ERROR_GROUP_PCI;
3173 info.group_index = 1;
3174 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3175 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3176 info.parent.status_mask = 1ull<<10 /* exc */;
3177 info.func = __cvmx_error_display;
3178 info.user_info = (long)
3179 "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
3180 " rdlh_bad_tlp_err\n";
3181 fail |= cvmx_error_add(&info);
3183 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3184 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3185 info.status_mask = 1ull<<17 /* dpeoosd */;
3186 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3187 info.enable_mask = 1ull<<17 /* dpeoosd */;
3189 info.group = CVMX_ERROR_GROUP_PCI;
3190 info.group_index = 1;
3191 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3192 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3193 info.parent.status_mask = 1ull<<10 /* exc */;
3194 info.func = __cvmx_error_display;
3195 info.user_info = (long)
3196 "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
3198 fail |= cvmx_error_add(&info);
3200 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3201 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3202 info.status_mask = 1ull<<18 /* fcpvwt */;
3203 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3204 info.enable_mask = 1ull<<18 /* fcpvwt */;
3206 info.group = CVMX_ERROR_GROUP_PCI;
3207 info.group_index = 1;
3208 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3209 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3210 info.parent.status_mask = 1ull<<10 /* exc */;
3211 info.func = __cvmx_error_display;
3212 info.user_info = (long)
3213 "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
3214 " rtlh_fc_prot_err\n";
3215 fail |= cvmx_error_add(&info);
3217 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3218 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3219 info.status_mask = 1ull<<19 /* rpe */;
3220 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3221 info.enable_mask = 1ull<<19 /* rpe */;
3223 info.group = CVMX_ERROR_GROUP_PCI;
3224 info.group_index = 1;
3225 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3226 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3227 info.parent.status_mask = 1ull<<10 /* exc */;
3228 info.func = __cvmx_error_display;
3229 info.user_info = (long)
3230 "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
3231 " (RxStatus = 3b100) or disparity error\n"
3232 " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
3235 fail |= cvmx_error_add(&info);
3237 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3238 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3239 info.status_mask = 1ull<<20 /* fcuv */;
3240 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3241 info.enable_mask = 1ull<<20 /* fcuv */;
3243 info.group = CVMX_ERROR_GROUP_PCI;
3244 info.group_index = 1;
3245 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3246 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3247 info.parent.status_mask = 1ull<<10 /* exc */;
3248 info.func = __cvmx_error_display;
3249 info.user_info = (long)
3250 "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
3251 " int_xadm_fc_prot_err\n";
3252 fail |= cvmx_error_add(&info);
3254 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3255 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3256 info.status_mask = 1ull<<21 /* rqo */;
3257 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3258 info.enable_mask = 1ull<<21 /* rqo */;
3260 info.group = CVMX_ERROR_GROUP_PCI;
3261 info.group_index = 1;
3262 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3263 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3264 info.parent.status_mask = 1ull<<10 /* exc */;
3265 info.func = __cvmx_error_display;
3266 info.user_info = (long)
3267 "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
3268 " flow control advertisements are ignored\n"
3269 " radm_qoverflow\n";
3270 fail |= cvmx_error_add(&info);
3272 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3273 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3274 info.status_mask = 1ull<<22 /* rauc */;
3275 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3276 info.enable_mask = 1ull<<22 /* rauc */;
3278 info.group = CVMX_ERROR_GROUP_PCI;
3279 info.group_index = 1;
3280 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3281 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3282 info.parent.status_mask = 1ull<<10 /* exc */;
3283 info.func = __cvmx_error_display;
3284 info.user_info = (long)
3285 "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
3286 " radm_unexp_cpl_err\n";
3287 fail |= cvmx_error_add(&info);
3289 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3290 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3291 info.status_mask = 1ull<<23 /* racur */;
3292 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3293 info.enable_mask = 1ull<<23 /* racur */;
3295 info.group = CVMX_ERROR_GROUP_PCI;
3296 info.group_index = 1;
3297 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3298 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3299 info.parent.status_mask = 1ull<<10 /* exc */;
3300 info.func = __cvmx_error_display;
3301 info.user_info = (long)
3302 "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
3303 " radm_rcvd_cpl_ur\n";
3304 fail |= cvmx_error_add(&info);
3306 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3307 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3308 info.status_mask = 1ull<<24 /* racca */;
3309 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3310 info.enable_mask = 1ull<<24 /* racca */;
3312 info.group = CVMX_ERROR_GROUP_PCI;
3313 info.group_index = 1;
3314 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3315 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3316 info.parent.status_mask = 1ull<<10 /* exc */;
3317 info.func = __cvmx_error_display;
3318 info.user_info = (long)
3319 "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
3320 " radm_rcvd_cpl_ca\n";
3321 fail |= cvmx_error_add(&info);
3323 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3324 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3325 info.status_mask = 1ull<<25 /* caar */;
3326 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3327 info.enable_mask = 1ull<<25 /* caar */;
3329 info.group = CVMX_ERROR_GROUP_PCI;
3330 info.group_index = 1;
3331 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3332 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3333 info.parent.status_mask = 1ull<<10 /* exc */;
3334 info.func = __cvmx_error_display;
3335 info.user_info = (long)
3336 "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
3337 " radm_rcvd_ca_req\n"
3338 " This bit will never be set because Octeon does\n"
3339 " not generate Completer Aborts.\n";
3340 fail |= cvmx_error_add(&info);
3342 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3343 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3344 info.status_mask = 1ull<<26 /* rarwdns */;
3345 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3346 info.enable_mask = 1ull<<26 /* rarwdns */;
3348 info.group = CVMX_ERROR_GROUP_PCI;
3349 info.group_index = 1;
3350 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3351 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3352 info.parent.status_mask = 1ull<<10 /* exc */;
3353 info.func = __cvmx_error_display;
3354 info.user_info = (long)
3355 "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
3356 " radm_rcvd_ur_req\n";
3357 fail |= cvmx_error_add(&info);
3359 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3360 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3361 info.status_mask = 1ull<<27 /* ramtlp */;
3362 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3363 info.enable_mask = 1ull<<27 /* ramtlp */;
3365 info.group = CVMX_ERROR_GROUP_PCI;
3366 info.group_index = 1;
3367 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3368 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3369 info.parent.status_mask = 1ull<<10 /* exc */;
3370 info.func = __cvmx_error_display;
3371 info.user_info = (long)
3372 "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
3373 " radm_mlf_tlp_err\n";
3374 fail |= cvmx_error_add(&info);
3376 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3377 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3378 info.status_mask = 1ull<<28 /* racpp */;
3379 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3380 info.enable_mask = 1ull<<28 /* racpp */;
3382 info.group = CVMX_ERROR_GROUP_PCI;
3383 info.group_index = 1;
3384 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3385 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3386 info.parent.status_mask = 1ull<<10 /* exc */;
3387 info.func = __cvmx_error_display;
3388 info.user_info = (long)
3389 "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
3390 " radm_rcvd_cpl_poisoned\n";
3391 fail |= cvmx_error_add(&info);
3393 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3394 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3395 info.status_mask = 1ull<<29 /* rawwpp */;
3396 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3397 info.enable_mask = 1ull<<29 /* rawwpp */;
3399 info.group = CVMX_ERROR_GROUP_PCI;
3400 info.group_index = 1;
3401 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3402 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3403 info.parent.status_mask = 1ull<<10 /* exc */;
3404 info.func = __cvmx_error_display;
3405 info.user_info = (long)
3406 "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
3407 " radm_rcvd_wreq_poisoned\n";
3408 fail |= cvmx_error_add(&info);
3410 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3411 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3412 info.status_mask = 1ull<<30 /* ecrc_e */;
3413 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3414 info.enable_mask = 1ull<<30 /* ecrc_e */;
3416 info.group = CVMX_ERROR_GROUP_PCI;
3417 info.group_index = 1;
3418 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3419 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3420 info.parent.status_mask = 1ull<<10 /* exc */;
3421 info.func = __cvmx_error_display;
3422 info.user_info = (long)
3423 "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
3425 fail |= cvmx_error_add(&info);
3427 /* CVMX_FPA_INT_SUM */
3428 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3429 info.status_addr = CVMX_FPA_INT_SUM;
3430 info.status_mask = 1ull<<0 /* fed0_sbe */;
3431 info.enable_addr = CVMX_FPA_INT_ENB;
3432 info.enable_mask = 1ull<<0 /* fed0_sbe */;
3434 info.group = CVMX_ERROR_GROUP_INTERNAL;
3435 info.group_index = 0;
3436 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3437 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3438 info.parent.status_mask = 1ull<<5 /* fpa */;
3439 info.func = __cvmx_error_display;
3440 info.user_info = (long)
3441 "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
3442 fail |= cvmx_error_add(&info);
3444 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3445 info.status_addr = CVMX_FPA_INT_SUM;
3446 info.status_mask = 1ull<<1 /* fed0_dbe */;
3447 info.enable_addr = CVMX_FPA_INT_ENB;
3448 info.enable_mask = 1ull<<1 /* fed0_dbe */;
3450 info.group = CVMX_ERROR_GROUP_INTERNAL;
3451 info.group_index = 0;
3452 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3453 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3454 info.parent.status_mask = 1ull<<5 /* fpa */;
3455 info.func = __cvmx_error_display;
3456 info.user_info = (long)
3457 "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
3458 fail |= cvmx_error_add(&info);
3460 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3461 info.status_addr = CVMX_FPA_INT_SUM;
3462 info.status_mask = 1ull<<2 /* fed1_sbe */;
3463 info.enable_addr = CVMX_FPA_INT_ENB;
3464 info.enable_mask = 1ull<<2 /* fed1_sbe */;
3466 info.group = CVMX_ERROR_GROUP_INTERNAL;
3467 info.group_index = 0;
3468 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3469 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3470 info.parent.status_mask = 1ull<<5 /* fpa */;
3471 info.func = __cvmx_error_display;
3472 info.user_info = (long)
3473 "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
3474 fail |= cvmx_error_add(&info);
3476 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3477 info.status_addr = CVMX_FPA_INT_SUM;
3478 info.status_mask = 1ull<<3 /* fed1_dbe */;
3479 info.enable_addr = CVMX_FPA_INT_ENB;
3480 info.enable_mask = 1ull<<3 /* fed1_dbe */;
3482 info.group = CVMX_ERROR_GROUP_INTERNAL;
3483 info.group_index = 0;
3484 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3485 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3486 info.parent.status_mask = 1ull<<5 /* fpa */;
3487 info.func = __cvmx_error_display;
3488 info.user_info = (long)
3489 "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
3490 fail |= cvmx_error_add(&info);
3492 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3493 info.status_addr = CVMX_FPA_INT_SUM;
3494 info.status_mask = 1ull<<4 /* q0_und */;
3495 info.enable_addr = CVMX_FPA_INT_ENB;
3496 info.enable_mask = 1ull<<4 /* q0_und */;
3498 info.group = CVMX_ERROR_GROUP_INTERNAL;
3499 info.group_index = 0;
3500 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3501 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3502 info.parent.status_mask = 1ull<<5 /* fpa */;
3503 info.func = __cvmx_error_display;
3504 info.user_info = (long)
3505 "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
3507 fail |= cvmx_error_add(&info);
3509 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3510 info.status_addr = CVMX_FPA_INT_SUM;
3511 info.status_mask = 1ull<<5 /* q0_coff */;
3512 info.enable_addr = CVMX_FPA_INT_ENB;
3513 info.enable_mask = 1ull<<5 /* q0_coff */;
3515 info.group = CVMX_ERROR_GROUP_INTERNAL;
3516 info.group_index = 0;
3517 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3518 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3519 info.parent.status_mask = 1ull<<5 /* fpa */;
3520 info.func = __cvmx_error_display;
3521 info.user_info = (long)
3522 "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
3523 " the count available is greater than pointers\n"
3524 " present in the FPA.\n";
3525 fail |= cvmx_error_add(&info);
3527 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3528 info.status_addr = CVMX_FPA_INT_SUM;
3529 info.status_mask = 1ull<<6 /* q0_perr */;
3530 info.enable_addr = CVMX_FPA_INT_ENB;
3531 info.enable_mask = 1ull<<6 /* q0_perr */;
3533 info.group = CVMX_ERROR_GROUP_INTERNAL;
3534 info.group_index = 0;
3535 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3536 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3537 info.parent.status_mask = 1ull<<5 /* fpa */;
3538 info.func = __cvmx_error_display;
3539 info.user_info = (long)
3540 "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
3541 " the L2C does not have the FPA owner ship bit set.\n";
3542 fail |= cvmx_error_add(&info);
3544 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3545 info.status_addr = CVMX_FPA_INT_SUM;
3546 info.status_mask = 1ull<<7 /* q1_und */;
3547 info.enable_addr = CVMX_FPA_INT_ENB;
3548 info.enable_mask = 1ull<<7 /* q1_und */;
3550 info.group = CVMX_ERROR_GROUP_INTERNAL;
3551 info.group_index = 0;
3552 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3553 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3554 info.parent.status_mask = 1ull<<5 /* fpa */;
3555 info.func = __cvmx_error_display;
3556 info.user_info = (long)
3557 "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
3559 fail |= cvmx_error_add(&info);
3561 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3562 info.status_addr = CVMX_FPA_INT_SUM;
3563 info.status_mask = 1ull<<8 /* q1_coff */;
3564 info.enable_addr = CVMX_FPA_INT_ENB;
3565 info.enable_mask = 1ull<<8 /* q1_coff */;
3567 info.group = CVMX_ERROR_GROUP_INTERNAL;
3568 info.group_index = 0;
3569 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3570 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3571 info.parent.status_mask = 1ull<<5 /* fpa */;
3572 info.func = __cvmx_error_display;
3573 info.user_info = (long)
3574 "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
3575 " the count available is greater than pointers\n"
3576 " present in the FPA.\n";
3577 fail |= cvmx_error_add(&info);
3579 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3580 info.status_addr = CVMX_FPA_INT_SUM;
3581 info.status_mask = 1ull<<9 /* q1_perr */;
3582 info.enable_addr = CVMX_FPA_INT_ENB;
3583 info.enable_mask = 1ull<<9 /* q1_perr */;
3585 info.group = CVMX_ERROR_GROUP_INTERNAL;
3586 info.group_index = 0;
3587 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3588 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3589 info.parent.status_mask = 1ull<<5 /* fpa */;
3590 info.func = __cvmx_error_display;
3591 info.user_info = (long)
3592 "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
3593 " the L2C does not have the FPA owner ship bit set.\n";
3594 fail |= cvmx_error_add(&info);
3596 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3597 info.status_addr = CVMX_FPA_INT_SUM;
3598 info.status_mask = 1ull<<10 /* q2_und */;
3599 info.enable_addr = CVMX_FPA_INT_ENB;
3600 info.enable_mask = 1ull<<10 /* q2_und */;
3602 info.group = CVMX_ERROR_GROUP_INTERNAL;
3603 info.group_index = 0;
3604 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3605 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3606 info.parent.status_mask = 1ull<<5 /* fpa */;
3607 info.func = __cvmx_error_display;
3608 info.user_info = (long)
3609 "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
3611 fail |= cvmx_error_add(&info);
3613 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3614 info.status_addr = CVMX_FPA_INT_SUM;
3615 info.status_mask = 1ull<<11 /* q2_coff */;
3616 info.enable_addr = CVMX_FPA_INT_ENB;
3617 info.enable_mask = 1ull<<11 /* q2_coff */;
3619 info.group = CVMX_ERROR_GROUP_INTERNAL;
3620 info.group_index = 0;
3621 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3622 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3623 info.parent.status_mask = 1ull<<5 /* fpa */;
3624 info.func = __cvmx_error_display;
3625 info.user_info = (long)
3626 "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
3627 " the count available is greater than than pointers\n"
3628 " present in the FPA.\n";
3629 fail |= cvmx_error_add(&info);
3631 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3632 info.status_addr = CVMX_FPA_INT_SUM;
3633 info.status_mask = 1ull<<12 /* q2_perr */;
3634 info.enable_addr = CVMX_FPA_INT_ENB;
3635 info.enable_mask = 1ull<<12 /* q2_perr */;
3637 info.group = CVMX_ERROR_GROUP_INTERNAL;
3638 info.group_index = 0;
3639 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3640 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3641 info.parent.status_mask = 1ull<<5 /* fpa */;
3642 info.func = __cvmx_error_display;
3643 info.user_info = (long)
3644 "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
3645 " the L2C does not have the FPA owner ship bit set.\n";
3646 fail |= cvmx_error_add(&info);
3648 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3649 info.status_addr = CVMX_FPA_INT_SUM;
3650 info.status_mask = 1ull<<13 /* q3_und */;
3651 info.enable_addr = CVMX_FPA_INT_ENB;
3652 info.enable_mask = 1ull<<13 /* q3_und */;
3654 info.group = CVMX_ERROR_GROUP_INTERNAL;
3655 info.group_index = 0;
3656 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3657 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3658 info.parent.status_mask = 1ull<<5 /* fpa */;
3659 info.func = __cvmx_error_display;
3660 info.user_info = (long)
3661 "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
3663 fail |= cvmx_error_add(&info);
3665 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3666 info.status_addr = CVMX_FPA_INT_SUM;
3667 info.status_mask = 1ull<<14 /* q3_coff */;
3668 info.enable_addr = CVMX_FPA_INT_ENB;
3669 info.enable_mask = 1ull<<14 /* q3_coff */;
3671 info.group = CVMX_ERROR_GROUP_INTERNAL;
3672 info.group_index = 0;
3673 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3674 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3675 info.parent.status_mask = 1ull<<5 /* fpa */;
3676 info.func = __cvmx_error_display;
3677 info.user_info = (long)
3678 "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
3679 " the count available is greater than than pointers\n"
3680 " present in the FPA.\n";
3681 fail |= cvmx_error_add(&info);
3683 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3684 info.status_addr = CVMX_FPA_INT_SUM;
3685 info.status_mask = 1ull<<15 /* q3_perr */;
3686 info.enable_addr = CVMX_FPA_INT_ENB;
3687 info.enable_mask = 1ull<<15 /* q3_perr */;
3689 info.group = CVMX_ERROR_GROUP_INTERNAL;
3690 info.group_index = 0;
3691 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3692 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3693 info.parent.status_mask = 1ull<<5 /* fpa */;
3694 info.func = __cvmx_error_display;
3695 info.user_info = (long)
3696 "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
3697 " the L2C does not have the FPA owner ship bit set.\n";
3698 fail |= cvmx_error_add(&info);
3700 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3701 info.status_addr = CVMX_FPA_INT_SUM;
3702 info.status_mask = 1ull<<16 /* q4_und */;
3703 info.enable_addr = CVMX_FPA_INT_ENB;
3704 info.enable_mask = 1ull<<16 /* q4_und */;
3706 info.group = CVMX_ERROR_GROUP_INTERNAL;
3707 info.group_index = 0;
3708 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3709 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3710 info.parent.status_mask = 1ull<<5 /* fpa */;
3711 info.func = __cvmx_error_display;
3712 info.user_info = (long)
3713 "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
3715 fail |= cvmx_error_add(&info);
3717 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3718 info.status_addr = CVMX_FPA_INT_SUM;
3719 info.status_mask = 1ull<<17 /* q4_coff */;
3720 info.enable_addr = CVMX_FPA_INT_ENB;
3721 info.enable_mask = 1ull<<17 /* q4_coff */;
3723 info.group = CVMX_ERROR_GROUP_INTERNAL;
3724 info.group_index = 0;
3725 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3726 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3727 info.parent.status_mask = 1ull<<5 /* fpa */;
3728 info.func = __cvmx_error_display;
3729 info.user_info = (long)
3730 "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
3731 " the count available is greater than than pointers\n"
3732 " present in the FPA.\n";
3733 fail |= cvmx_error_add(&info);
3735 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3736 info.status_addr = CVMX_FPA_INT_SUM;
3737 info.status_mask = 1ull<<18 /* q4_perr */;
3738 info.enable_addr = CVMX_FPA_INT_ENB;
3739 info.enable_mask = 1ull<<18 /* q4_perr */;
3741 info.group = CVMX_ERROR_GROUP_INTERNAL;
3742 info.group_index = 0;
3743 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3744 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3745 info.parent.status_mask = 1ull<<5 /* fpa */;
3746 info.func = __cvmx_error_display;
3747 info.user_info = (long)
3748 "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
3749 " the L2C does not have the FPA owner ship bit set.\n";
3750 fail |= cvmx_error_add(&info);
3752 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3753 info.status_addr = CVMX_FPA_INT_SUM;
3754 info.status_mask = 1ull<<19 /* q5_und */;
3755 info.enable_addr = CVMX_FPA_INT_ENB;
3756 info.enable_mask = 1ull<<19 /* q5_und */;
3758 info.group = CVMX_ERROR_GROUP_INTERNAL;
3759 info.group_index = 0;
3760 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3761 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3762 info.parent.status_mask = 1ull<<5 /* fpa */;
3763 info.func = __cvmx_error_display;
3764 info.user_info = (long)
3765 "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
3767 fail |= cvmx_error_add(&info);
3769 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3770 info.status_addr = CVMX_FPA_INT_SUM;
3771 info.status_mask = 1ull<<20 /* q5_coff */;
3772 info.enable_addr = CVMX_FPA_INT_ENB;
3773 info.enable_mask = 1ull<<20 /* q5_coff */;
3775 info.group = CVMX_ERROR_GROUP_INTERNAL;
3776 info.group_index = 0;
3777 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3778 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3779 info.parent.status_mask = 1ull<<5 /* fpa */;
3780 info.func = __cvmx_error_display;
3781 info.user_info = (long)
3782 "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
3783 " the count available is greater than than pointers\n"
3784 " present in the FPA.\n";
3785 fail |= cvmx_error_add(&info);
3787 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3788 info.status_addr = CVMX_FPA_INT_SUM;
3789 info.status_mask = 1ull<<21 /* q5_perr */;
3790 info.enable_addr = CVMX_FPA_INT_ENB;
3791 info.enable_mask = 1ull<<21 /* q5_perr */;
3793 info.group = CVMX_ERROR_GROUP_INTERNAL;
3794 info.group_index = 0;
3795 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3796 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3797 info.parent.status_mask = 1ull<<5 /* fpa */;
3798 info.func = __cvmx_error_display;
3799 info.user_info = (long)
3800 "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
3801 " the L2C does not have the FPA owner ship bit set.\n";
3802 fail |= cvmx_error_add(&info);
3804 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3805 info.status_addr = CVMX_FPA_INT_SUM;
3806 info.status_mask = 1ull<<22 /* q6_und */;
3807 info.enable_addr = CVMX_FPA_INT_ENB;
3808 info.enable_mask = 1ull<<22 /* q6_und */;
3810 info.group = CVMX_ERROR_GROUP_INTERNAL;
3811 info.group_index = 0;
3812 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3813 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3814 info.parent.status_mask = 1ull<<5 /* fpa */;
3815 info.func = __cvmx_error_display;
3816 info.user_info = (long)
3817 "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
3819 fail |= cvmx_error_add(&info);
3821 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3822 info.status_addr = CVMX_FPA_INT_SUM;
3823 info.status_mask = 1ull<<23 /* q6_coff */;
3824 info.enable_addr = CVMX_FPA_INT_ENB;
3825 info.enable_mask = 1ull<<23 /* q6_coff */;
3827 info.group = CVMX_ERROR_GROUP_INTERNAL;
3828 info.group_index = 0;
3829 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3830 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3831 info.parent.status_mask = 1ull<<5 /* fpa */;
3832 info.func = __cvmx_error_display;
3833 info.user_info = (long)
3834 "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
3835 " the count available is greater than than pointers\n"
3836 " present in the FPA.\n";
3837 fail |= cvmx_error_add(&info);
3839 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3840 info.status_addr = CVMX_FPA_INT_SUM;
3841 info.status_mask = 1ull<<24 /* q6_perr */;
3842 info.enable_addr = CVMX_FPA_INT_ENB;
3843 info.enable_mask = 1ull<<24 /* q6_perr */;
3845 info.group = CVMX_ERROR_GROUP_INTERNAL;
3846 info.group_index = 0;
3847 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3848 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3849 info.parent.status_mask = 1ull<<5 /* fpa */;
3850 info.func = __cvmx_error_display;
3851 info.user_info = (long)
3852 "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
3853 " the L2C does not have the FPA owner ship bit set.\n";
3854 fail |= cvmx_error_add(&info);
3856 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3857 info.status_addr = CVMX_FPA_INT_SUM;
3858 info.status_mask = 1ull<<25 /* q7_und */;
3859 info.enable_addr = CVMX_FPA_INT_ENB;
3860 info.enable_mask = 1ull<<25 /* q7_und */;
3862 info.group = CVMX_ERROR_GROUP_INTERNAL;
3863 info.group_index = 0;
3864 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3865 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3866 info.parent.status_mask = 1ull<<5 /* fpa */;
3867 info.func = __cvmx_error_display;
3868 info.user_info = (long)
3869 "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
3871 fail |= cvmx_error_add(&info);
3873 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3874 info.status_addr = CVMX_FPA_INT_SUM;
3875 info.status_mask = 1ull<<26 /* q7_coff */;
3876 info.enable_addr = CVMX_FPA_INT_ENB;
3877 info.enable_mask = 1ull<<26 /* q7_coff */;
3879 info.group = CVMX_ERROR_GROUP_INTERNAL;
3880 info.group_index = 0;
3881 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3882 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3883 info.parent.status_mask = 1ull<<5 /* fpa */;
3884 info.func = __cvmx_error_display;
3885 info.user_info = (long)
3886 "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
3887 " the count available is greater than than pointers\n"
3888 " present in the FPA.\n";
3889 fail |= cvmx_error_add(&info);
3891 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3892 info.status_addr = CVMX_FPA_INT_SUM;
3893 info.status_mask = 1ull<<27 /* q7_perr */;
3894 info.enable_addr = CVMX_FPA_INT_ENB;
3895 info.enable_mask = 1ull<<27 /* q7_perr */;
3897 info.group = CVMX_ERROR_GROUP_INTERNAL;
3898 info.group_index = 0;
3899 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3900 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3901 info.parent.status_mask = 1ull<<5 /* fpa */;
3902 info.func = __cvmx_error_display;
3903 info.user_info = (long)
3904 "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
3905 " the L2C does not have the FPA owner ship bit set.\n";
3906 fail |= cvmx_error_add(&info);
3908 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3909 info.status_addr = CVMX_FPA_INT_SUM;
3910 info.status_mask = 1ull<<28 /* pool0th */;
3911 info.enable_addr = CVMX_FPA_INT_ENB;
3912 info.enable_mask = 1ull<<28 /* pool0th */;
3914 info.group = CVMX_ERROR_GROUP_INTERNAL;
3915 info.group_index = 0;
3916 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3917 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3918 info.parent.status_mask = 1ull<<5 /* fpa */;
3919 info.func = __cvmx_error_display;
3920 info.user_info = (long)
3921 "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
3922 " FPA_POOL`_THRESHOLD[THRESH] and a pointer is\n"
3923 " allocated or de-allocated.\n";
3924 fail |= cvmx_error_add(&info);
3926 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3927 info.status_addr = CVMX_FPA_INT_SUM;
3928 info.status_mask = 1ull<<29 /* pool1th */;
3929 info.enable_addr = CVMX_FPA_INT_ENB;
3930 info.enable_mask = 1ull<<29 /* pool1th */;
3932 info.group = CVMX_ERROR_GROUP_INTERNAL;
3933 info.group_index = 0;
3934 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3935 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3936 info.parent.status_mask = 1ull<<5 /* fpa */;
3937 info.func = __cvmx_error_display;
3938 info.user_info = (long)
3939 "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
3940 " FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
3941 " allocated or de-allocated.\n";
3942 fail |= cvmx_error_add(&info);
3944 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3945 info.status_addr = CVMX_FPA_INT_SUM;
3946 info.status_mask = 1ull<<30 /* pool2th */;
3947 info.enable_addr = CVMX_FPA_INT_ENB;
3948 info.enable_mask = 1ull<<30 /* pool2th */;
3950 info.group = CVMX_ERROR_GROUP_INTERNAL;
3951 info.group_index = 0;
3952 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3953 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3954 info.parent.status_mask = 1ull<<5 /* fpa */;
3955 info.func = __cvmx_error_display;
3956 info.user_info = (long)
3957 "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
3958 " FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
3959 " allocated or de-allocated.\n";
3960 fail |= cvmx_error_add(&info);
3962 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3963 info.status_addr = CVMX_FPA_INT_SUM;
3964 info.status_mask = 1ull<<31 /* pool3th */;
3965 info.enable_addr = CVMX_FPA_INT_ENB;
3966 info.enable_mask = 1ull<<31 /* pool3th */;
3968 info.group = CVMX_ERROR_GROUP_INTERNAL;
3969 info.group_index = 0;
3970 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3971 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3972 info.parent.status_mask = 1ull<<5 /* fpa */;
3973 info.func = __cvmx_error_display;
3974 info.user_info = (long)
3975 "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
3976 " FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
3977 " allocated or de-allocated.\n";
3978 fail |= cvmx_error_add(&info);
3980 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3981 info.status_addr = CVMX_FPA_INT_SUM;
3982 info.status_mask = 1ull<<32 /* pool4th */;
3983 info.enable_addr = CVMX_FPA_INT_ENB;
3984 info.enable_mask = 1ull<<32 /* pool4th */;
3986 info.group = CVMX_ERROR_GROUP_INTERNAL;
3987 info.group_index = 0;
3988 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3989 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3990 info.parent.status_mask = 1ull<<5 /* fpa */;
3991 info.func = __cvmx_error_display;
3992 info.user_info = (long)
3993 "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
3994 " FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
3995 " allocated or de-allocated.\n";
3996 fail |= cvmx_error_add(&info);
3998 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3999 info.status_addr = CVMX_FPA_INT_SUM;
4000 info.status_mask = 1ull<<33 /* pool5th */;
4001 info.enable_addr = CVMX_FPA_INT_ENB;
4002 info.enable_mask = 1ull<<33 /* pool5th */;
4004 info.group = CVMX_ERROR_GROUP_INTERNAL;
4005 info.group_index = 0;
4006 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4007 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4008 info.parent.status_mask = 1ull<<5 /* fpa */;
4009 info.func = __cvmx_error_display;
4010 info.user_info = (long)
4011 "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
4012 " FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
4013 " allocated or de-allocated.\n";
4014 fail |= cvmx_error_add(&info);
4016 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4017 info.status_addr = CVMX_FPA_INT_SUM;
4018 info.status_mask = 1ull<<34 /* pool6th */;
4019 info.enable_addr = CVMX_FPA_INT_ENB;
4020 info.enable_mask = 1ull<<34 /* pool6th */;
4022 info.group = CVMX_ERROR_GROUP_INTERNAL;
4023 info.group_index = 0;
4024 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4025 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4026 info.parent.status_mask = 1ull<<5 /* fpa */;
4027 info.func = __cvmx_error_display;
4028 info.user_info = (long)
4029 "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
4030 " FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
4031 " allocated or de-allocated.\n";
4032 fail |= cvmx_error_add(&info);
4034 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4035 info.status_addr = CVMX_FPA_INT_SUM;
4036 info.status_mask = 1ull<<35 /* pool7th */;
4037 info.enable_addr = CVMX_FPA_INT_ENB;
4038 info.enable_mask = 1ull<<35 /* pool7th */;
4040 info.group = CVMX_ERROR_GROUP_INTERNAL;
4041 info.group_index = 0;
4042 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4043 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4044 info.parent.status_mask = 1ull<<5 /* fpa */;
4045 info.func = __cvmx_error_display;
4046 info.user_info = (long)
4047 "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
4048 " FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
4049 " allocated or de-allocated.\n";
4050 fail |= cvmx_error_add(&info);
4052 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4053 info.status_addr = CVMX_FPA_INT_SUM;
4054 info.status_mask = 1ull<<36 /* free0 */;
4055 info.enable_addr = CVMX_FPA_INT_ENB;
4056 info.enable_mask = 1ull<<36 /* free0 */;
4058 info.group = CVMX_ERROR_GROUP_INTERNAL;
4059 info.group_index = 0;
4060 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4061 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4062 info.parent.status_mask = 1ull<<5 /* fpa */;
4063 info.func = __cvmx_error_display;
4064 info.user_info = (long)
4065 "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
4066 fail |= cvmx_error_add(&info);
4068 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4069 info.status_addr = CVMX_FPA_INT_SUM;
4070 info.status_mask = 1ull<<37 /* free1 */;
4071 info.enable_addr = CVMX_FPA_INT_ENB;
4072 info.enable_mask = 1ull<<37 /* free1 */;
4074 info.group = CVMX_ERROR_GROUP_INTERNAL;
4075 info.group_index = 0;
4076 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4077 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4078 info.parent.status_mask = 1ull<<5 /* fpa */;
4079 info.func = __cvmx_error_display;
4080 info.user_info = (long)
4081 "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
4082 fail |= cvmx_error_add(&info);
4084 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4085 info.status_addr = CVMX_FPA_INT_SUM;
4086 info.status_mask = 1ull<<38 /* free2 */;
4087 info.enable_addr = CVMX_FPA_INT_ENB;
4088 info.enable_mask = 1ull<<38 /* free2 */;
4090 info.group = CVMX_ERROR_GROUP_INTERNAL;
4091 info.group_index = 0;
4092 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4093 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4094 info.parent.status_mask = 1ull<<5 /* fpa */;
4095 info.func = __cvmx_error_display;
4096 info.user_info = (long)
4097 "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
4098 fail |= cvmx_error_add(&info);
4100 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4101 info.status_addr = CVMX_FPA_INT_SUM;
4102 info.status_mask = 1ull<<39 /* free3 */;
4103 info.enable_addr = CVMX_FPA_INT_ENB;
4104 info.enable_mask = 1ull<<39 /* free3 */;
4106 info.group = CVMX_ERROR_GROUP_INTERNAL;
4107 info.group_index = 0;
4108 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4109 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4110 info.parent.status_mask = 1ull<<5 /* fpa */;
4111 info.func = __cvmx_error_display;
4112 info.user_info = (long)
4113 "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
4114 fail |= cvmx_error_add(&info);
4116 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4117 info.status_addr = CVMX_FPA_INT_SUM;
4118 info.status_mask = 1ull<<40 /* free4 */;
4119 info.enable_addr = CVMX_FPA_INT_ENB;
4120 info.enable_mask = 1ull<<40 /* free4 */;
4122 info.group = CVMX_ERROR_GROUP_INTERNAL;
4123 info.group_index = 0;
4124 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4125 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4126 info.parent.status_mask = 1ull<<5 /* fpa */;
4127 info.func = __cvmx_error_display;
4128 info.user_info = (long)
4129 "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
4130 fail |= cvmx_error_add(&info);
4132 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4133 info.status_addr = CVMX_FPA_INT_SUM;
4134 info.status_mask = 1ull<<41 /* free5 */;
4135 info.enable_addr = CVMX_FPA_INT_ENB;
4136 info.enable_mask = 1ull<<41 /* free5 */;
4138 info.group = CVMX_ERROR_GROUP_INTERNAL;
4139 info.group_index = 0;
4140 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4141 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4142 info.parent.status_mask = 1ull<<5 /* fpa */;
4143 info.func = __cvmx_error_display;
4144 info.user_info = (long)
4145 "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
4146 fail |= cvmx_error_add(&info);
4148 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4149 info.status_addr = CVMX_FPA_INT_SUM;
4150 info.status_mask = 1ull<<42 /* free6 */;
4151 info.enable_addr = CVMX_FPA_INT_ENB;
4152 info.enable_mask = 1ull<<42 /* free6 */;
4154 info.group = CVMX_ERROR_GROUP_INTERNAL;
4155 info.group_index = 0;
4156 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4157 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4158 info.parent.status_mask = 1ull<<5 /* fpa */;
4159 info.func = __cvmx_error_display;
4160 info.user_info = (long)
4161 "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
4162 fail |= cvmx_error_add(&info);
4164 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4165 info.status_addr = CVMX_FPA_INT_SUM;
4166 info.status_mask = 1ull<<43 /* free7 */;
4167 info.enable_addr = CVMX_FPA_INT_ENB;
4168 info.enable_mask = 1ull<<43 /* free7 */;
4170 info.group = CVMX_ERROR_GROUP_INTERNAL;
4171 info.group_index = 0;
4172 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4173 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4174 info.parent.status_mask = 1ull<<5 /* fpa */;
4175 info.func = __cvmx_error_display;
4176 info.user_info = (long)
4177 "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
4178 fail |= cvmx_error_add(&info);
4180 /* CVMX_UCTLX_INT_REG(0) */
4181 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4182 info.status_addr = CVMX_UCTLX_INT_REG(0);
4183 info.status_mask = 1ull<<0 /* pp_psh_f */;
4184 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4185 info.enable_mask = 1ull<<0 /* pp_psh_f */;
4187 info.group = CVMX_ERROR_GROUP_USB;
4188 info.group_index = 0;
4189 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4190 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4191 info.parent.status_mask = 1ull<<13 /* usb */;
4192 info.func = __cvmx_error_display;
4193 info.user_info = (long)
4194 "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO Pushed When Full\n";
4195 fail |= cvmx_error_add(&info);
4197 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4198 info.status_addr = CVMX_UCTLX_INT_REG(0);
4199 info.status_mask = 1ull<<1 /* er_psh_f */;
4200 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4201 info.enable_mask = 1ull<<1 /* er_psh_f */;
4203 info.group = CVMX_ERROR_GROUP_USB;
4204 info.group_index = 0;
4205 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4206 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4207 info.parent.status_mask = 1ull<<13 /* usb */;
4208 info.func = __cvmx_error_display;
4209 info.user_info = (long)
4210 "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
4211 fail |= cvmx_error_add(&info);
4213 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4214 info.status_addr = CVMX_UCTLX_INT_REG(0);
4215 info.status_mask = 1ull<<2 /* or_psh_f */;
4216 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4217 info.enable_mask = 1ull<<2 /* or_psh_f */;
4219 info.group = CVMX_ERROR_GROUP_USB;
4220 info.group_index = 0;
4221 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4222 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4223 info.parent.status_mask = 1ull<<13 /* usb */;
4224 info.func = __cvmx_error_display;
4225 info.user_info = (long)
4226 "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
4227 fail |= cvmx_error_add(&info);
4229 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4230 info.status_addr = CVMX_UCTLX_INT_REG(0);
4231 info.status_mask = 1ull<<3 /* cf_psh_f */;
4232 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4233 info.enable_mask = 1ull<<3 /* cf_psh_f */;
4235 info.group = CVMX_ERROR_GROUP_USB;
4236 info.group_index = 0;
4237 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4238 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4239 info.parent.status_mask = 1ull<<13 /* usb */;
4240 info.func = __cvmx_error_display;
4241 info.user_info = (long)
4242 "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
4243 fail |= cvmx_error_add(&info);
4245 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4246 info.status_addr = CVMX_UCTLX_INT_REG(0);
4247 info.status_mask = 1ull<<4 /* wb_psh_f */;
4248 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4249 info.enable_mask = 1ull<<4 /* wb_psh_f */;
4251 info.group = CVMX_ERROR_GROUP_USB;
4252 info.group_index = 0;
4253 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4254 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4255 info.parent.status_mask = 1ull<<13 /* usb */;
4256 info.func = __cvmx_error_display;
4257 info.user_info = (long)
4258 "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
4259 fail |= cvmx_error_add(&info);
4261 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4262 info.status_addr = CVMX_UCTLX_INT_REG(0);
4263 info.status_mask = 1ull<<5 /* wb_pop_e */;
4264 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4265 info.enable_mask = 1ull<<5 /* wb_pop_e */;
4267 info.group = CVMX_ERROR_GROUP_USB;
4268 info.group_index = 0;
4269 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4270 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4271 info.parent.status_mask = 1ull<<13 /* usb */;
4272 info.func = __cvmx_error_display;
4273 info.user_info = (long)
4274 "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
4275 fail |= cvmx_error_add(&info);
4277 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4278 info.status_addr = CVMX_UCTLX_INT_REG(0);
4279 info.status_mask = 1ull<<6 /* oc_ovf_e */;
4280 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4281 info.enable_mask = 1ull<<6 /* oc_ovf_e */;
4283 info.group = CVMX_ERROR_GROUP_USB;
4284 info.group_index = 0;
4285 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4286 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4287 info.parent.status_mask = 1ull<<13 /* usb */;
4288 info.func = __cvmx_error_display;
4289 info.user_info = (long)
4290 "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
4291 " When the error happenes, the whole NCB system needs\n"
4293 fail |= cvmx_error_add(&info);
4295 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4296 info.status_addr = CVMX_UCTLX_INT_REG(0);
4297 info.status_mask = 1ull<<7 /* ec_ovf_e */;
4298 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4299 info.enable_mask = 1ull<<7 /* ec_ovf_e */;
4301 info.group = CVMX_ERROR_GROUP_USB;
4302 info.group_index = 0;
4303 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4304 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4305 info.parent.status_mask = 1ull<<13 /* usb */;
4306 info.func = __cvmx_error_display;
4307 info.user_info = (long)
4308 "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
4309 " When the error happenes, the whole NCB system needs\n"
4311 fail |= cvmx_error_add(&info);
4313 /* CVMX_MIO_BOOT_ERR */
4314 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4315 info.status_addr = CVMX_MIO_BOOT_ERR;
4316 info.status_mask = 1ull<<0 /* adr_err */;
4317 info.enable_addr = CVMX_MIO_BOOT_INT;
4318 info.enable_mask = 1ull<<0 /* adr_int */;
4320 info.group = CVMX_ERROR_GROUP_INTERNAL;
4321 info.group_index = 0;
4322 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4323 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4324 info.parent.status_mask = 1ull<<0 /* mio */;
4325 info.func = __cvmx_error_display;
4326 info.user_info = (long)
4327 "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
4328 fail |= cvmx_error_add(&info);
4330 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4331 info.status_addr = CVMX_MIO_BOOT_ERR;
4332 info.status_mask = 1ull<<1 /* wait_err */;
4333 info.enable_addr = CVMX_MIO_BOOT_INT;
4334 info.enable_mask = 1ull<<1 /* wait_int */;
4336 info.group = CVMX_ERROR_GROUP_INTERNAL;
4337 info.group_index = 0;
4338 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4339 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4340 info.parent.status_mask = 1ull<<0 /* mio */;
4341 info.func = __cvmx_error_display;
4342 info.user_info = (long)
4343 "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
4344 fail |= cvmx_error_add(&info);
4346 /* CVMX_MIO_RST_INT */
4347 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4348 info.status_addr = CVMX_MIO_RST_INT;
4349 info.status_mask = 1ull<<0 /* rst_link0 */;
4350 info.enable_addr = CVMX_MIO_RST_INT_EN;
4351 info.enable_mask = 1ull<<0 /* rst_link0 */;
4353 info.group = CVMX_ERROR_GROUP_INTERNAL;
4354 info.group_index = 0;
4355 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4356 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4357 info.parent.status_mask = 1ull<<0 /* mio */;
4358 info.func = __cvmx_error_display;
4359 info.user_info = (long)
4360 "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
4361 " MIO_RST_CTL0[RST_LINK]=0. Software must assert\n"
4362 " then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
4363 fail |= cvmx_error_add(&info);
4365 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4366 info.status_addr = CVMX_MIO_RST_INT;
4367 info.status_mask = 1ull<<1 /* rst_link1 */;
4368 info.enable_addr = CVMX_MIO_RST_INT_EN;
4369 info.enable_mask = 1ull<<1 /* rst_link1 */;
4371 info.group = CVMX_ERROR_GROUP_INTERNAL;
4372 info.group_index = 0;
4373 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4374 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4375 info.parent.status_mask = 1ull<<0 /* mio */;
4376 info.func = __cvmx_error_display;
4377 info.user_info = (long)
4378 "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
4379 " MIO_RST_CTL1[RST_LINK]=0. Software must assert\n"
4380 " then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
4381 fail |= cvmx_error_add(&info);
4383 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4384 info.status_addr = CVMX_MIO_RST_INT;
4385 info.status_mask = 1ull<<8 /* perst0 */;
4386 info.enable_addr = CVMX_MIO_RST_INT_EN;
4387 info.enable_mask = 1ull<<8 /* perst0 */;
4389 info.group = CVMX_ERROR_GROUP_INTERNAL;
4390 info.group_index = 0;
4391 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4392 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4393 info.parent.status_mask = 1ull<<0 /* mio */;
4394 info.func = __cvmx_error_display;
4395 info.user_info = (long)
4396 "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
4397 " and MIO_RST_CTL0[RST_CHIP]=0\n";
4398 fail |= cvmx_error_add(&info);
4400 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4401 info.status_addr = CVMX_MIO_RST_INT;
4402 info.status_mask = 1ull<<9 /* perst1 */;
4403 info.enable_addr = CVMX_MIO_RST_INT_EN;
4404 info.enable_mask = 1ull<<9 /* perst1 */;
4406 info.group = CVMX_ERROR_GROUP_INTERNAL;
4407 info.group_index = 0;
4408 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4409 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4410 info.parent.status_mask = 1ull<<0 /* mio */;
4411 info.func = __cvmx_error_display;
4412 info.user_info = (long)
4413 "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
4414 " and MIO_RST_CTL1[RST_CHIP]=0\n";
4415 fail |= cvmx_error_add(&info);
4417 /* CVMX_DFM_FNT_STAT */
4418 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4419 info.status_addr = CVMX_DFM_FNT_STAT;
4420 info.status_mask = 1ull<<0 /* sbe_err */;
4421 info.enable_addr = CVMX_DFM_FNT_IENA;
4422 info.enable_mask = 1ull<<0 /* sbe_intena */;
4424 info.group = CVMX_ERROR_GROUP_INTERNAL;
4425 info.group_index = 0;
4426 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4427 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4428 info.parent.status_mask = 1ull<<40 /* dfm */;
4429 info.func = __cvmx_error_display;
4430 info.user_info = (long)
4431 "ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during\n"
4433 " Write of 1 will clear the corresponding error bit\n";
4434 fail |= cvmx_error_add(&info);
4436 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4437 info.status_addr = CVMX_DFM_FNT_STAT;
4438 info.status_mask = 1ull<<1 /* dbe_err */;
4439 info.enable_addr = CVMX_DFM_FNT_IENA;
4440 info.enable_mask = 1ull<<1 /* dbe_intena */;
4442 info.group = CVMX_ERROR_GROUP_INTERNAL;
4443 info.group_index = 0;
4444 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4445 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4446 info.parent.status_mask = 1ull<<40 /* dfm */;
4447 info.func = __cvmx_error_display;
4448 info.user_info = (long)
4449 "ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during\n"
4451 " Write of 1 will clear the corresponding error bit\n";
4452 fail |= cvmx_error_add(&info);
4454 /* CVMX_TIM_REG_ERROR */
4455 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4456 info.status_addr = CVMX_TIM_REG_ERROR;
4457 info.status_mask = 0xffffull<<0 /* mask */;
4458 info.enable_addr = CVMX_TIM_REG_INT_MASK;
4459 info.enable_mask = 0xffffull<<0 /* mask */;
4461 info.group = CVMX_ERROR_GROUP_INTERNAL;
4462 info.group_index = 0;
4463 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4464 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4465 info.parent.status_mask = 1ull<<11 /* tim */;
4466 info.func = __cvmx_error_display;
4467 info.user_info = (long)
4468 "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
4469 fail |= cvmx_error_add(&info);
4471 /* CVMX_LMCX_INT(0) */
4472 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4473 info.status_addr = CVMX_LMCX_INT(0);
4474 info.status_mask = 0xfull<<1 /* sec_err */;
4475 info.enable_addr = CVMX_LMCX_INT_EN(0);
4476 info.enable_mask = 1ull<<1 /* intr_sec_ena */;
4477 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
4478 info.group = CVMX_ERROR_GROUP_LMC;
4479 info.group_index = 0;
4480 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4481 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4482 info.parent.status_mask = 1ull<<17 /* lmc0 */;
4483 info.func = __cvmx_error_display;
4484 info.user_info = (long)
4485 "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
4486 " [0] corresponds to DQ[63:0]_c0_p0\n"
4487 " [1] corresponds to DQ[63:0]_c0_p1\n"
4488 " [2] corresponds to DQ[63:0]_c1_p0\n"
4489 " [3] corresponds to DQ[63:0]_c1_p1\n"
4490 " where _cC_pP denotes cycle C and phase P\n"
4491 " Write of 1 will clear the corresponding error bit\n";
4492 fail |= cvmx_error_add(&info);
4494 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4495 info.status_addr = CVMX_LMCX_INT(0);
4496 info.status_mask = 1ull<<0 /* nxm_wr_err */;
4497 info.enable_addr = CVMX_LMCX_INT_EN(0);
4498 info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
4500 info.group = CVMX_ERROR_GROUP_LMC;
4501 info.group_index = 0;
4502 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4503 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4504 info.parent.status_mask = 1ull<<17 /* lmc0 */;
4505 info.func = __cvmx_error_display;
4506 info.user_info = (long)
4507 "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
4508 " Write of 1 will clear the corresponding error bit\n";
4509 fail |= cvmx_error_add(&info);
4511 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4512 info.status_addr = CVMX_LMCX_INT(0);
4513 info.status_mask = 0xfull<<5 /* ded_err */;
4514 info.enable_addr = CVMX_LMCX_INT_EN(0);
4515 info.enable_mask = 1ull<<2 /* intr_ded_ena */;
4517 info.group = CVMX_ERROR_GROUP_LMC;
4518 info.group_index = 0;
4519 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4520 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4521 info.parent.status_mask = 1ull<<17 /* lmc0 */;
4522 info.func = __cvmx_error_display;
4523 info.user_info = (long)
4524 "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
4525 " [0] corresponds to DQ[63:0]_c0_p0\n"
4526 " [1] corresponds to DQ[63:0]_c0_p1\n"
4527 " [2] corresponds to DQ[63:0]_c1_p0\n"
4528 " [3] corresponds to DQ[63:0]_c1_p1\n"
4529 " where _cC_pP denotes cycle C and phase P\n"
4530 " Write of 1 will clear the corresponding error bit\n";
4531 fail |= cvmx_error_add(&info);
4533 /* CVMX_KEY_INT_SUM */
4534 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4535 info.status_addr = CVMX_KEY_INT_SUM;
4536 info.status_mask = 1ull<<0 /* ked0_sbe */;
4537 info.enable_addr = CVMX_KEY_INT_ENB;
4538 info.enable_mask = 1ull<<0 /* ked0_sbe */;
4540 info.group = CVMX_ERROR_GROUP_INTERNAL;
4541 info.group_index = 0;
4542 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4543 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4544 info.parent.status_mask = 1ull<<4 /* key */;
4545 info.func = __cvmx_error_display;
4546 info.user_info = (long)
4547 "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
4549 fail |= cvmx_error_add(&info);
4551 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4552 info.status_addr = CVMX_KEY_INT_SUM;
4553 info.status_mask = 1ull<<1 /* ked0_dbe */;
4554 info.enable_addr = CVMX_KEY_INT_ENB;
4555 info.enable_mask = 1ull<<1 /* ked0_dbe */;
4557 info.group = CVMX_ERROR_GROUP_INTERNAL;
4558 info.group_index = 0;
4559 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4560 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4561 info.parent.status_mask = 1ull<<4 /* key */;
4562 info.func = __cvmx_error_display;
4563 info.user_info = (long)
4564 "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
4566 fail |= cvmx_error_add(&info);
4568 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4569 info.status_addr = CVMX_KEY_INT_SUM;
4570 info.status_mask = 1ull<<2 /* ked1_sbe */;
4571 info.enable_addr = CVMX_KEY_INT_ENB;
4572 info.enable_mask = 1ull<<2 /* ked1_sbe */;
4574 info.group = CVMX_ERROR_GROUP_INTERNAL;
4575 info.group_index = 0;
4576 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4577 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4578 info.parent.status_mask = 1ull<<4 /* key */;
4579 info.func = __cvmx_error_display;
4580 info.user_info = (long)
4581 "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
4583 fail |= cvmx_error_add(&info);
4585 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4586 info.status_addr = CVMX_KEY_INT_SUM;
4587 info.status_mask = 1ull<<3 /* ked1_dbe */;
4588 info.enable_addr = CVMX_KEY_INT_ENB;
4589 info.enable_mask = 1ull<<3 /* ked1_dbe */;
4591 info.group = CVMX_ERROR_GROUP_INTERNAL;
4592 info.group_index = 0;
4593 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4594 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4595 info.parent.status_mask = 1ull<<4 /* key */;
4596 info.func = __cvmx_error_display;
4597 info.user_info = (long)
4598 "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
4600 fail |= cvmx_error_add(&info);
4602 /* CVMX_GMXX_BAD_REG(0) */
4603 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4604 info.status_addr = CVMX_GMXX_BAD_REG(0);
4605 info.status_mask = 0xfull<<2 /* out_ovr */;
4606 info.enable_addr = 0;
4607 info.enable_mask = 0;
4609 info.group = CVMX_ERROR_GROUP_ETHERNET;
4610 info.group_index = 0;
4611 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4612 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4613 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4614 info.func = __cvmx_error_display;
4615 info.user_info = (long)
4616 "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
4617 fail |= cvmx_error_add(&info);
4619 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4620 info.status_addr = CVMX_GMXX_BAD_REG(0);
4621 info.status_mask = 0xfull<<22 /* loststat */;
4622 info.enable_addr = 0;
4623 info.enable_mask = 0;
4625 info.group = CVMX_ERROR_GROUP_ETHERNET;
4626 info.group_index = 0;
4627 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4628 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4629 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4630 info.func = __cvmx_error_display;
4631 info.user_info = (long)
4632 "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
4633 " In SGMII, one bit per port\n"
4634 " In XAUI, only port0 is used\n"
4635 " TX Stats are corrupted\n";
4636 fail |= cvmx_error_add(&info);
4638 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4639 info.status_addr = CVMX_GMXX_BAD_REG(0);
4640 info.status_mask = 1ull<<26 /* statovr */;
4641 info.enable_addr = 0;
4642 info.enable_mask = 0;
4644 info.group = CVMX_ERROR_GROUP_ETHERNET;
4645 info.group_index = 0;
4646 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4647 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4648 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4649 info.func = __cvmx_error_display;
4650 info.user_info = (long)
4651 "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
4652 " The common FIFO to SGMII and XAUI had an overflow\n"
4653 " TX Stats are corrupted\n";
4654 fail |= cvmx_error_add(&info);
4656 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4657 info.status_addr = CVMX_GMXX_BAD_REG(0);
4658 info.status_mask = 0xfull<<27 /* inb_nxa */;
4659 info.enable_addr = 0;
4660 info.enable_mask = 0;
4662 info.group = CVMX_ERROR_GROUP_ETHERNET;
4663 info.group_index = 0;
4664 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4665 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4666 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4667 info.func = __cvmx_error_display;
4668 info.user_info = (long)
4669 "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
4670 fail |= cvmx_error_add(&info);
4672 /* CVMX_GMXX_RXX_INT_REG(0,0) */
4673 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4674 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4675 info.status_mask = 1ull<<1 /* carext */;
4676 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4677 info.enable_mask = 1ull<<1 /* carext */;
4679 info.group = CVMX_ERROR_GROUP_ETHERNET;
4680 info.group_index = 0;
4681 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4682 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4683 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4684 info.func = __cvmx_error_display;
4685 info.user_info = (long)
4686 "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
4687 " (SGMII/1000Base-X only)\n";
4688 fail |= cvmx_error_add(&info);
4690 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4691 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4692 info.status_mask = 1ull<<8 /* skperr */;
4693 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4694 info.enable_mask = 1ull<<8 /* skperr */;
4696 info.group = CVMX_ERROR_GROUP_ETHERNET;
4697 info.group_index = 0;
4698 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4699 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4700 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4701 info.func = __cvmx_error_display;
4702 info.user_info = (long)
4703 "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
4704 fail |= cvmx_error_add(&info);
4706 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4707 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4708 info.status_mask = 1ull<<10 /* ovrerr */;
4709 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4710 info.enable_mask = 1ull<<10 /* ovrerr */;
4712 info.group = CVMX_ERROR_GROUP_ETHERNET;
4713 info.group_index = 0;
4714 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4715 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4716 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4717 info.func = __cvmx_error_display;
4718 info.user_info = (long)
4719 "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
4720 " This interrupt should never assert\n"
4721 " (SGMII/1000Base-X only)\n";
4722 fail |= cvmx_error_add(&info);
4724 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4725 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4726 info.status_mask = 1ull<<20 /* loc_fault */;
4727 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4728 info.enable_mask = 1ull<<20 /* loc_fault */;
4730 info.group = CVMX_ERROR_GROUP_ETHERNET;
4731 info.group_index = 0;
4732 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4733 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4734 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4735 info.func = __cvmx_error_display;
4736 info.user_info = (long)
4737 "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
4738 " (XAUI Mode only)\n";
4739 fail |= cvmx_error_add(&info);
4741 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4742 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4743 info.status_mask = 1ull<<21 /* rem_fault */;
4744 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4745 info.enable_mask = 1ull<<21 /* rem_fault */;
4747 info.group = CVMX_ERROR_GROUP_ETHERNET;
4748 info.group_index = 0;
4749 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4750 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4751 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4752 info.func = __cvmx_error_display;
4753 info.user_info = (long)
4754 "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
4755 " (XAUI Mode only)\n";
4756 fail |= cvmx_error_add(&info);
4758 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4759 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4760 info.status_mask = 1ull<<22 /* bad_seq */;
4761 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4762 info.enable_mask = 1ull<<22 /* bad_seq */;
4764 info.group = CVMX_ERROR_GROUP_ETHERNET;
4765 info.group_index = 0;
4766 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4767 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4768 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4769 info.func = __cvmx_error_display;
4770 info.user_info = (long)
4771 "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
4772 " (XAUI Mode only)\n";
4773 fail |= cvmx_error_add(&info);
4775 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4776 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4777 info.status_mask = 1ull<<23 /* bad_term */;
4778 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4779 info.enable_mask = 1ull<<23 /* bad_term */;
4781 info.group = CVMX_ERROR_GROUP_ETHERNET;
4782 info.group_index = 0;
4783 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4784 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4785 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4786 info.func = __cvmx_error_display;
4787 info.user_info = (long)
4788 "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
4789 " than /T/. The error propagation control\n"
4790 " character /E/ will be included as part of the\n"
4791 " frame and does not cause a frame termination.\n"
4792 " (XAUI Mode only)\n";
4793 fail |= cvmx_error_add(&info);
4795 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4796 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4797 info.status_mask = 1ull<<24 /* unsop */;
4798 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4799 info.enable_mask = 1ull<<24 /* unsop */;
4801 info.group = CVMX_ERROR_GROUP_ETHERNET;
4802 info.group_index = 0;
4803 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4804 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4805 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4806 info.func = __cvmx_error_display;
4807 info.user_info = (long)
4808 "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
4809 " (XAUI Mode only)\n";
4810 fail |= cvmx_error_add(&info);
4812 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4813 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4814 info.status_mask = 1ull<<25 /* uneop */;
4815 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4816 info.enable_mask = 1ull<<25 /* uneop */;
4818 info.group = CVMX_ERROR_GROUP_ETHERNET;
4819 info.group_index = 0;
4820 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4821 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4822 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4823 info.func = __cvmx_error_display;
4824 info.user_info = (long)
4825 "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
4826 " (XAUI Mode only)\n";
4827 fail |= cvmx_error_add(&info);
4829 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4830 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4831 info.status_mask = 1ull<<26 /* undat */;
4832 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4833 info.enable_mask = 1ull<<26 /* undat */;
4835 info.group = CVMX_ERROR_GROUP_ETHERNET;
4836 info.group_index = 0;
4837 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4838 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4839 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4840 info.func = __cvmx_error_display;
4841 info.user_info = (long)
4842 "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
4843 " (XAUI Mode only)\n";
4844 fail |= cvmx_error_add(&info);
4846 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4847 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4848 info.status_mask = 1ull<<27 /* hg2fld */;
4849 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4850 info.enable_mask = 1ull<<27 /* hg2fld */;
4852 info.group = CVMX_ERROR_GROUP_ETHERNET;
4853 info.group_index = 0;
4854 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4855 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4856 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4857 info.func = __cvmx_error_display;
4858 info.user_info = (long)
4859 "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
4860 " 1) MSG_TYPE field not 6'b00_0000\n"
4861 " i.e. it is not a FLOW CONTROL message, which\n"
4862 " is the only defined type for HiGig2\n"
4863 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
4864 " which is the only defined type for HiGig2\n"
4865 " 3) FC_OBJECT field is neither 4'b0000 for\n"
4866 " Physical Link nor 4'b0010 for Logical Link.\n"
4867 " Those are the only two defined types in HiGig2\n";
4868 fail |= cvmx_error_add(&info);
4870 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4871 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4872 info.status_mask = 1ull<<28 /* hg2cc */;
4873 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4874 info.enable_mask = 1ull<<28 /* hg2cc */;
4876 info.group = CVMX_ERROR_GROUP_ETHERNET;
4877 info.group_index = 0;
4878 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4879 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4880 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4881 info.func = __cvmx_error_display;
4882 info.user_info = (long)
4883 "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
4884 " Set when either CRC8 error detected or when\n"
4885 " a Control Character is found in the message\n"
4886 " bytes after the K.SOM\n"
4887 " NOTE: HG2CC has higher priority than HG2FLD\n"
4888 " i.e. a HiGig2 message that results in HG2CC\n"
4889 " getting set, will never set HG2FLD.\n";
4890 fail |= cvmx_error_add(&info);
4892 /* CVMX_GMXX_RXX_INT_REG(1,0) */
4893 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4894 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4895 info.status_mask = 1ull<<1 /* carext */;
4896 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4897 info.enable_mask = 1ull<<1 /* carext */;
4899 info.group = CVMX_ERROR_GROUP_ETHERNET;
4900 info.group_index = 1;
4901 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4902 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4903 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4904 info.func = __cvmx_error_display;
4905 info.user_info = (long)
4906 "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
4907 " (SGMII/1000Base-X only)\n";
4908 fail |= cvmx_error_add(&info);
4910 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4911 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4912 info.status_mask = 1ull<<8 /* skperr */;
4913 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4914 info.enable_mask = 1ull<<8 /* skperr */;
4916 info.group = CVMX_ERROR_GROUP_ETHERNET;
4917 info.group_index = 1;
4918 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4919 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4920 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4921 info.func = __cvmx_error_display;
4922 info.user_info = (long)
4923 "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
4924 fail |= cvmx_error_add(&info);
4926 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4927 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4928 info.status_mask = 1ull<<10 /* ovrerr */;
4929 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4930 info.enable_mask = 1ull<<10 /* ovrerr */;
4932 info.group = CVMX_ERROR_GROUP_ETHERNET;
4933 info.group_index = 1;
4934 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4935 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4936 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4937 info.func = __cvmx_error_display;
4938 info.user_info = (long)
4939 "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
4940 " This interrupt should never assert\n"
4941 " (SGMII/1000Base-X only)\n";
4942 fail |= cvmx_error_add(&info);
4944 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4945 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4946 info.status_mask = 1ull<<20 /* loc_fault */;
4947 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4948 info.enable_mask = 1ull<<20 /* loc_fault */;
4950 info.group = CVMX_ERROR_GROUP_ETHERNET;
4951 info.group_index = 1;
4952 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4953 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4954 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4955 info.func = __cvmx_error_display;
4956 info.user_info = (long)
4957 "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
4958 " (XAUI Mode only)\n";
4959 fail |= cvmx_error_add(&info);
4961 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4962 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4963 info.status_mask = 1ull<<21 /* rem_fault */;
4964 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4965 info.enable_mask = 1ull<<21 /* rem_fault */;
4967 info.group = CVMX_ERROR_GROUP_ETHERNET;
4968 info.group_index = 1;
4969 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4970 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4971 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4972 info.func = __cvmx_error_display;
4973 info.user_info = (long)
4974 "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
4975 " (XAUI Mode only)\n";
4976 fail |= cvmx_error_add(&info);
4978 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4979 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4980 info.status_mask = 1ull<<22 /* bad_seq */;
4981 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4982 info.enable_mask = 1ull<<22 /* bad_seq */;
4984 info.group = CVMX_ERROR_GROUP_ETHERNET;
4985 info.group_index = 1;
4986 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4987 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4988 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4989 info.func = __cvmx_error_display;
4990 info.user_info = (long)
4991 "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
4992 " (XAUI Mode only)\n";
4993 fail |= cvmx_error_add(&info);
4995 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4996 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4997 info.status_mask = 1ull<<23 /* bad_term */;
4998 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4999 info.enable_mask = 1ull<<23 /* bad_term */;
5001 info.group = CVMX_ERROR_GROUP_ETHERNET;
5002 info.group_index = 1;
5003 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5004 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5005 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5006 info.func = __cvmx_error_display;
5007 info.user_info = (long)
5008 "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
5009 " than /T/. The error propagation control\n"
5010 " character /E/ will be included as part of the\n"
5011 " frame and does not cause a frame termination.\n"
5012 " (XAUI Mode only)\n";
5013 fail |= cvmx_error_add(&info);
5015 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5016 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5017 info.status_mask = 1ull<<24 /* unsop */;
5018 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5019 info.enable_mask = 1ull<<24 /* unsop */;
5021 info.group = CVMX_ERROR_GROUP_ETHERNET;
5022 info.group_index = 1;
5023 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5024 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5025 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5026 info.func = __cvmx_error_display;
5027 info.user_info = (long)
5028 "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
5029 " (XAUI Mode only)\n";
5030 fail |= cvmx_error_add(&info);
5032 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5033 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5034 info.status_mask = 1ull<<25 /* uneop */;
5035 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5036 info.enable_mask = 1ull<<25 /* uneop */;
5038 info.group = CVMX_ERROR_GROUP_ETHERNET;
5039 info.group_index = 1;
5040 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5041 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5042 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5043 info.func = __cvmx_error_display;
5044 info.user_info = (long)
5045 "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
5046 " (XAUI Mode only)\n";
5047 fail |= cvmx_error_add(&info);
5049 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5050 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5051 info.status_mask = 1ull<<26 /* undat */;
5052 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5053 info.enable_mask = 1ull<<26 /* undat */;
5055 info.group = CVMX_ERROR_GROUP_ETHERNET;
5056 info.group_index = 1;
5057 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5058 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5059 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5060 info.func = __cvmx_error_display;
5061 info.user_info = (long)
5062 "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
5063 " (XAUI Mode only)\n";
5064 fail |= cvmx_error_add(&info);
5066 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5067 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5068 info.status_mask = 1ull<<27 /* hg2fld */;
5069 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5070 info.enable_mask = 1ull<<27 /* hg2fld */;
5072 info.group = CVMX_ERROR_GROUP_ETHERNET;
5073 info.group_index = 1;
5074 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5075 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5076 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5077 info.func = __cvmx_error_display;
5078 info.user_info = (long)
5079 "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
5080 " 1) MSG_TYPE field not 6'b00_0000\n"
5081 " i.e. it is not a FLOW CONTROL message, which\n"
5082 " is the only defined type for HiGig2\n"
5083 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
5084 " which is the only defined type for HiGig2\n"
5085 " 3) FC_OBJECT field is neither 4'b0000 for\n"
5086 " Physical Link nor 4'b0010 for Logical Link.\n"
5087 " Those are the only two defined types in HiGig2\n";
5088 fail |= cvmx_error_add(&info);
5090 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5091 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5092 info.status_mask = 1ull<<28 /* hg2cc */;
5093 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5094 info.enable_mask = 1ull<<28 /* hg2cc */;
5096 info.group = CVMX_ERROR_GROUP_ETHERNET;
5097 info.group_index = 1;
5098 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5099 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5100 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5101 info.func = __cvmx_error_display;
5102 info.user_info = (long)
5103 "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
5104 " Set when either CRC8 error detected or when\n"
5105 " a Control Character is found in the message\n"
5106 " bytes after the K.SOM\n"
5107 " NOTE: HG2CC has higher priority than HG2FLD\n"
5108 " i.e. a HiGig2 message that results in HG2CC\n"
5109 " getting set, will never set HG2FLD.\n";
5110 fail |= cvmx_error_add(&info);
5112 /* CVMX_GMXX_RXX_INT_REG(2,0) */
5113 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5114 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5115 info.status_mask = 1ull<<1 /* carext */;
5116 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5117 info.enable_mask = 1ull<<1 /* carext */;
5119 info.group = CVMX_ERROR_GROUP_ETHERNET;
5120 info.group_index = 2;
5121 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5122 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5123 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5124 info.func = __cvmx_error_display;
5125 info.user_info = (long)
5126 "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
5127 " (SGMII/1000Base-X only)\n";
5128 fail |= cvmx_error_add(&info);
5130 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5131 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5132 info.status_mask = 1ull<<8 /* skperr */;
5133 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5134 info.enable_mask = 1ull<<8 /* skperr */;
5136 info.group = CVMX_ERROR_GROUP_ETHERNET;
5137 info.group_index = 2;
5138 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5139 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5140 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5141 info.func = __cvmx_error_display;
5142 info.user_info = (long)
5143 "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
5144 fail |= cvmx_error_add(&info);
5146 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5147 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5148 info.status_mask = 1ull<<10 /* ovrerr */;
5149 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5150 info.enable_mask = 1ull<<10 /* ovrerr */;
5152 info.group = CVMX_ERROR_GROUP_ETHERNET;
5153 info.group_index = 2;
5154 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5155 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5156 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5157 info.func = __cvmx_error_display;
5158 info.user_info = (long)
5159 "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
5160 " This interrupt should never assert\n"
5161 " (SGMII/1000Base-X only)\n";
5162 fail |= cvmx_error_add(&info);
5164 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5165 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5166 info.status_mask = 1ull<<20 /* loc_fault */;
5167 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5168 info.enable_mask = 1ull<<20 /* loc_fault */;
5170 info.group = CVMX_ERROR_GROUP_ETHERNET;
5171 info.group_index = 2;
5172 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5173 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5174 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5175 info.func = __cvmx_error_display;
5176 info.user_info = (long)
5177 "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
5178 " (XAUI Mode only)\n";
5179 fail |= cvmx_error_add(&info);
5181 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5182 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5183 info.status_mask = 1ull<<21 /* rem_fault */;
5184 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5185 info.enable_mask = 1ull<<21 /* rem_fault */;
5187 info.group = CVMX_ERROR_GROUP_ETHERNET;
5188 info.group_index = 2;
5189 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5190 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5191 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5192 info.func = __cvmx_error_display;
5193 info.user_info = (long)
5194 "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
5195 " (XAUI Mode only)\n";
5196 fail |= cvmx_error_add(&info);
5198 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5199 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5200 info.status_mask = 1ull<<22 /* bad_seq */;
5201 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5202 info.enable_mask = 1ull<<22 /* bad_seq */;
5204 info.group = CVMX_ERROR_GROUP_ETHERNET;
5205 info.group_index = 2;
5206 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5207 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5208 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5209 info.func = __cvmx_error_display;
5210 info.user_info = (long)
5211 "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
5212 " (XAUI Mode only)\n";
5213 fail |= cvmx_error_add(&info);
5215 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5216 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5217 info.status_mask = 1ull<<23 /* bad_term */;
5218 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5219 info.enable_mask = 1ull<<23 /* bad_term */;
5221 info.group = CVMX_ERROR_GROUP_ETHERNET;
5222 info.group_index = 2;
5223 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5224 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5225 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5226 info.func = __cvmx_error_display;
5227 info.user_info = (long)
5228 "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
5229 " than /T/. The error propagation control\n"
5230 " character /E/ will be included as part of the\n"
5231 " frame and does not cause a frame termination.\n"
5232 " (XAUI Mode only)\n";
5233 fail |= cvmx_error_add(&info);
5235 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5236 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5237 info.status_mask = 1ull<<24 /* unsop */;
5238 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5239 info.enable_mask = 1ull<<24 /* unsop */;
5241 info.group = CVMX_ERROR_GROUP_ETHERNET;
5242 info.group_index = 2;
5243 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5244 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5245 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5246 info.func = __cvmx_error_display;
5247 info.user_info = (long)
5248 "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
5249 " (XAUI Mode only)\n";
5250 fail |= cvmx_error_add(&info);
5252 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5253 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5254 info.status_mask = 1ull<<25 /* uneop */;
5255 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5256 info.enable_mask = 1ull<<25 /* uneop */;
5258 info.group = CVMX_ERROR_GROUP_ETHERNET;
5259 info.group_index = 2;
5260 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5261 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5262 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5263 info.func = __cvmx_error_display;
5264 info.user_info = (long)
5265 "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
5266 " (XAUI Mode only)\n";
5267 fail |= cvmx_error_add(&info);
5269 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5270 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5271 info.status_mask = 1ull<<26 /* undat */;
5272 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5273 info.enable_mask = 1ull<<26 /* undat */;
5275 info.group = CVMX_ERROR_GROUP_ETHERNET;
5276 info.group_index = 2;
5277 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5278 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5279 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5280 info.func = __cvmx_error_display;
5281 info.user_info = (long)
5282 "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
5283 " (XAUI Mode only)\n";
5284 fail |= cvmx_error_add(&info);
5286 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5287 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5288 info.status_mask = 1ull<<27 /* hg2fld */;
5289 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5290 info.enable_mask = 1ull<<27 /* hg2fld */;
5292 info.group = CVMX_ERROR_GROUP_ETHERNET;
5293 info.group_index = 2;
5294 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5295 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5296 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5297 info.func = __cvmx_error_display;
5298 info.user_info = (long)
5299 "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
5300 " 1) MSG_TYPE field not 6'b00_0000\n"
5301 " i.e. it is not a FLOW CONTROL message, which\n"
5302 " is the only defined type for HiGig2\n"
5303 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
5304 " which is the only defined type for HiGig2\n"
5305 " 3) FC_OBJECT field is neither 4'b0000 for\n"
5306 " Physical Link nor 4'b0010 for Logical Link.\n"
5307 " Those are the only two defined types in HiGig2\n";
5308 fail |= cvmx_error_add(&info);
5310 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5311 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5312 info.status_mask = 1ull<<28 /* hg2cc */;
5313 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5314 info.enable_mask = 1ull<<28 /* hg2cc */;
5316 info.group = CVMX_ERROR_GROUP_ETHERNET;
5317 info.group_index = 2;
5318 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5319 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5320 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5321 info.func = __cvmx_error_display;
5322 info.user_info = (long)
5323 "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
5324 " Set when either CRC8 error detected or when\n"
5325 " a Control Character is found in the message\n"
5326 " bytes after the K.SOM\n"
5327 " NOTE: HG2CC has higher priority than HG2FLD\n"
5328 " i.e. a HiGig2 message that results in HG2CC\n"
5329 " getting set, will never set HG2FLD.\n";
5330 fail |= cvmx_error_add(&info);
5332 /* CVMX_GMXX_RXX_INT_REG(3,0) */
5333 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5334 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5335 info.status_mask = 1ull<<1 /* carext */;
5336 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5337 info.enable_mask = 1ull<<1 /* carext */;
5339 info.group = CVMX_ERROR_GROUP_ETHERNET;
5340 info.group_index = 3;
5341 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5342 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5343 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5344 info.func = __cvmx_error_display;
5345 info.user_info = (long)
5346 "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
5347 " (SGMII/1000Base-X only)\n";
5348 fail |= cvmx_error_add(&info);
5350 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5351 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5352 info.status_mask = 1ull<<8 /* skperr */;
5353 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5354 info.enable_mask = 1ull<<8 /* skperr */;
5356 info.group = CVMX_ERROR_GROUP_ETHERNET;
5357 info.group_index = 3;
5358 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5359 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5360 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5361 info.func = __cvmx_error_display;
5362 info.user_info = (long)
5363 "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
5364 fail |= cvmx_error_add(&info);
5366 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5367 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5368 info.status_mask = 1ull<<10 /* ovrerr */;
5369 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5370 info.enable_mask = 1ull<<10 /* ovrerr */;
5372 info.group = CVMX_ERROR_GROUP_ETHERNET;
5373 info.group_index = 3;
5374 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5375 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5376 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5377 info.func = __cvmx_error_display;
5378 info.user_info = (long)
5379 "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
5380 " This interrupt should never assert\n"
5381 " (SGMII/1000Base-X only)\n";
5382 fail |= cvmx_error_add(&info);
5384 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5385 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5386 info.status_mask = 1ull<<20 /* loc_fault */;
5387 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5388 info.enable_mask = 1ull<<20 /* loc_fault */;
5390 info.group = CVMX_ERROR_GROUP_ETHERNET;
5391 info.group_index = 3;
5392 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5393 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5394 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5395 info.func = __cvmx_error_display;
5396 info.user_info = (long)
5397 "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
5398 " (XAUI Mode only)\n";
5399 fail |= cvmx_error_add(&info);
5401 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5402 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5403 info.status_mask = 1ull<<21 /* rem_fault */;
5404 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5405 info.enable_mask = 1ull<<21 /* rem_fault */;
5407 info.group = CVMX_ERROR_GROUP_ETHERNET;
5408 info.group_index = 3;
5409 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5410 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5411 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5412 info.func = __cvmx_error_display;
5413 info.user_info = (long)
5414 "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
5415 " (XAUI Mode only)\n";
5416 fail |= cvmx_error_add(&info);
5418 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5419 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5420 info.status_mask = 1ull<<22 /* bad_seq */;
5421 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5422 info.enable_mask = 1ull<<22 /* bad_seq */;
5424 info.group = CVMX_ERROR_GROUP_ETHERNET;
5425 info.group_index = 3;
5426 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5427 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5428 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5429 info.func = __cvmx_error_display;
5430 info.user_info = (long)
5431 "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
5432 " (XAUI Mode only)\n";
5433 fail |= cvmx_error_add(&info);
5435 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5436 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5437 info.status_mask = 1ull<<23 /* bad_term */;
5438 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5439 info.enable_mask = 1ull<<23 /* bad_term */;
5441 info.group = CVMX_ERROR_GROUP_ETHERNET;
5442 info.group_index = 3;
5443 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5444 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5445 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5446 info.func = __cvmx_error_display;
5447 info.user_info = (long)
5448 "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
5449 " than /T/. The error propagation control\n"
5450 " character /E/ will be included as part of the\n"
5451 " frame and does not cause a frame termination.\n"
5452 " (XAUI Mode only)\n";
5453 fail |= cvmx_error_add(&info);
5455 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5456 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5457 info.status_mask = 1ull<<24 /* unsop */;
5458 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5459 info.enable_mask = 1ull<<24 /* unsop */;
5461 info.group = CVMX_ERROR_GROUP_ETHERNET;
5462 info.group_index = 3;
5463 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5464 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5465 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5466 info.func = __cvmx_error_display;
5467 info.user_info = (long)
5468 "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
5469 " (XAUI Mode only)\n";
5470 fail |= cvmx_error_add(&info);
5472 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5473 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5474 info.status_mask = 1ull<<25 /* uneop */;
5475 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5476 info.enable_mask = 1ull<<25 /* uneop */;
5478 info.group = CVMX_ERROR_GROUP_ETHERNET;
5479 info.group_index = 3;
5480 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5481 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5482 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5483 info.func = __cvmx_error_display;
5484 info.user_info = (long)
5485 "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
5486 " (XAUI Mode only)\n";
5487 fail |= cvmx_error_add(&info);
5489 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5490 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5491 info.status_mask = 1ull<<26 /* undat */;
5492 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5493 info.enable_mask = 1ull<<26 /* undat */;
5495 info.group = CVMX_ERROR_GROUP_ETHERNET;
5496 info.group_index = 3;
5497 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5498 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5499 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5500 info.func = __cvmx_error_display;
5501 info.user_info = (long)
5502 "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
5503 " (XAUI Mode only)\n";
5504 fail |= cvmx_error_add(&info);
5506 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5507 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5508 info.status_mask = 1ull<<27 /* hg2fld */;
5509 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5510 info.enable_mask = 1ull<<27 /* hg2fld */;
5512 info.group = CVMX_ERROR_GROUP_ETHERNET;
5513 info.group_index = 3;
5514 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5515 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5516 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5517 info.func = __cvmx_error_display;
5518 info.user_info = (long)
5519 "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
5520 " 1) MSG_TYPE field not 6'b00_0000\n"
5521 " i.e. it is not a FLOW CONTROL message, which\n"
5522 " is the only defined type for HiGig2\n"
5523 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
5524 " which is the only defined type for HiGig2\n"
5525 " 3) FC_OBJECT field is neither 4'b0000 for\n"
5526 " Physical Link nor 4'b0010 for Logical Link.\n"
5527 " Those are the only two defined types in HiGig2\n";
5528 fail |= cvmx_error_add(&info);
5530 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5531 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5532 info.status_mask = 1ull<<28 /* hg2cc */;
5533 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5534 info.enable_mask = 1ull<<28 /* hg2cc */;
5536 info.group = CVMX_ERROR_GROUP_ETHERNET;
5537 info.group_index = 3;
5538 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5539 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5540 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5541 info.func = __cvmx_error_display;
5542 info.user_info = (long)
5543 "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
5544 " Set when either CRC8 error detected or when\n"
5545 " a Control Character is found in the message\n"
5546 " bytes after the K.SOM\n"
5547 " NOTE: HG2CC has higher priority than HG2FLD\n"
5548 " i.e. a HiGig2 message that results in HG2CC\n"
5549 " getting set, will never set HG2FLD.\n";
5550 fail |= cvmx_error_add(&info);
5552 /* CVMX_GMXX_TX_INT_REG(0) */
5553 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5554 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
5555 info.status_mask = 1ull<<0 /* pko_nxa */;
5556 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
5557 info.enable_mask = 1ull<<0 /* pko_nxa */;
5559 info.group = CVMX_ERROR_GROUP_ETHERNET;
5560 info.group_index = 0;
5561 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5562 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5563 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5564 info.func = __cvmx_error_display;
5565 info.user_info = (long)
5566 "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
5567 fail |= cvmx_error_add(&info);
5569 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5570 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
5571 info.status_mask = 0xfull<<2 /* undflw */;
5572 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
5573 info.enable_mask = 0xfull<<2 /* undflw */;
5575 info.group = CVMX_ERROR_GROUP_ETHERNET;
5576 info.group_index = 0;
5577 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5578 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5579 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5580 info.func = __cvmx_error_display;
5581 info.user_info = (long)
5582 "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
5583 fail |= cvmx_error_add(&info);
5585 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5586 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
5587 info.status_mask = 0xfull<<20 /* ptp_lost */;
5588 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
5589 info.enable_mask = 0xfull<<20 /* ptp_lost */;
5591 info.group = CVMX_ERROR_GROUP_ETHERNET;
5592 info.group_index = 0;
5593 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5594 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5595 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5596 info.func = __cvmx_error_display;
5597 info.user_info = (long)
5598 "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
5599 " sent due to XSCOL\n";
5600 fail |= cvmx_error_add(&info);
5602 /* CVMX_IOB_INT_SUM */
5603 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5604 info.status_addr = CVMX_IOB_INT_SUM;
5605 info.status_mask = 1ull<<0 /* np_sop */;
5606 info.enable_addr = CVMX_IOB_INT_ENB;
5607 info.enable_mask = 1ull<<0 /* np_sop */;
5609 info.group = CVMX_ERROR_GROUP_INTERNAL;
5610 info.group_index = 0;
5611 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5612 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5613 info.parent.status_mask = 1ull<<30 /* iob */;
5614 info.func = __cvmx_error_display;
5615 info.user_info = (long)
5616 "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
5617 " port for a non-passthrough packet.\n"
5618 " The first detected error associated with bits [5:0]\n"
5619 " of this register will only be set here. A new bit\n"
5620 " can be set when the previous reported bit is cleared.\n";
5621 fail |= cvmx_error_add(&info);
5623 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5624 info.status_addr = CVMX_IOB_INT_SUM;
5625 info.status_mask = 1ull<<1 /* np_eop */;
5626 info.enable_addr = CVMX_IOB_INT_ENB;
5627 info.enable_mask = 1ull<<1 /* np_eop */;
5629 info.group = CVMX_ERROR_GROUP_INTERNAL;
5630 info.group_index = 0;
5631 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5632 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5633 info.parent.status_mask = 1ull<<30 /* iob */;
5634 info.func = __cvmx_error_display;
5635 info.user_info = (long)
5636 "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
5637 " port for a non-passthrough packet.\n"
5638 " The first detected error associated with bits [5:0]\n"
5639 " of this register will only be set here. A new bit\n"
5640 " can be set when the previous reported bit is cleared.\n";
5641 fail |= cvmx_error_add(&info);
5643 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5644 info.status_addr = CVMX_IOB_INT_SUM;
5645 info.status_mask = 1ull<<2 /* p_sop */;
5646 info.enable_addr = CVMX_IOB_INT_ENB;
5647 info.enable_mask = 1ull<<2 /* p_sop */;
5649 info.group = CVMX_ERROR_GROUP_INTERNAL;
5650 info.group_index = 0;
5651 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5652 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5653 info.parent.status_mask = 1ull<<30 /* iob */;
5654 info.func = __cvmx_error_display;
5655 info.user_info = (long)
5656 "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
5657 " port for a passthrough packet.\n"
5658 " The first detected error associated with bits [5:0]\n"
5659 " of this register will only be set here. A new bit\n"
5660 " can be set when the previous reported bit is cleared.\n";
5661 fail |= cvmx_error_add(&info);
5663 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5664 info.status_addr = CVMX_IOB_INT_SUM;
5665 info.status_mask = 1ull<<3 /* p_eop */;
5666 info.enable_addr = CVMX_IOB_INT_ENB;
5667 info.enable_mask = 1ull<<3 /* p_eop */;
5669 info.group = CVMX_ERROR_GROUP_INTERNAL;
5670 info.group_index = 0;
5671 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5672 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5673 info.parent.status_mask = 1ull<<30 /* iob */;
5674 info.func = __cvmx_error_display;
5675 info.user_info = (long)
5676 "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
5677 " port for a passthrough packet.\n"
5678 " The first detected error associated with bits [5:0]\n"
5679 " of this register will only be set here. A new bit\n"
5680 " can be set when the previous reported bit is cleared.\n";
5681 fail |= cvmx_error_add(&info);
5683 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5684 info.status_addr = CVMX_IOB_INT_SUM;
5685 info.status_mask = 1ull<<4 /* np_dat */;
5686 info.enable_addr = CVMX_IOB_INT_ENB;
5687 info.enable_mask = 1ull<<4 /* np_dat */;
5689 info.group = CVMX_ERROR_GROUP_INTERNAL;
5690 info.group_index = 0;
5691 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5692 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5693 info.parent.status_mask = 1ull<<30 /* iob */;
5694 info.func = __cvmx_error_display;
5695 info.user_info = (long)
5696 "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
5697 " port for a non-passthrough packet.\n"
5698 " The first detected error associated with bits [5:0]\n"
5699 " of this register will only be set here. A new bit\n"
5700 " can be set when the previous reported bit is cleared.\n";
5701 fail |= cvmx_error_add(&info);
5703 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5704 info.status_addr = CVMX_IOB_INT_SUM;
5705 info.status_mask = 1ull<<5 /* p_dat */;
5706 info.enable_addr = CVMX_IOB_INT_ENB;
5707 info.enable_mask = 1ull<<5 /* p_dat */;
5709 info.group = CVMX_ERROR_GROUP_INTERNAL;
5710 info.group_index = 0;
5711 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5712 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5713 info.parent.status_mask = 1ull<<30 /* iob */;
5714 info.func = __cvmx_error_display;
5715 info.user_info = (long)
5716 "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
5717 " port for a passthrough packet.\n"
5718 " The first detected error associated with bits [5:0]\n"
5719 " of this register will only be set here. A new bit\n"
5720 " can be set when the previous reported bit is cleared.\n";
5721 fail |= cvmx_error_add(&info);
5723 /* CVMX_AGL_GMX_BAD_REG */
5724 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5725 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5726 info.status_mask = 1ull<<32 /* ovrflw */;
5727 info.enable_addr = 0;
5728 info.enable_mask = 0;
5730 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5731 info.group_index = 0;
5732 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5733 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5734 info.parent.status_mask = 1ull<<28 /* agl */;
5735 info.func = __cvmx_error_display;
5736 info.user_info = (long)
5737 "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
5738 fail |= cvmx_error_add(&info);
5740 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5741 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5742 info.status_mask = 1ull<<33 /* txpop */;
5743 info.enable_addr = 0;
5744 info.enable_mask = 0;
5746 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5747 info.group_index = 0;
5748 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5749 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5750 info.parent.status_mask = 1ull<<28 /* agl */;
5751 info.func = __cvmx_error_display;
5752 info.user_info = (long)
5753 "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
5754 fail |= cvmx_error_add(&info);
5756 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5757 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5758 info.status_mask = 1ull<<34 /* txpsh */;
5759 info.enable_addr = 0;
5760 info.enable_mask = 0;
5762 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5763 info.group_index = 0;
5764 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5765 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5766 info.parent.status_mask = 1ull<<28 /* agl */;
5767 info.func = __cvmx_error_display;
5768 info.user_info = (long)
5769 "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
5770 fail |= cvmx_error_add(&info);
5772 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5773 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5774 info.status_mask = 1ull<<35 /* ovrflw1 */;
5775 info.enable_addr = 0;
5776 info.enable_mask = 0;
5778 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5779 info.group_index = 0;
5780 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5781 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5782 info.parent.status_mask = 1ull<<28 /* agl */;
5783 info.func = __cvmx_error_display;
5784 info.user_info = (long)
5785 "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
5786 fail |= cvmx_error_add(&info);
5788 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5789 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5790 info.status_mask = 1ull<<36 /* txpop1 */;
5791 info.enable_addr = 0;
5792 info.enable_mask = 0;
5794 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5795 info.group_index = 0;
5796 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5797 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5798 info.parent.status_mask = 1ull<<28 /* agl */;
5799 info.func = __cvmx_error_display;
5800 info.user_info = (long)
5801 "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
5802 fail |= cvmx_error_add(&info);
5804 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5805 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5806 info.status_mask = 1ull<<37 /* txpsh1 */;
5807 info.enable_addr = 0;
5808 info.enable_mask = 0;
5810 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5811 info.group_index = 0;
5812 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5813 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5814 info.parent.status_mask = 1ull<<28 /* agl */;
5815 info.func = __cvmx_error_display;
5816 info.user_info = (long)
5817 "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
5818 fail |= cvmx_error_add(&info);
5820 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5821 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5822 info.status_mask = 0x3ull<<2 /* out_ovr */;
5823 info.enable_addr = 0;
5824 info.enable_mask = 0;
5826 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5827 info.group_index = 0;
5828 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5829 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5830 info.parent.status_mask = 1ull<<28 /* agl */;
5831 info.func = __cvmx_error_display;
5832 info.user_info = (long)
5833 "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
5834 fail |= cvmx_error_add(&info);
5836 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5837 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5838 info.status_mask = 0x3ull<<22 /* loststat */;
5839 info.enable_addr = 0;
5840 info.enable_mask = 0;
5842 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5843 info.group_index = 0;
5844 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5845 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5846 info.parent.status_mask = 1ull<<28 /* agl */;
5847 info.func = __cvmx_error_display;
5848 info.user_info = (long)
5849 "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
5850 " In MII/RGMII, one bit per port\n"
5851 " TX Stats are corrupted\n";
5852 fail |= cvmx_error_add(&info);
5854 /* CVMX_AGL_GMX_RXX_INT_REG(0) */
5855 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5856 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
5857 info.status_mask = 1ull<<8 /* skperr */;
5858 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
5859 info.enable_mask = 1ull<<8 /* skperr */;
5861 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5862 info.group_index = 0;
5863 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5864 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5865 info.parent.status_mask = 1ull<<28 /* agl */;
5866 info.func = __cvmx_error_display;
5867 info.user_info = (long)
5868 "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
5869 fail |= cvmx_error_add(&info);
5871 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5872 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
5873 info.status_mask = 1ull<<10 /* ovrerr */;
5874 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
5875 info.enable_mask = 1ull<<10 /* ovrerr */;
5877 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5878 info.group_index = 0;
5879 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5880 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5881 info.parent.status_mask = 1ull<<28 /* agl */;
5882 info.func = __cvmx_error_display;
5883 info.user_info = (long)
5884 "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
5885 " This interrupt should never assert\n";
5886 fail |= cvmx_error_add(&info);
5888 /* CVMX_AGL_GMX_RXX_INT_REG(1) */
5889 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5890 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
5891 info.status_mask = 1ull<<8 /* skperr */;
5892 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
5893 info.enable_mask = 1ull<<8 /* skperr */;
5895 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5896 info.group_index = 1;
5897 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5898 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5899 info.parent.status_mask = 1ull<<28 /* agl */;
5900 info.func = __cvmx_error_display;
5901 info.user_info = (long)
5902 "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
5903 fail |= cvmx_error_add(&info);
5905 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5906 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
5907 info.status_mask = 1ull<<10 /* ovrerr */;
5908 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
5909 info.enable_mask = 1ull<<10 /* ovrerr */;
5911 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5912 info.group_index = 1;
5913 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5914 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5915 info.parent.status_mask = 1ull<<28 /* agl */;
5916 info.func = __cvmx_error_display;
5917 info.user_info = (long)
5918 "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
5919 " This interrupt should never assert\n";
5920 fail |= cvmx_error_add(&info);
5922 /* CVMX_AGL_GMX_TX_INT_REG */
5923 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5924 info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
5925 info.status_mask = 1ull<<0 /* pko_nxa */;
5926 info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
5927 info.enable_mask = 1ull<<0 /* pko_nxa */;
5929 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5930 info.group_index = 0;
5931 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5932 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5933 info.parent.status_mask = 1ull<<28 /* agl */;
5934 info.func = __cvmx_error_display;
5935 info.user_info = (long)
5936 "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
5937 fail |= cvmx_error_add(&info);
5939 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5940 info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
5941 info.status_mask = 0x3ull<<2 /* undflw */;
5942 info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
5943 info.enable_mask = 0x3ull<<2 /* undflw */;
5945 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5946 info.group_index = 0;
5947 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5948 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5949 info.parent.status_mask = 1ull<<28 /* agl */;
5950 info.func = __cvmx_error_display;
5951 info.user_info = (long)
5952 "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
5953 fail |= cvmx_error_add(&info);
5955 /* CVMX_ZIP_ERROR */
5956 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5957 info.status_addr = CVMX_ZIP_ERROR;
5958 info.status_mask = 1ull<<0 /* doorbell */;
5959 info.enable_addr = CVMX_ZIP_INT_MASK;
5960 info.enable_mask = 1ull<<0 /* doorbell */;
5962 info.group = CVMX_ERROR_GROUP_INTERNAL;
5963 info.group_index = 0;
5964 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5965 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5966 info.parent.status_mask = 1ull<<7 /* zip */;
5967 info.func = __cvmx_error_display;
5968 info.user_info = (long)
5969 "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
5970 fail |= cvmx_error_add(&info);
5972 /* CVMX_DFA_ERROR */
5973 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5974 info.status_addr = CVMX_DFA_ERROR;
5975 info.status_mask = 1ull<<0 /* dblovf */;
5976 info.enable_addr = CVMX_DFA_INTMSK;
5977 info.enable_mask = 1ull<<0 /* dblina */;
5979 info.group = CVMX_ERROR_GROUP_INTERNAL;
5980 info.group_index = 0;
5981 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5982 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5983 info.parent.status_mask = 1ull<<6 /* dfa */;
5984 info.func = __cvmx_error_display;
5985 info.user_info = (long)
5986 "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
5987 " When set, the 20b accumulated doorbell register\n"
5988 " had overflowed (SW wrote too many doorbell requests).\n"
5989 " If the DBLINA had previously been enabled(set),\n"
5990 " an interrupt will be posted. Software can clear\n"
5991 " the interrupt by writing a 1 to this register bit.\n"
5992 " NOTE: Detection of a Doorbell Register overflow\n"
5993 " is a catastrophic error which may leave the DFA\n"
5994 " HW in an unrecoverable state.\n";
5995 fail |= cvmx_error_add(&info);
5997 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5998 info.status_addr = CVMX_DFA_ERROR;
5999 info.status_mask = 0x7ull<<1 /* dc0perr */;
6000 info.enable_addr = CVMX_DFA_INTMSK;
6001 info.enable_mask = 0x7ull<<1 /* dc0pena */;
6003 info.group = CVMX_ERROR_GROUP_INTERNAL;
6004 info.group_index = 0;
6005 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6006 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6007 info.parent.status_mask = 1ull<<6 /* dfa */;
6008 info.func = __cvmx_error_display;
6009 info.user_info = (long)
6010 "ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0\n"
6011 " See also DFA_DTCFADR register which contains the\n"
6012 " failing addresses for the internal node cache RAMs.\n";
6013 fail |= cvmx_error_add(&info);
6015 /* CVMX_SRIOX_INT_REG(0) */
6016 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6017 info.status_addr = CVMX_SRIOX_INT_REG(0);
6018 info.status_mask = 1ull<<4 /* bar_err */;
6019 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6020 info.enable_mask = 1ull<<4 /* bar_err */;
6022 info.group = CVMX_ERROR_GROUP_SRIO;
6023 info.group_index = 0;
6024 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6025 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6026 info.parent.status_mask = 1ull<<32 /* srio0 */;
6027 info.func = __cvmx_error_display;
6028 info.user_info = (long)
6029 "ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
6030 fail |= cvmx_error_add(&info);
6032 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6033 info.status_addr = CVMX_SRIOX_INT_REG(0);
6034 info.status_mask = 1ull<<5 /* deny_wr */;
6035 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6036 info.enable_mask = 1ull<<5 /* deny_wr */;
6038 info.group = CVMX_ERROR_GROUP_SRIO;
6039 info.group_index = 0;
6040 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6041 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6042 info.parent.status_mask = 1ull<<32 /* srio0 */;
6043 info.func = __cvmx_error_display;
6044 info.user_info = (long)
6045 "ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
6046 fail |= cvmx_error_add(&info);
6048 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6049 info.status_addr = CVMX_SRIOX_INT_REG(0);
6050 info.status_mask = 1ull<<6 /* sli_err */;
6051 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6052 info.enable_mask = 1ull<<6 /* sli_err */;
6054 info.group = CVMX_ERROR_GROUP_SRIO;
6055 info.group_index = 0;
6056 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6057 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6058 info.parent.status_mask = 1ull<<32 /* srio0 */;
6059 info.func = __cvmx_error_display;
6060 info.user_info = (long)
6061 "ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
6062 " See SRIO(0..1)_INT_INFO[1:0]\n";
6063 fail |= cvmx_error_add(&info);
6065 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6066 info.status_addr = CVMX_SRIOX_INT_REG(0);
6067 info.status_mask = 1ull<<9 /* mce_rx */;
6068 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6069 info.enable_mask = 1ull<<9 /* mce_rx */;
6071 info.group = CVMX_ERROR_GROUP_SRIO;
6072 info.group_index = 0;
6073 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6074 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6075 info.parent.status_mask = 1ull<<32 /* srio0 */;
6076 info.func = __cvmx_error_display;
6077 info.user_info = (long)
6078 "ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol\n";
6079 fail |= cvmx_error_add(&info);
6081 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6082 info.status_addr = CVMX_SRIOX_INT_REG(0);
6083 info.status_mask = 1ull<<12 /* log_erb */;
6084 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6085 info.enable_mask = 1ull<<12 /* log_erb */;
6087 info.group = CVMX_ERROR_GROUP_SRIO;
6088 info.group_index = 0;
6089 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6090 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6091 info.parent.status_mask = 1ull<<32 /* srio0 */;
6092 info.func = __cvmx_error_display;
6093 info.user_info = (long)
6094 "ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
6095 " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
6096 fail |= cvmx_error_add(&info);
6098 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6099 info.status_addr = CVMX_SRIOX_INT_REG(0);
6100 info.status_mask = 1ull<<13 /* phy_erb */;
6101 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6102 info.enable_mask = 1ull<<13 /* phy_erb */;
6104 info.group = CVMX_ERROR_GROUP_SRIO;
6105 info.group_index = 0;
6106 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6107 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6108 info.parent.status_mask = 1ull<<32 /* srio0 */;
6109 info.func = __cvmx_error_display;
6110 info.user_info = (long)
6111 "ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB\n"
6112 " See SRIOMAINT*_ERB_ATTR_CAPT\n";
6113 fail |= cvmx_error_add(&info);
6115 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6116 info.status_addr = CVMX_SRIOX_INT_REG(0);
6117 info.status_mask = 1ull<<18 /* omsg_err */;
6118 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6119 info.enable_mask = 1ull<<18 /* omsg_err */;
6121 info.group = CVMX_ERROR_GROUP_SRIO;
6122 info.group_index = 0;
6123 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6124 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6125 info.parent.status_mask = 1ull<<32 /* srio0 */;
6126 info.func = __cvmx_error_display;
6127 info.user_info = (long)
6128 "ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
6129 " See SRIO(0..1)_INT_INFO2\n";
6130 fail |= cvmx_error_add(&info);
6132 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6133 info.status_addr = CVMX_SRIOX_INT_REG(0);
6134 info.status_mask = 1ull<<19 /* pko_err */;
6135 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6136 info.enable_mask = 1ull<<19 /* pko_err */;
6138 info.group = CVMX_ERROR_GROUP_SRIO;
6139 info.group_index = 0;
6140 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6141 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6142 info.parent.status_mask = 1ull<<32 /* srio0 */;
6143 info.func = __cvmx_error_display;
6144 info.user_info = (long)
6145 "ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error\n";
6146 fail |= cvmx_error_add(&info);
6148 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6149 info.status_addr = CVMX_SRIOX_INT_REG(0);
6150 info.status_mask = 1ull<<20 /* rtry_err */;
6151 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6152 info.enable_mask = 1ull<<20 /* rtry_err */;
6154 info.group = CVMX_ERROR_GROUP_SRIO;
6155 info.group_index = 0;
6156 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6157 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6158 info.parent.status_mask = 1ull<<32 /* srio0 */;
6159 info.func = __cvmx_error_display;
6160 info.user_info = (long)
6161 "ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
6162 " See SRIO(0..1)_INT_INFO3\n"
6163 " When one or more of the segments in an outgoing\n"
6164 " message have a RTRY_ERR, SRIO will not set\n"
6165 " OMSG* after the message \"transfer\".\n";
6166 fail |= cvmx_error_add(&info);
6168 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6169 info.status_addr = CVMX_SRIOX_INT_REG(0);
6170 info.status_mask = 1ull<<21 /* f_error */;
6171 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6172 info.enable_mask = 1ull<<21 /* f_error */;
6174 info.group = CVMX_ERROR_GROUP_SRIO;
6175 info.group_index = 0;
6176 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6177 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6178 info.parent.status_mask = 1ull<<32 /* srio0 */;
6179 info.func = __cvmx_error_display;
6180 info.user_info = (long)
6181 "ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
6182 fail |= cvmx_error_add(&info);
6184 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6185 info.status_addr = CVMX_SRIOX_INT_REG(0);
6186 info.status_mask = 1ull<<22 /* mac_buf */;
6187 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6188 info.enable_mask = 1ull<<22 /* mac_buf */;
6190 info.group = CVMX_ERROR_GROUP_SRIO;
6191 info.group_index = 0;
6192 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6193 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6194 info.parent.status_mask = 1ull<<32 /* srio0 */;
6195 info.func = __cvmx_error_display;
6196 info.user_info = (long)
6197 "ERROR SRIOX_INT_REG(0)[MAC_BUF]: SRIO MAC Buffer CRC Error (Pass 2)\n"
6198 " See SRIO(0..1)_MAC_BUFFERS\n";
6199 fail |= cvmx_error_add(&info);
6201 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6202 info.status_addr = CVMX_SRIOX_INT_REG(0);
6203 info.status_mask = 1ull<<23 /* degrad */;
6204 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6205 info.enable_mask = 1ull<<23 /* degrade */;
6207 info.group = CVMX_ERROR_GROUP_SRIO;
6208 info.group_index = 0;
6209 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6210 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6211 info.parent.status_mask = 1ull<<32 /* srio0 */;
6212 info.func = __cvmx_error_display;
6213 info.user_info = (long)
6214 "ERROR SRIOX_INT_REG(0)[DEGRAD]: ERB Error Rate reached Degrade Count (Pass 2)\n"
6215 " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
6216 fail |= cvmx_error_add(&info);
6218 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6219 info.status_addr = CVMX_SRIOX_INT_REG(0);
6220 info.status_mask = 1ull<<24 /* fail */;
6221 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6222 info.enable_mask = 1ull<<24 /* fail */;
6224 info.group = CVMX_ERROR_GROUP_SRIO;
6225 info.group_index = 0;
6226 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6227 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6228 info.parent.status_mask = 1ull<<32 /* srio0 */;
6229 info.func = __cvmx_error_display;
6230 info.user_info = (long)
6231 "ERROR SRIOX_INT_REG(0)[FAIL]: ERB Error Rate reached Fail Count (Pass 2)\n"
6232 " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
6233 fail |= cvmx_error_add(&info);
6235 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6236 info.status_addr = CVMX_SRIOX_INT_REG(0);
6237 info.status_mask = 1ull<<25 /* ttl_tout */;
6238 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6239 info.enable_mask = 1ull<<25 /* ttl_tout */;
6241 info.group = CVMX_ERROR_GROUP_SRIO;
6242 info.group_index = 0;
6243 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6244 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6245 info.parent.status_mask = 1ull<<32 /* srio0 */;
6246 info.func = __cvmx_error_display;
6247 info.user_info = (long)
6248 "ERROR SRIOX_INT_REG(0)[TTL_TOUT]: Outgoing Packet Time to Live Timeout (Pass 2)\n"
6249 " See SRIOMAINT(0..1)_DROP_PACKET\n";
6250 fail |= cvmx_error_add(&info);
6252 /* CVMX_SRIOX_INT_REG(1) */
6253 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6254 info.status_addr = CVMX_SRIOX_INT_REG(1);
6255 info.status_mask = 1ull<<4 /* bar_err */;
6256 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6257 info.enable_mask = 1ull<<4 /* bar_err */;
6259 info.group = CVMX_ERROR_GROUP_SRIO;
6260 info.group_index = 1;
6261 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6262 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6263 info.parent.status_mask = 1ull<<33 /* srio1 */;
6264 info.func = __cvmx_error_display;
6265 info.user_info = (long)
6266 "ERROR SRIOX_INT_REG(1)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
6267 fail |= cvmx_error_add(&info);
6269 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6270 info.status_addr = CVMX_SRIOX_INT_REG(1);
6271 info.status_mask = 1ull<<5 /* deny_wr */;
6272 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6273 info.enable_mask = 1ull<<5 /* deny_wr */;
6275 info.group = CVMX_ERROR_GROUP_SRIO;
6276 info.group_index = 1;
6277 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6278 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6279 info.parent.status_mask = 1ull<<33 /* srio1 */;
6280 info.func = __cvmx_error_display;
6281 info.user_info = (long)
6282 "ERROR SRIOX_INT_REG(1)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
6283 fail |= cvmx_error_add(&info);
6285 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6286 info.status_addr = CVMX_SRIOX_INT_REG(1);
6287 info.status_mask = 1ull<<6 /* sli_err */;
6288 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6289 info.enable_mask = 1ull<<6 /* sli_err */;
6291 info.group = CVMX_ERROR_GROUP_SRIO;
6292 info.group_index = 1;
6293 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6294 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6295 info.parent.status_mask = 1ull<<33 /* srio1 */;
6296 info.func = __cvmx_error_display;
6297 info.user_info = (long)
6298 "ERROR SRIOX_INT_REG(1)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
6299 " See SRIO(0..1)_INT_INFO[1:0]\n";
6300 fail |= cvmx_error_add(&info);
6302 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6303 info.status_addr = CVMX_SRIOX_INT_REG(1);
6304 info.status_mask = 1ull<<9 /* mce_rx */;
6305 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6306 info.enable_mask = 1ull<<9 /* mce_rx */;
6308 info.group = CVMX_ERROR_GROUP_SRIO;
6309 info.group_index = 1;
6310 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6311 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6312 info.parent.status_mask = 1ull<<33 /* srio1 */;
6313 info.func = __cvmx_error_display;
6314 info.user_info = (long)
6315 "ERROR SRIOX_INT_REG(1)[MCE_RX]: Incoming Multicast Event Symbol\n";
6316 fail |= cvmx_error_add(&info);
6318 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6319 info.status_addr = CVMX_SRIOX_INT_REG(1);
6320 info.status_mask = 1ull<<12 /* log_erb */;
6321 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6322 info.enable_mask = 1ull<<12 /* log_erb */;
6324 info.group = CVMX_ERROR_GROUP_SRIO;
6325 info.group_index = 1;
6326 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6327 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6328 info.parent.status_mask = 1ull<<33 /* srio1 */;
6329 info.func = __cvmx_error_display;
6330 info.user_info = (long)
6331 "ERROR SRIOX_INT_REG(1)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
6332 " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
6333 fail |= cvmx_error_add(&info);
6335 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6336 info.status_addr = CVMX_SRIOX_INT_REG(1);
6337 info.status_mask = 1ull<<13 /* phy_erb */;
6338 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6339 info.enable_mask = 1ull<<13 /* phy_erb */;
6341 info.group = CVMX_ERROR_GROUP_SRIO;
6342 info.group_index = 1;
6343 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6344 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6345 info.parent.status_mask = 1ull<<33 /* srio1 */;
6346 info.func = __cvmx_error_display;
6347 info.user_info = (long)
6348 "ERROR SRIOX_INT_REG(1)[PHY_ERB]: Physical Layer Error detected in ERB\n"
6349 " See SRIOMAINT*_ERB_ATTR_CAPT\n";
6350 fail |= cvmx_error_add(&info);
6352 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6353 info.status_addr = CVMX_SRIOX_INT_REG(1);
6354 info.status_mask = 1ull<<18 /* omsg_err */;
6355 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6356 info.enable_mask = 1ull<<18 /* omsg_err */;
6358 info.group = CVMX_ERROR_GROUP_SRIO;
6359 info.group_index = 1;
6360 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6361 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6362 info.parent.status_mask = 1ull<<33 /* srio1 */;
6363 info.func = __cvmx_error_display;
6364 info.user_info = (long)
6365 "ERROR SRIOX_INT_REG(1)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
6366 " See SRIO(0..1)_INT_INFO2\n";
6367 fail |= cvmx_error_add(&info);
6369 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6370 info.status_addr = CVMX_SRIOX_INT_REG(1);
6371 info.status_mask = 1ull<<19 /* pko_err */;
6372 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6373 info.enable_mask = 1ull<<19 /* pko_err */;
6375 info.group = CVMX_ERROR_GROUP_SRIO;
6376 info.group_index = 1;
6377 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6378 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6379 info.parent.status_mask = 1ull<<33 /* srio1 */;
6380 info.func = __cvmx_error_display;
6381 info.user_info = (long)
6382 "ERROR SRIOX_INT_REG(1)[PKO_ERR]: Outbound Message Received PKO Error\n";
6383 fail |= cvmx_error_add(&info);
6385 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6386 info.status_addr = CVMX_SRIOX_INT_REG(1);
6387 info.status_mask = 1ull<<20 /* rtry_err */;
6388 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6389 info.enable_mask = 1ull<<20 /* rtry_err */;
6391 info.group = CVMX_ERROR_GROUP_SRIO;
6392 info.group_index = 1;
6393 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6394 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6395 info.parent.status_mask = 1ull<<33 /* srio1 */;
6396 info.func = __cvmx_error_display;
6397 info.user_info = (long)
6398 "ERROR SRIOX_INT_REG(1)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
6399 " See SRIO(0..1)_INT_INFO3\n"
6400 " When one or more of the segments in an outgoing\n"
6401 " message have a RTRY_ERR, SRIO will not set\n"
6402 " OMSG* after the message \"transfer\".\n";
6403 fail |= cvmx_error_add(&info);
6405 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6406 info.status_addr = CVMX_SRIOX_INT_REG(1);
6407 info.status_mask = 1ull<<21 /* f_error */;
6408 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6409 info.enable_mask = 1ull<<21 /* f_error */;
6411 info.group = CVMX_ERROR_GROUP_SRIO;
6412 info.group_index = 1;
6413 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6414 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6415 info.parent.status_mask = 1ull<<33 /* srio1 */;
6416 info.func = __cvmx_error_display;
6417 info.user_info = (long)
6418 "ERROR SRIOX_INT_REG(1)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
6419 fail |= cvmx_error_add(&info);
6421 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6422 info.status_addr = CVMX_SRIOX_INT_REG(1);
6423 info.status_mask = 1ull<<22 /* mac_buf */;
6424 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6425 info.enable_mask = 1ull<<22 /* mac_buf */;
6427 info.group = CVMX_ERROR_GROUP_SRIO;
6428 info.group_index = 1;
6429 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6430 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6431 info.parent.status_mask = 1ull<<33 /* srio1 */;
6432 info.func = __cvmx_error_display;
6433 info.user_info = (long)
6434 "ERROR SRIOX_INT_REG(1)[MAC_BUF]: SRIO MAC Buffer CRC Error (Pass 2)\n"
6435 " See SRIO(0..1)_MAC_BUFFERS\n";
6436 fail |= cvmx_error_add(&info);
6438 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6439 info.status_addr = CVMX_SRIOX_INT_REG(1);
6440 info.status_mask = 1ull<<23 /* degrad */;
6441 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6442 info.enable_mask = 1ull<<23 /* degrade */;
6444 info.group = CVMX_ERROR_GROUP_SRIO;
6445 info.group_index = 1;
6446 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6447 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6448 info.parent.status_mask = 1ull<<33 /* srio1 */;
6449 info.func = __cvmx_error_display;
6450 info.user_info = (long)
6451 "ERROR SRIOX_INT_REG(1)[DEGRAD]: ERB Error Rate reached Degrade Count (Pass 2)\n"
6452 " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
6453 fail |= cvmx_error_add(&info);
6455 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6456 info.status_addr = CVMX_SRIOX_INT_REG(1);
6457 info.status_mask = 1ull<<24 /* fail */;
6458 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6459 info.enable_mask = 1ull<<24 /* fail */;
6461 info.group = CVMX_ERROR_GROUP_SRIO;
6462 info.group_index = 1;
6463 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6464 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6465 info.parent.status_mask = 1ull<<33 /* srio1 */;
6466 info.func = __cvmx_error_display;
6467 info.user_info = (long)
6468 "ERROR SRIOX_INT_REG(1)[FAIL]: ERB Error Rate reached Fail Count (Pass 2)\n"
6469 " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
6470 fail |= cvmx_error_add(&info);
6472 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6473 info.status_addr = CVMX_SRIOX_INT_REG(1);
6474 info.status_mask = 1ull<<25 /* ttl_tout */;
6475 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6476 info.enable_mask = 1ull<<25 /* ttl_tout */;
6478 info.group = CVMX_ERROR_GROUP_SRIO;
6479 info.group_index = 1;
6480 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6481 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6482 info.parent.status_mask = 1ull<<33 /* srio1 */;
6483 info.func = __cvmx_error_display;
6484 info.user_info = (long)
6485 "ERROR SRIOX_INT_REG(1)[TTL_TOUT]: Outgoing Packet Time to Live Timeout (Pass 2)\n"
6486 " See SRIOMAINT(0..1)_DROP_PACKET\n";
6487 fail |= cvmx_error_add(&info);
6489 /* CVMX_PEXP_SLI_INT_SUM */
6490 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6491 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6492 info.status_mask = 1ull<<0 /* rml_to */;
6493 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6494 info.enable_mask = 1ull<<0 /* rml_to */;
6496 info.group = CVMX_ERROR_GROUP_INTERNAL;
6497 info.group_index = 0;
6498 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6499 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6500 info.parent.status_mask = 1ull<<3 /* sli */;
6501 info.func = __cvmx_error_display;
6502 info.user_info = (long)
6503 "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
6504 " within 0xffff core clocks.\n";
6505 fail |= cvmx_error_add(&info);
6507 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6508 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6509 info.status_mask = 1ull<<1 /* reserved_1_1 */;
6510 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6511 info.enable_mask = 1ull<<1 /* reserved_1_1 */;
6513 info.group = CVMX_ERROR_GROUP_INTERNAL;
6514 info.group_index = 0;
6515 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6516 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6517 info.parent.status_mask = 1ull<<3 /* sli */;
6518 info.func = __cvmx_error_display;
6519 info.user_info = (long)
6520 "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
6522 fail |= cvmx_error_add(&info);
6524 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6525 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6526 info.status_mask = 1ull<<2 /* bar0_to */;
6527 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6528 info.enable_mask = 1ull<<2 /* bar0_to */;
6530 info.group = CVMX_ERROR_GROUP_INTERNAL;
6531 info.group_index = 0;
6532 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6533 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6534 info.parent.status_mask = 1ull<<3 /* sli */;
6535 info.func = __cvmx_error_display;
6536 info.user_info = (long)
6537 "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
6538 " read-data/commit in 0xffff core clocks.\n";
6539 fail |= cvmx_error_add(&info);
6541 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6542 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6543 info.status_mask = 1ull<<3 /* iob2big */;
6544 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6545 info.enable_mask = 1ull<<3 /* iob2big */;
6547 info.group = CVMX_ERROR_GROUP_INTERNAL;
6548 info.group_index = 0;
6549 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6550 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6551 info.parent.status_mask = 1ull<<3 /* sli */;
6552 info.func = __cvmx_error_display;
6553 info.user_info = (long)
6554 "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
6555 fail |= cvmx_error_add(&info);
6557 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6558 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6559 info.status_mask = 0x3ull<<6 /* reserved_6_7 */;
6560 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6561 info.enable_mask = 0x3ull<<6 /* reserved_6_7 */;
6563 info.group = CVMX_ERROR_GROUP_INTERNAL;
6564 info.group_index = 0;
6565 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6566 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6567 info.parent.status_mask = 1ull<<3 /* sli */;
6568 info.func = __cvmx_error_display;
6569 info.user_info = (long)
6570 "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
6572 fail |= cvmx_error_add(&info);
6574 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6575 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6576 info.status_mask = 1ull<<8 /* m0_up_b0 */;
6577 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6578 info.enable_mask = 1ull<<8 /* m0_up_b0 */;
6580 info.group = CVMX_ERROR_GROUP_INTERNAL;
6581 info.group_index = 0;
6582 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6583 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6584 info.parent.status_mask = 1ull<<3 /* sli */;
6585 info.func = __cvmx_error_display;
6586 info.user_info = (long)
6587 "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
6588 " This occurs when the BAR 0 address space is\n"
6590 fail |= cvmx_error_add(&info);
6592 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6593 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6594 info.status_mask = 1ull<<9 /* m0_up_wi */;
6595 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6596 info.enable_mask = 1ull<<9 /* m0_up_wi */;
6598 info.group = CVMX_ERROR_GROUP_INTERNAL;
6599 info.group_index = 0;
6600 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6601 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6602 info.parent.status_mask = 1ull<<3 /* sli */;
6603 info.func = __cvmx_error_display;
6604 info.user_info = (long)
6605 "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
6606 " from MAC 0. This occurs when the window registers\n"
6607 " are disabeld and a window register access occurs.\n";
6608 fail |= cvmx_error_add(&info);
6610 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6611 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6612 info.status_mask = 1ull<<10 /* m0_un_b0 */;
6613 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6614 info.enable_mask = 1ull<<10 /* m0_un_b0 */;
6616 info.group = CVMX_ERROR_GROUP_INTERNAL;
6617 info.group_index = 0;
6618 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6619 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6620 info.parent.status_mask = 1ull<<3 /* sli */;
6621 info.func = __cvmx_error_display;
6622 info.user_info = (long)
6623 "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
6624 " This occurs when the BAR 0 address space is\n"
6626 fail |= cvmx_error_add(&info);
6628 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6629 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6630 info.status_mask = 1ull<<11 /* m0_un_wi */;
6631 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6632 info.enable_mask = 1ull<<11 /* m0_un_wi */;
6634 info.group = CVMX_ERROR_GROUP_INTERNAL;
6635 info.group_index = 0;
6636 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6637 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6638 info.parent.status_mask = 1ull<<3 /* sli */;
6639 info.func = __cvmx_error_display;
6640 info.user_info = (long)
6641 "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
6642 " from MAC 0. This occurs when the window registers\n"
6643 " are disabeld and a window register access occurs.\n";
6644 fail |= cvmx_error_add(&info);
6646 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6647 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6648 info.status_mask = 1ull<<12 /* m1_up_b0 */;
6649 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6650 info.enable_mask = 1ull<<12 /* m1_up_b0 */;
6652 info.group = CVMX_ERROR_GROUP_INTERNAL;
6653 info.group_index = 0;
6654 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6655 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6656 info.parent.status_mask = 1ull<<3 /* sli */;
6657 info.func = __cvmx_error_display;
6658 info.user_info = (long)
6659 "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
6660 " This occurs when the BAR 0 address space is\n"
6662 fail |= cvmx_error_add(&info);
6664 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6665 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6666 info.status_mask = 1ull<<13 /* m1_up_wi */;
6667 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6668 info.enable_mask = 1ull<<13 /* m1_up_wi */;
6670 info.group = CVMX_ERROR_GROUP_INTERNAL;
6671 info.group_index = 0;
6672 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6673 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6674 info.parent.status_mask = 1ull<<3 /* sli */;
6675 info.func = __cvmx_error_display;
6676 info.user_info = (long)
6677 "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
6678 " from MAC 1. This occurs when the window registers\n"
6679 " are disabeld and a window register access occurs.\n";
6680 fail |= cvmx_error_add(&info);
6682 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6683 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6684 info.status_mask = 1ull<<14 /* m1_un_b0 */;
6685 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6686 info.enable_mask = 1ull<<14 /* m1_un_b0 */;
6688 info.group = CVMX_ERROR_GROUP_INTERNAL;
6689 info.group_index = 0;
6690 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6691 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6692 info.parent.status_mask = 1ull<<3 /* sli */;
6693 info.func = __cvmx_error_display;
6694 info.user_info = (long)
6695 "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
6696 " This occurs when the BAR 0 address space is\n"
6698 fail |= cvmx_error_add(&info);
6700 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6701 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6702 info.status_mask = 1ull<<15 /* m1_un_wi */;
6703 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6704 info.enable_mask = 1ull<<15 /* m1_un_wi */;
6706 info.group = CVMX_ERROR_GROUP_INTERNAL;
6707 info.group_index = 0;
6708 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6709 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6710 info.parent.status_mask = 1ull<<3 /* sli */;
6711 info.func = __cvmx_error_display;
6712 info.user_info = (long)
6713 "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
6714 " from MAC 1. This occurs when the window registers\n"
6715 " are disabeld and a window register access occurs.\n";
6716 fail |= cvmx_error_add(&info);
6718 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6719 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6720 info.status_mask = 1ull<<48 /* pidbof */;
6721 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6722 info.enable_mask = 1ull<<48 /* pidbof */;
6724 info.group = CVMX_ERROR_GROUP_INTERNAL;
6725 info.group_index = 0;
6726 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6727 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6728 info.parent.status_mask = 1ull<<3 /* sli */;
6729 info.func = __cvmx_error_display;
6730 info.user_info = (long)
6731 "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
6732 " doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
6733 fail |= cvmx_error_add(&info);
6735 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6736 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6737 info.status_mask = 1ull<<49 /* psldbof */;
6738 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6739 info.enable_mask = 1ull<<49 /* psldbof */;
6741 info.group = CVMX_ERROR_GROUP_INTERNAL;
6742 info.group_index = 0;
6743 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6744 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6745 info.parent.status_mask = 1ull<<3 /* sli */;
6746 info.func = __cvmx_error_display;
6747 info.user_info = (long)
6748 "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
6749 " doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
6750 fail |= cvmx_error_add(&info);
6752 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6753 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6754 info.status_mask = 1ull<<50 /* pout_err */;
6755 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6756 info.enable_mask = 1ull<<50 /* pout_err */;
6758 info.group = CVMX_ERROR_GROUP_INTERNAL;
6759 info.group_index = 0;
6760 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6761 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6762 info.parent.status_mask = 1ull<<3 /* sli */;
6763 info.func = __cvmx_error_display;
6764 info.user_info = (long)
6765 "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
6767 fail |= cvmx_error_add(&info);
6769 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6770 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6771 info.status_mask = 1ull<<51 /* pin_bp */;
6772 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6773 info.enable_mask = 1ull<<51 /* pin_bp */;
6775 info.group = CVMX_ERROR_GROUP_INTERNAL;
6776 info.group_index = 0;
6777 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6778 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6779 info.parent.status_mask = 1ull<<3 /* sli */;
6780 info.func = __cvmx_error_display;
6781 info.user_info = (long)
6782 "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
6783 " See SLI_PKT_IN_BP\n";
6784 fail |= cvmx_error_add(&info);
6786 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6787 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6788 info.status_mask = 1ull<<52 /* pgl_err */;
6789 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6790 info.enable_mask = 1ull<<52 /* pgl_err */;
6792 info.group = CVMX_ERROR_GROUP_INTERNAL;
6793 info.group_index = 0;
6794 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6795 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6796 info.parent.status_mask = 1ull<<3 /* sli */;
6797 info.func = __cvmx_error_display;
6798 info.user_info = (long)
6799 "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
6800 " read this bit is set.\n";
6801 fail |= cvmx_error_add(&info);
6803 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6804 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6805 info.status_mask = 1ull<<53 /* pdi_err */;
6806 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6807 info.enable_mask = 1ull<<53 /* pdi_err */;
6809 info.group = CVMX_ERROR_GROUP_INTERNAL;
6810 info.group_index = 0;
6811 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6812 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6813 info.parent.status_mask = 1ull<<3 /* sli */;
6814 info.func = __cvmx_error_display;
6815 info.user_info = (long)
6816 "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
6817 " this bit is set.\n";
6818 fail |= cvmx_error_add(&info);
6820 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6821 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6822 info.status_mask = 1ull<<54 /* pop_err */;
6823 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6824 info.enable_mask = 1ull<<54 /* pop_err */;
6826 info.group = CVMX_ERROR_GROUP_INTERNAL;
6827 info.group_index = 0;
6828 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6829 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6830 info.parent.status_mask = 1ull<<3 /* sli */;
6831 info.func = __cvmx_error_display;
6832 info.user_info = (long)
6833 "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
6834 " pointer pair this bit is set.\n";
6835 fail |= cvmx_error_add(&info);
6837 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6838 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6839 info.status_mask = 1ull<<55 /* pins_err */;
6840 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6841 info.enable_mask = 1ull<<55 /* pins_err */;
6843 info.group = CVMX_ERROR_GROUP_INTERNAL;
6844 info.group_index = 0;
6845 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6846 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6847 info.parent.status_mask = 1ull<<3 /* sli */;
6848 info.func = __cvmx_error_display;
6849 info.user_info = (long)
6850 "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
6851 " this bit is set.\n";
6852 fail |= cvmx_error_add(&info);
6854 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6855 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6856 info.status_mask = 1ull<<56 /* sprt0_err */;
6857 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6858 info.enable_mask = 1ull<<56 /* sprt0_err */;
6860 info.group = CVMX_ERROR_GROUP_INTERNAL;
6861 info.group_index = 0;
6862 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6863 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6864 info.parent.status_mask = 1ull<<3 /* sli */;
6865 info.func = __cvmx_error_display;
6866 info.user_info = (long)
6867 "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
6868 " this bit is set.\n";
6869 fail |= cvmx_error_add(&info);
6871 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6872 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6873 info.status_mask = 1ull<<57 /* sprt1_err */;
6874 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6875 info.enable_mask = 1ull<<57 /* sprt1_err */;
6877 info.group = CVMX_ERROR_GROUP_INTERNAL;
6878 info.group_index = 0;
6879 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6880 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6881 info.parent.status_mask = 1ull<<3 /* sli */;
6882 info.func = __cvmx_error_display;
6883 info.user_info = (long)
6884 "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
6885 " this bit is set.\n";
6886 fail |= cvmx_error_add(&info);
6888 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6889 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6890 info.status_mask = 1ull<<60 /* ill_pad */;
6891 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6892 info.enable_mask = 1ull<<60 /* ill_pad */;
6894 info.group = CVMX_ERROR_GROUP_INTERNAL;
6895 info.group_index = 0;
6896 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6897 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6898 info.parent.status_mask = 1ull<<3 /* sli */;
6899 info.func = __cvmx_error_display;
6900 info.user_info = (long)
6901 "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
6902 " range of the Packet-CSR, but for an unused\n"
6904 fail |= cvmx_error_add(&info);
6906 /* CVMX_DPI_INT_REG */
6907 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6908 info.status_addr = CVMX_DPI_INT_REG;
6909 info.status_mask = 1ull<<0 /* nderr */;
6910 info.enable_addr = CVMX_DPI_INT_EN;
6911 info.enable_mask = 1ull<<0 /* nderr */;
6913 info.group = CVMX_ERROR_GROUP_INTERNAL;
6914 info.group_index = 0;
6915 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6916 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6917 info.parent.status_mask = 1ull<<41 /* dpi */;
6918 info.func = __cvmx_error_display;
6919 info.user_info = (long)
6920 "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
6921 " DPI received a NCB transaction on the outbound\n"
6922 " bus to the DPI deviceID, but the command was not\n"
6924 fail |= cvmx_error_add(&info);
6926 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6927 info.status_addr = CVMX_DPI_INT_REG;
6928 info.status_mask = 1ull<<1 /* nfovr */;
6929 info.enable_addr = CVMX_DPI_INT_EN;
6930 info.enable_mask = 1ull<<1 /* nfovr */;
6932 info.group = CVMX_ERROR_GROUP_INTERNAL;
6933 info.group_index = 0;
6934 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6935 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6936 info.parent.status_mask = 1ull<<41 /* dpi */;
6937 info.func = __cvmx_error_display;
6938 info.user_info = (long)
6939 "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
6940 " DPI can store upto 16 CSR request. The FIFO will\n"
6941 " overflow if that number is exceeded.\n";
6942 fail |= cvmx_error_add(&info);
6944 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6945 info.status_addr = CVMX_DPI_INT_REG;
6946 info.status_mask = 0xffull<<8 /* dmadbo */;
6947 info.enable_addr = CVMX_DPI_INT_EN;
6948 info.enable_mask = 0xffull<<8 /* dmadbo */;
6950 info.group = CVMX_ERROR_GROUP_INTERNAL;
6951 info.group_index = 0;
6952 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6953 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6954 info.parent.status_mask = 1ull<<41 /* dpi */;
6955 info.func = __cvmx_error_display;
6956 info.user_info = (long)
6957 "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
6958 " DPI has a 32-bit counter for each request's queue\n"
6959 " outstanding doorbell counts. Interrupt will fire\n"
6960 " if the count overflows.\n";
6961 fail |= cvmx_error_add(&info);
6963 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6964 info.status_addr = CVMX_DPI_INT_REG;
6965 info.status_mask = 1ull<<16 /* req_badadr */;
6966 info.enable_addr = CVMX_DPI_INT_EN;
6967 info.enable_mask = 1ull<<16 /* req_badadr */;
6969 info.group = CVMX_ERROR_GROUP_INTERNAL;
6970 info.group_index = 0;
6971 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6972 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6973 info.parent.status_mask = 1ull<<41 /* dpi */;
6974 info.func = __cvmx_error_display;
6975 info.user_info = (long)
6976 "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
6977 " Interrupt will fire if DPI forms an instruction\n"
6978 " fetch to the NULL pointer.\n";
6979 fail |= cvmx_error_add(&info);
6981 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6982 info.status_addr = CVMX_DPI_INT_REG;
6983 info.status_mask = 1ull<<17 /* req_badlen */;
6984 info.enable_addr = CVMX_DPI_INT_EN;
6985 info.enable_mask = 1ull<<17 /* req_badlen */;
6987 info.group = CVMX_ERROR_GROUP_INTERNAL;
6988 info.group_index = 0;
6989 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6990 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6991 info.parent.status_mask = 1ull<<41 /* dpi */;
6992 info.func = __cvmx_error_display;
6993 info.user_info = (long)
6994 "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
6995 " Interrupt will fire if DPI forms an instruction\n"
6996 " fetch with length of zero.\n";
6997 fail |= cvmx_error_add(&info);
6999 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7000 info.status_addr = CVMX_DPI_INT_REG;
7001 info.status_mask = 1ull<<18 /* req_ovrflw */;
7002 info.enable_addr = CVMX_DPI_INT_EN;
7003 info.enable_mask = 1ull<<18 /* req_ovrflw */;
7005 info.group = CVMX_ERROR_GROUP_INTERNAL;
7006 info.group_index = 0;
7007 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7008 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7009 info.parent.status_mask = 1ull<<41 /* dpi */;
7010 info.func = __cvmx_error_display;
7011 info.user_info = (long)
7012 "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
7013 " DPI tracks outstanding instructions fetches.\n"
7014 " Interrupt will fire when FIFO overflows.\n";
7015 fail |= cvmx_error_add(&info);
7017 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7018 info.status_addr = CVMX_DPI_INT_REG;
7019 info.status_mask = 1ull<<19 /* req_undflw */;
7020 info.enable_addr = CVMX_DPI_INT_EN;
7021 info.enable_mask = 1ull<<19 /* req_undflw */;
7023 info.group = CVMX_ERROR_GROUP_INTERNAL;
7024 info.group_index = 0;
7025 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7026 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7027 info.parent.status_mask = 1ull<<41 /* dpi */;
7028 info.func = __cvmx_error_display;
7029 info.user_info = (long)
7030 "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
7031 " DPI tracks outstanding instructions fetches.\n"
7032 " Interrupt will fire when FIFO underflows.\n";
7033 fail |= cvmx_error_add(&info);
7035 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7036 info.status_addr = CVMX_DPI_INT_REG;
7037 info.status_mask = 1ull<<20 /* req_anull */;
7038 info.enable_addr = CVMX_DPI_INT_EN;
7039 info.enable_mask = 1ull<<20 /* req_anull */;
7041 info.group = CVMX_ERROR_GROUP_INTERNAL;
7042 info.group_index = 0;
7043 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7044 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7045 info.parent.status_mask = 1ull<<41 /* dpi */;
7046 info.func = __cvmx_error_display;
7047 info.user_info = (long)
7048 "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
7049 " Fetched instruction word was 0.\n";
7050 fail |= cvmx_error_add(&info);
7052 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7053 info.status_addr = CVMX_DPI_INT_REG;
7054 info.status_mask = 1ull<<21 /* req_inull */;
7055 info.enable_addr = CVMX_DPI_INT_EN;
7056 info.enable_mask = 1ull<<21 /* req_inull */;
7058 info.group = CVMX_ERROR_GROUP_INTERNAL;
7059 info.group_index = 0;
7060 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7061 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7062 info.parent.status_mask = 1ull<<41 /* dpi */;
7063 info.func = __cvmx_error_display;
7064 info.user_info = (long)
7065 "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
7066 " Next pointer was NULL.\n";
7067 fail |= cvmx_error_add(&info);
7069 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7070 info.status_addr = CVMX_DPI_INT_REG;
7071 info.status_mask = 1ull<<22 /* req_badfil */;
7072 info.enable_addr = CVMX_DPI_INT_EN;
7073 info.enable_mask = 1ull<<22 /* req_badfil */;
7075 info.group = CVMX_ERROR_GROUP_INTERNAL;
7076 info.group_index = 0;
7077 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7078 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7079 info.parent.status_mask = 1ull<<41 /* dpi */;
7080 info.func = __cvmx_error_display;
7081 info.user_info = (long)
7082 "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
7083 " Instruction fill when none outstanding.\n";
7084 fail |= cvmx_error_add(&info);
7086 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7087 info.status_addr = CVMX_DPI_INT_REG;
7088 info.status_mask = 1ull<<24 /* sprt0_rst */;
7089 info.enable_addr = CVMX_DPI_INT_EN;
7090 info.enable_mask = 1ull<<24 /* sprt0_rst */;
7092 info.group = CVMX_ERROR_GROUP_INTERNAL;
7093 info.group_index = 0;
7094 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7095 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7096 info.parent.status_mask = 1ull<<41 /* dpi */;
7097 info.func = __cvmx_error_display;
7098 info.user_info = (long)
7099 "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
7100 " destination port was in reset.\n"
7101 " this bit is set.\n";
7102 fail |= cvmx_error_add(&info);
7104 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7105 info.status_addr = CVMX_DPI_INT_REG;
7106 info.status_mask = 1ull<<25 /* sprt1_rst */;
7107 info.enable_addr = CVMX_DPI_INT_EN;
7108 info.enable_mask = 1ull<<25 /* sprt1_rst */;
7110 info.group = CVMX_ERROR_GROUP_INTERNAL;
7111 info.group_index = 0;
7112 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7113 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7114 info.parent.status_mask = 1ull<<41 /* dpi */;
7115 info.func = __cvmx_error_display;
7116 info.user_info = (long)
7117 "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
7118 " destination port was in reset.\n"
7119 " this bit is set.\n";
7120 fail |= cvmx_error_add(&info);
7122 /* CVMX_DPI_PKT_ERR_RSP */
7123 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7124 info.status_addr = CVMX_DPI_PKT_ERR_RSP;
7125 info.status_mask = 1ull<<0 /* pkterr */;
7126 info.enable_addr = 0;
7127 info.enable_mask = 0;
7129 info.group = CVMX_ERROR_GROUP_INTERNAL;
7130 info.group_index = 0;
7131 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7132 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7133 info.parent.status_mask = 1ull<<41 /* dpi */;
7134 info.func = __cvmx_error_display;
7135 info.user_info = (long)
7136 "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
7137 " the I/O subsystem.\n";
7138 fail |= cvmx_error_add(&info);
7140 /* CVMX_DPI_REQ_ERR_RSP */
7141 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7142 info.status_addr = CVMX_DPI_REQ_ERR_RSP;
7143 info.status_mask = 0xffull<<0 /* qerr */;
7144 info.enable_addr = 0;
7145 info.enable_mask = 0;
7147 info.group = CVMX_ERROR_GROUP_INTERNAL;
7148 info.group_index = 0;
7149 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7150 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7151 info.parent.status_mask = 1ull<<41 /* dpi */;
7152 info.func = __cvmx_error_display;
7153 info.user_info = (long)
7154 "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
7155 " ErrorResponse from the I/O subsystem.\n"
7156 " SW must clear the bit before the the cooresponding\n"
7157 " instruction queue will continue processing\n"
7158 " instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
7159 fail |= cvmx_error_add(&info);
7161 /* CVMX_DPI_REQ_ERR_RST */
7162 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7163 info.status_addr = CVMX_DPI_REQ_ERR_RST;
7164 info.status_mask = 0xffull<<0 /* qerr */;
7165 info.enable_addr = 0;
7166 info.enable_mask = 0;
7168 info.group = CVMX_ERROR_GROUP_INTERNAL;
7169 info.group_index = 0;
7170 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7171 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7172 info.parent.status_mask = 1ull<<41 /* dpi */;
7173 info.func = __cvmx_error_display;
7174 info.user_info = (long)
7175 "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
7176 " instruction because the source or destination\n"
7178 " SW must clear the bit before the the cooresponding\n"
7179 " instruction queue will continue processing\n"
7180 " instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
7181 fail |= cvmx_error_add(&info);