1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_GPIO_TYPEDEFS_H__
53 #define __CVMX_GPIO_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
63 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
64 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
65 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
66 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15)))))
67 cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset);
68 return CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8;
71 #define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
73 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
74 #define CVMX_GPIO_BOOT_ENA CVMX_GPIO_BOOT_ENA_FUNC()
75 static inline uint64_t CVMX_GPIO_BOOT_ENA_FUNC(void)
77 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
78 cvmx_warn("CVMX_GPIO_BOOT_ENA not supported on this chip\n");
79 return CVMX_ADD_IO_SEG(0x00010700000008A8ull);
82 #define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
84 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
85 static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
88 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
89 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
90 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3)))))
91 cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset);
92 return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8;
95 #define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
97 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
98 static inline uint64_t CVMX_GPIO_CLK_QLMX(unsigned long offset)
101 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
102 cvmx_warn("CVMX_GPIO_CLK_QLMX(%lu) is invalid on this chip\n", offset);
103 return CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8;
106 #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
108 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
109 #define CVMX_GPIO_DBG_ENA CVMX_GPIO_DBG_ENA_FUNC()
110 static inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void)
112 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
113 cvmx_warn("CVMX_GPIO_DBG_ENA not supported on this chip\n");
114 return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
117 #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
119 #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
120 #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
121 #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
122 #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
123 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
124 static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
127 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) ||
128 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) ||
129 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23))))))
130 cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset);
131 return CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16;
134 #define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
140 union cvmx_gpio_bit_cfgx
143 struct cvmx_gpio_bit_cfgx_s
145 #if __BYTE_ORDER == __BIG_ENDIAN
146 uint64_t reserved_17_63 : 47;
147 uint64_t synce_sel : 2; /**< Selects the QLM clock output
148 x0=Normal GPIO output
149 01=GPIO QLM clock selected by GPIO_CLK_QLM0
150 11=GPIO QLM clock selected by GPIO_CLK_QLM1 */
151 uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */
152 uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */
153 uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
154 uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
155 uint64_t int_type : 1; /**< Type of interrupt
158 uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */
159 uint64_t rx_xor : 1; /**< Invert the GPIO pin */
160 uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
165 uint64_t int_type : 1;
166 uint64_t fil_cnt : 4;
167 uint64_t fil_sel : 4;
168 uint64_t clk_sel : 2;
169 uint64_t clk_gen : 1;
170 uint64_t synce_sel : 2;
171 uint64_t reserved_17_63 : 47;
174 struct cvmx_gpio_bit_cfgx_cn30xx
176 #if __BYTE_ORDER == __BIG_ENDIAN
177 uint64_t reserved_12_63 : 52;
178 uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
179 uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
180 uint64_t int_type : 1; /**< Type of interrupt
183 uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */
184 uint64_t rx_xor : 1; /**< Invert the GPIO pin */
185 uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
190 uint64_t int_type : 1;
191 uint64_t fil_cnt : 4;
192 uint64_t fil_sel : 4;
193 uint64_t reserved_12_63 : 52;
196 struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
197 struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
198 struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
199 struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
200 struct cvmx_gpio_bit_cfgx_cn52xx
202 #if __BYTE_ORDER == __BIG_ENDIAN
203 uint64_t reserved_15_63 : 49;
204 uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */
205 uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */
206 uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
207 uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
208 uint64_t int_type : 1; /**< Type of interrupt
211 uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */
212 uint64_t rx_xor : 1; /**< Invert the GPIO pin */
213 uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
218 uint64_t int_type : 1;
219 uint64_t fil_cnt : 4;
220 uint64_t fil_sel : 4;
221 uint64_t clk_sel : 2;
222 uint64_t clk_gen : 1;
223 uint64_t reserved_15_63 : 49;
226 struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
227 struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
228 struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
229 struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
230 struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
231 struct cvmx_gpio_bit_cfgx_s cn63xx;
232 struct cvmx_gpio_bit_cfgx_s cn63xxp1;
234 typedef union cvmx_gpio_bit_cfgx cvmx_gpio_bit_cfgx_t;
239 union cvmx_gpio_boot_ena
242 struct cvmx_gpio_boot_ena_s
244 #if __BYTE_ORDER == __BIG_ENDIAN
245 uint64_t reserved_12_63 : 52;
246 uint64_t boot_ena : 4; /**< Drive boot bus chip enables [7:4] on gpio [11:8] */
247 uint64_t reserved_0_7 : 8;
249 uint64_t reserved_0_7 : 8;
250 uint64_t boot_ena : 4;
251 uint64_t reserved_12_63 : 52;
254 struct cvmx_gpio_boot_ena_s cn30xx;
255 struct cvmx_gpio_boot_ena_s cn31xx;
256 struct cvmx_gpio_boot_ena_s cn50xx;
258 typedef union cvmx_gpio_boot_ena cvmx_gpio_boot_ena_t;
263 union cvmx_gpio_clk_genx
266 struct cvmx_gpio_clk_genx_s
268 #if __BYTE_ORDER == __BIG_ENDIAN
269 uint64_t reserved_32_63 : 32;
270 uint64_t n : 32; /**< Determines the frequency of the GPIO clk generator
271 NOTE: Fgpio_clk = Feclk * N / 2^32
272 N = (Fgpio_clk / Feclk) * 2^32
273 NOTE: writing N == 0 stops the clock generator
274 N should be <= 2^31-1. */
277 uint64_t reserved_32_63 : 32;
280 struct cvmx_gpio_clk_genx_s cn52xx;
281 struct cvmx_gpio_clk_genx_s cn52xxp1;
282 struct cvmx_gpio_clk_genx_s cn56xx;
283 struct cvmx_gpio_clk_genx_s cn56xxp1;
284 struct cvmx_gpio_clk_genx_s cn63xx;
285 struct cvmx_gpio_clk_genx_s cn63xxp1;
287 typedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t;
293 * Clock speed output for different modes ...
295 * Speed With Speed with
296 * SERDES speed (Gbaud) DIV=0 (MHz) DIV=1 (MHz)
297 * **********************************************************
300 * 3.125 156.25 78.125
304 union cvmx_gpio_clk_qlmx
307 struct cvmx_gpio_clk_qlmx_s
309 #if __BYTE_ORDER == __BIG_ENDIAN
310 uint64_t reserved_3_63 : 61;
311 uint64_t div : 1; /**< Internal clock divider
314 uint64_t lane_sel : 2; /**< Selects which RX lane clock from QLM2 to use as
315 the GPIO internal QLMx clock. The GPIO block can
316 support upto two unique clocks to send out any
317 GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
318 The clock can either be a divided by 2 or divide
319 by 4 of the selected RX lane clock. */
321 uint64_t lane_sel : 2;
323 uint64_t reserved_3_63 : 61;
326 struct cvmx_gpio_clk_qlmx_s cn63xx;
327 struct cvmx_gpio_clk_qlmx_s cn63xxp1;
329 typedef union cvmx_gpio_clk_qlmx cvmx_gpio_clk_qlmx_t;
334 union cvmx_gpio_dbg_ena
337 struct cvmx_gpio_dbg_ena_s
339 #if __BYTE_ORDER == __BIG_ENDIAN
340 uint64_t reserved_21_63 : 43;
341 uint64_t dbg_ena : 21; /**< Enable the debug port to be driven on the gpio */
343 uint64_t dbg_ena : 21;
344 uint64_t reserved_21_63 : 43;
347 struct cvmx_gpio_dbg_ena_s cn30xx;
348 struct cvmx_gpio_dbg_ena_s cn31xx;
349 struct cvmx_gpio_dbg_ena_s cn50xx;
351 typedef union cvmx_gpio_dbg_ena cvmx_gpio_dbg_ena_t;
356 union cvmx_gpio_int_clr
359 struct cvmx_gpio_int_clr_s
361 #if __BYTE_ORDER == __BIG_ENDIAN
362 uint64_t reserved_16_63 : 48;
363 uint64_t type : 16; /**< Clear the interrupt rising edge detector */
366 uint64_t reserved_16_63 : 48;
369 struct cvmx_gpio_int_clr_s cn30xx;
370 struct cvmx_gpio_int_clr_s cn31xx;
371 struct cvmx_gpio_int_clr_s cn38xx;
372 struct cvmx_gpio_int_clr_s cn38xxp2;
373 struct cvmx_gpio_int_clr_s cn50xx;
374 struct cvmx_gpio_int_clr_s cn52xx;
375 struct cvmx_gpio_int_clr_s cn52xxp1;
376 struct cvmx_gpio_int_clr_s cn56xx;
377 struct cvmx_gpio_int_clr_s cn56xxp1;
378 struct cvmx_gpio_int_clr_s cn58xx;
379 struct cvmx_gpio_int_clr_s cn58xxp1;
380 struct cvmx_gpio_int_clr_s cn63xx;
381 struct cvmx_gpio_int_clr_s cn63xxp1;
383 typedef union cvmx_gpio_int_clr cvmx_gpio_int_clr_t;
388 union cvmx_gpio_rx_dat
391 struct cvmx_gpio_rx_dat_s
393 #if __BYTE_ORDER == __BIG_ENDIAN
394 uint64_t reserved_24_63 : 40;
395 uint64_t dat : 24; /**< GPIO Read Data */
398 uint64_t reserved_24_63 : 40;
401 struct cvmx_gpio_rx_dat_s cn30xx;
402 struct cvmx_gpio_rx_dat_s cn31xx;
403 struct cvmx_gpio_rx_dat_cn38xx
405 #if __BYTE_ORDER == __BIG_ENDIAN
406 uint64_t reserved_16_63 : 48;
407 uint64_t dat : 16; /**< GPIO Read Data */
410 uint64_t reserved_16_63 : 48;
413 struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
414 struct cvmx_gpio_rx_dat_s cn50xx;
415 struct cvmx_gpio_rx_dat_cn38xx cn52xx;
416 struct cvmx_gpio_rx_dat_cn38xx cn52xxp1;
417 struct cvmx_gpio_rx_dat_cn38xx cn56xx;
418 struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
419 struct cvmx_gpio_rx_dat_cn38xx cn58xx;
420 struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
421 struct cvmx_gpio_rx_dat_cn38xx cn63xx;
422 struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
424 typedef union cvmx_gpio_rx_dat cvmx_gpio_rx_dat_t;
429 union cvmx_gpio_tx_clr
432 struct cvmx_gpio_tx_clr_s
434 #if __BYTE_ORDER == __BIG_ENDIAN
435 uint64_t reserved_24_63 : 40;
436 uint64_t clr : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
437 to '0'. When read, CLR returns the GPIO_TX_DAT
441 uint64_t reserved_24_63 : 40;
444 struct cvmx_gpio_tx_clr_s cn30xx;
445 struct cvmx_gpio_tx_clr_s cn31xx;
446 struct cvmx_gpio_tx_clr_cn38xx
448 #if __BYTE_ORDER == __BIG_ENDIAN
449 uint64_t reserved_16_63 : 48;
450 uint64_t clr : 16; /**< Bit mask to indicate which bits to drive to '0'. */
453 uint64_t reserved_16_63 : 48;
456 struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
457 struct cvmx_gpio_tx_clr_s cn50xx;
458 struct cvmx_gpio_tx_clr_cn38xx cn52xx;
459 struct cvmx_gpio_tx_clr_cn38xx cn52xxp1;
460 struct cvmx_gpio_tx_clr_cn38xx cn56xx;
461 struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
462 struct cvmx_gpio_tx_clr_cn38xx cn58xx;
463 struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
464 struct cvmx_gpio_tx_clr_cn38xx cn63xx;
465 struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
467 typedef union cvmx_gpio_tx_clr cvmx_gpio_tx_clr_t;
472 union cvmx_gpio_tx_set
475 struct cvmx_gpio_tx_set_s
477 #if __BYTE_ORDER == __BIG_ENDIAN
478 uint64_t reserved_24_63 : 40;
479 uint64_t set : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
480 to '1'. When read, SET returns the GPIO_TX_DAT
484 uint64_t reserved_24_63 : 40;
487 struct cvmx_gpio_tx_set_s cn30xx;
488 struct cvmx_gpio_tx_set_s cn31xx;
489 struct cvmx_gpio_tx_set_cn38xx
491 #if __BYTE_ORDER == __BIG_ENDIAN
492 uint64_t reserved_16_63 : 48;
493 uint64_t set : 16; /**< Bit mask to indicate which bits to drive to '1'. */
496 uint64_t reserved_16_63 : 48;
499 struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
500 struct cvmx_gpio_tx_set_s cn50xx;
501 struct cvmx_gpio_tx_set_cn38xx cn52xx;
502 struct cvmx_gpio_tx_set_cn38xx cn52xxp1;
503 struct cvmx_gpio_tx_set_cn38xx cn56xx;
504 struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
505 struct cvmx_gpio_tx_set_cn38xx cn58xx;
506 struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
507 struct cvmx_gpio_tx_set_cn38xx cn63xx;
508 struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
510 typedef union cvmx_gpio_tx_set cvmx_gpio_tx_set_t;
513 * cvmx_gpio_xbit_cfg#
515 union cvmx_gpio_xbit_cfgx
518 struct cvmx_gpio_xbit_cfgx_s
520 #if __BYTE_ORDER == __BIG_ENDIAN
521 uint64_t reserved_12_63 : 52;
522 uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
523 uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
524 uint64_t reserved_2_3 : 2;
525 uint64_t rx_xor : 1; /**< Invert the GPIO pin */
526 uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
530 uint64_t reserved_2_3 : 2;
531 uint64_t fil_cnt : 4;
532 uint64_t fil_sel : 4;
533 uint64_t reserved_12_63 : 52;
536 struct cvmx_gpio_xbit_cfgx_s cn30xx;
537 struct cvmx_gpio_xbit_cfgx_s cn31xx;
538 struct cvmx_gpio_xbit_cfgx_s cn50xx;
540 typedef union cvmx_gpio_xbit_cfgx cvmx_gpio_xbit_cfgx_t;