1 /***********************license start***************
2 * Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
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14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
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19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
35 * For any questions regarding licensing please contact marketing@caviumnetworks.com
37 ***********************license end**************************************/
42 * Automatically generated functions useful for enabling
43 * and decoding RSL_INT_BLOCKS interrupts.
45 * This file is auto generated. Do not edit.
52 #include "cvmx-interrupt.h"
53 #include "cvmx-pcie.h"
56 #define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
59 void __cvmx_interrupt_pci_int_enb2_enable(void);
60 void __cvmx_interrupt_pci_int_sum2_decode(void);
61 void __cvmx_interrupt_pescx_dbg_info_en_enable(int index);
62 void __cvmx_interrupt_pescx_dbg_info_decode(int index);
65 * __cvmx_interrupt_agl_gmx_rxx_int_en_enable enables all interrupt bits in cvmx_agl_gmx_rxx_int_en_t
67 void __cvmx_interrupt_agl_gmx_rxx_int_en_enable(int index)
69 cvmx_agl_gmx_rxx_int_en_t agl_gmx_rx_int_en;
70 cvmx_write_csr(CVMX_AGL_GMX_RXX_INT_REG(index), cvmx_read_csr(CVMX_AGL_GMX_RXX_INT_REG(index)));
71 agl_gmx_rx_int_en.u64 = 0;
72 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
74 // Skipping agl_gmx_rx_int_en.s.reserved_20_63
75 agl_gmx_rx_int_en.s.pause_drp = 1;
76 // Skipping agl_gmx_rx_int_en.s.reserved_16_18
77 agl_gmx_rx_int_en.s.ifgerr = 1;
78 //agl_gmx_rx_int_en.s.coldet = 1; // Collsion detect
79 //agl_gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
80 //agl_gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
81 //agl_gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
82 agl_gmx_rx_int_en.s.ovrerr = 1;
83 // Skipping agl_gmx_rx_int_en.s.reserved_9_9
84 agl_gmx_rx_int_en.s.skperr = 1;
85 agl_gmx_rx_int_en.s.rcverr = 1;
86 agl_gmx_rx_int_en.s.lenerr = 1;
87 agl_gmx_rx_int_en.s.alnerr = 1;
88 agl_gmx_rx_int_en.s.fcserr = 1;
89 agl_gmx_rx_int_en.s.jabber = 1;
90 agl_gmx_rx_int_en.s.maxerr = 1;
91 // Skipping agl_gmx_rx_int_en.s.reserved_1_1
92 agl_gmx_rx_int_en.s.minerr = 1;
94 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
96 // Skipping agl_gmx_rx_int_en.s.reserved_20_63
97 agl_gmx_rx_int_en.s.pause_drp = 1;
98 // Skipping agl_gmx_rx_int_en.s.reserved_16_18
99 agl_gmx_rx_int_en.s.ifgerr = 1;
100 //agl_gmx_rx_int_en.s.coldet = 1; // Collsion detect
101 //agl_gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
102 //agl_gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
103 //agl_gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
104 agl_gmx_rx_int_en.s.ovrerr = 1;
105 // Skipping agl_gmx_rx_int_en.s.reserved_9_9
106 agl_gmx_rx_int_en.s.skperr = 1;
107 agl_gmx_rx_int_en.s.rcverr = 1;
108 agl_gmx_rx_int_en.s.lenerr = 1;
109 agl_gmx_rx_int_en.s.alnerr = 1;
110 agl_gmx_rx_int_en.s.fcserr = 1;
111 agl_gmx_rx_int_en.s.jabber = 1;
112 agl_gmx_rx_int_en.s.maxerr = 1;
113 // Skipping agl_gmx_rx_int_en.s.reserved_1_1
114 agl_gmx_rx_int_en.s.minerr = 1;
116 cvmx_write_csr(CVMX_AGL_GMX_RXX_INT_EN(index), agl_gmx_rx_int_en.u64);
121 * __cvmx_interrupt_agl_gmx_rxx_int_reg_decode decodes all interrupt bits in cvmx_agl_gmx_rxx_int_reg_t
123 void __cvmx_interrupt_agl_gmx_rxx_int_reg_decode(int index)
125 cvmx_agl_gmx_rxx_int_reg_t agl_gmx_rx_int_reg;
126 agl_gmx_rx_int_reg.u64 = cvmx_read_csr(CVMX_AGL_GMX_RXX_INT_REG(index));
127 agl_gmx_rx_int_reg.u64 &= cvmx_read_csr(CVMX_AGL_GMX_RXX_INT_EN(index));
128 cvmx_write_csr(CVMX_AGL_GMX_RXX_INT_REG(index), agl_gmx_rx_int_reg.u64);
129 // Skipping agl_gmx_rx_int_reg.s.reserved_20_63
130 if (agl_gmx_rx_int_reg.s.pause_drp)
131 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[PAUSE_DRP]: Pause packet was dropped due to full GMX RX FIFO\n", index);
132 // Skipping agl_gmx_rx_int_reg.s.reserved_16_18
133 if (agl_gmx_rx_int_reg.s.ifgerr)
134 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[IFGERR]: Interframe Gap Violation\n"
135 " Does not necessarily indicate a failure\n", index);
136 if (agl_gmx_rx_int_reg.s.coldet)
137 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[COLDET]: Collision Detection\n", index);
138 if (agl_gmx_rx_int_reg.s.falerr)
139 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[FALERR]: False carrier error or extend error after slottime\n", index);
140 if (agl_gmx_rx_int_reg.s.rsverr)
141 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[RSVERR]: MII reserved opcodes\n", index);
142 if (agl_gmx_rx_int_reg.s.pcterr)
143 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[PCTERR]: Bad Preamble / Protocol\n", index);
144 if (agl_gmx_rx_int_reg.s.ovrerr)
145 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[OVRERR]: Internal Data Aggregation Overflow\n"
146 " This interrupt should never assert\n", index);
147 // Skipping agl_gmx_rx_int_reg.s.reserved_9_9
148 if (agl_gmx_rx_int_reg.s.skperr)
149 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[SKPERR]: Skipper error\n", index);
150 if (agl_gmx_rx_int_reg.s.rcverr)
151 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[RCVERR]: Frame was received with MII Data reception error\n", index);
152 if (agl_gmx_rx_int_reg.s.lenerr)
153 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[LENERR]: Frame was received with length error\n", index);
154 if (agl_gmx_rx_int_reg.s.alnerr)
155 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[ALNERR]: Frame was received with an alignment error\n", index);
156 if (agl_gmx_rx_int_reg.s.fcserr)
157 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[FCSERR]: Frame was received with FCS/CRC error\n", index);
158 if (agl_gmx_rx_int_reg.s.jabber)
159 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[JABBER]: Frame was received with length > sys_length\n", index);
160 if (agl_gmx_rx_int_reg.s.maxerr)
161 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[MAXERR]: Frame was received with length > max_length\n", index);
162 // Skipping agl_gmx_rx_int_reg.s.reserved_1_1
163 if (agl_gmx_rx_int_reg.s.minerr)
164 PRINT_ERROR("AGL_GMX_RX%d_INT_REG[MINERR]: Frame was received with length < min_length\n", index);
169 * __cvmx_interrupt_fpa_int_enb_enable enables all interrupt bits in cvmx_fpa_int_enb_t
171 void __cvmx_interrupt_fpa_int_enb_enable(void)
173 cvmx_fpa_int_enb_t fpa_int_enb;
174 cvmx_write_csr(CVMX_FPA_INT_SUM, cvmx_read_csr(CVMX_FPA_INT_SUM));
176 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
178 // Skipping fpa_int_enb.s.reserved_28_63
179 fpa_int_enb.s.q7_perr = 1;
180 fpa_int_enb.s.q7_coff = 1;
181 fpa_int_enb.s.q7_und = 1;
182 fpa_int_enb.s.q6_perr = 1;
183 fpa_int_enb.s.q6_coff = 1;
184 fpa_int_enb.s.q6_und = 1;
185 fpa_int_enb.s.q5_perr = 1;
186 fpa_int_enb.s.q5_coff = 1;
187 fpa_int_enb.s.q5_und = 1;
188 fpa_int_enb.s.q4_perr = 1;
189 fpa_int_enb.s.q4_coff = 1;
190 fpa_int_enb.s.q4_und = 1;
191 fpa_int_enb.s.q3_perr = 1;
192 fpa_int_enb.s.q3_coff = 1;
193 fpa_int_enb.s.q3_und = 1;
194 fpa_int_enb.s.q2_perr = 1;
195 fpa_int_enb.s.q2_coff = 1;
196 fpa_int_enb.s.q2_und = 1;
197 fpa_int_enb.s.q1_perr = 1;
198 fpa_int_enb.s.q1_coff = 1;
199 fpa_int_enb.s.q1_und = 1;
200 fpa_int_enb.s.q0_perr = 1;
201 fpa_int_enb.s.q0_coff = 1;
202 fpa_int_enb.s.q0_und = 1;
203 fpa_int_enb.s.fed1_dbe = 1;
204 fpa_int_enb.s.fed1_sbe = 1;
205 fpa_int_enb.s.fed0_dbe = 1;
206 fpa_int_enb.s.fed0_sbe = 1;
208 if (OCTEON_IS_MODEL(OCTEON_CN30XX))
210 // Skipping fpa_int_enb.s.reserved_28_63
211 fpa_int_enb.s.q7_perr = 1;
212 fpa_int_enb.s.q7_coff = 1;
213 fpa_int_enb.s.q7_und = 1;
214 fpa_int_enb.s.q6_perr = 1;
215 fpa_int_enb.s.q6_coff = 1;
216 fpa_int_enb.s.q6_und = 1;
217 fpa_int_enb.s.q5_perr = 1;
218 fpa_int_enb.s.q5_coff = 1;
219 fpa_int_enb.s.q5_und = 1;
220 fpa_int_enb.s.q4_perr = 1;
221 fpa_int_enb.s.q4_coff = 1;
222 fpa_int_enb.s.q4_und = 1;
223 fpa_int_enb.s.q3_perr = 1;
224 fpa_int_enb.s.q3_coff = 1;
225 fpa_int_enb.s.q3_und = 1;
226 fpa_int_enb.s.q2_perr = 1;
227 fpa_int_enb.s.q2_coff = 1;
228 fpa_int_enb.s.q2_und = 1;
229 fpa_int_enb.s.q1_perr = 1;
230 fpa_int_enb.s.q1_coff = 1;
231 fpa_int_enb.s.q1_und = 1;
232 fpa_int_enb.s.q0_perr = 1;
233 fpa_int_enb.s.q0_coff = 1;
234 fpa_int_enb.s.q0_und = 1;
235 fpa_int_enb.s.fed1_dbe = 1;
236 fpa_int_enb.s.fed1_sbe = 1;
237 fpa_int_enb.s.fed0_dbe = 1;
238 fpa_int_enb.s.fed0_sbe = 1;
240 if (OCTEON_IS_MODEL(OCTEON_CN50XX))
242 // Skipping fpa_int_enb.s.reserved_28_63
243 fpa_int_enb.s.q7_perr = 1;
244 fpa_int_enb.s.q7_coff = 1;
245 fpa_int_enb.s.q7_und = 1;
246 fpa_int_enb.s.q6_perr = 1;
247 fpa_int_enb.s.q6_coff = 1;
248 fpa_int_enb.s.q6_und = 1;
249 fpa_int_enb.s.q5_perr = 1;
250 fpa_int_enb.s.q5_coff = 1;
251 fpa_int_enb.s.q5_und = 1;
252 fpa_int_enb.s.q4_perr = 1;
253 fpa_int_enb.s.q4_coff = 1;
254 fpa_int_enb.s.q4_und = 1;
255 fpa_int_enb.s.q3_perr = 1;
256 fpa_int_enb.s.q3_coff = 1;
257 fpa_int_enb.s.q3_und = 1;
258 fpa_int_enb.s.q2_perr = 1;
259 fpa_int_enb.s.q2_coff = 1;
260 fpa_int_enb.s.q2_und = 1;
261 fpa_int_enb.s.q1_perr = 1;
262 fpa_int_enb.s.q1_coff = 1;
263 fpa_int_enb.s.q1_und = 1;
264 fpa_int_enb.s.q0_perr = 1;
265 fpa_int_enb.s.q0_coff = 1;
266 fpa_int_enb.s.q0_und = 1;
267 fpa_int_enb.s.fed1_dbe = 1;
268 fpa_int_enb.s.fed1_sbe = 1;
269 fpa_int_enb.s.fed0_dbe = 1;
270 fpa_int_enb.s.fed0_sbe = 1;
272 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
274 // Skipping fpa_int_enb.s.reserved_28_63
275 fpa_int_enb.s.q7_perr = 1;
276 fpa_int_enb.s.q7_coff = 1;
277 fpa_int_enb.s.q7_und = 1;
278 fpa_int_enb.s.q6_perr = 1;
279 fpa_int_enb.s.q6_coff = 1;
280 fpa_int_enb.s.q6_und = 1;
281 fpa_int_enb.s.q5_perr = 1;
282 fpa_int_enb.s.q5_coff = 1;
283 fpa_int_enb.s.q5_und = 1;
284 fpa_int_enb.s.q4_perr = 1;
285 fpa_int_enb.s.q4_coff = 1;
286 fpa_int_enb.s.q4_und = 1;
287 fpa_int_enb.s.q3_perr = 1;
288 fpa_int_enb.s.q3_coff = 1;
289 fpa_int_enb.s.q3_und = 1;
290 fpa_int_enb.s.q2_perr = 1;
291 fpa_int_enb.s.q2_coff = 1;
292 fpa_int_enb.s.q2_und = 1;
293 fpa_int_enb.s.q1_perr = 1;
294 fpa_int_enb.s.q1_coff = 1;
295 fpa_int_enb.s.q1_und = 1;
296 fpa_int_enb.s.q0_perr = 1;
297 fpa_int_enb.s.q0_coff = 1;
298 fpa_int_enb.s.q0_und = 1;
299 fpa_int_enb.s.fed1_dbe = 1;
300 fpa_int_enb.s.fed1_sbe = 1;
301 fpa_int_enb.s.fed0_dbe = 1;
302 fpa_int_enb.s.fed0_sbe = 1;
304 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
306 // Skipping fpa_int_enb.s.reserved_28_63
307 fpa_int_enb.s.q7_perr = 1;
308 fpa_int_enb.s.q7_coff = 1;
309 fpa_int_enb.s.q7_und = 1;
310 fpa_int_enb.s.q6_perr = 1;
311 fpa_int_enb.s.q6_coff = 1;
312 fpa_int_enb.s.q6_und = 1;
313 fpa_int_enb.s.q5_perr = 1;
314 fpa_int_enb.s.q5_coff = 1;
315 fpa_int_enb.s.q5_und = 1;
316 fpa_int_enb.s.q4_perr = 1;
317 fpa_int_enb.s.q4_coff = 1;
318 fpa_int_enb.s.q4_und = 1;
319 fpa_int_enb.s.q3_perr = 1;
320 fpa_int_enb.s.q3_coff = 1;
321 fpa_int_enb.s.q3_und = 1;
322 fpa_int_enb.s.q2_perr = 1;
323 fpa_int_enb.s.q2_coff = 1;
324 fpa_int_enb.s.q2_und = 1;
325 fpa_int_enb.s.q1_perr = 1;
326 fpa_int_enb.s.q1_coff = 1;
327 fpa_int_enb.s.q1_und = 1;
328 fpa_int_enb.s.q0_perr = 1;
329 fpa_int_enb.s.q0_coff = 1;
330 fpa_int_enb.s.q0_und = 1;
331 fpa_int_enb.s.fed1_dbe = 1;
332 fpa_int_enb.s.fed1_sbe = 1;
333 fpa_int_enb.s.fed0_dbe = 1;
334 fpa_int_enb.s.fed0_sbe = 1;
336 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
338 // Skipping fpa_int_enb.s.reserved_28_63
339 fpa_int_enb.s.q7_perr = 1;
340 fpa_int_enb.s.q7_coff = 1;
341 fpa_int_enb.s.q7_und = 1;
342 fpa_int_enb.s.q6_perr = 1;
343 fpa_int_enb.s.q6_coff = 1;
344 fpa_int_enb.s.q6_und = 1;
345 fpa_int_enb.s.q5_perr = 1;
346 fpa_int_enb.s.q5_coff = 1;
347 fpa_int_enb.s.q5_und = 1;
348 fpa_int_enb.s.q4_perr = 1;
349 fpa_int_enb.s.q4_coff = 1;
350 fpa_int_enb.s.q4_und = 1;
351 fpa_int_enb.s.q3_perr = 1;
352 fpa_int_enb.s.q3_coff = 1;
353 fpa_int_enb.s.q3_und = 1;
354 fpa_int_enb.s.q2_perr = 1;
355 fpa_int_enb.s.q2_coff = 1;
356 fpa_int_enb.s.q2_und = 1;
357 fpa_int_enb.s.q1_perr = 1;
358 fpa_int_enb.s.q1_coff = 1;
359 fpa_int_enb.s.q1_und = 1;
360 fpa_int_enb.s.q0_perr = 1;
361 fpa_int_enb.s.q0_coff = 1;
362 fpa_int_enb.s.q0_und = 1;
363 fpa_int_enb.s.fed1_dbe = 1;
364 fpa_int_enb.s.fed1_sbe = 1;
365 fpa_int_enb.s.fed0_dbe = 1;
366 fpa_int_enb.s.fed0_sbe = 1;
368 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
370 // Skipping fpa_int_enb.s.reserved_28_63
371 fpa_int_enb.s.q7_perr = 1;
372 fpa_int_enb.s.q7_coff = 1;
373 fpa_int_enb.s.q7_und = 1;
374 fpa_int_enb.s.q6_perr = 1;
375 fpa_int_enb.s.q6_coff = 1;
376 fpa_int_enb.s.q6_und = 1;
377 fpa_int_enb.s.q5_perr = 1;
378 fpa_int_enb.s.q5_coff = 1;
379 fpa_int_enb.s.q5_und = 1;
380 fpa_int_enb.s.q4_perr = 1;
381 fpa_int_enb.s.q4_coff = 1;
382 fpa_int_enb.s.q4_und = 1;
383 fpa_int_enb.s.q3_perr = 1;
384 fpa_int_enb.s.q3_coff = 1;
385 fpa_int_enb.s.q3_und = 1;
386 fpa_int_enb.s.q2_perr = 1;
387 fpa_int_enb.s.q2_coff = 1;
388 fpa_int_enb.s.q2_und = 1;
389 fpa_int_enb.s.q1_perr = 1;
390 fpa_int_enb.s.q1_coff = 1;
391 fpa_int_enb.s.q1_und = 1;
392 fpa_int_enb.s.q0_perr = 1;
393 fpa_int_enb.s.q0_coff = 1;
394 fpa_int_enb.s.q0_und = 1;
395 fpa_int_enb.s.fed1_dbe = 1;
396 fpa_int_enb.s.fed1_sbe = 1;
397 fpa_int_enb.s.fed0_dbe = 1;
398 fpa_int_enb.s.fed0_sbe = 1;
400 cvmx_write_csr(CVMX_FPA_INT_ENB, fpa_int_enb.u64);
405 * __cvmx_interrupt_fpa_int_sum_decode decodes all interrupt bits in cvmx_fpa_int_sum_t
407 void __cvmx_interrupt_fpa_int_sum_decode(void)
409 cvmx_fpa_int_sum_t fpa_int_sum;
410 fpa_int_sum.u64 = cvmx_read_csr(CVMX_FPA_INT_SUM);
411 fpa_int_sum.u64 &= cvmx_read_csr(CVMX_FPA_INT_ENB);
412 cvmx_write_csr(CVMX_FPA_INT_SUM, fpa_int_sum.u64);
413 // Skipping fpa_int_sum.s.reserved_28_63
414 if (fpa_int_sum.s.q7_perr)
415 PRINT_ERROR("FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
416 " the L2C does not have the FPA owner ship bit set.\n");
417 if (fpa_int_sum.s.q7_coff)
418 PRINT_ERROR("FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
419 " the count available is greater than than pointers\n"
420 " present in the FPA.\n");
421 if (fpa_int_sum.s.q7_und)
422 PRINT_ERROR("FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
424 if (fpa_int_sum.s.q6_perr)
425 PRINT_ERROR("FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
426 " the L2C does not have the FPA owner ship bit set.\n");
427 if (fpa_int_sum.s.q6_coff)
428 PRINT_ERROR("FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
429 " the count available is greater than than pointers\n"
430 " present in the FPA.\n");
431 if (fpa_int_sum.s.q6_und)
432 PRINT_ERROR("FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
434 if (fpa_int_sum.s.q5_perr)
435 PRINT_ERROR("FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
436 " the L2C does not have the FPA owner ship bit set.\n");
437 if (fpa_int_sum.s.q5_coff)
438 PRINT_ERROR("FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
439 " the count available is greater than than pointers\n"
440 " present in the FPA.\n");
441 if (fpa_int_sum.s.q5_und)
442 PRINT_ERROR("FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
444 if (fpa_int_sum.s.q4_perr)
445 PRINT_ERROR("FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
446 " the L2C does not have the FPA owner ship bit set.\n");
447 if (fpa_int_sum.s.q4_coff)
448 PRINT_ERROR("FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
449 " the count available is greater than than pointers\n"
450 " present in the FPA.\n");
451 if (fpa_int_sum.s.q4_und)
452 PRINT_ERROR("FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
454 if (fpa_int_sum.s.q3_perr)
455 PRINT_ERROR("FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
456 " the L2C does not have the FPA owner ship bit set.\n");
457 if (fpa_int_sum.s.q3_coff)
458 PRINT_ERROR("FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
459 " the count available is greater than than pointers\n"
460 " present in the FPA.\n");
461 if (fpa_int_sum.s.q3_und)
462 PRINT_ERROR("FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
464 if (fpa_int_sum.s.q2_perr)
465 PRINT_ERROR("FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
466 " the L2C does not have the FPA owner ship bit set.\n");
467 if (fpa_int_sum.s.q2_coff)
468 PRINT_ERROR("FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
469 " the count available is greater than than pointers\n"
470 " present in the FPA.\n");
471 if (fpa_int_sum.s.q2_und)
472 PRINT_ERROR("FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
474 if (fpa_int_sum.s.q1_perr)
475 PRINT_ERROR("FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
476 " the L2C does not have the FPA owner ship bit set.\n");
477 if (fpa_int_sum.s.q1_coff)
478 PRINT_ERROR("FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
479 " the count available is greater than pointers\n"
480 " present in the FPA.\n");
481 if (fpa_int_sum.s.q1_und)
482 PRINT_ERROR("FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
484 if (fpa_int_sum.s.q0_perr)
485 PRINT_ERROR("FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
486 " the L2C does not have the FPA owner ship bit set.\n");
487 if (fpa_int_sum.s.q0_coff)
488 PRINT_ERROR("FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
489 " the count available is greater than pointers\n"
490 " present in the FPA.\n");
491 if (fpa_int_sum.s.q0_und)
492 PRINT_ERROR("FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
494 if (fpa_int_sum.s.fed1_dbe)
495 PRINT_ERROR("FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n");
496 if (fpa_int_sum.s.fed1_sbe)
497 PRINT_ERROR("FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n");
498 if (fpa_int_sum.s.fed0_dbe)
499 PRINT_ERROR("FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n");
500 if (fpa_int_sum.s.fed0_sbe)
501 PRINT_ERROR("FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n");
506 * __cvmx_interrupt_gmxx_rxx_int_en_enable enables all interrupt bits in cvmx_gmxx_rxx_int_en_t
508 void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
510 cvmx_gmxx_rxx_int_en_t gmx_rx_int_en;
511 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block)));
512 gmx_rx_int_en.u64 = 0;
513 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
515 // Skipping gmx_rx_int_en.s.reserved_29_63
516 gmx_rx_int_en.s.hg2cc = 1;
517 gmx_rx_int_en.s.hg2fld = 1;
518 gmx_rx_int_en.s.undat = 1;
519 gmx_rx_int_en.s.uneop = 1;
520 gmx_rx_int_en.s.unsop = 1;
521 gmx_rx_int_en.s.bad_term = 1;
522 gmx_rx_int_en.s.bad_seq = 1;
523 gmx_rx_int_en.s.rem_fault = 1;
524 gmx_rx_int_en.s.loc_fault = 1;
525 gmx_rx_int_en.s.pause_drp = 1;
526 // Skipping gmx_rx_int_en.s.reserved_16_18
527 //gmx_rx_int_en.s.ifgerr = 1;
528 //gmx_rx_int_en.s.coldet = 1; // Collsion detect
529 //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
530 //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
531 //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
532 gmx_rx_int_en.s.ovrerr = 1;
533 // Skipping gmx_rx_int_en.s.reserved_9_9
534 gmx_rx_int_en.s.skperr = 1;
535 gmx_rx_int_en.s.rcverr = 1;
536 // Skipping gmx_rx_int_en.s.reserved_5_6
537 //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
538 gmx_rx_int_en.s.jabber = 1;
539 // Skipping gmx_rx_int_en.s.reserved_2_2
540 gmx_rx_int_en.s.carext = 1;
541 // Skipping gmx_rx_int_en.s.reserved_0_0
543 if (OCTEON_IS_MODEL(OCTEON_CN30XX))
545 // Skipping gmx_rx_int_en.s.reserved_19_63
546 //gmx_rx_int_en.s.phy_dupx = 1;
547 //gmx_rx_int_en.s.phy_spd = 1;
548 //gmx_rx_int_en.s.phy_link = 1;
549 //gmx_rx_int_en.s.ifgerr = 1;
550 //gmx_rx_int_en.s.coldet = 1; // Collsion detect
551 //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
552 //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
553 //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
554 gmx_rx_int_en.s.ovrerr = 1;
555 gmx_rx_int_en.s.niberr = 1;
556 gmx_rx_int_en.s.skperr = 1;
557 gmx_rx_int_en.s.rcverr = 1;
558 //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
559 gmx_rx_int_en.s.alnerr = 1;
560 //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
561 gmx_rx_int_en.s.jabber = 1;
562 gmx_rx_int_en.s.maxerr = 1;
563 gmx_rx_int_en.s.carext = 1;
564 gmx_rx_int_en.s.minerr = 1;
566 if (OCTEON_IS_MODEL(OCTEON_CN50XX))
568 // Skipping gmx_rx_int_en.s.reserved_20_63
569 gmx_rx_int_en.s.pause_drp = 1;
570 //gmx_rx_int_en.s.phy_dupx = 1;
571 //gmx_rx_int_en.s.phy_spd = 1;
572 //gmx_rx_int_en.s.phy_link = 1;
573 //gmx_rx_int_en.s.ifgerr = 1;
574 //gmx_rx_int_en.s.coldet = 1; // Collsion detect
575 //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
576 //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
577 //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
578 gmx_rx_int_en.s.ovrerr = 1;
579 gmx_rx_int_en.s.niberr = 1;
580 gmx_rx_int_en.s.skperr = 1;
581 gmx_rx_int_en.s.rcverr = 1;
582 // Skipping gmx_rx_int_en.s.reserved_6_6
583 gmx_rx_int_en.s.alnerr = 1;
584 //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
585 gmx_rx_int_en.s.jabber = 1;
586 // Skipping gmx_rx_int_en.s.reserved_2_2
587 gmx_rx_int_en.s.carext = 1;
588 // Skipping gmx_rx_int_en.s.reserved_0_0
590 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
592 // Skipping gmx_rx_int_en.s.reserved_19_63
593 //gmx_rx_int_en.s.phy_dupx = 1;
594 //gmx_rx_int_en.s.phy_spd = 1;
595 //gmx_rx_int_en.s.phy_link = 1;
596 //gmx_rx_int_en.s.ifgerr = 1;
597 //gmx_rx_int_en.s.coldet = 1; // Collsion detect
598 //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
599 //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
600 //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
601 gmx_rx_int_en.s.ovrerr = 1;
602 gmx_rx_int_en.s.niberr = 1;
603 gmx_rx_int_en.s.skperr = 1;
604 gmx_rx_int_en.s.rcverr = 1;
605 //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
606 gmx_rx_int_en.s.alnerr = 1;
607 //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
608 gmx_rx_int_en.s.jabber = 1;
609 gmx_rx_int_en.s.maxerr = 1;
610 gmx_rx_int_en.s.carext = 1;
611 gmx_rx_int_en.s.minerr = 1;
613 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
615 // Skipping gmx_rx_int_en.s.reserved_19_63
616 //gmx_rx_int_en.s.phy_dupx = 1;
617 //gmx_rx_int_en.s.phy_spd = 1;
618 //gmx_rx_int_en.s.phy_link = 1;
619 //gmx_rx_int_en.s.ifgerr = 1;
620 //gmx_rx_int_en.s.coldet = 1; // Collsion detect
621 //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
622 //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
623 //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
624 gmx_rx_int_en.s.ovrerr = 1;
625 gmx_rx_int_en.s.niberr = 1;
626 gmx_rx_int_en.s.skperr = 1;
627 gmx_rx_int_en.s.rcverr = 1;
628 //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
629 gmx_rx_int_en.s.alnerr = 1;
630 //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
631 gmx_rx_int_en.s.jabber = 1;
632 gmx_rx_int_en.s.maxerr = 1;
633 gmx_rx_int_en.s.carext = 1;
634 gmx_rx_int_en.s.minerr = 1;
636 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
638 // Skipping gmx_rx_int_en.s.reserved_20_63
639 gmx_rx_int_en.s.pause_drp = 1;
640 //gmx_rx_int_en.s.phy_dupx = 1;
641 //gmx_rx_int_en.s.phy_spd = 1;
642 //gmx_rx_int_en.s.phy_link = 1;
643 //gmx_rx_int_en.s.ifgerr = 1;
644 //gmx_rx_int_en.s.coldet = 1; // Collsion detect
645 //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
646 //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
647 //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
648 gmx_rx_int_en.s.ovrerr = 1;
649 gmx_rx_int_en.s.niberr = 1;
650 gmx_rx_int_en.s.skperr = 1;
651 gmx_rx_int_en.s.rcverr = 1;
652 //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
653 gmx_rx_int_en.s.alnerr = 1;
654 //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
655 gmx_rx_int_en.s.jabber = 1;
656 gmx_rx_int_en.s.maxerr = 1;
657 gmx_rx_int_en.s.carext = 1;
658 gmx_rx_int_en.s.minerr = 1;
660 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
662 // Skipping gmx_rx_int_en.s.reserved_29_63
663 gmx_rx_int_en.s.hg2cc = 1;
664 gmx_rx_int_en.s.hg2fld = 1;
665 gmx_rx_int_en.s.undat = 1;
666 gmx_rx_int_en.s.uneop = 1;
667 gmx_rx_int_en.s.unsop = 1;
668 gmx_rx_int_en.s.bad_term = 1;
669 gmx_rx_int_en.s.bad_seq = 0;
670 gmx_rx_int_en.s.rem_fault = 1;
671 gmx_rx_int_en.s.loc_fault = 0;
672 gmx_rx_int_en.s.pause_drp = 1;
673 // Skipping gmx_rx_int_en.s.reserved_16_18
674 //gmx_rx_int_en.s.ifgerr = 1;
675 //gmx_rx_int_en.s.coldet = 1; // Collsion detect
676 //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
677 //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
678 //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
679 gmx_rx_int_en.s.ovrerr = 1;
680 // Skipping gmx_rx_int_en.s.reserved_9_9
681 gmx_rx_int_en.s.skperr = 1;
682 gmx_rx_int_en.s.rcverr = 1;
683 // Skipping gmx_rx_int_en.s.reserved_5_6
684 //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
685 gmx_rx_int_en.s.jabber = 1;
686 // Skipping gmx_rx_int_en.s.reserved_2_2
687 gmx_rx_int_en.s.carext = 1;
688 // Skipping gmx_rx_int_en.s.reserved_0_0
690 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64);
695 * __cvmx_interrupt_gmxx_rxx_int_reg_decode decodes all interrupt bits in cvmx_gmxx_rxx_int_reg_t
697 void __cvmx_interrupt_gmxx_rxx_int_reg_decode(int index, int block)
699 cvmx_gmxx_rxx_int_reg_t gmx_rx_int_reg;
700 gmx_rx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block));
701 /* Don't clear inband status bits so someone else can use them */
702 gmx_rx_int_reg.s.phy_dupx = 0;
703 gmx_rx_int_reg.s.phy_spd = 0;
704 gmx_rx_int_reg.s.phy_link = 0;
705 gmx_rx_int_reg.u64 &= cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, block));
706 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), gmx_rx_int_reg.u64);
707 // Skipping gmx_rx_int_reg.s.reserved_29_63
708 if (gmx_rx_int_reg.s.hg2cc)
709 PRINT_ERROR("GMX%d_RX%d_INT_REG[HG2CC]: HiGig2 received message CRC or Control char error\n"
710 " Set when either CRC8 error detected or when\n"
711 " a Control Character is found in the message\n"
712 " bytes after the K.SOM\n"
713 " NOTE: HG2CC has higher priority than HG2FLD\n"
714 " i.e. a HiGig2 message that results in HG2CC\n"
715 " getting set, will never set HG2FLD.\n", block, index);
716 if (gmx_rx_int_reg.s.hg2fld)
717 PRINT_ERROR("GMX%d_RX%d_INT_REG[HG2FLD]: HiGig2 received message field error, as below\n"
718 " 1) MSG_TYPE field not 6'b00_0000\n"
719 " i.e. it is not a FLOW CONTROL message, which\n"
720 " is the only defined type for HiGig2\n"
721 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
722 " which is the only defined type for HiGig2\n"
723 " 3) FC_OBJECT field is neither 4'b0000 for\n"
724 " Physical Link nor 4'b0010 for Logical Link.\n"
725 " Those are the only two defined types in HiGig2\n", block, index);
726 if (gmx_rx_int_reg.s.undat)
727 PRINT_ERROR("GMX%d_RX%d_INT_REG[UNDAT]: Unexpected Data\n"
728 " (XAUI Mode only)\n", block, index);
729 if (gmx_rx_int_reg.s.uneop)
730 PRINT_ERROR("GMX%d_RX%d_INT_REG[UNEOP]: Unexpected EOP\n"
731 " (XAUI Mode only)\n", block, index);
732 if (gmx_rx_int_reg.s.unsop)
733 PRINT_ERROR("GMX%d_RX%d_INT_REG[UNSOP]: Unexpected SOP\n"
734 " (XAUI Mode only)\n", block, index);
735 if (gmx_rx_int_reg.s.bad_term)
736 PRINT_ERROR("GMX%d_RX%d_INT_REG[BAD_TERM]: Frame is terminated by control character other\n"
737 " than /T/. The error propagation control\n"
738 " character /E/ will be included as part of the\n"
739 " frame and does not cause a frame termination.\n"
740 " (XAUI Mode only)\n", block, index);
741 if (gmx_rx_int_reg.s.bad_seq)
742 PRINT_ERROR("GMX%d_RX%d_INT_REG[BAD_SEQ]: Reserved Sequence Deteted\n"
743 " (XAUI Mode only)\n", block, index);
744 if (gmx_rx_int_reg.s.rem_fault)
745 PRINT_ERROR("GMX%d_RX%d_INT_REG[REM_FAULT]: Remote Fault Sequence Deteted\n"
746 " (XAUI Mode only)\n", block, index);
747 if (gmx_rx_int_reg.s.loc_fault)
748 PRINT_ERROR("GMX%d_RX%d_INT_REG[LOC_FAULT]: Local Fault Sequence Deteted\n"
749 " (XAUI Mode only)\n", block, index);
750 if (gmx_rx_int_reg.s.pause_drp)
751 PRINT_ERROR("GMX%d_RX%d_INT_REG[PAUSE_DRP]: Pause packet was dropped due to full GMX RX FIFO\n", block, index);
753 if (gmx_rx_int_reg.s.phy_dupx)
754 PRINT_ERROR("GMX%d_RX%d_INT_REG[PHY_DUPX]: Change in the RMGII inbound LinkDuplex\n", block, index);
755 if (gmx_rx_int_reg.s.phy_spd)
756 PRINT_ERROR("GMX%d_RX%d_INT_REG[PHY_SPD]: Change in the RMGII inbound LinkSpeed\n", block, index);
757 if (gmx_rx_int_reg.s.phy_link)
758 PRINT_ERROR("GMX%d_RX%d_INT_REG[PHY_LINK]: Change in the RMGII inbound LinkStatus\n", block, index);
760 if (gmx_rx_int_reg.s.ifgerr)
761 PRINT_ERROR("GMX%d_RX%d_INT_REG[IFGERR]: Interframe Gap Violation\n"
762 " Does not necessarily indicate a failure\n", block, index);
763 if (gmx_rx_int_reg.s.coldet)
764 PRINT_ERROR("GMX%d_RX%d_INT_REG[COLDET]: Collision Detection\n", block, index);
765 if (gmx_rx_int_reg.s.falerr)
766 PRINT_ERROR("GMX%d_RX%d_INT_REG[FALERR]: False carrier error or extend error after slottime\n", block, index);
767 if (gmx_rx_int_reg.s.rsverr)
768 PRINT_ERROR("GMX%d_RX%d_INT_REG[RSVERR]: RGMII reserved opcodes\n", block, index);
769 if (gmx_rx_int_reg.s.pcterr)
770 PRINT_ERROR("GMX%d_RX%d_INT_REG[PCTERR]: Bad Preamble / Protocol\n", block, index);
771 if (gmx_rx_int_reg.s.ovrerr)
772 PRINT_ERROR("GMX%d_RX%d_INT_REG[OVRERR]: Internal Data Aggregation Overflow\n"
773 " This interrupt should never assert\n", block, index);
774 if (gmx_rx_int_reg.s.niberr)
775 PRINT_ERROR("GMX%d_RX%d_INT_REG[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n", block, index);
776 if (gmx_rx_int_reg.s.skperr)
777 PRINT_ERROR("GMX%d_RX%d_INT_REG[SKPERR]: Skipper error\n", block, index);
778 if (gmx_rx_int_reg.s.rcverr)
779 PRINT_ERROR("GMX%d_RX%d_INT_REG[RCVERR]: Frame was received with RMGII Data reception error\n", block, index);
780 if (gmx_rx_int_reg.s.lenerr)
781 PRINT_ERROR("GMX%d_RX%d_INT_REG[LENERR]: Frame was received with length error\n", block, index);
782 if (gmx_rx_int_reg.s.alnerr)
783 PRINT_ERROR("GMX%d_RX%d_INT_REG[ALNERR]: Frame was received with an alignment error\n", block, index);
784 if (gmx_rx_int_reg.s.fcserr)
785 PRINT_ERROR("GMX%d_RX%d_INT_REG[FCSERR]: Frame was received with FCS/CRC error\n", block, index);
786 if (gmx_rx_int_reg.s.jabber)
787 PRINT_ERROR("GMX%d_RX%d_INT_REG[JABBER]: Frame was received with length > sys_length\n", block, index);
788 if (gmx_rx_int_reg.s.maxerr)
789 PRINT_ERROR("GMX%d_RX%d_INT_REG[MAXERR]: Frame was received with length > max_length\n", block, index);
790 if (gmx_rx_int_reg.s.carext)
791 PRINT_ERROR("GMX%d_RX%d_INT_REG[CAREXT]: RGMII carrier extend error\n", block, index);
792 if (gmx_rx_int_reg.s.minerr)
793 PRINT_ERROR("GMX%d_RX%d_INT_REG[MINERR]: Frame was received with length < min_length\n", block, index);
798 * __cvmx_interrupt_iob_int_enb_enable enables all interrupt bits in cvmx_iob_int_enb_t
800 void __cvmx_interrupt_iob_int_enb_enable(void)
802 cvmx_iob_int_enb_t iob_int_enb;
803 cvmx_write_csr(CVMX_IOB_INT_SUM, cvmx_read_csr(CVMX_IOB_INT_SUM));
805 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
807 // Skipping iob_int_enb.s.reserved_6_63
808 iob_int_enb.s.p_dat = 1;
809 iob_int_enb.s.p_eop = 1;
810 iob_int_enb.s.p_sop = 1;
811 /* These interrupts are disabled on CN56XXp2.X due to errata IOB-800 */
812 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X))
814 iob_int_enb.s.np_dat = 1;
815 iob_int_enb.s.np_eop = 1;
816 iob_int_enb.s.np_sop = 1;
819 if (OCTEON_IS_MODEL(OCTEON_CN30XX))
821 // Skipping iob_int_enb.s.reserved_4_63
822 iob_int_enb.s.p_eop = 1;
823 iob_int_enb.s.p_sop = 1;
824 iob_int_enb.s.np_eop = 1;
825 iob_int_enb.s.np_sop = 1;
827 if (OCTEON_IS_MODEL(OCTEON_CN50XX))
829 // Skipping iob_int_enb.s.reserved_6_63
830 iob_int_enb.s.p_dat = 1;
831 iob_int_enb.s.np_dat = 1;
832 iob_int_enb.s.p_eop = 1;
833 iob_int_enb.s.p_sop = 1;
834 iob_int_enb.s.np_eop = 1;
835 iob_int_enb.s.np_sop = 1;
837 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
839 // Skipping iob_int_enb.s.reserved_4_63
840 iob_int_enb.s.p_eop = 1;
841 iob_int_enb.s.p_sop = 1;
842 iob_int_enb.s.np_eop = 1;
843 iob_int_enb.s.np_sop = 1;
845 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
847 // Skipping iob_int_enb.s.reserved_4_63
848 iob_int_enb.s.p_eop = 1;
849 iob_int_enb.s.p_sop = 1;
850 iob_int_enb.s.np_eop = 1;
851 iob_int_enb.s.np_sop = 1;
853 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
855 // Skipping iob_int_enb.s.reserved_6_63
856 iob_int_enb.s.p_dat = 1;
857 iob_int_enb.s.np_dat = 1;
858 iob_int_enb.s.p_eop = 1;
859 iob_int_enb.s.p_sop = 1;
860 iob_int_enb.s.np_eop = 1;
861 iob_int_enb.s.np_sop = 1;
863 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
865 // Skipping iob_int_enb.s.reserved_6_63
866 iob_int_enb.s.p_dat = 1;
867 iob_int_enb.s.p_eop = 1;
868 iob_int_enb.s.p_sop = 1;
869 /* These interrupts are disabled on CN52XXp2.X due to errata IOB-800 */
870 if (!OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X))
872 iob_int_enb.s.np_dat = 1;
873 iob_int_enb.s.np_eop = 1;
874 iob_int_enb.s.np_sop = 1;
877 cvmx_write_csr(CVMX_IOB_INT_ENB, iob_int_enb.u64);
882 * __cvmx_interrupt_iob_int_sum_decode decodes all interrupt bits in cvmx_iob_int_sum_t
884 void __cvmx_interrupt_iob_int_sum_decode(void)
886 cvmx_iob_int_sum_t iob_int_sum;
887 iob_int_sum.u64 = cvmx_read_csr(CVMX_IOB_INT_SUM);
888 iob_int_sum.u64 &= cvmx_read_csr(CVMX_IOB_INT_ENB);
889 cvmx_write_csr(CVMX_IOB_INT_SUM, iob_int_sum.u64);
890 // Skipping iob_int_sum.s.reserved_6_63
891 if (iob_int_sum.s.p_dat)
892 PRINT_ERROR("IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
893 " port for a passthrough packet.\n"
894 " The first detected error associated with bits [5:0]\n"
895 " of this register will only be set here. A new bit\n"
896 " can be set when the previous reported bit is cleared.\n");
897 if (iob_int_sum.s.np_dat)
898 PRINT_ERROR("IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
899 " port for a non-passthrough packet.\n"
900 " The first detected error associated with bits [5:0]\n"
901 " of this register will only be set here. A new bit\n"
902 " can be set when the previous reported bit is cleared.\n");
903 if (iob_int_sum.s.p_eop)
904 PRINT_ERROR("IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
905 " port for a passthrough packet.\n"
906 " The first detected error associated with bits [5:0]\n"
907 " of this register will only be set here. A new bit\n"
908 " can be set when the previous reported bit is cleared.\n");
909 if (iob_int_sum.s.p_sop)
910 PRINT_ERROR("IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
911 " port for a passthrough packet.\n"
912 " The first detected error associated with bits [5:0]\n"
913 " of this register will only be set here. A new bit\n"
914 " can be set when the previous reported bit is cleared.\n");
915 if (iob_int_sum.s.np_eop)
916 PRINT_ERROR("IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
917 " port for a non-passthrough packet.\n"
918 " The first detected error associated with bits [5:0]\n"
919 " of this register will only be set here. A new bit\n"
920 " can be set when the previous reported bit is cleared.\n");
921 if (iob_int_sum.s.np_sop)
922 PRINT_ERROR("IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
923 " port for a non-passthrough packet.\n"
924 " The first detected error associated with bits [5:0]\n"
925 " of this register will only be set here. A new bit\n"
926 " can be set when the previous reported bit is cleared.\n");
931 * __cvmx_interrupt_ipd_int_enb_enable enables all interrupt bits in cvmx_ipd_int_enb_t
933 void __cvmx_interrupt_ipd_int_enb_enable(void)
935 cvmx_ipd_int_enb_t ipd_int_enb;
936 cvmx_write_csr(CVMX_IPD_INT_SUM, cvmx_read_csr(CVMX_IPD_INT_SUM));
938 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
940 // Skipping ipd_int_enb.s.reserved_12_63
941 //ipd_int_enb.s.pq_sub = 1; // Disable per port backpressure overflow checking since it happens when not in use
942 //ipd_int_enb.s.pq_add = 1; // Disable per port backpressure overflow checking since it happens when not in use
943 ipd_int_enb.s.bc_ovr = 1;
944 ipd_int_enb.s.d_coll = 1;
945 ipd_int_enb.s.c_coll = 1;
946 ipd_int_enb.s.cc_ovr = 1;
947 ipd_int_enb.s.dc_ovr = 1;
948 ipd_int_enb.s.bp_sub = 1;
949 ipd_int_enb.s.prc_par3 = 1;
950 ipd_int_enb.s.prc_par2 = 1;
951 ipd_int_enb.s.prc_par1 = 1;
952 ipd_int_enb.s.prc_par0 = 1;
954 if (OCTEON_IS_MODEL(OCTEON_CN30XX))
956 // Skipping ipd_int_enb.s.reserved_5_63
957 ipd_int_enb.s.bp_sub = 1;
958 ipd_int_enb.s.prc_par3 = 1;
959 ipd_int_enb.s.prc_par2 = 1;
960 ipd_int_enb.s.prc_par1 = 1;
961 ipd_int_enb.s.prc_par0 = 1;
963 if (OCTEON_IS_MODEL(OCTEON_CN50XX))
965 // Skipping ipd_int_enb.s.reserved_10_63
966 ipd_int_enb.s.bc_ovr = 1;
967 ipd_int_enb.s.d_coll = 1;
968 ipd_int_enb.s.c_coll = 1;
969 ipd_int_enb.s.cc_ovr = 1;
970 ipd_int_enb.s.dc_ovr = 1;
971 ipd_int_enb.s.bp_sub = 1;
972 ipd_int_enb.s.prc_par3 = 1;
973 ipd_int_enb.s.prc_par2 = 1;
974 ipd_int_enb.s.prc_par1 = 1;
975 ipd_int_enb.s.prc_par0 = 1;
977 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
979 // Skipping ipd_int_enb.s.reserved_10_63
980 if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
982 ipd_int_enb.s.bc_ovr = 1;
983 ipd_int_enb.s.d_coll = 1;
984 ipd_int_enb.s.c_coll = 1;
985 ipd_int_enb.s.cc_ovr = 1;
986 ipd_int_enb.s.dc_ovr = 1;
988 ipd_int_enb.s.bp_sub = 1;
989 ipd_int_enb.s.prc_par3 = 1;
990 ipd_int_enb.s.prc_par2 = 1;
991 ipd_int_enb.s.prc_par1 = 1;
992 ipd_int_enb.s.prc_par0 = 1;
994 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
996 // Skipping ipd_int_enb.s.reserved_5_63
997 ipd_int_enb.s.bp_sub = 1;
998 ipd_int_enb.s.prc_par3 = 1;
999 ipd_int_enb.s.prc_par2 = 1;
1000 ipd_int_enb.s.prc_par1 = 1;
1001 ipd_int_enb.s.prc_par0 = 1;
1003 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
1005 // Skipping ipd_int_enb.s.reserved_10_63
1006 ipd_int_enb.s.bc_ovr = 1;
1007 ipd_int_enb.s.d_coll = 1;
1008 ipd_int_enb.s.c_coll = 1;
1009 ipd_int_enb.s.cc_ovr = 1;
1010 ipd_int_enb.s.dc_ovr = 1;
1011 ipd_int_enb.s.bp_sub = 1;
1012 ipd_int_enb.s.prc_par3 = 1;
1013 ipd_int_enb.s.prc_par2 = 1;
1014 ipd_int_enb.s.prc_par1 = 1;
1015 ipd_int_enb.s.prc_par0 = 1;
1017 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
1019 // Skipping ipd_int_enb.s.reserved_12_63
1020 //ipd_int_enb.s.pq_sub = 1; // Disable per port backpressure overflow checking since it happens when not in use
1021 //ipd_int_enb.s.pq_add = 1; // Disable per port backpressure overflow checking since it happens when not in use
1022 ipd_int_enb.s.bc_ovr = 1;
1023 ipd_int_enb.s.d_coll = 1;
1024 ipd_int_enb.s.c_coll = 1;
1025 ipd_int_enb.s.cc_ovr = 1;
1026 ipd_int_enb.s.dc_ovr = 1;
1027 ipd_int_enb.s.bp_sub = 1;
1028 ipd_int_enb.s.prc_par3 = 1;
1029 ipd_int_enb.s.prc_par2 = 1;
1030 ipd_int_enb.s.prc_par1 = 1;
1031 ipd_int_enb.s.prc_par0 = 1;
1033 cvmx_write_csr(CVMX_IPD_INT_ENB, ipd_int_enb.u64);
1038 * __cvmx_interrupt_ipd_int_sum_decode decodes all interrupt bits in cvmx_ipd_int_sum_t
1040 void __cvmx_interrupt_ipd_int_sum_decode(void)
1042 cvmx_ipd_int_sum_t ipd_int_sum;
1043 ipd_int_sum.u64 = cvmx_read_csr(CVMX_IPD_INT_SUM);
1044 ipd_int_sum.u64 &= cvmx_read_csr(CVMX_IPD_INT_ENB);
1045 cvmx_write_csr(CVMX_IPD_INT_SUM, ipd_int_sum.u64);
1046 // Skipping ipd_int_sum.s.reserved_12_63
1047 if (ipd_int_sum.s.pq_sub)
1048 PRINT_ERROR("IPD_INT_SUM[PQ_SUB]: Set when a port-qos does an sub to the count\n"
1049 " that causes the counter to wrap.\n");
1050 if (ipd_int_sum.s.pq_add)
1051 PRINT_ERROR("IPD_INT_SUM[PQ_ADD]: Set when a port-qos does an add to the count\n"
1052 " that causes the counter to wrap.\n");
1053 if (ipd_int_sum.s.bc_ovr)
1054 PRINT_ERROR("IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
1055 " This is a PASS-3 Field.\n");
1056 if (ipd_int_sum.s.d_coll)
1057 PRINT_ERROR("IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
1059 " This is a PASS-3 Field.\n");
1060 if (ipd_int_sum.s.c_coll)
1061 PRINT_ERROR("IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
1063 " This is a PASS-3 Field.\n");
1064 if (ipd_int_sum.s.cc_ovr)
1065 PRINT_ERROR("IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
1066 " This is a PASS-3 Field.\n");
1067 if (ipd_int_sum.s.dc_ovr)
1068 PRINT_ERROR("IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
1069 " This is a PASS-3 Field.\n");
1070 if (ipd_int_sum.s.bp_sub)
1071 PRINT_ERROR("IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
1072 " supplied illegal value.\n");
1073 if (ipd_int_sum.s.prc_par3)
1074 PRINT_ERROR("IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
1075 " [127:96] of the PBM memory.\n");
1076 if (ipd_int_sum.s.prc_par2)
1077 PRINT_ERROR("IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
1078 " [95:64] of the PBM memory.\n");
1079 if (ipd_int_sum.s.prc_par1)
1080 PRINT_ERROR("IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
1081 " [63:32] of the PBM memory.\n");
1082 if (ipd_int_sum.s.prc_par0)
1083 PRINT_ERROR("IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
1084 " [31:0] of the PBM memory.\n");
1089 * __cvmx_interrupt_key_int_enb_enable enables all interrupt bits in cvmx_key_int_enb_t
1091 void __cvmx_interrupt_key_int_enb_enable(void)
1093 cvmx_key_int_enb_t key_int_enb;
1094 cvmx_write_csr(CVMX_KEY_INT_SUM, cvmx_read_csr(CVMX_KEY_INT_SUM));
1095 key_int_enb.u64 = 0;
1096 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
1098 // Skipping key_int_enb.s.reserved_4_63
1099 key_int_enb.s.ked1_dbe = 1;
1100 key_int_enb.s.ked1_sbe = 1;
1101 key_int_enb.s.ked0_dbe = 1;
1102 key_int_enb.s.ked0_sbe = 1;
1104 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
1106 // Skipping key_int_enb.s.reserved_4_63
1107 key_int_enb.s.ked1_dbe = 1;
1108 key_int_enb.s.ked1_sbe = 1;
1109 key_int_enb.s.ked0_dbe = 1;
1110 key_int_enb.s.ked0_sbe = 1;
1112 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
1114 // Skipping key_int_enb.s.reserved_4_63
1115 key_int_enb.s.ked1_dbe = 1;
1116 key_int_enb.s.ked1_sbe = 1;
1117 key_int_enb.s.ked0_dbe = 1;
1118 key_int_enb.s.ked0_sbe = 1;
1120 cvmx_write_csr(CVMX_KEY_INT_ENB, key_int_enb.u64);
1125 * __cvmx_interrupt_key_int_sum_decode decodes all interrupt bits in cvmx_key_int_sum_t
1127 void __cvmx_interrupt_key_int_sum_decode(void)
1129 cvmx_key_int_sum_t key_int_sum;
1130 key_int_sum.u64 = cvmx_read_csr(CVMX_KEY_INT_SUM);
1131 key_int_sum.u64 &= cvmx_read_csr(CVMX_KEY_INT_ENB);
1132 cvmx_write_csr(CVMX_KEY_INT_SUM, key_int_sum.u64);
1133 // Skipping key_int_sum.s.reserved_4_63
1134 if (key_int_sum.s.ked1_dbe)
1135 PRINT_ERROR("KEY_INT_SUM[KED1_DBE]: Error bit\n");
1136 if (key_int_sum.s.ked1_sbe)
1137 PRINT_ERROR("KEY_INT_SUM[KED1_SBE]: Error bit\n");
1138 if (key_int_sum.s.ked0_dbe)
1139 PRINT_ERROR("KEY_INT_SUM[KED0_DBE]: Error bit\n");
1140 if (key_int_sum.s.ked0_sbe)
1141 PRINT_ERROR("KEY_INT_SUM[KED0_SBE]: Error bit\n");
1146 * __cvmx_interrupt_mio_boot_int_enable enables all interrupt bits in cvmx_mio_boot_int_t
1148 void __cvmx_interrupt_mio_boot_int_enable(void)
1150 cvmx_mio_boot_int_t mio_boot_int;
1151 cvmx_write_csr(CVMX_MIO_BOOT_ERR, cvmx_read_csr(CVMX_MIO_BOOT_ERR));
1152 mio_boot_int.u64 = 0;
1153 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
1155 // Skipping mio_boot_int.s.reserved_2_63
1156 mio_boot_int.s.wait_int = 1;
1157 mio_boot_int.s.adr_int = 1;
1159 if (OCTEON_IS_MODEL(OCTEON_CN30XX))
1161 // Skipping mio_boot_int.s.reserved_2_63
1162 mio_boot_int.s.wait_int = 1;
1163 mio_boot_int.s.adr_int = 1;
1165 if (OCTEON_IS_MODEL(OCTEON_CN50XX))
1167 // Skipping mio_boot_int.s.reserved_2_63
1168 mio_boot_int.s.wait_int = 1;
1169 mio_boot_int.s.adr_int = 1;
1171 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
1173 // Skipping mio_boot_int.s.reserved_2_63
1174 mio_boot_int.s.wait_int = 1;
1175 mio_boot_int.s.adr_int = 1;
1177 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
1179 // Skipping mio_boot_int.s.reserved_2_63
1180 mio_boot_int.s.wait_int = 1;
1181 mio_boot_int.s.adr_int = 1;
1183 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
1185 // Skipping mio_boot_int.s.reserved_2_63
1186 mio_boot_int.s.wait_int = 1;
1187 mio_boot_int.s.adr_int = 1;
1189 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
1191 // Skipping mio_boot_int.s.reserved_2_63
1192 mio_boot_int.s.wait_int = 1;
1193 mio_boot_int.s.adr_int = 1;
1195 cvmx_write_csr(CVMX_MIO_BOOT_INT, mio_boot_int.u64);
1200 * __cvmx_interrupt_mio_boot_err_decode decodes all interrupt bits in cvmx_mio_boot_err_t
1202 void __cvmx_interrupt_mio_boot_err_decode(void)
1204 cvmx_mio_boot_err_t mio_boot_err;
1205 mio_boot_err.u64 = cvmx_read_csr(CVMX_MIO_BOOT_ERR);
1206 mio_boot_err.u64 &= cvmx_read_csr(CVMX_MIO_BOOT_INT);
1207 cvmx_write_csr(CVMX_MIO_BOOT_ERR, mio_boot_err.u64);
1208 // Skipping mio_boot_err.s.reserved_2_63
1209 if (mio_boot_err.s.wait_err)
1210 PRINT_ERROR("MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n");
1211 if (mio_boot_err.s.adr_err)
1212 PRINT_ERROR("MIO_BOOT_ERR[ADR_ERR]: Address decode error\n");
1217 * __cvmx_interrupt_npei_int_sum_decode decodes all interrupt bits in cvmx_npei_int_sum_t
1219 void __cvmx_interrupt_npei_int_sum_decode(void)
1221 cvmx_npei_int_sum_t npei_int_sum;
1222 npei_int_sum.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM);
1223 /* Note that NPEI_INT_ENB2 controls the internal RSL interrupts.
1224 NPEI_INT_ENB controls external forwarding which is not what we
1225 want. It is a little strange that we are using NPEI_INT_SUM with
1226 NPEI_INT_ENB2, but we need the R/W version of NPEI_INT_SUM2 and
1227 internal RSL interrupts */
1228 npei_int_sum.u64 &= cvmx_read_csr(CVMX_PEXP_NPEI_INT_ENB2);
1229 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, npei_int_sum.u64);
1230 if (npei_int_sum.s.mio_inta)
1231 PRINT_ERROR("NPEI_INT_SUM[MIO_INTA]: Interrupt from MIO.\n");
1232 // Skipping npei_int_sum.s.reserved_62_62
1233 if (npei_int_sum.s.int_a)
1234 PRINT_ERROR("NPEI_INT_SUM[INT_A]: Set when a bit in the NPEI_INT_A_SUM register and\n"
1235 " the cooresponding bit in the NPEI_INT_A_ENB\n"
1236 " register is set.\n");
1237 if (npei_int_sum.s.c1_ldwn)
1239 cvmx_ciu_soft_prst_t ciu_soft_prst;
1240 PRINT_ERROR("NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n");
1241 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1242 if (!ciu_soft_prst.s.soft_prst)
1244 /* Attempt to automatically bring the link back up */
1245 cvmx_pcie_rc_shutdown(1);
1246 cvmx_pcie_rc_initialize(1);
1248 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
1250 if (npei_int_sum.s.c0_ldwn)
1252 cvmx_ciu_soft_prst_t ciu_soft_prst;
1253 PRINT_ERROR("NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n");
1254 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1255 if (!ciu_soft_prst.s.soft_prst)
1257 /* Attempt to automatically bring the link back up */
1258 cvmx_pcie_rc_shutdown(0);
1259 cvmx_pcie_rc_initialize(0);
1261 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
1263 if (npei_int_sum.s.c1_exc)
1266 PRINT_ERROR("NPEI_INT_SUM[C1_EXC]: Set when the PESC1_DBG_INFO register has a bit\n"
1267 " set and its cooresponding PESC1_DBG_INFO_EN bit\n"
1270 __cvmx_interrupt_pescx_dbg_info_decode(1);
1272 if (npei_int_sum.s.c0_exc)
1275 PRINT_ERROR("NPEI_INT_SUM[C0_EXC]: Set when the PESC0_DBG_INFO register has a bit\n"
1276 " set and its cooresponding PESC0_DBG_INFO_EN bit\n"
1279 __cvmx_interrupt_pescx_dbg_info_decode(0);
1281 if (npei_int_sum.s.c1_up_wf)
1282 PRINT_ERROR("NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
1283 " register. Core1.\n");
1284 if (npei_int_sum.s.c0_up_wf)
1285 PRINT_ERROR("NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
1286 " register. Core0.\n");
1287 if (npei_int_sum.s.c1_un_wf)
1288 PRINT_ERROR("NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
1289 " register. Core1.\n");
1290 if (npei_int_sum.s.c0_un_wf)
1291 PRINT_ERROR("NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
1292 " register. Core0.\n");
1293 if (npei_int_sum.s.c1_un_bx)
1294 PRINT_ERROR("NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
1296 if (npei_int_sum.s.c1_un_wi)
1297 PRINT_ERROR("NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
1299 if (npei_int_sum.s.c1_un_b2)
1300 PRINT_ERROR("NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
1302 if (npei_int_sum.s.c1_un_b1)
1303 PRINT_ERROR("NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
1305 if (npei_int_sum.s.c1_un_b0)
1306 PRINT_ERROR("NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
1308 if (npei_int_sum.s.c1_up_bx)
1309 PRINT_ERROR("NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
1311 if (npei_int_sum.s.c1_up_wi)
1312 PRINT_ERROR("NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
1314 if (npei_int_sum.s.c1_up_b2)
1315 PRINT_ERROR("NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
1317 if (npei_int_sum.s.c1_up_b1)
1318 PRINT_ERROR("NPEI_INT_SUM[C1_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
1320 if (npei_int_sum.s.c1_up_b0)
1321 PRINT_ERROR("NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
1323 if (npei_int_sum.s.c0_un_bx)
1324 PRINT_ERROR("NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
1326 if (npei_int_sum.s.c0_un_wi)
1327 PRINT_ERROR("NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
1329 if (npei_int_sum.s.c0_un_b2)
1330 PRINT_ERROR("NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
1332 if (npei_int_sum.s.c0_un_b1)
1333 PRINT_ERROR("NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
1335 if (npei_int_sum.s.c0_un_b0)
1336 PRINT_ERROR("NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
1338 if (npei_int_sum.s.c0_up_bx)
1339 PRINT_ERROR("NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
1341 if (npei_int_sum.s.c0_up_wi)
1342 PRINT_ERROR("NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
1344 if (npei_int_sum.s.c0_up_b2)
1345 PRINT_ERROR("NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
1347 if (npei_int_sum.s.c0_up_b1)
1348 PRINT_ERROR("NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
1350 if (npei_int_sum.s.c0_up_b0)
1351 PRINT_ERROR("NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
1353 if (npei_int_sum.s.c1_hpint)
1354 PRINT_ERROR("NPEI_INT_SUM[C1_HPINT]: Hot-Plug Interrupt.\n"
1355 " Pcie Core 1 (hp_int).\n"
1356 " This interrupt will only be generated when\n"
1357 " PCIERC1_CFG034[DLLS_C] is generated. Hot plug is\n"
1358 " not supported.\n");
1359 if (npei_int_sum.s.c1_pmei)
1360 PRINT_ERROR("NPEI_INT_SUM[C1_PMEI]: PME Interrupt.\n"
1361 " Pcie Core 1. (cfg_pme_int)\n");
1362 if (npei_int_sum.s.c1_wake)
1363 PRINT_ERROR("NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
1364 " Pcie Core 1. (wake_n)\n"
1365 " Octeon will never generate this interrupt.\n");
1366 if (npei_int_sum.s.crs1_dr)
1367 PRINT_ERROR("NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n");
1368 if (npei_int_sum.s.c1_se)
1369 PRINT_ERROR("NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
1370 " Pcie Core 1. (cfg_sys_err_rc)\n");
1371 if (npei_int_sum.s.crs1_er)
1372 PRINT_ERROR("NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n");
1373 if (npei_int_sum.s.c1_aeri)
1374 PRINT_ERROR("NPEI_INT_SUM[C1_AERI]: Advanced Error Reporting Interrupt, RC Mode Only.\n"
1376 if (npei_int_sum.s.c0_hpint)
1377 PRINT_ERROR("NPEI_INT_SUM[C0_HPINT]: Hot-Plug Interrupt.\n"
1378 " Pcie Core 0 (hp_int).\n"
1379 " This interrupt will only be generated when\n"
1380 " PCIERC0_CFG034[DLLS_C] is generated. Hot plug is\n"
1381 " not supported.\n");
1382 if (npei_int_sum.s.c0_pmei)
1383 PRINT_ERROR("NPEI_INT_SUM[C0_PMEI]: PME Interrupt.\n"
1384 " Pcie Core 0. (cfg_pme_int)\n");
1385 if (npei_int_sum.s.c0_wake)
1386 PRINT_ERROR("NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
1387 " Pcie Core 0. (wake_n)\n"
1388 " Octeon will never generate this interrupt.\n");
1389 if (npei_int_sum.s.crs0_dr)
1390 PRINT_ERROR("NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n");
1391 if (npei_int_sum.s.c0_se)
1392 PRINT_ERROR("NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
1393 " Pcie Core 0. (cfg_sys_err_rc)\n");
1394 if (npei_int_sum.s.crs0_er)
1395 PRINT_ERROR("NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n");
1396 if (npei_int_sum.s.c0_aeri)
1397 PRINT_ERROR("NPEI_INT_SUM[C0_AERI]: Advanced Error Reporting Interrupt, RC Mode Only.\n"
1398 " Pcie Core 0 (cfg_aer_rc_err_int).\n");
1399 if (npei_int_sum.s.ptime)
1400 PRINT_ERROR("NPEI_INT_SUM[PTIME]: Packet Timer has an interrupt. Which rings can\n"
1401 " be found in NPEI_PKT_TIME_INT.\n");
1402 if (npei_int_sum.s.pcnt)
1403 PRINT_ERROR("NPEI_INT_SUM[PCNT]: Packet Counter has an interrupt. Which rings can\n"
1404 " be found in NPEI_PKT_CNT_INT.\n");
1405 if (npei_int_sum.s.pidbof)
1406 PRINT_ERROR("NPEI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
1407 " doorbell can be found in NPEI_INT_INFO[PIDBOF]\n");
1408 if (npei_int_sum.s.psldbof)
1409 PRINT_ERROR("NPEI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
1410 " doorbell can be found in NPEI_INT_INFO[PSLDBOF]\n");
1411 if (npei_int_sum.s.dtime1)
1412 PRINT_ERROR("NPEI_INT_SUM[DTIME1]: Whenever NPEI_DMA_CNTS[DMA1] is not 0, the\n"
1413 " DMA_CNT1 timer increments every core clock. When\n"
1414 " DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],\n"
1415 " this bit is set. Writing a '1' to this bit also\n"
1416 " clears the DMA_CNT1 timer.\n");
1417 if (npei_int_sum.s.dtime0)
1418 PRINT_ERROR("NPEI_INT_SUM[DTIME0]: Whenever NPEI_DMA_CNTS[DMA0] is not 0, the\n"
1419 " DMA_CNT0 timer increments every core clock. When\n"
1420 " DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],\n"
1421 " this bit is set. Writing a '1' to this bit also\n"
1422 " clears the DMA_CNT0 timer.\n");
1423 if (npei_int_sum.s.dcnt1)
1424 PRINT_ERROR("NPEI_INT_SUM[DCNT1]: This bit indicates that NPEI_DMA_CNTS[DMA1] was/is\n"
1425 " greater than NPEI_DMA1_INT_LEVEL[CNT].\n");
1426 if (npei_int_sum.s.dcnt0)
1427 PRINT_ERROR("NPEI_INT_SUM[DCNT0]: This bit indicates that NPEI_DMA_CNTS[DMA0] was/is\n"
1428 " greater than NPEI_DMA0_INT_LEVEL[CNT].\n");
1429 if (npei_int_sum.s.dma1fi)
1430 PRINT_ERROR("NPEI_INT_SUM[DMA1FI]: DMA0 set Forced Interrupt.\n");
1431 if (npei_int_sum.s.dma0fi)
1432 PRINT_ERROR("NPEI_INT_SUM[DMA0FI]: DMA0 set Forced Interrupt.\n");
1433 if (npei_int_sum.s.dma4dbo)
1434 PRINT_ERROR("NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
1435 " Bit[32] of the doorbell count was set.\n");
1436 if (npei_int_sum.s.dma3dbo)
1437 PRINT_ERROR("NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
1438 " Bit[32] of the doorbell count was set.\n");
1439 if (npei_int_sum.s.dma2dbo)
1440 PRINT_ERROR("NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
1441 " Bit[32] of the doorbell count was set.\n");
1442 if (npei_int_sum.s.dma1dbo)
1443 PRINT_ERROR("NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
1444 " Bit[32] of the doorbell count was set.\n");
1445 if (npei_int_sum.s.dma0dbo)
1446 PRINT_ERROR("NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
1447 " Bit[32] of the doorbell count was set.\n");
1448 if (npei_int_sum.s.iob2big)
1449 PRINT_ERROR("NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n");
1450 if (npei_int_sum.s.bar0_to)
1451 PRINT_ERROR("NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
1452 " read-data/commit in 0xffff core clocks.\n");
1453 if (npei_int_sum.s.rml_wto)
1454 PRINT_ERROR("NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n");
1455 if (npei_int_sum.s.rml_rto)
1456 PRINT_ERROR("NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n");
1461 * __cvmx_interrupt_npei_int_enb2_enable enables all interrupt bits in cvmx_npei_int_enb2_t
1463 void __cvmx_interrupt_npei_int_enb2_enable(void)
1465 int enable_pcie0 = 0;
1466 int enable_pcie1 = 0;
1467 cvmx_npei_int_enb2_t npei_int_enb2;
1468 /* Reset NPEI_INT_SUM, as NPEI_INT_SUM2 is a read-only copy of NPEI_INT_SUM. */
1469 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
1470 npei_int_enb2.u64 = 0;
1471 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
1473 cvmx_pescx_ctl_status2_t pescx_ctl_status2;
1474 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(0));
1475 enable_pcie0 = !pescx_ctl_status2.s.pcierst;
1476 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(1));
1477 enable_pcie1 = !pescx_ctl_status2.s.pcierst;
1479 // Skipping npei_int_enb2.s.reserved_62_63
1480 npei_int_enb2.s.int_a = 1;
1481 npei_int_enb2.s.c1_ldwn = enable_pcie1;
1482 npei_int_enb2.s.c0_ldwn = enable_pcie0;
1483 npei_int_enb2.s.c1_exc = enable_pcie1;
1484 npei_int_enb2.s.c0_exc = enable_pcie0;
1485 npei_int_enb2.s.c1_up_wf = enable_pcie1;
1486 npei_int_enb2.s.c0_up_wf = enable_pcie0;
1487 npei_int_enb2.s.c1_un_wf = enable_pcie1;
1488 npei_int_enb2.s.c0_un_wf = enable_pcie0;
1489 npei_int_enb2.s.c1_un_bx = enable_pcie1;
1490 npei_int_enb2.s.c1_un_wi = enable_pcie1;
1491 npei_int_enb2.s.c1_un_b2 = enable_pcie1;
1492 npei_int_enb2.s.c1_un_b1 = enable_pcie1;
1493 npei_int_enb2.s.c1_un_b0 = enable_pcie1;
1494 npei_int_enb2.s.c1_up_bx = enable_pcie1;
1495 npei_int_enb2.s.c1_up_wi = enable_pcie1;
1496 npei_int_enb2.s.c1_up_b2 = enable_pcie1;
1497 npei_int_enb2.s.c1_up_b1 = enable_pcie1;
1498 npei_int_enb2.s.c1_up_b0 = enable_pcie1;
1499 npei_int_enb2.s.c0_un_bx = enable_pcie0;
1500 npei_int_enb2.s.c0_un_wi = enable_pcie0;
1501 npei_int_enb2.s.c0_un_b2 = enable_pcie0;
1502 npei_int_enb2.s.c0_un_b1 = enable_pcie0;
1503 npei_int_enb2.s.c0_un_b0 = enable_pcie0;
1504 npei_int_enb2.s.c0_up_bx = enable_pcie0;
1505 npei_int_enb2.s.c0_up_wi = enable_pcie0;
1506 npei_int_enb2.s.c0_up_b2 = enable_pcie0;
1507 npei_int_enb2.s.c0_up_b1 = enable_pcie0;
1508 npei_int_enb2.s.c0_up_b0 = enable_pcie0;
1509 npei_int_enb2.s.c1_hpint = enable_pcie1;
1510 npei_int_enb2.s.c1_pmei = enable_pcie1;
1511 npei_int_enb2.s.c1_wake = enable_pcie1;
1512 npei_int_enb2.s.crs1_dr = enable_pcie1;
1513 npei_int_enb2.s.c1_se = enable_pcie1;
1514 npei_int_enb2.s.crs1_er = enable_pcie1;
1515 npei_int_enb2.s.c1_aeri = enable_pcie1;
1516 npei_int_enb2.s.c0_hpint = enable_pcie0;
1517 npei_int_enb2.s.c0_pmei = enable_pcie0;
1518 npei_int_enb2.s.c0_wake = enable_pcie0;
1519 npei_int_enb2.s.crs0_dr = enable_pcie0;
1520 npei_int_enb2.s.c0_se = enable_pcie0;
1521 npei_int_enb2.s.crs0_er = enable_pcie0;
1522 npei_int_enb2.s.c0_aeri = enable_pcie0;
1523 npei_int_enb2.s.ptime = 1;
1524 npei_int_enb2.s.pcnt = 1;
1525 npei_int_enb2.s.pidbof = 1;
1526 npei_int_enb2.s.psldbof = 1;
1527 npei_int_enb2.s.dtime1 = 1;
1528 npei_int_enb2.s.dtime0 = 1;
1529 npei_int_enb2.s.dcnt1 = 1;
1530 npei_int_enb2.s.dcnt0 = 1;
1531 npei_int_enb2.s.dma1fi = 1;
1532 npei_int_enb2.s.dma0fi = 1;
1533 npei_int_enb2.s.dma4dbo = 1;
1534 npei_int_enb2.s.dma3dbo = 1;
1535 npei_int_enb2.s.dma2dbo = 1;
1536 npei_int_enb2.s.dma1dbo = 1;
1537 npei_int_enb2.s.dma0dbo = 1;
1538 npei_int_enb2.s.iob2big = 1;
1539 npei_int_enb2.s.bar0_to = 1;
1540 npei_int_enb2.s.rml_wto = 1;
1541 npei_int_enb2.s.rml_rto = 1;
1543 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
1545 cvmx_pescx_ctl_status2_t pescx_ctl_status2;
1546 cvmx_npei_dbg_data_t npei_dbg_data;
1547 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(0));
1548 enable_pcie0 = !pescx_ctl_status2.s.pcierst;
1549 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1550 if (!npei_dbg_data.cn52xx.qlm0_link_width)
1552 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(1));
1553 enable_pcie1 = !pescx_ctl_status2.s.pcierst;
1556 // Skipping npei_int_enb2.s.reserved_62_63
1557 npei_int_enb2.s.int_a = 1;
1558 npei_int_enb2.s.c1_ldwn = enable_pcie1;
1559 npei_int_enb2.s.c0_ldwn = enable_pcie0;
1560 npei_int_enb2.s.c1_exc = enable_pcie1;
1561 npei_int_enb2.s.c0_exc = enable_pcie0;
1562 npei_int_enb2.s.c1_up_wf = enable_pcie1;
1563 npei_int_enb2.s.c0_up_wf = enable_pcie0;
1564 npei_int_enb2.s.c1_un_wf = enable_pcie1;
1565 npei_int_enb2.s.c0_un_wf = enable_pcie0;
1566 npei_int_enb2.s.c1_un_bx = enable_pcie1;
1567 npei_int_enb2.s.c1_un_wi = enable_pcie1;
1568 npei_int_enb2.s.c1_un_b2 = enable_pcie1;
1569 npei_int_enb2.s.c1_un_b1 = enable_pcie1;
1570 npei_int_enb2.s.c1_un_b0 = enable_pcie1;
1571 npei_int_enb2.s.c1_up_bx = enable_pcie1;
1572 npei_int_enb2.s.c1_up_wi = enable_pcie1;
1573 npei_int_enb2.s.c1_up_b2 = enable_pcie1;
1574 npei_int_enb2.s.c1_up_b1 = enable_pcie1;
1575 npei_int_enb2.s.c1_up_b0 = enable_pcie1;
1576 npei_int_enb2.s.c0_un_bx = enable_pcie0;
1577 npei_int_enb2.s.c0_un_wi = enable_pcie0;
1578 npei_int_enb2.s.c0_un_b2 = enable_pcie0;
1579 npei_int_enb2.s.c0_un_b1 = enable_pcie0;
1580 npei_int_enb2.s.c0_un_b0 = enable_pcie0;
1581 npei_int_enb2.s.c0_up_bx = enable_pcie0;
1582 npei_int_enb2.s.c0_up_wi = enable_pcie0;
1583 npei_int_enb2.s.c0_up_b2 = enable_pcie0;
1584 npei_int_enb2.s.c0_up_b1 = enable_pcie0;
1585 npei_int_enb2.s.c0_up_b0 = enable_pcie0;
1586 npei_int_enb2.s.c1_hpint = enable_pcie1;
1587 npei_int_enb2.s.c1_pmei = enable_pcie1;
1588 npei_int_enb2.s.c1_wake = enable_pcie1;
1589 npei_int_enb2.s.crs1_dr = enable_pcie1;
1590 npei_int_enb2.s.c1_se = enable_pcie1;
1591 npei_int_enb2.s.crs1_er = enable_pcie1;
1592 npei_int_enb2.s.c1_aeri = enable_pcie1;
1593 npei_int_enb2.s.c0_hpint = enable_pcie0;
1594 npei_int_enb2.s.c0_pmei = enable_pcie0;
1595 npei_int_enb2.s.c0_wake = enable_pcie0;
1596 npei_int_enb2.s.crs0_dr = enable_pcie0;
1597 npei_int_enb2.s.c0_se = enable_pcie0;
1598 npei_int_enb2.s.crs0_er = enable_pcie0;
1599 npei_int_enb2.s.c0_aeri = enable_pcie0;
1600 npei_int_enb2.s.ptime = 1;
1601 npei_int_enb2.s.pcnt = 1;
1602 npei_int_enb2.s.pidbof = 1;
1603 npei_int_enb2.s.psldbof = 1;
1604 npei_int_enb2.s.dtime1 = 1;
1605 npei_int_enb2.s.dtime0 = 1;
1606 npei_int_enb2.s.dcnt1 = 1;
1607 npei_int_enb2.s.dcnt0 = 1;
1608 npei_int_enb2.s.dma1fi = 1;
1609 npei_int_enb2.s.dma0fi = 1;
1610 if (!OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
1611 npei_int_enb2.s.dma4dbo = 1;
1612 npei_int_enb2.s.dma3dbo = 1;
1613 npei_int_enb2.s.dma2dbo = 1;
1614 npei_int_enb2.s.dma1dbo = 1;
1615 npei_int_enb2.s.dma0dbo = 1;
1616 npei_int_enb2.s.iob2big = 1;
1617 npei_int_enb2.s.bar0_to = 1;
1618 npei_int_enb2.s.rml_wto = 1;
1619 npei_int_enb2.s.rml_rto = 1;
1621 cvmx_write_csr(CVMX_PEXP_NPEI_INT_ENB2, npei_int_enb2.u64);
1623 __cvmx_interrupt_pescx_dbg_info_en_enable(0);
1625 __cvmx_interrupt_pescx_dbg_info_en_enable(1);
1630 * __cvmx_interrupt_npi_int_enb_enable enables all interrupt bits in cvmx_npi_int_enb_t
1632 void __cvmx_interrupt_npi_int_enb_enable(void)
1634 cvmx_npi_int_enb_t npi_int_enb;
1635 cvmx_write_csr(CVMX_NPI_INT_SUM, cvmx_read_csr(CVMX_NPI_INT_SUM));
1636 npi_int_enb.u64 = 0;
1637 if (OCTEON_IS_MODEL(OCTEON_CN30XX))
1639 // Skipping npi_int_enb.s.reserved_62_63
1640 npi_int_enb.s.q1_a_f = 1;
1641 npi_int_enb.s.q1_s_e = 1;
1642 npi_int_enb.s.pdf_p_f = 1;
1643 npi_int_enb.s.pdf_p_e = 1;
1644 npi_int_enb.s.pcf_p_f = 1;
1645 npi_int_enb.s.pcf_p_e = 1;
1646 npi_int_enb.s.rdx_s_e = 1;
1647 npi_int_enb.s.rwx_s_e = 1;
1648 npi_int_enb.s.pnc_a_f = 1;
1649 npi_int_enb.s.pnc_s_e = 1;
1650 npi_int_enb.s.com_a_f = 1;
1651 npi_int_enb.s.com_s_e = 1;
1652 npi_int_enb.s.q3_a_f = 1;
1653 npi_int_enb.s.q3_s_e = 1;
1654 npi_int_enb.s.q2_a_f = 1;
1655 npi_int_enb.s.q2_s_e = 1;
1656 npi_int_enb.s.pcr_a_f = 1;
1657 npi_int_enb.s.pcr_s_e = 1;
1658 npi_int_enb.s.fcr_a_f = 1;
1659 npi_int_enb.s.fcr_s_e = 1;
1660 npi_int_enb.s.iobdma = 1;
1661 npi_int_enb.s.p_dperr = 1;
1662 npi_int_enb.s.win_rto = 1;
1663 // Skipping npi_int_enb.s.reserved_36_38
1664 npi_int_enb.s.i0_pperr = 1;
1665 // Skipping npi_int_enb.s.reserved_32_34
1666 npi_int_enb.s.p0_ptout = 1;
1667 // Skipping npi_int_enb.s.reserved_28_30
1668 npi_int_enb.s.p0_pperr = 1;
1669 // Skipping npi_int_enb.s.reserved_24_26
1670 npi_int_enb.s.g0_rtout = 1;
1671 // Skipping npi_int_enb.s.reserved_20_22
1672 npi_int_enb.s.p0_perr = 1;
1673 // Skipping npi_int_enb.s.reserved_16_18
1674 npi_int_enb.s.p0_rtout = 1;
1675 // Skipping npi_int_enb.s.reserved_12_14
1676 npi_int_enb.s.i0_overf = 1;
1677 // Skipping npi_int_enb.s.reserved_8_10
1678 npi_int_enb.s.i0_rtout = 1;
1679 // Skipping npi_int_enb.s.reserved_4_6
1680 npi_int_enb.s.po0_2sml = 1;
1681 npi_int_enb.s.pci_rsl = 1;
1682 npi_int_enb.s.rml_wto = 1;
1683 npi_int_enb.s.rml_rto = 1;
1685 if (OCTEON_IS_MODEL(OCTEON_CN50XX))
1687 // Skipping npi_int_enb.s.reserved_62_63
1688 npi_int_enb.s.q1_a_f = 1;
1689 npi_int_enb.s.q1_s_e = 1;
1690 npi_int_enb.s.pdf_p_f = 1;
1691 npi_int_enb.s.pdf_p_e = 1;
1692 npi_int_enb.s.pcf_p_f = 1;
1693 npi_int_enb.s.pcf_p_e = 1;
1694 npi_int_enb.s.rdx_s_e = 1;
1695 npi_int_enb.s.rwx_s_e = 1;
1696 npi_int_enb.s.pnc_a_f = 1;
1697 npi_int_enb.s.pnc_s_e = 1;
1698 npi_int_enb.s.com_a_f = 1;
1699 npi_int_enb.s.com_s_e = 1;
1700 npi_int_enb.s.q3_a_f = 1;
1701 npi_int_enb.s.q3_s_e = 1;
1702 npi_int_enb.s.q2_a_f = 1;
1703 npi_int_enb.s.q2_s_e = 1;
1704 npi_int_enb.s.pcr_a_f = 1;
1705 npi_int_enb.s.pcr_s_e = 1;
1706 npi_int_enb.s.fcr_a_f = 1;
1707 npi_int_enb.s.fcr_s_e = 1;
1708 npi_int_enb.s.iobdma = 1;
1709 npi_int_enb.s.p_dperr = 1;
1710 npi_int_enb.s.win_rto = 1;
1711 // Skipping npi_int_enb.s.reserved_37_38
1712 npi_int_enb.s.i1_pperr = 1;
1713 npi_int_enb.s.i0_pperr = 1;
1714 // Skipping npi_int_enb.s.reserved_33_34
1715 npi_int_enb.s.p1_ptout = 1;
1716 npi_int_enb.s.p0_ptout = 1;
1717 // Skipping npi_int_enb.s.reserved_29_30
1718 npi_int_enb.s.p1_pperr = 1;
1719 npi_int_enb.s.p0_pperr = 1;
1720 // Skipping npi_int_enb.s.reserved_25_26
1721 npi_int_enb.s.g1_rtout = 1;
1722 npi_int_enb.s.g0_rtout = 1;
1723 // Skipping npi_int_enb.s.reserved_21_22
1724 npi_int_enb.s.p1_perr = 1;
1725 npi_int_enb.s.p0_perr = 1;
1726 // Skipping npi_int_enb.s.reserved_17_18
1727 npi_int_enb.s.p1_rtout = 1;
1728 npi_int_enb.s.p0_rtout = 1;
1729 // Skipping npi_int_enb.s.reserved_13_14
1730 npi_int_enb.s.i1_overf = 1;
1731 npi_int_enb.s.i0_overf = 1;
1732 // Skipping npi_int_enb.s.reserved_9_10
1733 npi_int_enb.s.i1_rtout = 1;
1734 npi_int_enb.s.i0_rtout = 1;
1735 // Skipping npi_int_enb.s.reserved_5_6
1736 npi_int_enb.s.po1_2sml = 1;
1737 npi_int_enb.s.po0_2sml = 1;
1738 npi_int_enb.s.pci_rsl = 1;
1739 npi_int_enb.s.rml_wto = 1;
1740 npi_int_enb.s.rml_rto = 1;
1742 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
1744 // Skipping npi_int_enb.s.reserved_62_63
1745 npi_int_enb.s.q1_a_f = 1;
1746 npi_int_enb.s.q1_s_e = 1;
1747 npi_int_enb.s.pdf_p_f = 1;
1748 npi_int_enb.s.pdf_p_e = 1;
1749 npi_int_enb.s.pcf_p_f = 1;
1750 npi_int_enb.s.pcf_p_e = 1;
1751 npi_int_enb.s.rdx_s_e = 1;
1752 npi_int_enb.s.rwx_s_e = 1;
1753 npi_int_enb.s.pnc_a_f = 1;
1754 npi_int_enb.s.pnc_s_e = 1;
1755 npi_int_enb.s.com_a_f = 1;
1756 npi_int_enb.s.com_s_e = 1;
1757 npi_int_enb.s.q3_a_f = 1;
1758 npi_int_enb.s.q3_s_e = 1;
1759 npi_int_enb.s.q2_a_f = 1;
1760 npi_int_enb.s.q2_s_e = 1;
1761 npi_int_enb.s.pcr_a_f = 1;
1762 npi_int_enb.s.pcr_s_e = 1;
1763 npi_int_enb.s.fcr_a_f = 1;
1764 npi_int_enb.s.fcr_s_e = 1;
1765 npi_int_enb.s.iobdma = 1;
1766 npi_int_enb.s.p_dperr = 1;
1767 npi_int_enb.s.win_rto = 1;
1768 npi_int_enb.s.i3_pperr = 1;
1769 npi_int_enb.s.i2_pperr = 1;
1770 npi_int_enb.s.i1_pperr = 1;
1771 npi_int_enb.s.i0_pperr = 1;
1772 npi_int_enb.s.p3_ptout = 1;
1773 npi_int_enb.s.p2_ptout = 1;
1774 npi_int_enb.s.p1_ptout = 1;
1775 npi_int_enb.s.p0_ptout = 1;
1776 npi_int_enb.s.p3_pperr = 1;
1777 npi_int_enb.s.p2_pperr = 1;
1778 npi_int_enb.s.p1_pperr = 1;
1779 npi_int_enb.s.p0_pperr = 1;
1780 npi_int_enb.s.g3_rtout = 1;
1781 npi_int_enb.s.g2_rtout = 1;
1782 npi_int_enb.s.g1_rtout = 1;
1783 npi_int_enb.s.g0_rtout = 1;
1784 npi_int_enb.s.p3_perr = 1;
1785 npi_int_enb.s.p2_perr = 1;
1786 npi_int_enb.s.p1_perr = 1;
1787 npi_int_enb.s.p0_perr = 1;
1788 npi_int_enb.s.p3_rtout = 1;
1789 npi_int_enb.s.p2_rtout = 1;
1790 npi_int_enb.s.p1_rtout = 1;
1791 npi_int_enb.s.p0_rtout = 1;
1792 npi_int_enb.s.i3_overf = 1;
1793 npi_int_enb.s.i2_overf = 1;
1794 npi_int_enb.s.i1_overf = 1;
1795 npi_int_enb.s.i0_overf = 1;
1796 npi_int_enb.s.i3_rtout = 1;
1797 npi_int_enb.s.i2_rtout = 1;
1798 npi_int_enb.s.i1_rtout = 1;
1799 npi_int_enb.s.i0_rtout = 1;
1800 npi_int_enb.s.po3_2sml = 1;
1801 npi_int_enb.s.po2_2sml = 1;
1802 npi_int_enb.s.po1_2sml = 1;
1803 npi_int_enb.s.po0_2sml = 1;
1804 npi_int_enb.s.pci_rsl = 1;
1805 npi_int_enb.s.rml_wto = 1;
1806 npi_int_enb.s.rml_rto = 1;
1808 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
1810 // Skipping npi_int_enb.s.reserved_62_63
1811 npi_int_enb.s.q1_a_f = 1;
1812 npi_int_enb.s.q1_s_e = 1;
1813 npi_int_enb.s.pdf_p_f = 1;
1814 npi_int_enb.s.pdf_p_e = 1;
1815 npi_int_enb.s.pcf_p_f = 1;
1816 npi_int_enb.s.pcf_p_e = 1;
1817 npi_int_enb.s.rdx_s_e = 1;
1818 npi_int_enb.s.rwx_s_e = 1;
1819 npi_int_enb.s.pnc_a_f = 1;
1820 npi_int_enb.s.pnc_s_e = 1;
1821 npi_int_enb.s.com_a_f = 1;
1822 npi_int_enb.s.com_s_e = 1;
1823 npi_int_enb.s.q3_a_f = 1;
1824 npi_int_enb.s.q3_s_e = 1;
1825 npi_int_enb.s.q2_a_f = 1;
1826 npi_int_enb.s.q2_s_e = 1;
1827 npi_int_enb.s.pcr_a_f = 1;
1828 npi_int_enb.s.pcr_s_e = 1;
1829 npi_int_enb.s.fcr_a_f = 1;
1830 npi_int_enb.s.fcr_s_e = 1;
1831 npi_int_enb.s.iobdma = 1;
1832 npi_int_enb.s.p_dperr = 1;
1833 npi_int_enb.s.win_rto = 1;
1834 // Skipping npi_int_enb.s.reserved_37_38
1835 npi_int_enb.s.i1_pperr = 1;
1836 npi_int_enb.s.i0_pperr = 1;
1837 // Skipping npi_int_enb.s.reserved_33_34
1838 npi_int_enb.s.p1_ptout = 1;
1839 npi_int_enb.s.p0_ptout = 1;
1840 // Skipping npi_int_enb.s.reserved_29_30
1841 npi_int_enb.s.p1_pperr = 1;
1842 npi_int_enb.s.p0_pperr = 1;
1843 // Skipping npi_int_enb.s.reserved_25_26
1844 npi_int_enb.s.g1_rtout = 1;
1845 npi_int_enb.s.g0_rtout = 1;
1846 // Skipping npi_int_enb.s.reserved_21_22
1847 npi_int_enb.s.p1_perr = 1;
1848 npi_int_enb.s.p0_perr = 1;
1849 // Skipping npi_int_enb.s.reserved_17_18
1850 npi_int_enb.s.p1_rtout = 1;
1851 npi_int_enb.s.p0_rtout = 1;
1852 // Skipping npi_int_enb.s.reserved_13_14
1853 npi_int_enb.s.i1_overf = 1;
1854 npi_int_enb.s.i0_overf = 1;
1855 // Skipping npi_int_enb.s.reserved_9_10
1856 npi_int_enb.s.i1_rtout = 1;
1857 npi_int_enb.s.i0_rtout = 1;
1858 // Skipping npi_int_enb.s.reserved_5_6
1859 npi_int_enb.s.po1_2sml = 1;
1860 npi_int_enb.s.po0_2sml = 1;
1861 npi_int_enb.s.pci_rsl = 1;
1862 npi_int_enb.s.rml_wto = 1;
1863 npi_int_enb.s.rml_rto = 1;
1865 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
1867 // Skipping npi_int_enb.s.reserved_62_63
1868 npi_int_enb.s.q1_a_f = 1;
1869 npi_int_enb.s.q1_s_e = 1;
1870 npi_int_enb.s.pdf_p_f = 1;
1871 npi_int_enb.s.pdf_p_e = 1;
1872 npi_int_enb.s.pcf_p_f = 1;
1873 npi_int_enb.s.pcf_p_e = 1;
1874 npi_int_enb.s.rdx_s_e = 1;
1875 npi_int_enb.s.rwx_s_e = 1;
1876 npi_int_enb.s.pnc_a_f = 1;
1877 npi_int_enb.s.pnc_s_e = 1;
1878 npi_int_enb.s.com_a_f = 1;
1879 npi_int_enb.s.com_s_e = 1;
1880 npi_int_enb.s.q3_a_f = 1;
1881 npi_int_enb.s.q3_s_e = 1;
1882 npi_int_enb.s.q2_a_f = 1;
1883 npi_int_enb.s.q2_s_e = 1;
1884 npi_int_enb.s.pcr_a_f = 1;
1885 npi_int_enb.s.pcr_s_e = 1;
1886 npi_int_enb.s.fcr_a_f = 1;
1887 npi_int_enb.s.fcr_s_e = 1;
1888 npi_int_enb.s.iobdma = 1;
1889 npi_int_enb.s.p_dperr = 1;
1890 npi_int_enb.s.win_rto = 1;
1891 npi_int_enb.s.i3_pperr = 1;
1892 npi_int_enb.s.i2_pperr = 1;
1893 npi_int_enb.s.i1_pperr = 1;
1894 npi_int_enb.s.i0_pperr = 1;
1895 npi_int_enb.s.p3_ptout = 1;
1896 npi_int_enb.s.p2_ptout = 1;
1897 npi_int_enb.s.p1_ptout = 1;
1898 npi_int_enb.s.p0_ptout = 1;
1899 npi_int_enb.s.p3_pperr = 1;
1900 npi_int_enb.s.p2_pperr = 1;
1901 npi_int_enb.s.p1_pperr = 1;
1902 npi_int_enb.s.p0_pperr = 1;
1903 npi_int_enb.s.g3_rtout = 1;
1904 npi_int_enb.s.g2_rtout = 1;
1905 npi_int_enb.s.g1_rtout = 1;
1906 npi_int_enb.s.g0_rtout = 1;
1907 npi_int_enb.s.p3_perr = 1;
1908 npi_int_enb.s.p2_perr = 1;
1909 npi_int_enb.s.p1_perr = 1;
1910 npi_int_enb.s.p0_perr = 1;
1911 npi_int_enb.s.p3_rtout = 1;
1912 npi_int_enb.s.p2_rtout = 1;
1913 npi_int_enb.s.p1_rtout = 1;
1914 npi_int_enb.s.p0_rtout = 1;
1915 npi_int_enb.s.i3_overf = 1;
1916 npi_int_enb.s.i2_overf = 1;
1917 npi_int_enb.s.i1_overf = 1;
1918 npi_int_enb.s.i0_overf = 1;
1919 npi_int_enb.s.i3_rtout = 1;
1920 npi_int_enb.s.i2_rtout = 1;
1921 npi_int_enb.s.i1_rtout = 1;
1922 npi_int_enb.s.i0_rtout = 1;
1923 npi_int_enb.s.po3_2sml = 1;
1924 npi_int_enb.s.po2_2sml = 1;
1925 npi_int_enb.s.po1_2sml = 1;
1926 npi_int_enb.s.po0_2sml = 1;
1927 npi_int_enb.s.pci_rsl = 1;
1928 npi_int_enb.s.rml_wto = 1;
1929 npi_int_enb.s.rml_rto = 1;
1931 cvmx_write_csr(CVMX_NPI_INT_ENB, npi_int_enb.u64);
1932 __cvmx_interrupt_pci_int_enb2_enable();
1937 * __cvmx_interrupt_npi_int_sum_decode decodes all interrupt bits in cvmx_npi_int_sum_t
1939 void __cvmx_interrupt_npi_int_sum_decode(void)
1941 cvmx_npi_int_sum_t npi_int_sum;
1942 npi_int_sum.u64 = cvmx_read_csr(CVMX_NPI_INT_SUM);
1943 npi_int_sum.u64 &= cvmx_read_csr(CVMX_NPI_INT_ENB);
1944 cvmx_write_csr(CVMX_NPI_INT_SUM, npi_int_sum.u64);
1945 // Skipping npi_int_sum.s.reserved_62_63
1946 if (npi_int_sum.s.q1_a_f)
1947 PRINT_ERROR("NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"
1949 if (npi_int_sum.s.q1_s_e)
1950 PRINT_ERROR("NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"
1952 if (npi_int_sum.s.pdf_p_f)
1953 PRINT_ERROR("NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"
1955 if (npi_int_sum.s.pdf_p_e)
1956 PRINT_ERROR("NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"
1958 if (npi_int_sum.s.pcf_p_f)
1959 PRINT_ERROR("NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"
1961 if (npi_int_sum.s.pcf_p_e)
1962 PRINT_ERROR("NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"
1964 if (npi_int_sum.s.rdx_s_e)
1965 PRINT_ERROR("NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"
1967 if (npi_int_sum.s.rwx_s_e)
1968 PRINT_ERROR("NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"
1970 if (npi_int_sum.s.pnc_a_f)
1971 PRINT_ERROR("NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"
1973 if (npi_int_sum.s.pnc_s_e)
1974 PRINT_ERROR("NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"
1976 if (npi_int_sum.s.com_a_f)
1977 PRINT_ERROR("NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"
1979 if (npi_int_sum.s.com_s_e)
1980 PRINT_ERROR("NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"
1982 if (npi_int_sum.s.q3_a_f)
1983 PRINT_ERROR("NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"
1985 if (npi_int_sum.s.q3_s_e)
1986 PRINT_ERROR("NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"
1988 if (npi_int_sum.s.q2_a_f)
1989 PRINT_ERROR("NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"
1991 if (npi_int_sum.s.q2_s_e)
1992 PRINT_ERROR("NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"
1994 if (npi_int_sum.s.pcr_a_f)
1995 PRINT_ERROR("NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"
1997 if (npi_int_sum.s.pcr_s_e)
1998 PRINT_ERROR("NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"
2000 if (npi_int_sum.s.fcr_a_f)
2001 PRINT_ERROR("NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"
2003 if (npi_int_sum.s.fcr_s_e)
2004 PRINT_ERROR("NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"
2006 if (npi_int_sum.s.iobdma)
2007 PRINT_ERROR("NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n");
2008 if (npi_int_sum.s.p_dperr)
2009 PRINT_ERROR("NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
2010 " from the PCI this bit may be set.\n");
2011 if (npi_int_sum.s.win_rto)
2012 PRINT_ERROR("NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n");
2013 if (npi_int_sum.s.i3_pperr)
2014 PRINT_ERROR("NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
2015 " this bit may be set.\n");
2016 if (npi_int_sum.s.i2_pperr)
2017 PRINT_ERROR("NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
2018 " this bit may be set.\n");
2019 if (npi_int_sum.s.i1_pperr)
2020 PRINT_ERROR("NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
2021 " this bit may be set.\n");
2022 if (npi_int_sum.s.i0_pperr)
2023 PRINT_ERROR("NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
2024 " this bit may be set.\n");
2025 if (npi_int_sum.s.p3_ptout)
2026 PRINT_ERROR("NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
2028 if (npi_int_sum.s.p2_ptout)
2029 PRINT_ERROR("NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
2031 if (npi_int_sum.s.p1_ptout)
2032 PRINT_ERROR("NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
2034 if (npi_int_sum.s.p0_ptout)
2035 PRINT_ERROR("NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
2037 if (npi_int_sum.s.p3_pperr)
2038 PRINT_ERROR("NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
2039 " pointer-pair, this bit may be set.\n");
2040 if (npi_int_sum.s.p2_pperr)
2041 PRINT_ERROR("NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
2042 " pointer-pair, this bit may be set.\n");
2043 if (npi_int_sum.s.p1_pperr)
2044 PRINT_ERROR("NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
2045 " pointer-pair, this bit may be set.\n");
2046 if (npi_int_sum.s.p0_pperr)
2047 PRINT_ERROR("NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
2048 " pointer-pair, this bit may be set.\n");
2049 if (npi_int_sum.s.g3_rtout)
2050 PRINT_ERROR("NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
2051 " read a gather list.\n");
2052 if (npi_int_sum.s.g2_rtout)
2053 PRINT_ERROR("NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
2054 " read a gather list.\n");
2055 if (npi_int_sum.s.g1_rtout)
2056 PRINT_ERROR("NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
2057 " read a gather list.\n");
2058 if (npi_int_sum.s.g0_rtout)
2059 PRINT_ERROR("NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
2060 " read a gather list.\n");
2061 if (npi_int_sum.s.p3_perr)
2062 PRINT_ERROR("NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
2063 " data this bit may be set.\n");
2064 if (npi_int_sum.s.p2_perr)
2065 PRINT_ERROR("NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
2066 " data this bit may be set.\n");
2067 if (npi_int_sum.s.p1_perr)
2068 PRINT_ERROR("NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
2069 " data this bit may be set.\n");
2070 if (npi_int_sum.s.p0_perr)
2071 PRINT_ERROR("NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
2072 " data this bit may be set.\n");
2073 if (npi_int_sum.s.p3_rtout)
2074 PRINT_ERROR("NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
2075 " read packet data.\n");
2076 if (npi_int_sum.s.p2_rtout)
2077 PRINT_ERROR("NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
2078 " read packet data.\n");
2079 if (npi_int_sum.s.p1_rtout)
2080 PRINT_ERROR("NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
2081 " read packet data.\n");
2082 if (npi_int_sum.s.p0_rtout)
2083 PRINT_ERROR("NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
2084 " read packet data.\n");
2085 if (npi_int_sum.s.i3_overf)
2086 PRINT_ERROR("NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
2087 " doorbell count was set.\n");
2088 if (npi_int_sum.s.i2_overf)
2089 PRINT_ERROR("NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
2090 " doorbell count was set.\n");
2091 if (npi_int_sum.s.i1_overf)
2092 PRINT_ERROR("NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
2093 " doorbell count was set.\n");
2094 if (npi_int_sum.s.i0_overf)
2095 PRINT_ERROR("NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
2096 " doorbell count was set.\n");
2097 if (npi_int_sum.s.i3_rtout)
2098 PRINT_ERROR("NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
2099 " read instructions.\n");
2100 if (npi_int_sum.s.i2_rtout)
2101 PRINT_ERROR("NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
2102 " read instructions.\n");
2103 if (npi_int_sum.s.i1_rtout)
2104 PRINT_ERROR("NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
2105 " read instructions.\n");
2106 if (npi_int_sum.s.i0_rtout)
2107 PRINT_ERROR("NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
2108 " read instructions.\n");
2109 if (npi_int_sum.s.po3_2sml)
2110 PRINT_ERROR("NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
2111 " than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n");
2112 if (npi_int_sum.s.po2_2sml)
2113 PRINT_ERROR("NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
2114 " than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n");
2115 if (npi_int_sum.s.po1_2sml)
2116 PRINT_ERROR("NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
2117 " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n");
2118 if (npi_int_sum.s.po0_2sml)
2119 PRINT_ERROR("NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
2120 " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n");
2121 if (npi_int_sum.s.pci_rsl)
2124 PRINT_ERROR("NPI_INT_SUM[PCI_RSL]: This '1' when a bit in PCI_INT_SUM2 is SET and the\n"
2125 " corresponding bit in the PCI_INT_ENB2 is SET.\n");
2127 __cvmx_interrupt_pci_int_sum2_decode();
2129 if (npi_int_sum.s.rml_wto)
2130 PRINT_ERROR("NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
2131 " back from a RSL after sending a write command to\n"
2133 if (npi_int_sum.s.rml_rto)
2134 PRINT_ERROR("NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
2135 " back from a RSL after sending a read command to\n"
2141 * __cvmx_interrupt_pci_int_enb2_enable enables all interrupt bits in cvmx_pci_int_enb2_t
2143 void __cvmx_interrupt_pci_int_enb2_enable(void)
2145 cvmx_pci_int_enb2_t pci_int_enb2;
2146 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, cvmx_read_csr(CVMX_NPI_PCI_INT_SUM2));
2147 pci_int_enb2.u64 = 0;
2148 if (OCTEON_IS_MODEL(OCTEON_CN30XX))
2150 // Skipping pci_int_enb2.s.reserved_34_63
2151 pci_int_enb2.s.ill_rd = 1;
2152 pci_int_enb2.s.ill_wr = 1;
2153 pci_int_enb2.s.win_wr = 1;
2154 // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
2155 // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
2156 // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
2157 // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
2158 // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
2159 // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
2160 // Skipping pci_int_enb2.s.reserved_22_24
2161 // pci_int_enb2.s.rptime0 = 1; // Not an error condition
2162 // Skipping pci_int_enb2.s.reserved_18_20
2163 // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
2164 // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
2165 pci_int_enb2.s.ill_rrd = 1;
2166 pci_int_enb2.s.ill_rwr = 1;
2167 pci_int_enb2.s.rdperr = 1;
2168 pci_int_enb2.s.raperr = 1;
2169 pci_int_enb2.s.rserr = 1;
2170 pci_int_enb2.s.rtsr_abt = 1;
2171 pci_int_enb2.s.rmsc_msg = 1;
2172 pci_int_enb2.s.rmsi_mabt = 1;
2173 pci_int_enb2.s.rmsi_tabt = 1;
2174 pci_int_enb2.s.rmsi_per = 1;
2175 pci_int_enb2.s.rmr_tto = 1;
2176 pci_int_enb2.s.rmr_abt = 1;
2177 pci_int_enb2.s.rtr_abt = 1;
2178 pci_int_enb2.s.rmr_wtto = 1;
2179 pci_int_enb2.s.rmr_wabt = 1;
2180 pci_int_enb2.s.rtr_wabt = 1;
2182 if (OCTEON_IS_MODEL(OCTEON_CN50XX))
2184 // Skipping pci_int_enb2.s.reserved_34_63
2185 pci_int_enb2.s.ill_rd = 1;
2186 pci_int_enb2.s.ill_wr = 1;
2187 pci_int_enb2.s.win_wr = 1;
2188 // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
2189 // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
2190 // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
2191 // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
2192 // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
2193 // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
2194 // Skipping pci_int_enb2.s.reserved_23_24
2195 // pci_int_enb2.s.rptime1 = 1; // Not an error condition
2196 // pci_int_enb2.s.rptime0 = 1; // Not an error condition
2197 // Skipping pci_int_enb2.s.reserved_19_20
2198 // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
2199 // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
2200 // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
2201 pci_int_enb2.s.ill_rrd = 1;
2202 pci_int_enb2.s.ill_rwr = 1;
2203 pci_int_enb2.s.rdperr = 1;
2204 pci_int_enb2.s.raperr = 1;
2205 pci_int_enb2.s.rserr = 1;
2206 pci_int_enb2.s.rtsr_abt = 1;
2207 pci_int_enb2.s.rmsc_msg = 1;
2208 pci_int_enb2.s.rmsi_mabt = 1;
2209 pci_int_enb2.s.rmsi_tabt = 1;
2210 pci_int_enb2.s.rmsi_per = 1;
2211 pci_int_enb2.s.rmr_tto = 1;
2212 pci_int_enb2.s.rmr_abt = 1;
2213 pci_int_enb2.s.rtr_abt = 1;
2214 pci_int_enb2.s.rmr_wtto = 1;
2215 pci_int_enb2.s.rmr_wabt = 1;
2216 pci_int_enb2.s.rtr_wabt = 1;
2218 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
2220 // Skipping pci_int_enb2.s.reserved_34_63
2221 pci_int_enb2.s.ill_rd = 1;
2222 pci_int_enb2.s.ill_wr = 1;
2223 pci_int_enb2.s.win_wr = 1;
2224 // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
2225 // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
2226 // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
2227 // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
2228 // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
2229 // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
2230 // pci_int_enb2.s.rptime3 = 1; // Not an error condition
2231 // pci_int_enb2.s.rptime2 = 1; // Not an error condition
2232 // pci_int_enb2.s.rptime1 = 1; // Not an error condition
2233 // pci_int_enb2.s.rptime0 = 1; // Not an error condition
2234 // pci_int_enb2.s.rpcnt3 = 1; // Not an error condition
2235 // pci_int_enb2.s.rpcnt2 = 1; // Not an error condition
2236 // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
2237 // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
2238 // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
2239 pci_int_enb2.s.ill_rrd = 1;
2240 pci_int_enb2.s.ill_rwr = 1;
2241 pci_int_enb2.s.rdperr = 1;
2242 pci_int_enb2.s.raperr = 1;
2243 pci_int_enb2.s.rserr = 1;
2244 pci_int_enb2.s.rtsr_abt = 1;
2245 pci_int_enb2.s.rmsc_msg = 1;
2246 pci_int_enb2.s.rmsi_mabt = 1;
2247 pci_int_enb2.s.rmsi_tabt = 1;
2248 pci_int_enb2.s.rmsi_per = 1;
2249 pci_int_enb2.s.rmr_tto = 1;
2250 pci_int_enb2.s.rmr_abt = 1;
2251 pci_int_enb2.s.rtr_abt = 1;
2252 pci_int_enb2.s.rmr_wtto = 1;
2253 pci_int_enb2.s.rmr_wabt = 1;
2254 pci_int_enb2.s.rtr_wabt = 1;
2256 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
2258 // Skipping pci_int_enb2.s.reserved_34_63
2259 pci_int_enb2.s.ill_rd = 1;
2260 pci_int_enb2.s.ill_wr = 1;
2261 pci_int_enb2.s.win_wr = 1;
2262 // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
2263 // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
2264 // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
2265 // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
2266 // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
2267 // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
2268 // Skipping pci_int_enb2.s.reserved_23_24
2269 // pci_int_enb2.s.rptime1 = 1; // Not an error condition
2270 // pci_int_enb2.s.rptime0 = 1; // Not an error condition
2271 // Skipping pci_int_enb2.s.reserved_19_20
2272 // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
2273 // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
2274 // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
2275 pci_int_enb2.s.ill_rrd = 1;
2276 pci_int_enb2.s.ill_rwr = 1;
2277 pci_int_enb2.s.rdperr = 1;
2278 pci_int_enb2.s.raperr = 1;
2279 pci_int_enb2.s.rserr = 1;
2280 pci_int_enb2.s.rtsr_abt = 1;
2281 pci_int_enb2.s.rmsc_msg = 1;
2282 pci_int_enb2.s.rmsi_mabt = 1;
2283 pci_int_enb2.s.rmsi_tabt = 1;
2284 pci_int_enb2.s.rmsi_per = 1;
2285 pci_int_enb2.s.rmr_tto = 1;
2286 pci_int_enb2.s.rmr_abt = 1;
2287 pci_int_enb2.s.rtr_abt = 1;
2288 pci_int_enb2.s.rmr_wtto = 1;
2289 pci_int_enb2.s.rmr_wabt = 1;
2290 pci_int_enb2.s.rtr_wabt = 1;
2292 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
2294 // Skipping pci_int_enb2.s.reserved_34_63
2295 pci_int_enb2.s.ill_rd = 1;
2296 pci_int_enb2.s.ill_wr = 1;
2297 pci_int_enb2.s.win_wr = 1;
2298 // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
2299 // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
2300 // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
2301 // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
2302 // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
2303 // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
2304 // pci_int_enb2.s.rptime3 = 1; // Not an error condition
2305 // pci_int_enb2.s.rptime2 = 1; // Not an error condition
2306 // pci_int_enb2.s.rptime1 = 1; // Not an error condition
2307 // pci_int_enb2.s.rptime0 = 1; // Not an error condition
2308 // pci_int_enb2.s.rpcnt3 = 1; // Not an error condition
2309 // pci_int_enb2.s.rpcnt2 = 1; // Not an error condition
2310 // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
2311 // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
2312 // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
2313 pci_int_enb2.s.ill_rrd = 1;
2314 pci_int_enb2.s.ill_rwr = 1;
2315 pci_int_enb2.s.rdperr = 1;
2316 pci_int_enb2.s.raperr = 1;
2317 pci_int_enb2.s.rserr = 1;
2318 pci_int_enb2.s.rtsr_abt = 1;
2319 pci_int_enb2.s.rmsc_msg = 1;
2320 pci_int_enb2.s.rmsi_mabt = 1;
2321 pci_int_enb2.s.rmsi_tabt = 1;
2322 pci_int_enb2.s.rmsi_per = 1;
2323 pci_int_enb2.s.rmr_tto = 1;
2324 pci_int_enb2.s.rmr_abt = 1;
2325 pci_int_enb2.s.rtr_abt = 1;
2326 pci_int_enb2.s.rmr_wtto = 1;
2327 pci_int_enb2.s.rmr_wabt = 1;
2328 pci_int_enb2.s.rtr_wabt = 1;
2330 cvmx_write_csr(CVMX_NPI_PCI_INT_ENB2, pci_int_enb2.u64);
2335 * __cvmx_interrupt_pci_int_sum2_decode decodes all interrupt bits in cvmx_pci_int_sum2_t
2337 void __cvmx_interrupt_pci_int_sum2_decode(void)
2339 cvmx_pci_int_sum2_t pci_int_sum2;
2340 pci_int_sum2.u64 = cvmx_read_csr(CVMX_NPI_PCI_INT_SUM2);
2341 pci_int_sum2.u64 &= cvmx_read_csr(CVMX_NPI_PCI_INT_ENB2);
2342 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, pci_int_sum2.u64);
2343 // Skipping pci_int_sum2.s.reserved_34_63
2344 if (pci_int_sum2.s.ill_rd)
2345 PRINT_ERROR("PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
2346 " when the mem area is disabled.\n");
2347 if (pci_int_sum2.s.ill_wr)
2348 PRINT_ERROR("PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
2349 " when the mem area is disabled.\n");
2350 if (pci_int_sum2.s.win_wr)
2351 PRINT_ERROR("PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
2352 " Read-Address Register took place.\n");
2353 if (pci_int_sum2.s.dma1_fi)
2354 PRINT_ERROR("PCI_INT_SUM2[DMA1_FI]: A DMA operation operation finished that was\n"
2355 " required to set the FORCE-INT bit for counter 1.\n");
2356 if (pci_int_sum2.s.dma0_fi)
2357 PRINT_ERROR("PCI_INT_SUM2[DMA0_FI]: A DMA operation operation finished that was\n"
2358 " required to set the FORCE-INT bit for counter 0.\n");
2359 if (pci_int_sum2.s.dtime1)
2360 PRINT_ERROR("PCI_INT_SUM2[DTIME1]: When the value in the PCI_DMA_CNT1\n"
2361 " register is not 0 the DMA_CNT1 timer counts.\n"
2362 " When the DMA1_CNT timer has a value greater\n"
2363 " than the PCI_DMA_TIME1 register this\n"
2364 " bit is set. The timer is reset when bit is\n"
2365 " written with a one.\n");
2366 if (pci_int_sum2.s.dtime0)
2367 PRINT_ERROR("PCI_INT_SUM2[DTIME0]: When the value in the PCI_DMA_CNT0\n"
2368 " register is not 0 the DMA_CNT0 timer counts.\n"
2369 " When the DMA0_CNT timer has a value greater\n"
2370 " than the PCI_DMA_TIME0 register this\n"
2371 " bit is set. The timer is reset when bit is\n"
2372 " written with a one.\n");
2373 if (pci_int_sum2.s.dcnt1)
2374 PRINT_ERROR("PCI_INT_SUM2[DCNT1]: This bit indicates that PCI_DMA_CNT1\n"
2375 " value is greater than the value\n"
2376 " in the PCI_DMA_INT_LEV1 register.\n");
2377 if (pci_int_sum2.s.dcnt0)
2378 PRINT_ERROR("PCI_INT_SUM2[DCNT0]: This bit indicates that PCI_DMA_CNT0\n"
2379 " value is greater than the value\n"
2380 " in the PCI_DMA_INT_LEV0 register.\n");
2381 if (pci_int_sum2.s.ptime3)
2382 PRINT_ERROR("PCI_INT_SUM2[PTIME3]: When the value in the PCI_PKTS_SENT3\n"
2383 " register is not 0 the Sent-3 timer counts.\n"
2384 " When the Sent-3 timer has a value greater\n"
2385 " than the PCI_PKTS_SENT_TIME3 register this\n"
2386 " bit is set. The timer is reset when bit is\n"
2387 " written with a one.\n");
2388 if (pci_int_sum2.s.ptime2)
2389 PRINT_ERROR("PCI_INT_SUM2[PTIME2]: When the value in the PCI_PKTS_SENT2\n"
2390 " register is not 0 the Sent-2 timer counts.\n"
2391 " When the Sent-2 timer has a value greater\n"
2392 " than the PCI_PKTS_SENT_TIME2 register this\n"
2393 " bit is set. The timer is reset when bit is\n"
2394 " written with a one.\n");
2395 if (pci_int_sum2.s.ptime1)
2396 PRINT_ERROR("PCI_INT_SUM2[PTIME1]: When the value in the PCI_PKTS_SENT1\n"
2397 " register is not 0 the Sent-1 timer counts.\n"
2398 " When the Sent-1 timer has a value greater\n"
2399 " than the PCI_PKTS_SENT_TIME1 register this\n"
2400 " bit is set. The timer is reset when bit is\n"
2401 " written with a one.\n");
2402 if (pci_int_sum2.s.ptime0)
2403 PRINT_ERROR("PCI_INT_SUM2[PTIME0]: When the value in the PCI_PKTS_SENT0\n"
2404 " register is not 0 the Sent-0 timer counts.\n"
2405 " When the Sent-0 timer has a value greater\n"
2406 " than the PCI_PKTS_SENT_TIME0 register this\n"
2407 " bit is set. The timer is reset when bit is\n"
2408 " written with a one.\n");
2409 if (pci_int_sum2.s.pcnt3)
2410 PRINT_ERROR("PCI_INT_SUM2[PCNT3]: This bit indicates that PCI_PKTS_SENT3\n"
2411 " value is greater than the value\n"
2412 " in the PCI_PKTS_SENT_INT_LEV3 register.\n");
2413 if (pci_int_sum2.s.pcnt2)
2414 PRINT_ERROR("PCI_INT_SUM2[PCNT2]: This bit indicates that PCI_PKTS_SENT2\n"
2415 " value is greater than the value\n"
2416 " in the PCI_PKTS_SENT_INT_LEV2 register.\n");
2417 if (pci_int_sum2.s.pcnt1)
2418 PRINT_ERROR("PCI_INT_SUM2[PCNT1]: This bit indicates that PCI_PKTS_SENT1\n"
2419 " value is greater than the value\n"
2420 " in the PCI_PKTS_SENT_INT_LEV1 register.\n");
2421 if (pci_int_sum2.s.pcnt0)
2422 PRINT_ERROR("PCI_INT_SUM2[PCNT0]: This bit indicates that PCI_PKTS_SENT0\n"
2423 " value is greater than the value\n"
2424 " in the PCI_PKTS_SENT_INT_LEV0 register.\n");
2425 if (pci_int_sum2.s.rsl_int)
2426 PRINT_ERROR("PCI_INT_SUM2[RSL_INT]: This bit is set when the RSL Chain has\n"
2427 " generated an interrupt.\n");
2428 if (pci_int_sum2.s.ill_rrd)
2429 PRINT_ERROR("PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n");
2430 if (pci_int_sum2.s.ill_rwr)
2431 PRINT_ERROR("PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n");
2432 if (pci_int_sum2.s.dperr)
2433 PRINT_ERROR("PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n");
2434 if (pci_int_sum2.s.aperr)
2435 PRINT_ERROR("PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n");
2436 if (pci_int_sum2.s.serr)
2437 PRINT_ERROR("PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n");
2438 if (pci_int_sum2.s.tsr_abt)
2439 PRINT_ERROR("PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n");
2440 if (pci_int_sum2.s.msc_msg)
2441 PRINT_ERROR("PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n");
2442 if (pci_int_sum2.s.msi_mabt)
2443 PRINT_ERROR("PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n");
2444 if (pci_int_sum2.s.msi_tabt)
2445 PRINT_ERROR("PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n");
2446 if (pci_int_sum2.s.msi_per)
2447 PRINT_ERROR("PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n");
2448 if (pci_int_sum2.s.mr_tto)
2449 PRINT_ERROR("PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n");
2450 if (pci_int_sum2.s.mr_abt)
2451 PRINT_ERROR("PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n");
2452 if (pci_int_sum2.s.tr_abt)
2453 PRINT_ERROR("PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n");
2454 if (pci_int_sum2.s.mr_wtto)
2455 PRINT_ERROR("PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n");
2456 if (pci_int_sum2.s.mr_wabt)
2457 PRINT_ERROR("PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n");
2458 if (pci_int_sum2.s.tr_wabt)
2459 PRINT_ERROR("PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n");
2464 * __cvmx_interrupt_pcsx_intx_en_reg_enable enables all interrupt bits in cvmx_pcsx_intx_en_reg_t
2466 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block)
2468 cvmx_pcsx_intx_en_reg_t pcs_int_en_reg;
2469 cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block)));
2470 pcs_int_en_reg.u64 = 0;
2471 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
2473 // Skipping pcs_int_en_reg.s.reserved_12_63
2474 //pcs_int_en_reg.s.dup = 1; // This happens during normal operation
2475 pcs_int_en_reg.s.sync_bad_en = 1;
2476 pcs_int_en_reg.s.an_bad_en = 1;
2477 pcs_int_en_reg.s.rxlock_en = 1;
2478 pcs_int_en_reg.s.rxbad_en = 1;
2479 //pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation
2480 pcs_int_en_reg.s.txbad_en = 1;
2481 pcs_int_en_reg.s.txfifo_en = 1;
2482 pcs_int_en_reg.s.txfifu_en = 1;
2483 pcs_int_en_reg.s.an_err_en = 1;
2484 //pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation
2485 //pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation
2487 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
2489 // Skipping pcs_int_en_reg.s.reserved_12_63
2490 //pcs_int_en_reg.s.dup = 1; // This happens during normal operation
2491 pcs_int_en_reg.s.sync_bad_en = 1;
2492 pcs_int_en_reg.s.an_bad_en = 1;
2493 pcs_int_en_reg.s.rxlock_en = 1;
2494 pcs_int_en_reg.s.rxbad_en = 1;
2495 //pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation
2496 pcs_int_en_reg.s.txbad_en = 1;
2497 pcs_int_en_reg.s.txfifo_en = 1;
2498 pcs_int_en_reg.s.txfifu_en = 1;
2499 pcs_int_en_reg.s.an_err_en = 1;
2500 //pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation
2501 //pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation
2503 cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64);
2508 * __cvmx_interrupt_pcsx_intx_reg_decode decodes all interrupt bits in cvmx_pcsx_intx_reg_t
2510 void __cvmx_interrupt_pcsx_intx_reg_decode(int index, int block)
2512 cvmx_pcsx_intx_reg_t pcs_int_reg;
2513 pcs_int_reg.u64 = cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block));
2514 pcs_int_reg.u64 &= cvmx_read_csr(CVMX_PCSX_INTX_EN_REG(index, block));
2515 cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), pcs_int_reg.u64);
2516 // Skipping pcs_int_reg.s.reserved_12_63
2517 if (pcs_int_reg.s.dup)
2518 PRINT_ERROR("PCS%d_INT%d_REG[DUP]: Set whenever Duplex mode changes on the link\n", block, index);
2519 if (pcs_int_reg.s.sync_bad)
2520 PRINT_ERROR("PCS%d_INT%d_REG[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
2521 " state. Should never be set during normal operation\n", block, index);
2522 if (pcs_int_reg.s.an_bad)
2523 PRINT_ERROR("PCS%d_INT%d_REG[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
2524 " state. Should never be set during normal operation\n", block, index);
2525 if (pcs_int_reg.s.rxlock)
2526 PRINT_ERROR("PCS%d_INT%d_REG[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
2528 " Cannot fire in loopback1 mode\n", block, index);
2529 if (pcs_int_reg.s.rxbad)
2530 PRINT_ERROR("PCS%d_INT%d_REG[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
2531 " state. Should never be set during normal operation\n", block, index);
2532 if (pcs_int_reg.s.rxerr)
2533 PRINT_ERROR("PCS%d_INT%d_REG[RXERR]: Set whenever RX receives a code group error in\n"
2534 " 10 bit to 8 bit decode logic\n"
2535 " Cannot fire in loopback1 mode\n", block, index);
2536 if (pcs_int_reg.s.txbad)
2537 PRINT_ERROR("PCS%d_INT%d_REG[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
2538 " state. Should never be set during normal operation\n", block, index);
2539 if (pcs_int_reg.s.txfifo)
2540 PRINT_ERROR("PCS%d_INT%d_REG[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
2541 " condition\n", block, index);
2542 if (pcs_int_reg.s.txfifu)
2543 PRINT_ERROR("PCS%d_INT%d_REG[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
2544 " condition\n", block, index);
2545 if (pcs_int_reg.s.an_err)
2546 PRINT_ERROR("PCS%d_INT%d_REG[AN_ERR]: AN Error, AN resolution function failed\n", block, index);
2547 if (pcs_int_reg.s.xmit)
2548 PRINT_ERROR("PCS%d_INT%d_REG[XMIT]: Set whenever HW detects a change in the XMIT\n"
2549 " variable. XMIT variable states are IDLE, CONFIG and\n"
2550 " DATA\n", block, index);
2551 if (pcs_int_reg.s.lnkspd)
2552 PRINT_ERROR("PCS%d_INT%d_REG[LNKSPD]: Set by HW whenever Link Speed has changed\n", block, index);
2557 * __cvmx_interrupt_pcsxx_int_en_reg_enable enables all interrupt bits in cvmx_pcsxx_int_en_reg_t
2559 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index)
2561 cvmx_pcsxx_int_en_reg_t pcsx_int_en_reg;
2562 cvmx_write_csr(CVMX_PCSXX_INT_REG(index), cvmx_read_csr(CVMX_PCSXX_INT_REG(index)));
2563 pcsx_int_en_reg.u64 = 0;
2564 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
2566 // Skipping pcsx_int_en_reg.s.reserved_6_63
2567 pcsx_int_en_reg.s.algnlos_en = 1;
2568 pcsx_int_en_reg.s.synlos_en = 1;
2569 pcsx_int_en_reg.s.bitlckls_en = 1;
2570 pcsx_int_en_reg.s.rxsynbad_en = 1;
2571 pcsx_int_en_reg.s.rxbad_en = 1;
2572 pcsx_int_en_reg.s.txflt_en = 1;
2574 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
2576 // Skipping pcsx_int_en_reg.s.reserved_6_63
2577 pcsx_int_en_reg.s.algnlos_en = 1;
2578 pcsx_int_en_reg.s.synlos_en = 1;
2579 pcsx_int_en_reg.s.bitlckls_en = 0; // Happens if XAUI module is not installed
2580 pcsx_int_en_reg.s.rxsynbad_en = 1;
2581 pcsx_int_en_reg.s.rxbad_en = 1;
2582 pcsx_int_en_reg.s.txflt_en = 1;
2584 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64);
2589 * __cvmx_interrupt_pcsxx_int_reg_decode decodes all interrupt bits in cvmx_pcsxx_int_reg_t
2591 void __cvmx_interrupt_pcsxx_int_reg_decode(int index)
2593 cvmx_pcsxx_int_reg_t pcsx_int_reg;
2594 pcsx_int_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_REG(index));
2595 pcsx_int_reg.u64 &= cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(index));
2596 cvmx_write_csr(CVMX_PCSXX_INT_REG(index), pcsx_int_reg.u64);
2597 // Skipping pcsx_int_reg.s.reserved_6_63
2598 if (pcsx_int_reg.s.algnlos)
2599 PRINT_ERROR("PCSX%d_INT_REG[ALGNLOS]: Set when XAUI lanes lose alignment\n", index);
2600 if (pcsx_int_reg.s.synlos)
2601 PRINT_ERROR("PCSX%d_INT_REG[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n", index);
2602 if (pcsx_int_reg.s.bitlckls)
2603 PRINT_ERROR("PCSX%d_INT_REG[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n", index);
2604 if (pcsx_int_reg.s.rxsynbad)
2605 PRINT_ERROR("PCSX%d_INT_REG[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
2606 " in one of the 4 xaui lanes\n", index);
2607 if (pcsx_int_reg.s.rxbad)
2608 PRINT_ERROR("PCSX%d_INT_REG[RXBAD]: Set when RX state machine in bad state\n", index);
2609 if (pcsx_int_reg.s.txflt)
2610 PRINT_ERROR("PCSX%d_INT_REG[TXFLT]: None defined at this time, always 0x0\n", index);
2615 * __cvmx_interrupt_pescx_dbg_info_en_enable enables all interrupt bits in cvmx_pescx_dbg_info_en_t
2617 void __cvmx_interrupt_pescx_dbg_info_en_enable(int index)
2619 cvmx_pescx_dbg_info_en_t pesc_dbg_info_en;
2620 cvmx_write_csr(CVMX_PESCX_DBG_INFO(index), cvmx_read_csr(CVMX_PESCX_DBG_INFO(index)));
2621 pesc_dbg_info_en.u64 = 0;
2622 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
2624 // Skipping pesc_dbg_info_en.s.reserved_31_63
2625 pesc_dbg_info_en.s.ecrc_e = 1;
2626 pesc_dbg_info_en.s.rawwpp = 1;
2627 pesc_dbg_info_en.s.racpp = 1;
2628 pesc_dbg_info_en.s.ramtlp = 1;
2629 pesc_dbg_info_en.s.rarwdns = 1;
2630 pesc_dbg_info_en.s.caar = 1;
2631 pesc_dbg_info_en.s.racca = 1;
2632 pesc_dbg_info_en.s.racur = 1;
2633 pesc_dbg_info_en.s.rauc = 1;
2634 pesc_dbg_info_en.s.rqo = 1;
2635 pesc_dbg_info_en.s.fcuv = 1;
2636 pesc_dbg_info_en.s.rpe = 1;
2637 pesc_dbg_info_en.s.fcpvwt = 1;
2638 pesc_dbg_info_en.s.dpeoosd = 1;
2639 pesc_dbg_info_en.s.rtwdle = 1;
2640 pesc_dbg_info_en.s.rdwdle = 1;
2641 pesc_dbg_info_en.s.mre = 1;
2642 pesc_dbg_info_en.s.rte = 1;
2643 pesc_dbg_info_en.s.acto = 1;
2644 pesc_dbg_info_en.s.rvdm = 1;
2645 pesc_dbg_info_en.s.rumep = 1;
2646 pesc_dbg_info_en.s.rptamrc = 1;
2647 pesc_dbg_info_en.s.rpmerc = 1;
2648 pesc_dbg_info_en.s.rfemrc = 1;
2649 pesc_dbg_info_en.s.rnfemrc = 1;
2650 pesc_dbg_info_en.s.rcemrc = 1;
2651 pesc_dbg_info_en.s.rpoison = 1;
2652 pesc_dbg_info_en.s.recrce = 1;
2653 pesc_dbg_info_en.s.rtlplle = 1;
2655 /* RTLPMAL is disabled since it will be generated under normal conditions,
2656 like devices causing legacy PCI interrupts */
2657 pesc_dbg_info_en.s.rtlpmal = 1;
2659 pesc_dbg_info_en.s.spoison = 1;
2661 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
2663 // Skipping pesc_dbg_info_en.s.reserved_31_63
2664 pesc_dbg_info_en.s.ecrc_e = 1;
2665 pesc_dbg_info_en.s.rawwpp = 1;
2666 pesc_dbg_info_en.s.racpp = 1;
2667 pesc_dbg_info_en.s.ramtlp = 1;
2668 pesc_dbg_info_en.s.rarwdns = 1;
2669 pesc_dbg_info_en.s.caar = 1;
2670 pesc_dbg_info_en.s.racca = 1;
2671 pesc_dbg_info_en.s.racur = 1;
2672 pesc_dbg_info_en.s.rauc = 1;
2673 pesc_dbg_info_en.s.rqo = 1;
2674 pesc_dbg_info_en.s.fcuv = 1;
2675 pesc_dbg_info_en.s.rpe = 1;
2676 pesc_dbg_info_en.s.fcpvwt = 1;
2677 pesc_dbg_info_en.s.dpeoosd = 1;
2678 pesc_dbg_info_en.s.rtwdle = 1;
2679 pesc_dbg_info_en.s.rdwdle = 1;
2680 pesc_dbg_info_en.s.mre = 1;
2681 pesc_dbg_info_en.s.rte = 1;
2682 pesc_dbg_info_en.s.acto = 1;
2683 pesc_dbg_info_en.s.rvdm = 1;
2684 pesc_dbg_info_en.s.rumep = 1;
2685 pesc_dbg_info_en.s.rptamrc = 1;
2686 pesc_dbg_info_en.s.rpmerc = 1;
2687 pesc_dbg_info_en.s.rfemrc = 1;
2688 pesc_dbg_info_en.s.rnfemrc = 1;
2689 pesc_dbg_info_en.s.rcemrc = 1;
2690 pesc_dbg_info_en.s.rpoison = 1;
2691 pesc_dbg_info_en.s.recrce = 1;
2692 pesc_dbg_info_en.s.rtlplle = 1;
2694 /* RTLPMAL is disabled since it will be generated under normal conditions,
2695 like devices causing legacy PCI interrupts */
2696 pesc_dbg_info_en.s.rtlpmal = 1;
2698 pesc_dbg_info_en.s.spoison = 1;
2700 cvmx_write_csr(CVMX_PESCX_DBG_INFO_EN(index), pesc_dbg_info_en.u64);
2705 * __cvmx_interrupt_pescx_dbg_info_decode decodes all interrupt bits in cvmx_pescx_dbg_info_t
2707 void __cvmx_interrupt_pescx_dbg_info_decode(int index)
2709 cvmx_pescx_dbg_info_t pesc_dbg_info;
2710 pesc_dbg_info.u64 = cvmx_read_csr(CVMX_PESCX_DBG_INFO(index));
2711 pesc_dbg_info.u64 &= cvmx_read_csr(CVMX_PESCX_DBG_INFO_EN(index));
2712 cvmx_write_csr(CVMX_PESCX_DBG_INFO(index), pesc_dbg_info.u64);
2713 // Skipping pesc_dbg_info.s.reserved_31_63
2714 if (pesc_dbg_info.s.ecrc_e)
2715 PRINT_ERROR("PESC%d_DBG_INFO[ECRC_E]: Received a ECRC error.\n"
2716 " radm_ecrc_err\n", index);
2717 if (pesc_dbg_info.s.rawwpp)
2718 PRINT_ERROR("PESC%d_DBG_INFO[RAWWPP]: Received a write with poisoned payload\n"
2719 " radm_rcvd_wreq_poisoned\n", index);
2720 if (pesc_dbg_info.s.racpp)
2721 PRINT_ERROR("PESC%d_DBG_INFO[RACPP]: Received a completion with poisoned payload\n"
2722 " radm_rcvd_cpl_poisoned\n", index);
2723 if (pesc_dbg_info.s.ramtlp)
2724 PRINT_ERROR("PESC%d_DBG_INFO[RAMTLP]: Received a malformed TLP\n"
2725 " radm_mlf_tlp_err\n", index);
2726 if (pesc_dbg_info.s.rarwdns)
2727 PRINT_ERROR("PESC%d_DBG_INFO[RARWDNS]: Recieved a request which device does not support\n"
2728 " radm_rcvd_ur_req\n", index);
2729 if (pesc_dbg_info.s.caar)
2730 PRINT_ERROR("PESC%d_DBG_INFO[CAAR]: Completer aborted a request\n"
2731 " radm_rcvd_ca_req\n"
2732 " This bit will never be set because Octeon does\n"
2733 " not generate Completer Aborts.\n", index);
2734 if (pesc_dbg_info.s.racca)
2735 PRINT_ERROR("PESC%d_DBG_INFO[RACCA]: Received a completion with CA status\n"
2736 " radm_rcvd_cpl_ca\n", index);
2737 if (pesc_dbg_info.s.racur)
2738 PRINT_ERROR("PESC%d_DBG_INFO[RACUR]: Received a completion with UR status\n"
2739 " radm_rcvd_cpl_ur\n", index);
2740 if (pesc_dbg_info.s.rauc)
2741 PRINT_ERROR("PESC%d_DBG_INFO[RAUC]: Received an unexpected completion\n"
2742 " radm_unexp_cpl_err\n", index);
2743 if (pesc_dbg_info.s.rqo)
2744 PRINT_ERROR("PESC%d_DBG_INFO[RQO]: Receive queue overflow. Normally happens only when\n"
2745 " flow control advertisements are ignored\n"
2746 " radm_qoverflow\n", index);
2747 if (pesc_dbg_info.s.fcuv)
2748 PRINT_ERROR("PESC%d_DBG_INFO[FCUV]: Flow Control Update Violation (opt. checks)\n"
2749 " int_xadm_fc_prot_err\n", index);
2750 if (pesc_dbg_info.s.rpe)
2751 PRINT_ERROR("PESC%d_DBG_INFO[RPE]: When the PHY reports 8B/10B decode error\n"
2752 " (RxStatus = 3b100) or disparity error\n"
2753 " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
2755 " rmlh_rcvd_err\n", index);
2756 if (pesc_dbg_info.s.fcpvwt)
2757 PRINT_ERROR("PESC%d_DBG_INFO[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
2758 " rtlh_fc_prot_err\n", index);
2759 if (pesc_dbg_info.s.dpeoosd)
2760 PRINT_ERROR("PESC%d_DBG_INFO[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
2761 " rdlh_prot_err\n", index);
2762 if (pesc_dbg_info.s.rtwdle)
2763 PRINT_ERROR("PESC%d_DBG_INFO[RTWDLE]: Received TLP with DataLink Layer Error\n"
2764 " rdlh_bad_tlp_err\n", index);
2765 if (pesc_dbg_info.s.rdwdle)
2766 PRINT_ERROR("PESC%d_DBG_INFO[RDWDLE]: Received DLLP with DataLink Layer Error\n"
2767 " rdlh_bad_dllp_err\n", index);
2768 if (pesc_dbg_info.s.mre)
2769 PRINT_ERROR("PESC%d_DBG_INFO[MRE]: Max Retries Exceeded\n"
2770 " xdlh_replay_num_rlover_err\n", index);
2771 if (pesc_dbg_info.s.rte)
2772 PRINT_ERROR("PESC%d_DBG_INFO[RTE]: Replay Timer Expired\n"
2773 " xdlh_replay_timeout_err\n"
2774 " This bit is set when the REPLAY_TIMER expires in\n"
2775 " the PCIE core. The probability of this bit being\n"
2776 " set will increase with the traffic load.\n", index);
2777 if (pesc_dbg_info.s.acto)
2778 PRINT_ERROR("PESC%d_DBG_INFO[ACTO]: A Completion Timeout Occured\n"
2779 " pedc_radm_cpl_timeout\n", index);
2780 if (pesc_dbg_info.s.rvdm)
2781 PRINT_ERROR("PESC%d_DBG_INFO[RVDM]: Received Vendor-Defined Message\n"
2782 " pedc_radm_vendor_msg\n", index);
2783 if (pesc_dbg_info.s.rumep)
2784 PRINT_ERROR("PESC%d_DBG_INFO[RUMEP]: Received Unlock Message (EP Mode Only)\n"
2785 " pedc_radm_msg_unlock\n", index);
2786 if (pesc_dbg_info.s.rptamrc)
2787 PRINT_ERROR("PESC%d_DBG_INFO[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
2789 " pedc_radm_pm_to_ack\n", index);
2790 if (pesc_dbg_info.s.rpmerc)
2791 PRINT_ERROR("PESC%d_DBG_INFO[RPMERC]: Received PME Message (RC Mode only)\n"
2792 " pedc_radm_pm_pme\n", index);
2793 if (pesc_dbg_info.s.rfemrc)
2794 PRINT_ERROR("PESC%d_DBG_INFO[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
2795 " pedc_radm_fatal_err\n"
2796 " Bit set when a message with ERR_FATAL is set.\n", index);
2797 if (pesc_dbg_info.s.rnfemrc)
2798 PRINT_ERROR("PESC%d_DBG_INFO[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
2799 " pedc_radm_nonfatal_err\n", index);
2800 if (pesc_dbg_info.s.rcemrc)
2801 PRINT_ERROR("PESC%d_DBG_INFO[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
2802 " pedc_radm_correctable_err\n", index);
2803 if (pesc_dbg_info.s.rpoison)
2804 PRINT_ERROR("PESC%d_DBG_INFO[RPOISON]: Received Poisoned TLP\n"
2805 " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n", index);
2806 if (pesc_dbg_info.s.recrce)
2807 PRINT_ERROR("PESC%d_DBG_INFO[RECRCE]: Received ECRC Error\n"
2808 " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n", index);
2809 if (pesc_dbg_info.s.rtlplle)
2810 PRINT_ERROR("PESC%d_DBG_INFO[RTLPLLE]: Received TLP has link layer error\n"
2811 " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n", index);
2812 if (pesc_dbg_info.s.rtlpmal)
2813 PRINT_ERROR("PESC%d_DBG_INFO[RTLPMAL]: Received TLP is malformed or a message.\n"
2814 " pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot\n"
2815 " If the core receives a MSG (or Vendor Message)\n"
2816 " this bit will be set.\n", index);
2817 if (pesc_dbg_info.s.spoison)
2818 PRINT_ERROR("PESC%d_DBG_INFO[SPOISON]: Poisoned TLP sent\n"
2819 " peai__client0_tlp_ep & peai__client0_tlp_hv\n", index);
2824 * __cvmx_interrupt_pip_int_en_enable enables all interrupt bits in cvmx_pip_int_en_t
2826 void __cvmx_interrupt_pip_int_en_enable(void)
2828 cvmx_pip_int_en_t pip_int_en;
2829 cvmx_write_csr(CVMX_PIP_INT_REG, cvmx_read_csr(CVMX_PIP_INT_REG));
2831 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
2833 // Skipping pip_int_en.s.reserved_13_63
2834 pip_int_en.s.punyerr = 1;
2835 //pip_int_en.s.lenerr = 1; // Signalled in packet WQE
2836 //pip_int_en.s.maxerr = 1; // Signalled in packet WQE
2837 //pip_int_en.s.minerr = 1; // Signalled in packet WQE
2838 pip_int_en.s.beperr = 1;
2839 pip_int_en.s.feperr = 1;
2840 pip_int_en.s.todoovr = 1;
2841 pip_int_en.s.skprunt = 1;
2842 pip_int_en.s.badtag = 1;
2843 pip_int_en.s.prtnxa = 1;
2844 //pip_int_en.s.bckprs = 1; // Don't care
2845 //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
2846 //pip_int_en.s.pktdrp = 1; // Don't care
2848 if (OCTEON_IS_MODEL(OCTEON_CN30XX))
2850 // Skipping pip_int_en.s.reserved_9_63
2851 pip_int_en.s.beperr = 1;
2852 pip_int_en.s.feperr = 1;
2853 pip_int_en.s.todoovr = 1;
2854 pip_int_en.s.skprunt = 1;
2855 pip_int_en.s.badtag = 1;
2856 pip_int_en.s.prtnxa = 1;
2857 //pip_int_en.s.bckprs = 1; // Don't care
2858 //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
2859 //pip_int_en.s.pktdrp = 1; // Don't care
2861 if (OCTEON_IS_MODEL(OCTEON_CN50XX))
2863 // Skipping pip_int_en.s.reserved_12_63
2864 //pip_int_en.s.lenerr = 1; // Signalled in packet WQE
2865 //pip_int_en.s.maxerr = 1; // Signalled in packet WQE
2866 //pip_int_en.s.minerr = 1; // Signalled in packet WQE
2867 pip_int_en.s.beperr = 1;
2868 pip_int_en.s.feperr = 1;
2869 pip_int_en.s.todoovr = 1;
2870 pip_int_en.s.skprunt = 1;
2871 pip_int_en.s.badtag = 1;
2872 pip_int_en.s.prtnxa = 1;
2873 //pip_int_en.s.bckprs = 1; // Don't care
2874 // Skipping pip_int_en.s.reserved_1_1
2875 //pip_int_en.s.pktdrp = 1; // Don't care
2877 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
2879 // Skipping pip_int_en.s.reserved_9_63
2880 pip_int_en.s.beperr = 1;
2881 pip_int_en.s.feperr = 1;
2882 pip_int_en.s.todoovr = 1;
2883 pip_int_en.s.skprunt = 1;
2884 pip_int_en.s.badtag = 1;
2885 pip_int_en.s.prtnxa = 1;
2886 //pip_int_en.s.bckprs = 1; // Don't care
2887 //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
2888 //pip_int_en.s.pktdrp = 1; // Don't care
2890 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
2892 // Skipping pip_int_en.s.reserved_9_63
2893 pip_int_en.s.beperr = 1;
2894 pip_int_en.s.feperr = 1;
2895 pip_int_en.s.todoovr = 1;
2896 pip_int_en.s.skprunt = 1;
2897 pip_int_en.s.badtag = 1;
2898 pip_int_en.s.prtnxa = 1;
2899 //pip_int_en.s.bckprs = 1; // Don't care
2900 //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
2901 //pip_int_en.s.pktdrp = 1; // Don't care
2903 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
2905 // Skipping pip_int_en.s.reserved_13_63
2906 pip_int_en.s.punyerr = 1;
2907 // Skipping pip_int_en.s.reserved_9_11
2908 pip_int_en.s.beperr = 1;
2909 pip_int_en.s.feperr = 1;
2910 pip_int_en.s.todoovr = 1;
2911 pip_int_en.s.skprunt = 1;
2912 pip_int_en.s.badtag = 1;
2913 pip_int_en.s.prtnxa = 1;
2914 //pip_int_en.s.bckprs = 1; // Don't care
2915 //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
2916 //pip_int_en.s.pktdrp = 1; // Don't care
2918 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
2920 // Skipping pip_int_en.s.reserved_13_63
2921 pip_int_en.s.punyerr = 1;
2922 //pip_int_en.s.lenerr = 1; // Signalled in packet WQE
2923 //pip_int_en.s.maxerr = 1; // Signalled in packet WQE
2924 //pip_int_en.s.minerr = 1; // Signalled in packet WQE
2925 pip_int_en.s.beperr = 1;
2926 pip_int_en.s.feperr = 1;
2927 pip_int_en.s.todoovr = 1;
2928 pip_int_en.s.skprunt = 1;
2929 pip_int_en.s.badtag = 1;
2930 pip_int_en.s.prtnxa = 1;
2931 //pip_int_en.s.bckprs = 1; // Don't care
2932 // Skipping pip_int_en.s.reserved_1_1
2933 //pip_int_en.s.pktdrp = 1; // Don't care
2935 cvmx_write_csr(CVMX_PIP_INT_EN, pip_int_en.u64);
2940 * __cvmx_interrupt_pip_int_reg_decode decodes all interrupt bits in cvmx_pip_int_reg_t
2942 void __cvmx_interrupt_pip_int_reg_decode(void)
2944 cvmx_pip_int_reg_t pip_int_reg;
2945 pip_int_reg.u64 = cvmx_read_csr(CVMX_PIP_INT_REG);
2946 pip_int_reg.u64 &= cvmx_read_csr(CVMX_PIP_INT_EN);
2947 cvmx_write_csr(CVMX_PIP_INT_REG, pip_int_reg.u64);
2948 // Skipping pip_int_reg.s.reserved_13_63
2949 if (pip_int_reg.s.punyerr)
2950 PRINT_ERROR("PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
2951 " stripping in IPD is enable\n");
2952 if (pip_int_reg.s.lenerr)
2953 PRINT_ERROR("PIP_INT_REG[LENERR]: Frame was received with length error\n");
2954 if (pip_int_reg.s.maxerr)
2955 PRINT_ERROR("PIP_INT_REG[MAXERR]: Frame was received with length > max_length\n");
2956 if (pip_int_reg.s.minerr)
2957 PRINT_ERROR("PIP_INT_REG[MINERR]: Frame was received with length < min_length\n");
2958 if (pip_int_reg.s.beperr)
2959 PRINT_ERROR("PIP_INT_REG[BEPERR]: Parity Error in back end memory\n");
2960 if (pip_int_reg.s.feperr)
2961 PRINT_ERROR("PIP_INT_REG[FEPERR]: Parity Error in front end memory\n");
2962 if (pip_int_reg.s.todoovr)
2963 PRINT_ERROR("PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n");
2964 if (pip_int_reg.s.skprunt)
2965 PRINT_ERROR("PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
2966 " This interrupt can occur with received PARTIAL\n"
2967 " packets that are truncated to SKIP bytes or\n"
2969 if (pip_int_reg.s.badtag)
2970 PRINT_ERROR("PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n");
2971 if (pip_int_reg.s.prtnxa)
2972 PRINT_ERROR("PIP_INT_REG[PRTNXA]: Non-existent port\n");
2973 if (pip_int_reg.s.bckprs)
2974 PRINT_ERROR("PIP_INT_REG[BCKPRS]: PIP asserted backpressure\n");
2975 if (pip_int_reg.s.crcerr)
2976 PRINT_ERROR("PIP_INT_REG[CRCERR]: PIP calculated bad CRC\n");
2977 if (pip_int_reg.s.pktdrp)
2978 PRINT_ERROR("PIP_INT_REG[PKTDRP]: Packet Dropped due to QOS\n");
2983 * __cvmx_interrupt_pko_reg_int_mask_enable enables all interrupt bits in cvmx_pko_reg_int_mask_t
2985 void __cvmx_interrupt_pko_reg_int_mask_enable(void)
2987 cvmx_pko_reg_int_mask_t pko_reg_int_mask;
2988 cvmx_write_csr(CVMX_PKO_REG_ERROR, cvmx_read_csr(CVMX_PKO_REG_ERROR));
2989 pko_reg_int_mask.u64 = 0;
2990 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
2992 // Skipping pko_reg_int_mask.s.reserved_3_63
2993 pko_reg_int_mask.s.currzero = 1;
2994 pko_reg_int_mask.s.doorbell = 1;
2995 pko_reg_int_mask.s.parity = 1;
2997 if (OCTEON_IS_MODEL(OCTEON_CN30XX))
2999 // Skipping pko_reg_int_mask.s.reserved_2_63
3000 pko_reg_int_mask.s.doorbell = 1;
3001 pko_reg_int_mask.s.parity = 1;
3003 if (OCTEON_IS_MODEL(OCTEON_CN50XX))
3005 // Skipping pko_reg_int_mask.s.reserved_3_63
3006 pko_reg_int_mask.s.currzero = 1;
3007 pko_reg_int_mask.s.doorbell = 1;
3008 pko_reg_int_mask.s.parity = 1;
3010 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
3012 // Skipping pko_reg_int_mask.s.reserved_2_63
3013 pko_reg_int_mask.s.doorbell = 1;
3014 pko_reg_int_mask.s.parity = 1;
3016 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
3018 // Skipping pko_reg_int_mask.s.reserved_2_63
3019 pko_reg_int_mask.s.doorbell = 1;
3020 pko_reg_int_mask.s.parity = 1;
3022 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
3024 // Skipping pko_reg_int_mask.s.reserved_3_63
3025 pko_reg_int_mask.s.currzero = 1;
3026 pko_reg_int_mask.s.doorbell = 1;
3027 pko_reg_int_mask.s.parity = 1;
3029 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
3031 // Skipping pko_reg_int_mask.s.reserved_3_63
3032 pko_reg_int_mask.s.currzero = 1;
3033 pko_reg_int_mask.s.doorbell = 1;
3034 pko_reg_int_mask.s.parity = 1;
3036 cvmx_write_csr(CVMX_PKO_REG_INT_MASK, pko_reg_int_mask.u64);
3041 * __cvmx_interrupt_pko_reg_error_decode decodes all interrupt bits in cvmx_pko_reg_error_t
3043 void __cvmx_interrupt_pko_reg_error_decode(void)
3045 cvmx_pko_reg_error_t pko_reg_error;
3046 pko_reg_error.u64 = cvmx_read_csr(CVMX_PKO_REG_ERROR);
3047 pko_reg_error.u64 &= cvmx_read_csr(CVMX_PKO_REG_INT_MASK);
3048 cvmx_write_csr(CVMX_PKO_REG_ERROR, pko_reg_error.u64);
3049 // Skipping pko_reg_error.s.reserved_3_63
3050 if (pko_reg_error.s.currzero)
3051 PRINT_ERROR("PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n");
3052 if (pko_reg_error.s.doorbell)
3053 PRINT_ERROR("PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n");
3054 if (pko_reg_error.s.parity)
3055 PRINT_ERROR("PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n");
3060 * __cvmx_interrupt_rad_reg_int_mask_enable enables all interrupt bits in cvmx_rad_reg_int_mask_t
3062 void __cvmx_interrupt_rad_reg_int_mask_enable(void)
3064 cvmx_rad_reg_int_mask_t rad_reg_int_mask;
3065 cvmx_write_csr(CVMX_RAD_REG_ERROR, cvmx_read_csr(CVMX_RAD_REG_ERROR));
3066 rad_reg_int_mask.u64 = 0;
3067 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
3069 // Skipping rad_reg_int_mask.s.reserved_1_63
3070 rad_reg_int_mask.s.doorbell = 1;
3072 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
3074 // Skipping rad_reg_int_mask.s.reserved_1_63
3075 rad_reg_int_mask.s.doorbell = 1;
3077 cvmx_write_csr(CVMX_RAD_REG_INT_MASK, rad_reg_int_mask.u64);
3082 * __cvmx_interrupt_rad_reg_error_decode decodes all interrupt bits in cvmx_rad_reg_error_t
3084 void __cvmx_interrupt_rad_reg_error_decode(void)
3086 cvmx_rad_reg_error_t rad_reg_error;
3087 rad_reg_error.u64 = cvmx_read_csr(CVMX_RAD_REG_ERROR);
3088 rad_reg_error.u64 &= cvmx_read_csr(CVMX_RAD_REG_INT_MASK);
3089 cvmx_write_csr(CVMX_RAD_REG_ERROR, rad_reg_error.u64);
3090 // Skipping rad_reg_error.s.reserved_1_63
3091 if (rad_reg_error.s.doorbell)
3092 PRINT_ERROR("RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n");
3097 * __cvmx_interrupt_spxx_int_msk_enable enables all interrupt bits in cvmx_spxx_int_msk_t
3099 void __cvmx_interrupt_spxx_int_msk_enable(int index)
3101 cvmx_spxx_int_msk_t spx_int_msk;
3102 cvmx_write_csr(CVMX_SPXX_INT_REG(index), cvmx_read_csr(CVMX_SPXX_INT_REG(index)));
3103 spx_int_msk.u64 = 0;
3104 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
3106 // Skipping spx_int_msk.s.reserved_12_63
3107 spx_int_msk.s.calerr = 1;
3108 spx_int_msk.s.syncerr = 1;
3109 spx_int_msk.s.diperr = 1;
3110 spx_int_msk.s.tpaovr = 1;
3111 spx_int_msk.s.rsverr = 1;
3112 spx_int_msk.s.drwnng = 1;
3113 spx_int_msk.s.clserr = 1;
3114 spx_int_msk.s.spiovr = 1;
3115 // Skipping spx_int_msk.s.reserved_2_3
3116 spx_int_msk.s.abnorm = 1;
3117 spx_int_msk.s.prtnxa = 1;
3119 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
3121 // Skipping spx_int_msk.s.reserved_12_63
3122 spx_int_msk.s.calerr = 1;
3123 spx_int_msk.s.syncerr = 1;
3124 spx_int_msk.s.diperr = 1;
3125 spx_int_msk.s.tpaovr = 1;
3126 spx_int_msk.s.rsverr = 1;
3127 spx_int_msk.s.drwnng = 1;
3128 spx_int_msk.s.clserr = 1;
3129 spx_int_msk.s.spiovr = 1;
3130 // Skipping spx_int_msk.s.reserved_2_3
3131 spx_int_msk.s.abnorm = 1;
3132 spx_int_msk.s.prtnxa = 1;
3134 cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64);
3139 * __cvmx_interrupt_spxx_int_reg_decode decodes all interrupt bits in cvmx_spxx_int_reg_t
3141 void __cvmx_interrupt_spxx_int_reg_decode(int index)
3143 cvmx_spxx_int_reg_t spx_int_reg;
3144 spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(index));
3145 spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(index));
3146 cvmx_write_csr(CVMX_SPXX_INT_REG(index), spx_int_reg.u64);
3147 // Skipping spx_int_reg.s.reserved_32_63
3148 if (spx_int_reg.s.spf)
3149 PRINT_ERROR("SPX%d_INT_REG[SPF]: Spi interface down\n", index);
3150 // Skipping spx_int_reg.s.reserved_12_30
3151 if (spx_int_reg.s.calerr)
3152 PRINT_ERROR("SPX%d_INT_REG[CALERR]: Spi4 Calendar table parity error\n", index);
3153 if (spx_int_reg.s.syncerr)
3154 PRINT_ERROR("SPX%d_INT_REG[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
3155 " SPX_ERR_CTL[ERRCNT]\n", index);
3156 if (spx_int_reg.s.diperr)
3157 PRINT_ERROR("SPX%d_INT_REG[DIPERR]: Spi4 DIP4 error\n", index);
3158 if (spx_int_reg.s.tpaovr)
3159 PRINT_ERROR("SPX%d_INT_REG[TPAOVR]: Selected port has hit TPA overflow\n", index);
3160 if (spx_int_reg.s.rsverr)
3161 PRINT_ERROR("SPX%d_INT_REG[RSVERR]: Spi4 reserved control word detected\n", index);
3162 if (spx_int_reg.s.drwnng)
3163 PRINT_ERROR("SPX%d_INT_REG[DRWNNG]: Spi4 receive FIFO drowning/overflow\n", index);
3164 if (spx_int_reg.s.clserr)
3165 PRINT_ERROR("SPX%d_INT_REG[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n", index);
3166 if (spx_int_reg.s.spiovr)
3167 PRINT_ERROR("SPX%d_INT_REG[SPIOVR]: Spi async FIFO overflow\n", index);
3168 // Skipping spx_int_reg.s.reserved_2_3
3169 if (spx_int_reg.s.abnorm)
3170 PRINT_ERROR("SPX%d_INT_REG[ABNORM]: Abnormal packet termination (ERR bit)\n", index);
3171 if (spx_int_reg.s.prtnxa)
3172 PRINT_ERROR("SPX%d_INT_REG[PRTNXA]: Port out of range\n", index);
3177 * __cvmx_interrupt_stxx_int_msk_enable enables all interrupt bits in cvmx_stxx_int_msk_t
3179 void __cvmx_interrupt_stxx_int_msk_enable(int index)
3181 cvmx_stxx_int_msk_t stx_int_msk;
3182 cvmx_write_csr(CVMX_STXX_INT_REG(index), cvmx_read_csr(CVMX_STXX_INT_REG(index)));
3183 stx_int_msk.u64 = 0;
3184 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
3186 // Skipping stx_int_msk.s.reserved_8_63
3187 stx_int_msk.s.frmerr = 1;
3188 stx_int_msk.s.unxfrm = 1;
3189 stx_int_msk.s.nosync = 1;
3190 stx_int_msk.s.diperr = 1;
3191 stx_int_msk.s.datovr = 1;
3192 stx_int_msk.s.ovrbst = 1;
3193 stx_int_msk.s.calpar1 = 1;
3194 stx_int_msk.s.calpar0 = 1;
3196 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
3198 // Skipping stx_int_msk.s.reserved_8_63
3199 stx_int_msk.s.frmerr = 1;
3200 stx_int_msk.s.unxfrm = 1;
3201 stx_int_msk.s.nosync = 1;
3202 stx_int_msk.s.diperr = 1;
3203 stx_int_msk.s.datovr = 1;
3204 stx_int_msk.s.ovrbst = 1;
3205 stx_int_msk.s.calpar1 = 1;
3206 stx_int_msk.s.calpar0 = 1;
3208 cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64);
3213 * __cvmx_interrupt_stxx_int_reg_decode decodes all interrupt bits in cvmx_stxx_int_reg_t
3215 void __cvmx_interrupt_stxx_int_reg_decode(int index)
3217 cvmx_stxx_int_reg_t stx_int_reg;
3218 stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(index));
3219 stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(index));
3220 cvmx_write_csr(CVMX_STXX_INT_REG(index), stx_int_reg.u64);
3221 // Skipping stx_int_reg.s.reserved_9_63
3222 if (stx_int_reg.s.syncerr)
3223 PRINT_ERROR("STX%d_INT_REG[SYNCERR]: Interface encountered a fatal error\n", index);
3224 if (stx_int_reg.s.frmerr)
3225 PRINT_ERROR("STX%d_INT_REG[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n", index);
3226 if (stx_int_reg.s.unxfrm)
3227 PRINT_ERROR("STX%d_INT_REG[UNXFRM]: Unexpected framing sequence\n", index);
3228 if (stx_int_reg.s.nosync)
3229 PRINT_ERROR("STX%d_INT_REG[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n", index);
3230 if (stx_int_reg.s.diperr)
3231 PRINT_ERROR("STX%d_INT_REG[DIPERR]: DIP2 error on the Spi4 Status channel\n", index);
3232 if (stx_int_reg.s.datovr)
3233 PRINT_ERROR("STX%d_INT_REG[DATOVR]: Spi4 FIFO overflow error\n", index);
3234 if (stx_int_reg.s.ovrbst)
3235 PRINT_ERROR("STX%d_INT_REG[OVRBST]: Transmit packet burst too big\n", index);
3236 if (stx_int_reg.s.calpar1)
3237 PRINT_ERROR("STX%d_INT_REG[CALPAR1]: STX Calendar Table Parity Error Bank1\n", index);
3238 if (stx_int_reg.s.calpar0)
3239 PRINT_ERROR("STX%d_INT_REG[CALPAR0]: STX Calendar Table Parity Error Bank0\n", index);
3244 * __cvmx_interrupt_usbnx_int_enb_enable enables all interrupt bits in cvmx_usbnx_int_enb_t
3246 void __cvmx_interrupt_usbnx_int_enb_enable(int index)
3248 cvmx_usbnx_int_enb_t usbn_int_enb;
3249 cvmx_write_csr(CVMX_USBNX_INT_SUM(index), cvmx_read_csr(CVMX_USBNX_INT_SUM(index)));
3250 usbn_int_enb.u64 = 0;
3251 if (OCTEON_IS_MODEL(OCTEON_CN30XX))
3253 // Skipping usbn_int_enb.s.reserved_38_63
3254 usbn_int_enb.s.nd4o_dpf = 1;
3255 usbn_int_enb.s.nd4o_dpe = 1;
3256 usbn_int_enb.s.nd4o_rpf = 1;
3257 usbn_int_enb.s.nd4o_rpe = 1;
3258 usbn_int_enb.s.ltl_f_pf = 1;
3259 usbn_int_enb.s.ltl_f_pe = 1;
3260 usbn_int_enb.s.u2n_c_pe = 1;
3261 usbn_int_enb.s.u2n_c_pf = 1;
3262 usbn_int_enb.s.u2n_d_pf = 1;
3263 usbn_int_enb.s.u2n_d_pe = 1;
3264 usbn_int_enb.s.n2u_pe = 1;
3265 usbn_int_enb.s.n2u_pf = 1;
3266 usbn_int_enb.s.uod_pf = 1;
3267 usbn_int_enb.s.uod_pe = 1;
3268 usbn_int_enb.s.rq_q3_e = 1;
3269 usbn_int_enb.s.rq_q3_f = 1;
3270 usbn_int_enb.s.rq_q2_e = 1;
3271 usbn_int_enb.s.rq_q2_f = 1;
3272 usbn_int_enb.s.rg_fi_f = 1;
3273 usbn_int_enb.s.rg_fi_e = 1;
3274 usbn_int_enb.s.l2_fi_f = 1;
3275 usbn_int_enb.s.l2_fi_e = 1;
3276 usbn_int_enb.s.l2c_a_f = 1;
3277 usbn_int_enb.s.l2c_s_e = 1;
3278 usbn_int_enb.s.dcred_f = 1;
3279 usbn_int_enb.s.dcred_e = 1;
3280 usbn_int_enb.s.lt_pu_f = 1;
3281 usbn_int_enb.s.lt_po_e = 1;
3282 usbn_int_enb.s.nt_pu_f = 1;
3283 usbn_int_enb.s.nt_po_e = 1;
3284 usbn_int_enb.s.pt_pu_f = 1;
3285 usbn_int_enb.s.pt_po_e = 1;
3286 usbn_int_enb.s.lr_pu_f = 1;
3287 usbn_int_enb.s.lr_po_e = 1;
3288 usbn_int_enb.s.nr_pu_f = 1;
3289 usbn_int_enb.s.nr_po_e = 1;
3290 usbn_int_enb.s.pr_pu_f = 1;
3291 usbn_int_enb.s.pr_po_e = 1;
3293 if (OCTEON_IS_MODEL(OCTEON_CN50XX))
3295 // Skipping usbn_int_enb.s.reserved_38_63
3296 usbn_int_enb.s.nd4o_dpf = 1;
3297 usbn_int_enb.s.nd4o_dpe = 1;
3298 usbn_int_enb.s.nd4o_rpf = 1;
3299 usbn_int_enb.s.nd4o_rpe = 1;
3300 usbn_int_enb.s.ltl_f_pf = 1;
3301 usbn_int_enb.s.ltl_f_pe = 1;
3302 // Skipping usbn_int_enb.s.reserved_26_31
3303 usbn_int_enb.s.uod_pf = 1;
3304 usbn_int_enb.s.uod_pe = 1;
3305 usbn_int_enb.s.rq_q3_e = 1;
3306 usbn_int_enb.s.rq_q3_f = 1;
3307 usbn_int_enb.s.rq_q2_e = 1;
3308 usbn_int_enb.s.rq_q2_f = 1;
3309 usbn_int_enb.s.rg_fi_f = 1;
3310 usbn_int_enb.s.rg_fi_e = 1;
3311 usbn_int_enb.s.l2_fi_f = 1;
3312 usbn_int_enb.s.l2_fi_e = 1;
3313 usbn_int_enb.s.l2c_a_f = 1;
3314 usbn_int_enb.s.l2c_s_e = 1;
3315 usbn_int_enb.s.dcred_f = 1;
3316 usbn_int_enb.s.dcred_e = 1;
3317 usbn_int_enb.s.lt_pu_f = 1;
3318 usbn_int_enb.s.lt_po_e = 1;
3319 usbn_int_enb.s.nt_pu_f = 1;
3320 usbn_int_enb.s.nt_po_e = 1;
3321 usbn_int_enb.s.pt_pu_f = 1;
3322 usbn_int_enb.s.pt_po_e = 1;
3323 usbn_int_enb.s.lr_pu_f = 1;
3324 usbn_int_enb.s.lr_po_e = 1;
3325 usbn_int_enb.s.nr_pu_f = 1;
3326 usbn_int_enb.s.nr_po_e = 1;
3327 usbn_int_enb.s.pr_pu_f = 1;
3328 usbn_int_enb.s.pr_po_e = 1;
3330 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
3332 // Skipping usbn_int_enb.s.reserved_38_63
3333 usbn_int_enb.s.nd4o_dpf = 1;
3334 usbn_int_enb.s.nd4o_dpe = 1;
3335 usbn_int_enb.s.nd4o_rpf = 1;
3336 usbn_int_enb.s.nd4o_rpe = 1;
3337 usbn_int_enb.s.ltl_f_pf = 1;
3338 usbn_int_enb.s.ltl_f_pe = 1;
3339 usbn_int_enb.s.u2n_c_pe = 1;
3340 usbn_int_enb.s.u2n_c_pf = 1;
3341 usbn_int_enb.s.u2n_d_pf = 1;
3342 usbn_int_enb.s.u2n_d_pe = 1;
3343 usbn_int_enb.s.n2u_pe = 1;
3344 usbn_int_enb.s.n2u_pf = 1;
3345 usbn_int_enb.s.uod_pf = 1;
3346 usbn_int_enb.s.uod_pe = 1;
3347 usbn_int_enb.s.rq_q3_e = 1;
3348 usbn_int_enb.s.rq_q3_f = 1;
3349 usbn_int_enb.s.rq_q2_e = 1;
3350 usbn_int_enb.s.rq_q2_f = 1;
3351 usbn_int_enb.s.rg_fi_f = 1;
3352 usbn_int_enb.s.rg_fi_e = 1;
3353 usbn_int_enb.s.l2_fi_f = 1;
3354 usbn_int_enb.s.l2_fi_e = 1;
3355 usbn_int_enb.s.l2c_a_f = 1;
3356 usbn_int_enb.s.l2c_s_e = 1;
3357 usbn_int_enb.s.dcred_f = 1;
3358 usbn_int_enb.s.dcred_e = 1;
3359 usbn_int_enb.s.lt_pu_f = 1;
3360 usbn_int_enb.s.lt_po_e = 1;
3361 usbn_int_enb.s.nt_pu_f = 1;
3362 usbn_int_enb.s.nt_po_e = 1;
3363 usbn_int_enb.s.pt_pu_f = 1;
3364 usbn_int_enb.s.pt_po_e = 1;
3365 usbn_int_enb.s.lr_pu_f = 1;
3366 usbn_int_enb.s.lr_po_e = 1;
3367 usbn_int_enb.s.nr_pu_f = 1;
3368 usbn_int_enb.s.nr_po_e = 1;
3369 usbn_int_enb.s.pr_pu_f = 1;
3370 usbn_int_enb.s.pr_po_e = 1;
3372 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
3374 // Skipping usbn_int_enb.s.reserved_38_63
3375 usbn_int_enb.s.nd4o_dpf = 1;
3376 usbn_int_enb.s.nd4o_dpe = 1;
3377 usbn_int_enb.s.nd4o_rpf = 1;
3378 usbn_int_enb.s.nd4o_rpe = 1;
3379 usbn_int_enb.s.ltl_f_pf = 1;
3380 usbn_int_enb.s.ltl_f_pe = 1;
3381 // Skipping usbn_int_enb.s.reserved_26_31
3382 usbn_int_enb.s.uod_pf = 1;
3383 usbn_int_enb.s.uod_pe = 1;
3384 usbn_int_enb.s.rq_q3_e = 1;
3385 usbn_int_enb.s.rq_q3_f = 1;
3386 usbn_int_enb.s.rq_q2_e = 1;
3387 usbn_int_enb.s.rq_q2_f = 1;
3388 usbn_int_enb.s.rg_fi_f = 1;
3389 usbn_int_enb.s.rg_fi_e = 1;
3390 usbn_int_enb.s.l2_fi_f = 1;
3391 usbn_int_enb.s.l2_fi_e = 1;
3392 usbn_int_enb.s.l2c_a_f = 1;
3393 usbn_int_enb.s.l2c_s_e = 1;
3394 usbn_int_enb.s.dcred_f = 1;
3395 usbn_int_enb.s.dcred_e = 1;
3396 usbn_int_enb.s.lt_pu_f = 1;
3397 usbn_int_enb.s.lt_po_e = 1;
3398 usbn_int_enb.s.nt_pu_f = 1;
3399 usbn_int_enb.s.nt_po_e = 1;
3400 usbn_int_enb.s.pt_pu_f = 1;
3401 usbn_int_enb.s.pt_po_e = 1;
3402 usbn_int_enb.s.lr_pu_f = 1;
3403 usbn_int_enb.s.lr_po_e = 1;
3404 usbn_int_enb.s.nr_pu_f = 1;
3405 usbn_int_enb.s.nr_po_e = 1;
3406 usbn_int_enb.s.pr_pu_f = 1;
3407 usbn_int_enb.s.pr_po_e = 1;
3409 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
3411 // Skipping usbn_int_enb.s.reserved_38_63
3412 usbn_int_enb.s.nd4o_dpf = 1;
3413 usbn_int_enb.s.nd4o_dpe = 1;
3414 usbn_int_enb.s.nd4o_rpf = 1;
3415 usbn_int_enb.s.nd4o_rpe = 1;
3416 usbn_int_enb.s.ltl_f_pf = 1;
3417 usbn_int_enb.s.ltl_f_pe = 1;
3418 // Skipping usbn_int_enb.s.reserved_26_31
3419 usbn_int_enb.s.uod_pf = 1;
3420 usbn_int_enb.s.uod_pe = 1;
3421 usbn_int_enb.s.rq_q3_e = 1;
3422 usbn_int_enb.s.rq_q3_f = 1;
3423 usbn_int_enb.s.rq_q2_e = 1;
3424 usbn_int_enb.s.rq_q2_f = 1;
3425 usbn_int_enb.s.rg_fi_f = 1;
3426 usbn_int_enb.s.rg_fi_e = 1;
3427 usbn_int_enb.s.l2_fi_f = 1;
3428 usbn_int_enb.s.l2_fi_e = 1;
3429 usbn_int_enb.s.l2c_a_f = 1;
3430 usbn_int_enb.s.l2c_s_e = 1;
3431 usbn_int_enb.s.dcred_f = 1;
3432 usbn_int_enb.s.dcred_e = 1;
3433 usbn_int_enb.s.lt_pu_f = 1;
3434 usbn_int_enb.s.lt_po_e = 1;
3435 usbn_int_enb.s.nt_pu_f = 1;
3436 usbn_int_enb.s.nt_po_e = 1;
3437 usbn_int_enb.s.pt_pu_f = 1;
3438 usbn_int_enb.s.pt_po_e = 1;
3439 usbn_int_enb.s.lr_pu_f = 1;
3440 usbn_int_enb.s.lr_po_e = 1;
3441 usbn_int_enb.s.nr_pu_f = 1;
3442 usbn_int_enb.s.nr_po_e = 1;
3443 usbn_int_enb.s.pr_pu_f = 1;
3444 usbn_int_enb.s.pr_po_e = 1;
3446 cvmx_write_csr(CVMX_USBNX_INT_ENB(index), usbn_int_enb.u64);
3451 * __cvmx_interrupt_usbnx_int_sum_decode decodes all interrupt bits in cvmx_usbnx_int_sum_t
3453 void __cvmx_interrupt_usbnx_int_sum_decode(int index)
3455 cvmx_usbnx_int_sum_t usbn_int_sum;
3456 usbn_int_sum.u64 = cvmx_read_csr(CVMX_USBNX_INT_SUM(index));
3457 usbn_int_sum.u64 &= cvmx_read_csr(CVMX_USBNX_INT_ENB(index));
3458 cvmx_write_csr(CVMX_USBNX_INT_SUM(index), usbn_int_sum.u64);
3459 // Skipping usbn_int_sum.s.reserved_38_63
3460 if (usbn_int_sum.s.nd4o_dpf)
3461 PRINT_ERROR("USBN%d_INT_SUM[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n", index);
3462 if (usbn_int_sum.s.nd4o_dpe)
3463 PRINT_ERROR("USBN%d_INT_SUM[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n", index);
3464 if (usbn_int_sum.s.nd4o_rpf)
3465 PRINT_ERROR("USBN%d_INT_SUM[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n", index);
3466 if (usbn_int_sum.s.nd4o_rpe)
3467 PRINT_ERROR("USBN%d_INT_SUM[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n", index);
3468 if (usbn_int_sum.s.ltl_f_pf)
3469 PRINT_ERROR("USBN%d_INT_SUM[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n", index);
3470 if (usbn_int_sum.s.ltl_f_pe)
3471 PRINT_ERROR("USBN%d_INT_SUM[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n", index);
3472 if (usbn_int_sum.s.u2n_c_pe)
3473 PRINT_ERROR("USBN%d_INT_SUM[U2N_C_PE]: U2N Control Fifo Pop Empty.\n", index);
3474 if (usbn_int_sum.s.u2n_c_pf)
3475 PRINT_ERROR("USBN%d_INT_SUM[U2N_C_PF]: U2N Control Fifo Push Full.\n", index);
3476 if (usbn_int_sum.s.u2n_d_pf)
3477 PRINT_ERROR("USBN%d_INT_SUM[U2N_D_PF]: U2N Data Fifo Push Full.\n", index);
3478 if (usbn_int_sum.s.u2n_d_pe)
3479 PRINT_ERROR("USBN%d_INT_SUM[U2N_D_PE]: U2N Data Fifo Pop Empty.\n", index);
3480 if (usbn_int_sum.s.n2u_pe)
3481 PRINT_ERROR("USBN%d_INT_SUM[N2U_PE]: N2U Fifo Pop Empty.\n", index);
3482 if (usbn_int_sum.s.n2u_pf)
3483 PRINT_ERROR("USBN%d_INT_SUM[N2U_PF]: N2U Fifo Push Full.\n", index);
3484 if (usbn_int_sum.s.uod_pf)
3485 PRINT_ERROR("USBN%d_INT_SUM[UOD_PF]: UOD Fifo Push Full.\n", index);
3486 if (usbn_int_sum.s.uod_pe)
3487 PRINT_ERROR("USBN%d_INT_SUM[UOD_PE]: UOD Fifo Pop Empty.\n", index);
3488 if (usbn_int_sum.s.rq_q3_e)
3489 PRINT_ERROR("USBN%d_INT_SUM[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n", index);
3490 if (usbn_int_sum.s.rq_q3_f)
3491 PRINT_ERROR("USBN%d_INT_SUM[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n", index);
3492 if (usbn_int_sum.s.rq_q2_e)
3493 PRINT_ERROR("USBN%d_INT_SUM[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n", index);
3494 if (usbn_int_sum.s.rq_q2_f)
3495 PRINT_ERROR("USBN%d_INT_SUM[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n", index);
3496 if (usbn_int_sum.s.rg_fi_f)
3497 PRINT_ERROR("USBN%d_INT_SUM[RG_FI_F]: Register Request Fifo Pushed When Full.\n", index);
3498 if (usbn_int_sum.s.rg_fi_e)
3499 PRINT_ERROR("USBN%d_INT_SUM[RG_FI_E]: Register Request Fifo Pushed When Full.\n", index);
3500 if (usbn_int_sum.s.lt_fi_f)
3501 PRINT_ERROR("USBN%d_INT_SUM[LT_FI_F]: L2C Request Fifo Pushed When Full.\n", index);
3502 if (usbn_int_sum.s.lt_fi_e)
3503 PRINT_ERROR("USBN%d_INT_SUM[LT_FI_E]: L2C Request Fifo Pushed When Full.\n", index);
3504 if (usbn_int_sum.s.l2c_a_f)
3505 PRINT_ERROR("USBN%d_INT_SUM[L2C_A_F]: L2C Credit Count Added When Full.\n", index);
3506 if (usbn_int_sum.s.l2c_s_e)
3507 PRINT_ERROR("USBN%d_INT_SUM[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n", index);
3508 if (usbn_int_sum.s.dcred_f)
3509 PRINT_ERROR("USBN%d_INT_SUM[DCRED_F]: Data CreditFifo Pushed When Full.\n", index);
3510 if (usbn_int_sum.s.dcred_e)
3511 PRINT_ERROR("USBN%d_INT_SUM[DCRED_E]: Data Credit Fifo Pushed When Full.\n", index);
3512 if (usbn_int_sum.s.lt_pu_f)
3513 PRINT_ERROR("USBN%d_INT_SUM[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n", index);
3514 if (usbn_int_sum.s.lt_po_e)
3515 PRINT_ERROR("USBN%d_INT_SUM[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n", index);
3516 if (usbn_int_sum.s.nt_pu_f)
3517 PRINT_ERROR("USBN%d_INT_SUM[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n", index);
3518 if (usbn_int_sum.s.nt_po_e)
3519 PRINT_ERROR("USBN%d_INT_SUM[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n", index);
3520 if (usbn_int_sum.s.pt_pu_f)
3521 PRINT_ERROR("USBN%d_INT_SUM[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n", index);
3522 if (usbn_int_sum.s.pt_po_e)
3523 PRINT_ERROR("USBN%d_INT_SUM[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n", index);
3524 if (usbn_int_sum.s.lr_pu_f)
3525 PRINT_ERROR("USBN%d_INT_SUM[LR_PU_F]: L2C Request Fifo Pushed When Full.\n", index);
3526 if (usbn_int_sum.s.lr_po_e)
3527 PRINT_ERROR("USBN%d_INT_SUM[LR_PO_E]: L2C Request Fifo Popped When Empty.\n", index);
3528 if (usbn_int_sum.s.nr_pu_f)
3529 PRINT_ERROR("USBN%d_INT_SUM[NR_PU_F]: NPI Request Fifo Pushed When Full.\n", index);
3530 if (usbn_int_sum.s.nr_po_e)
3531 PRINT_ERROR("USBN%d_INT_SUM[NR_PO_E]: NPI Request Fifo Popped When Empty.\n", index);
3532 if (usbn_int_sum.s.pr_pu_f)
3533 PRINT_ERROR("USBN%d_INT_SUM[PR_PU_F]: PP Request Fifo Pushed When Full.\n", index);
3534 if (usbn_int_sum.s.pr_po_e)
3535 PRINT_ERROR("USBN%d_INT_SUM[PR_PO_E]: PP Request Fifo Popped When Empty.\n", index);
3540 * __cvmx_interrupt_zip_int_mask_enable enables all interrupt bits in cvmx_zip_int_mask_t
3542 void __cvmx_interrupt_zip_int_mask_enable(void)
3544 cvmx_zip_int_mask_t zip_int_mask;
3545 cvmx_write_csr(CVMX_ZIP_ERROR, cvmx_read_csr(CVMX_ZIP_ERROR));
3546 zip_int_mask.u64 = 0;
3547 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
3549 // Skipping zip_int_mask.s.reserved_1_63
3550 zip_int_mask.s.doorbell = 1;
3552 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
3554 // Skipping zip_int_mask.s.reserved_1_63
3555 zip_int_mask.s.doorbell = 1;
3557 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
3559 // Skipping zip_int_mask.s.reserved_1_63
3560 zip_int_mask.s.doorbell = 1;
3562 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
3564 // Skipping zip_int_mask.s.reserved_1_63
3565 zip_int_mask.s.doorbell = 1;
3567 cvmx_write_csr(CVMX_ZIP_INT_MASK, zip_int_mask.u64);
3572 * __cvmx_interrupt_zip_error_decode decodes all interrupt bits in cvmx_zip_error_t
3574 void __cvmx_interrupt_zip_error_decode(void)
3576 cvmx_zip_error_t zip_error;
3577 zip_error.u64 = cvmx_read_csr(CVMX_ZIP_ERROR);
3578 zip_error.u64 &= cvmx_read_csr(CVMX_ZIP_INT_MASK);
3579 cvmx_write_csr(CVMX_ZIP_ERROR, zip_error.u64);
3580 // Skipping zip_error.s.reserved_1_63
3581 if (zip_error.s.doorbell)
3582 PRINT_ERROR("ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n");