1 /***********************license start***************
2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
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14 * copyright notice, this list of conditions and the following
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16 * with the distribution.
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20 * derived from this software without specific prior written
23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
35 * For any questions regarding licensing please contact marketing@caviumnetworks.com
37 ***********************license end**************************************/
47 #include <machine/asm.h>
48 #include <machine/regdef.h>
53 LEAF(cvmx_interrupt_stage1)
54 dla k0, cvmx_interrupt_stage2
55 jalr k1, k0 // Save our address in k1, so we can tell which
56 // vector we are coming from.
58 END(cvmx_interrupt_stage1)
60 #define STACK_SIZE (36*8)
61 LEAF(cvmx_interrupt_stage2)
62 dsubu sp, sp, STACK_SIZE
63 sd zero, 0(sp) // Just a place holder
64 sd $1, 8(sp) // start saving registers
91 mfhi k0 // Reading lo and high takes multiple cycles
92 mflo k1 // Do it here so it completes by the time we need it
94 daddu $1, sp, STACK_SIZE // Correct the SP for the space we used
97 sd $31, 248(sp) // saved all general purpose registers
98 sd k0, 256(sp) // save hi
99 sd k1, 264(sp) // save lo
100 /* Save DCACHE error register early, since any non-errored DCACHE accesses will clear
104 /* Store DEPC for GCC's frame unwinder. */
108 dla k0, cvmx_interrupt_do_irq
110 dadd a0, sp, 0 // First argument is array of registers
112 ld k0, 256(sp) // read hi
113 ld k1, 264(sp) // read lo
114 mthi k0 // restore hi
115 mtlo k1 // restore lo
117 ld $1, 8(sp) // start restoring registers
145 ld $31, 248(sp) // restored all general purpose registers
146 ld $29, 232(sp) // No need to correct for STACK_SIZE
149 END(cvmx_interrupt_stage2)
151 // Icache and Dcache exception handler. This code is executed
152 // with ERL set so we can't us virtual addresses. We save and restore
153 // K0 to a global memory location so we can handle cache errors from exception
154 // context. This means that if two cores get a cache exception at the same time
155 // the K0 might be corrupted. This entire handler MUST fit in 128 bytes.
156 #define K0_STORE_LOCATION 8
157 #define DCACHE_ERROR_COUNT 16
158 #define ICACHE_ERROR_COUNT 24
159 LEAF(cvmx_interrupt_cache_error)
162 sd k0, K0_STORE_LOCATION($0) // Store K0 into global loc in case we're in an exception
163 dmfc0 k0, $27, 1 // Get Dcache error status before any loads
164 bbit0 k0, 0, not_dcache_error // Skip dcache count if no error
165 dmtc0 k0, $27, 1 // Clear any Dcache errors
166 ld k0, DCACHE_ERROR_COUNT($0) // Load the dcache error count
167 daddu k0, 1 // Increment the dcache error count
168 sd k0, DCACHE_ERROR_COUNT($0) // Store the dcache error count
170 dmfc0 k0, $27, 0 // Get the Icache error status
171 bbit0 k0, 0, not_icache_error // Skip Icache count if no error
172 dmtc0 k0, $27, 0 // Clear any Icache errors
173 ld k0, ICACHE_ERROR_COUNT($0) // Load the icache error count
174 daddu k0, 1 // Increment the icache error count
175 sd k0, ICACHE_ERROR_COUNT($0) // Store the icache error count
177 ld k0, K0_STORE_LOCATION($0) // Restore K0 since we might have been in an exception
178 eret // Return from the Icache exception
180 END(cvmx_interrupt_cache_error)