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44 /* This file contains support functions for the Cortina IXF18201 SPI->XAUI dual
45 ** MAC. The IXF18201 has dual SPI and dual XAUI interfaces to provide 2 10 gigabit
47 ** This file supports the EBT5810 evaluation board. To support a different board,
48 ** the 16 bit read/write functions would need to be customized for that board, and the
49 ** IXF18201 may need to be initialized differently as well.
51 ** The IXF18201 and Octeon are configured for 2 SPI channels per interface (ports 0/1, and 16/17).
52 ** Ports 0 and 16 are the ports that are connected to the XAUI MACs (which are connected to the SFP+ modules)
53 ** Ports 1 and 17 are connected to the hairpin loopback port on the IXF SPI interface. All packets sent out
54 ** of these ports are looped back the same port they were sent on. The loopback ports are always enabled.
56 ** The MAC address filtering on the IXF is not enabled. Link up/down events are not detected, only SPI status
57 ** is monitored by default, which is independent of the XAUI/SFP+ link status.
62 #include "cvmx-swap.h"
68 #define PAL_BASE (1ull << 63 | 0x1d030000)
69 #define IXF_ADDR_HI (PAL_BASE + 0xa)
70 #define IXF_ADDR_LO (PAL_BASE + 0xb)
71 #define IXF_ADDR_16 IXF_ADDR_HI /* 16 bit access */
73 #define IXF_WR_DATA_HI (PAL_BASE + 0xc)
74 #define IXF_WR_DATA_LO (PAL_BASE + 0xd)
75 #define IXF_WR_DATA_16 IXF_WR_DATA_HI
77 #define IXF_RD_DATA_HI (PAL_BASE + 0x10)
78 #define IXF_RD_DATA_LO (PAL_BASE + 0x11)
79 #define IXF_RD_DATA_16 IXF_RD_DATA_HI
81 #define IXF_TRANS_TYPE (PAL_BASE + 0xe)
82 #define IXF_TRANS_STATUS (PAL_BASE + 0xf)
85 uint16_t cvmx_ixf18201_read16(uint16_t reg_addr)
87 cvmx_write64_uint16(IXF_ADDR_16, reg_addr);
88 cvmx_write64_uint8(IXF_TRANS_TYPE, 1); // Do read
92 return(cvmx_read64_uint16(IXF_RD_DATA_16));
95 void cvmx_ixf18201_write16(uint16_t reg_addr, uint16_t data)
97 cvmx_write64_uint16(IXF_ADDR_16, reg_addr);
98 cvmx_write64_uint16(IXF_WR_DATA_16, data);
99 cvmx_write64_uint8(IXF_TRANS_TYPE, 0);
105 uint32_t cvmx_ixf18201_read32(uint16_t reg_addr)
113 lo = cvmx_ixf18201_read16(reg_addr);
114 hi = cvmx_ixf18201_read16(reg_addr + 1);
115 return((hi << 16) | lo);
117 void cvmx_ixf18201_write32(uint16_t reg_addr, uint32_t data)
127 cvmx_ixf18201_write16(reg_addr, lo);
128 cvmx_ixf18201_write16(reg_addr + 1, hi);
133 #define IXF_REG_MDI_CMD_ADDR1 0x310E
134 #define IXF_REG_MDI_RD_WR1 0x3110
135 void cvmx_ixf18201_mii_write(int mii_addr, int mmd, uint16_t reg, uint16_t val)
137 uint32_t cmd_val = 0;
141 cmd_val |= 0x0 << 26; // Set address operation
142 cmd_val |= (mii_addr & 0x1f) << 21; // Set PHY addr
143 cmd_val |= (mmd & 0x1f) << 16; // Set MMD
144 cmd_val |= 1 << 30; // Do operation
145 cmd_val |= 1 << 31; // enable in progress bit
150 cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
152 while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
153 ; /* Wait for operation to complete */
156 cvmx_ixf18201_write32(IXF_REG_MDI_RD_WR1, val);
158 /* Do read operation */
160 cmd_val |= 0x1 << 26; // Set write operation
161 cmd_val |= (mii_addr & 0x1f) << 21; // Set PHY addr
162 cmd_val |= (mmd & 0x1f) << 16; // Set MMD
163 cmd_val |= 1 << 30; // Do operation
164 cmd_val |= 1 << 31; // enable in progress bit
165 cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
167 while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
168 ; /* Wait for operation to complete */
174 int cvmx_ixf18201_mii_read(int mii_addr, int mmd, uint16_t reg)
176 uint32_t cmd_val = 0;
180 cmd_val |= 0x0 << 26; // Set address operation
181 cmd_val |= (mii_addr & 0x1f) << 21; // Set PHY addr
182 cmd_val |= (mmd & 0x1f) << 16; // Set MMD
183 cmd_val |= 1 << 30; // Do operation
184 cmd_val |= 1 << 31; // enable in progress bit
189 cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
191 while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
192 ; /* Wait for operation to complete */
194 /* Do read operation */
196 cmd_val |= 0x3 << 26; // Set read operation
197 cmd_val |= (mii_addr & 0x1f) << 21; // Set PHY addr
198 cmd_val |= (mmd & 0x1f) << 16; // Set MMD
199 cmd_val |= 1 << 30; // Do operation
200 cmd_val |= 1 << 31; // enable in progress bit
201 cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
203 while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
204 ; /* Wait for operation to complete */
206 cmd_val = cvmx_ixf18201_read32(IXF_REG_MDI_RD_WR1);
208 return(cmd_val >> 16);
214 int cvmx_ixf18201_init(void)
216 int index; /* For indexing the two 'ports' on ixf */
219 /* Reset IXF, and take all blocks out of reset */
223 PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0000, new: 0x0001
224 PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0001, new: 0x0000
225 PP0:~CONSOLE-> **** LLM201(Lochlomond) Driver loaded ****
226 PP0:~CONSOLE-> LLM201 Driver - Released on Tue Aug 28 09:51:30 2007.
227 PP0:~CONSOLE-> retval is: 0
228 PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0000, new: 0x0001
229 PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0001, new: 0x0000
230 PP0:~CONSOLE-> Brought all blocks out of reset
231 PP0:~CONSOLE-> Getting default config.
235 cvmx_ixf18201_write16(0x0003, 0x0001);
236 cvmx_ixf18201_write16(0x0003, 0);
239 PP0:~CONSOLE-> Changing register value, addr 0x0000, old: 0x4014, new: 0x4010
240 PP0:~CONSOLE-> Changing register value, addr 0x0000, old: 0x4010, new: 0x4014
241 PP0:~CONSOLE-> Changing register value, addr 0x0004, old: 0x01ff, new: 0x0140
242 PP0:~CONSOLE-> Changing register value, addr 0x0009, old: 0x007f, new: 0x0000
244 cvmx_ixf18201_write16(0x0000, 0x4010);
245 cvmx_ixf18201_write16(0x0000, 0x4014);
246 cvmx_ixf18201_write16(0x0004, 0x0140);
247 cvmx_ixf18201_write16(0x0009, 0);
251 PP0:~CONSOLE-> Changing register value, addr 0x000e, old: 0x0000, new: 0x000f
252 PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0000, new: 0x0004
253 PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0004, new: 0x0006
254 PP0:~CONSOLE-> Changing register value, addr 0x000e, old: 0x000f, new: 0x00f0
255 PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0006, new: 0x0040
256 PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0040, new: 0x0060
258 // skip GPIO, 0xe/0xf
262 PP0:~CONSOLE-> Changing register value, addr 0x3100, old: 0x57fb, new: 0x7f7b
263 PP0:~CONSOLE-> Changing register value, addr 0x3600, old: 0x57fb, new: 0x7f7b
264 PP0:~CONSOLE-> Changing register value, addr 0x3005, old: 0x8010, new: 0x0040
265 PP0:~CONSOLE-> Changing register value, addr 0x3006, old: 0x061a, new: 0x0000
266 PP0:~CONSOLE-> Changing register value, addr 0x3505, old: 0x8010, new: 0x0040
267 PP0:~CONSOLE-> Changing register value, addr 0x3506, old: 0x061a, new: 0x0000
269 for (index = 0; index < 2;index++ )
271 offset = 0x500 * index;
272 cvmx_ixf18201_write32(0x3100 + offset, 0x47f7b);
273 cvmx_ixf18201_write16(0x3005 + offset, 0x0040);
274 cvmx_ixf18201_write16(0x3006 + offset, 0);
277 /*PP0:~CONSOLE-> *** SPI soft reset ***, block id: 0
278 PP0:~CONSOLE-> Changing register value, addr 0x3007, old: 0xf980, new: 0xf9c0
279 PP0:~CONSOLE-> Changing register value, addr 0x3008, old: 0xa6f0, new: 0x36f0
280 PP0:~CONSOLE-> Changing register value, addr 0x3000, old: 0x0080, new: 0x0060
281 PP0:~CONSOLE-> Changing register value, addr 0x3002, old: 0x0200, new: 0x0040
282 PP0:~CONSOLE-> Changing register value, addr 0x3003, old: 0x0100, new: 0x0000
283 PP0:~CONSOLE-> Changing register value, addr 0x30c2, old: 0x0080, new: 0x0060
284 PP0:~CONSOLE-> Changing register value, addr 0x300a, old: 0x0800, new: 0x0000
285 PP0:~CONSOLE-> Changing register value, addr 0x3007, old: 0xf9c0, new: 0x89c0
286 PP0:~CONSOLE-> Changing register value, addr 0x3016, old: 0x0000, new: 0x0010
287 PP0:~CONSOLE-> Changing register value, addr 0x3008, old: 0x36f0, new: 0x3610
288 PP0:~CONSOLE-> Changing register value, addr 0x3012, old: 0x0000, new: 0x0010
289 PP0:~CONSOLE-> Changing register value, addr 0x3007, old: 0x89c0, new: 0x8980
290 PP0:~CONSOLE-> Changing register value, addr 0x3008, old: 0x3610, new: 0xa210
296 for (index = 0; index < 2;index++ )
298 offset = 0x500 * index;
299 int cal_len_min_1 = 0; /* Calendar length -1. Must match number
300 ** of ports configured for interface.*/
301 cvmx_ixf18201_write16(0x3007 + offset, 0x81c0 | (cal_len_min_1 << 11));
302 cvmx_ixf18201_write16(0x3008 + offset, 0x3600 | (cal_len_min_1 << 4));
303 cvmx_ixf18201_write16(0x3000 + offset, 0x0060);
304 cvmx_ixf18201_write16(0x3002 + offset, 0x0040);
305 cvmx_ixf18201_write16(0x3003 + offset, 0x0000);
306 cvmx_ixf18201_write16(0x30c2 + offset, 0x0060);
307 cvmx_ixf18201_write16(0x300a + offset, 0x0000);
308 cvmx_ixf18201_write16(0x3007 + offset, 0x81c0 | (cal_len_min_1 << 11));
309 cvmx_ixf18201_write16(0x3016 + offset, 0x0010);
310 cvmx_ixf18201_write16(0x3008 + offset, 0x3600 | (cal_len_min_1 << 4));
311 cvmx_ixf18201_write16(0x3012 + offset, 0x0010);
312 cvmx_ixf18201_write16(0x3007 + offset, 0x8180 | (cal_len_min_1 << 11));
313 cvmx_ixf18201_write16(0x3008 + offset, 0xa200 | (cal_len_min_1 << 4));
315 cvmx_ixf18201_write16(0x3090 + offset, 0x0301); /* Enable hairpin loopback */
321 PP0:~CONSOLE-> Changing register value, addr 0x0004, old: 0x0140, new: 0x1fff
322 PP0:~CONSOLE-> Changing register value, addr 0x0009, old: 0x0000, new: 0x007f
323 PP0:~CONSOLE-> Changing register value, addr 0x310b, old: 0x0004, new: 0xffff
324 PP0:~CONSOLE-> Changing register value, addr 0x310a, old: 0x7f7b, new: 0xffff
328 cvmx_ixf18201_write16(0x0004, 0x1fff);
329 cvmx_ixf18201_write16(0x0009, 0x007f);
332 cvmx_ixf18201_write16(0x310b, 0xffff);
333 cvmx_ixf18201_write16(0x310a, 0xffff);
338 *** 32 bit register, trace only captures part of it...
339 PP0:~CONSOLE-> Changing register value, addr 0x3100, old: 0x7f7b, new: 0x7f78
340 PP0:~CONSOLE-> Changing register value, addr 0x3600, old: 0x7f7b, new: 0x7f78
343 for (index = 0; index < 2;index++ )
345 offset = 0x500 * index;
346 cvmx_ixf18201_write32(0x3100 + offset, 0x47f7c); /* Also enable jumbo frames */
347 /* Set max packet size to 9600 bytes, max supported by IXF18201 */
348 cvmx_ixf18201_write32(0x3114 + offset, 0x25800000);
352 cvmx_wait(100000000);
354 /* Now reset the PCS blocks in the phy. This seems to be required after
355 ** bringing up the Cortina. */
356 cvmx_ixf18201_mii_write(1, 3, 0, 0x8000);
357 cvmx_ixf18201_mii_write(5, 3, 0, 0x8000);