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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_L2D_TYPEDEFS_H__
53 #define __CVMX_L2D_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC()
57 static inline uint64_t CVMX_L2D_BST0_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
60 cvmx_warn("CVMX_L2D_BST0 not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180080000780ull);
64 #define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_L2D_BST1 CVMX_L2D_BST1_FUNC()
68 static inline uint64_t CVMX_L2D_BST1_FUNC(void)
70 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
71 cvmx_warn("CVMX_L2D_BST1 not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001180080000788ull);
75 #define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_L2D_BST2 CVMX_L2D_BST2_FUNC()
79 static inline uint64_t CVMX_L2D_BST2_FUNC(void)
81 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
82 cvmx_warn("CVMX_L2D_BST2 not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x0001180080000790ull);
86 #define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_L2D_BST3 CVMX_L2D_BST3_FUNC()
90 static inline uint64_t CVMX_L2D_BST3_FUNC(void)
92 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
93 cvmx_warn("CVMX_L2D_BST3 not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x0001180080000798ull);
97 #define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 #define CVMX_L2D_ERR CVMX_L2D_ERR_FUNC()
101 static inline uint64_t CVMX_L2D_ERR_FUNC(void)
103 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
104 cvmx_warn("CVMX_L2D_ERR not supported on this chip\n");
105 return CVMX_ADD_IO_SEG(0x0001180080000010ull);
108 #define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111 #define CVMX_L2D_FADR CVMX_L2D_FADR_FUNC()
112 static inline uint64_t CVMX_L2D_FADR_FUNC(void)
114 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
115 cvmx_warn("CVMX_L2D_FADR not supported on this chip\n");
116 return CVMX_ADD_IO_SEG(0x0001180080000018ull);
119 #define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
122 #define CVMX_L2D_FSYN0 CVMX_L2D_FSYN0_FUNC()
123 static inline uint64_t CVMX_L2D_FSYN0_FUNC(void)
125 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
126 cvmx_warn("CVMX_L2D_FSYN0 not supported on this chip\n");
127 return CVMX_ADD_IO_SEG(0x0001180080000020ull);
130 #define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 #define CVMX_L2D_FSYN1 CVMX_L2D_FSYN1_FUNC()
134 static inline uint64_t CVMX_L2D_FSYN1_FUNC(void)
136 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
137 cvmx_warn("CVMX_L2D_FSYN1 not supported on this chip\n");
138 return CVMX_ADD_IO_SEG(0x0001180080000028ull);
141 #define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
144 #define CVMX_L2D_FUS0 CVMX_L2D_FUS0_FUNC()
145 static inline uint64_t CVMX_L2D_FUS0_FUNC(void)
147 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
148 cvmx_warn("CVMX_L2D_FUS0 not supported on this chip\n");
149 return CVMX_ADD_IO_SEG(0x00011800800007A0ull);
152 #define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
154 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
155 #define CVMX_L2D_FUS1 CVMX_L2D_FUS1_FUNC()
156 static inline uint64_t CVMX_L2D_FUS1_FUNC(void)
158 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
159 cvmx_warn("CVMX_L2D_FUS1 not supported on this chip\n");
160 return CVMX_ADD_IO_SEG(0x00011800800007A8ull);
163 #define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
165 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
166 #define CVMX_L2D_FUS2 CVMX_L2D_FUS2_FUNC()
167 static inline uint64_t CVMX_L2D_FUS2_FUNC(void)
169 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
170 cvmx_warn("CVMX_L2D_FUS2 not supported on this chip\n");
171 return CVMX_ADD_IO_SEG(0x00011800800007B0ull);
174 #define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
176 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
177 #define CVMX_L2D_FUS3 CVMX_L2D_FUS3_FUNC()
178 static inline uint64_t CVMX_L2D_FUS3_FUNC(void)
180 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
181 cvmx_warn("CVMX_L2D_FUS3 not supported on this chip\n");
182 return CVMX_ADD_IO_SEG(0x00011800800007B8ull);
185 #define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
191 * L2D_BST0 = L2C Data Store QUAD0 BIST Status Register
197 struct cvmx_l2d_bst0_s
199 #if __BYTE_ORDER == __BIG_ENDIAN
200 uint64_t reserved_35_63 : 29;
201 uint64_t ftl : 1; /**< L2C Data Store Fatal Defect(across all QUADs)
202 2 or more columns were detected bad across all
203 QUADs[0-3]. Please refer to individual quad failures
204 for bad column = 0x7e to determine which QUAD was in
206 uint64_t q0stat : 34; /**< Bist Results for QUAD0
209 [13:7] bad high column
213 [30:24] bad high column
214 [23:17] bad low column
215 NOTES: For bad high/low column reporting:
217 0x7e: Fatal Defect: 2 or more bad columns
219 NOTE: If there are less than 2 failures then the
220 bad bank will be 0x7. */
222 uint64_t q0stat : 34;
224 uint64_t reserved_35_63 : 29;
227 struct cvmx_l2d_bst0_s cn30xx;
228 struct cvmx_l2d_bst0_s cn31xx;
229 struct cvmx_l2d_bst0_s cn38xx;
230 struct cvmx_l2d_bst0_s cn38xxp2;
231 struct cvmx_l2d_bst0_s cn50xx;
232 struct cvmx_l2d_bst0_s cn52xx;
233 struct cvmx_l2d_bst0_s cn52xxp1;
234 struct cvmx_l2d_bst0_s cn56xx;
235 struct cvmx_l2d_bst0_s cn56xxp1;
236 struct cvmx_l2d_bst0_s cn58xx;
237 struct cvmx_l2d_bst0_s cn58xxp1;
239 typedef union cvmx_l2d_bst0 cvmx_l2d_bst0_t;
244 * L2D_BST1 = L2C Data Store QUAD1 BIST Status Register
250 struct cvmx_l2d_bst1_s
252 #if __BYTE_ORDER == __BIG_ENDIAN
253 uint64_t reserved_34_63 : 30;
254 uint64_t q1stat : 34; /**< Bist Results for QUAD1
257 [13:7] bad high column
261 [30:24] bad high column
262 [23:17] bad low column
263 NOTES: For bad high/low column reporting:
265 0x7e: Fatal Defect: 2 or more bad columns
267 NOTE: If there are less than 2 failures then the
268 bad bank will be 0x7. */
270 uint64_t q1stat : 34;
271 uint64_t reserved_34_63 : 30;
274 struct cvmx_l2d_bst1_s cn30xx;
275 struct cvmx_l2d_bst1_s cn31xx;
276 struct cvmx_l2d_bst1_s cn38xx;
277 struct cvmx_l2d_bst1_s cn38xxp2;
278 struct cvmx_l2d_bst1_s cn50xx;
279 struct cvmx_l2d_bst1_s cn52xx;
280 struct cvmx_l2d_bst1_s cn52xxp1;
281 struct cvmx_l2d_bst1_s cn56xx;
282 struct cvmx_l2d_bst1_s cn56xxp1;
283 struct cvmx_l2d_bst1_s cn58xx;
284 struct cvmx_l2d_bst1_s cn58xxp1;
286 typedef union cvmx_l2d_bst1 cvmx_l2d_bst1_t;
291 * L2D_BST2 = L2C Data Store QUAD2 BIST Status Register
297 struct cvmx_l2d_bst2_s
299 #if __BYTE_ORDER == __BIG_ENDIAN
300 uint64_t reserved_34_63 : 30;
301 uint64_t q2stat : 34; /**< Bist Results for QUAD2
304 [13:7] bad high column
308 [30:24] bad high column
309 [23:17] bad low column
310 NOTES: For bad high/low column reporting:
312 0x7e: Fatal Defect: 2 or more bad columns
314 NOTE: If there are less than 2 failures then the
315 bad bank will be 0x7. */
317 uint64_t q2stat : 34;
318 uint64_t reserved_34_63 : 30;
321 struct cvmx_l2d_bst2_s cn30xx;
322 struct cvmx_l2d_bst2_s cn31xx;
323 struct cvmx_l2d_bst2_s cn38xx;
324 struct cvmx_l2d_bst2_s cn38xxp2;
325 struct cvmx_l2d_bst2_s cn50xx;
326 struct cvmx_l2d_bst2_s cn52xx;
327 struct cvmx_l2d_bst2_s cn52xxp1;
328 struct cvmx_l2d_bst2_s cn56xx;
329 struct cvmx_l2d_bst2_s cn56xxp1;
330 struct cvmx_l2d_bst2_s cn58xx;
331 struct cvmx_l2d_bst2_s cn58xxp1;
333 typedef union cvmx_l2d_bst2 cvmx_l2d_bst2_t;
338 * L2D_BST3 = L2C Data Store QUAD3 BIST Status Register
344 struct cvmx_l2d_bst3_s
346 #if __BYTE_ORDER == __BIG_ENDIAN
347 uint64_t reserved_34_63 : 30;
348 uint64_t q3stat : 34; /**< Bist Results for QUAD3
351 [13:7] bad high column
355 [30:24] bad high column
356 [23:17] bad low column
357 NOTES: For bad high/low column reporting:
359 0x7e: Fatal Defect: 2 or more bad columns
361 NOTE: If there are less than 2 failures then the
362 bad bank will be 0x7. */
364 uint64_t q3stat : 34;
365 uint64_t reserved_34_63 : 30;
368 struct cvmx_l2d_bst3_s cn30xx;
369 struct cvmx_l2d_bst3_s cn31xx;
370 struct cvmx_l2d_bst3_s cn38xx;
371 struct cvmx_l2d_bst3_s cn38xxp2;
372 struct cvmx_l2d_bst3_s cn50xx;
373 struct cvmx_l2d_bst3_s cn52xx;
374 struct cvmx_l2d_bst3_s cn52xxp1;
375 struct cvmx_l2d_bst3_s cn56xx;
376 struct cvmx_l2d_bst3_s cn56xxp1;
377 struct cvmx_l2d_bst3_s cn58xx;
378 struct cvmx_l2d_bst3_s cn58xxp1;
380 typedef union cvmx_l2d_bst3 cvmx_l2d_bst3_t;
385 * L2D_ERR = L2 Data Errors
387 * Description: L2 Data ECC SEC/DED Errors and Interrupt Enable
392 struct cvmx_l2d_err_s
394 #if __BYTE_ORDER == __BIG_ENDIAN
395 uint64_t reserved_6_63 : 58;
396 uint64_t bmhclsel : 1; /**< L2 Bit Map Half CacheLine ECC Selector
398 When L2C_DBG[L2T]=1/L2D_ERR[ECC_ENA]=0, the BMHCLSEL selects
399 which half cacheline to conditionally latch into
400 the L2D_FSYN0/L2D_FSYN1 registers when an LDD command
401 is detected from the diagnostic PP (see L2C_DBG[PPNUM]).
402 - 0: OW[0-3] ECC (from first 1/2 cacheline) is selected to
403 be conditionally latched into the L2D_FSYN0/1 CSRs.
404 - 1: OW[4-7] ECC (from last 1/2 cacheline) is selected to
405 be conditionally latched into
406 the L2D_FSYN0/1 CSRs. */
407 uint64_t ded_err : 1; /**< L2D Double Error detected (DED) */
408 uint64_t sec_err : 1; /**< L2D Single Error corrected (SEC) */
409 uint64_t ded_intena : 1; /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit
410 When set, allows interrupts to be reported on double bit
411 (uncorrectable) errors from the L2 Data Arrays. */
412 uint64_t sec_intena : 1; /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit
413 When set, allows interrupts to be reported on single bit
414 (correctable) errors from the L2 Data Arrays. */
415 uint64_t ecc_ena : 1; /**< L2 Data ECC Enable
416 When set, enables 10-bit SEC/DED codeword for 128bit L2
419 uint64_t ecc_ena : 1;
420 uint64_t sec_intena : 1;
421 uint64_t ded_intena : 1;
422 uint64_t sec_err : 1;
423 uint64_t ded_err : 1;
424 uint64_t bmhclsel : 1;
425 uint64_t reserved_6_63 : 58;
428 struct cvmx_l2d_err_s cn30xx;
429 struct cvmx_l2d_err_s cn31xx;
430 struct cvmx_l2d_err_s cn38xx;
431 struct cvmx_l2d_err_s cn38xxp2;
432 struct cvmx_l2d_err_s cn50xx;
433 struct cvmx_l2d_err_s cn52xx;
434 struct cvmx_l2d_err_s cn52xxp1;
435 struct cvmx_l2d_err_s cn56xx;
436 struct cvmx_l2d_err_s cn56xxp1;
437 struct cvmx_l2d_err_s cn58xx;
438 struct cvmx_l2d_err_s cn58xxp1;
440 typedef union cvmx_l2d_err cvmx_l2d_err_t;
445 * L2D_FADR = L2 Failing Address
447 * Description: L2 Data ECC SEC/DED Failing Address
450 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data store index.
451 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
456 struct cvmx_l2d_fadr_s
458 #if __BYTE_ORDER == __BIG_ENDIAN
459 uint64_t reserved_19_63 : 45;
460 uint64_t fadru : 1; /**< Failing L2 Data Store Upper Index bit(MSB) */
461 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
463 uint64_t fset : 3; /**< Failing SET# */
464 uint64_t fadr : 11; /**< Failing L2 Data Store Lower Index bits
465 (NOTE: L2 Data Store Index is for each 1/2 cacheline)
466 [FADRU, FADR[10:1]]: cacheline index[17:7]
467 FADR[0]: 1/2 cacheline index
468 NOTE: FADR[1] is used to select between upper/lower 1MB
469 physical L2 Data Store banks. */
475 uint64_t reserved_19_63 : 45;
478 struct cvmx_l2d_fadr_cn30xx
480 #if __BYTE_ORDER == __BIG_ENDIAN
481 uint64_t reserved_18_63 : 46;
482 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
484 uint64_t reserved_13_13 : 1;
485 uint64_t fset : 2; /**< Failing SET# */
486 uint64_t reserved_9_10 : 2;
487 uint64_t fadr : 9; /**< Failing L2 Data Store Index(1of512 = 1/2 CL address) */
490 uint64_t reserved_9_10 : 2;
492 uint64_t reserved_13_13 : 1;
494 uint64_t reserved_18_63 : 46;
497 struct cvmx_l2d_fadr_cn31xx
499 #if __BYTE_ORDER == __BIG_ENDIAN
500 uint64_t reserved_18_63 : 46;
501 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
503 uint64_t reserved_13_13 : 1;
504 uint64_t fset : 2; /**< Failing SET# */
505 uint64_t reserved_10_10 : 1;
506 uint64_t fadr : 10; /**< Failing L2 Data Store Index
507 (1 of 1024 = half cacheline indices) */
510 uint64_t reserved_10_10 : 1;
512 uint64_t reserved_13_13 : 1;
514 uint64_t reserved_18_63 : 46;
517 struct cvmx_l2d_fadr_cn38xx
519 #if __BYTE_ORDER == __BIG_ENDIAN
520 uint64_t reserved_18_63 : 46;
521 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
523 uint64_t fset : 3; /**< Failing SET# */
524 uint64_t fadr : 11; /**< Failing L2 Data Store Index (1of2K = 1/2 CL address) */
529 uint64_t reserved_18_63 : 46;
532 struct cvmx_l2d_fadr_cn38xx cn38xxp2;
533 struct cvmx_l2d_fadr_cn50xx
535 #if __BYTE_ORDER == __BIG_ENDIAN
536 uint64_t reserved_18_63 : 46;
537 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
539 uint64_t fset : 3; /**< Failing SET# */
540 uint64_t reserved_8_10 : 3;
541 uint64_t fadr : 8; /**< Failing L2 Data Store Lower Index bits
542 (NOTE: L2 Data Store Index is for each 1/2 cacheline)
543 FADR[7:1]: cacheline index[13:7]
544 FADR[0]: 1/2 cacheline index */
547 uint64_t reserved_8_10 : 3;
550 uint64_t reserved_18_63 : 46;
553 struct cvmx_l2d_fadr_cn52xx
555 #if __BYTE_ORDER == __BIG_ENDIAN
556 uint64_t reserved_18_63 : 46;
557 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
559 uint64_t fset : 3; /**< Failing SET# */
560 uint64_t reserved_10_10 : 1;
561 uint64_t fadr : 10; /**< Failing L2 Data Store Lower Index bits
562 (NOTE: L2 Data Store Index is for each 1/2 cacheline)
563 FADR[9:1]: cacheline index[15:7]
564 FADR[0]: 1/2 cacheline index */
567 uint64_t reserved_10_10 : 1;
570 uint64_t reserved_18_63 : 46;
573 struct cvmx_l2d_fadr_cn52xx cn52xxp1;
574 struct cvmx_l2d_fadr_s cn56xx;
575 struct cvmx_l2d_fadr_s cn56xxp1;
576 struct cvmx_l2d_fadr_s cn58xx;
577 struct cvmx_l2d_fadr_s cn58xxp1;
579 typedef union cvmx_l2d_fadr cvmx_l2d_fadr_t;
584 * L2D_FSYN0 = L2 Failing Syndrome [OW0,4 / OW1,5]
586 * Description: L2 Data ECC SEC/DED Failing Syndrome for lower cache line
589 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
590 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
595 struct cvmx_l2d_fsyn0_s
597 #if __BYTE_ORDER == __BIG_ENDIAN
598 uint64_t reserved_20_63 : 44;
599 uint64_t fsyn_ow1 : 10; /**< Failing L2 Data Store SYNDROME OW[1,5]
600 When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
601 or L2D_ERR[DED_ERR] are set, this field represents
602 the failing OWECC syndrome for the half cacheline
603 indexed by L2D_FADR[FADR].
604 NOTE: The L2D_FADR[FOWMSK] further qualifies which
605 OW lane(1of4) detected the error.
606 When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
607 command from the diagnostic PP will conditionally latch
608 the raw OWECC for the selected half cacheline.
609 (see: L2D_ERR[BMHCLSEL] */
610 uint64_t fsyn_ow0 : 10; /**< Failing L2 Data Store SYNDROME OW[0,4]
611 When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
612 or L2D_ERR[DED_ERR] are set, this field represents
613 the failing OWECC syndrome for the half cacheline
614 indexed by L2D_FADR[FADR].
615 NOTE: The L2D_FADR[FOWMSK] further qualifies which
616 OW lane(1of4) detected the error.
617 When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
618 (L1 load-miss) from the diagnostic PP will conditionally
619 latch the raw OWECC for the selected half cacheline.
620 (see: L2D_ERR[BMHCLSEL] */
622 uint64_t fsyn_ow0 : 10;
623 uint64_t fsyn_ow1 : 10;
624 uint64_t reserved_20_63 : 44;
627 struct cvmx_l2d_fsyn0_s cn30xx;
628 struct cvmx_l2d_fsyn0_s cn31xx;
629 struct cvmx_l2d_fsyn0_s cn38xx;
630 struct cvmx_l2d_fsyn0_s cn38xxp2;
631 struct cvmx_l2d_fsyn0_s cn50xx;
632 struct cvmx_l2d_fsyn0_s cn52xx;
633 struct cvmx_l2d_fsyn0_s cn52xxp1;
634 struct cvmx_l2d_fsyn0_s cn56xx;
635 struct cvmx_l2d_fsyn0_s cn56xxp1;
636 struct cvmx_l2d_fsyn0_s cn58xx;
637 struct cvmx_l2d_fsyn0_s cn58xxp1;
639 typedef union cvmx_l2d_fsyn0 cvmx_l2d_fsyn0_t;
644 * L2D_FSYN1 = L2 Failing Syndrome [OW2,6 / OW3,7]
646 * Description: L2 Data ECC SEC/DED Failing Syndrome for upper cache line
649 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
650 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
655 struct cvmx_l2d_fsyn1_s
657 #if __BYTE_ORDER == __BIG_ENDIAN
658 uint64_t reserved_20_63 : 44;
659 uint64_t fsyn_ow3 : 10; /**< Failing L2 Data Store SYNDROME OW[3,7] */
660 uint64_t fsyn_ow2 : 10; /**< Failing L2 Data Store SYNDROME OW[2,5] */
662 uint64_t fsyn_ow2 : 10;
663 uint64_t fsyn_ow3 : 10;
664 uint64_t reserved_20_63 : 44;
667 struct cvmx_l2d_fsyn1_s cn30xx;
668 struct cvmx_l2d_fsyn1_s cn31xx;
669 struct cvmx_l2d_fsyn1_s cn38xx;
670 struct cvmx_l2d_fsyn1_s cn38xxp2;
671 struct cvmx_l2d_fsyn1_s cn50xx;
672 struct cvmx_l2d_fsyn1_s cn52xx;
673 struct cvmx_l2d_fsyn1_s cn52xxp1;
674 struct cvmx_l2d_fsyn1_s cn56xx;
675 struct cvmx_l2d_fsyn1_s cn56xxp1;
676 struct cvmx_l2d_fsyn1_s cn58xx;
677 struct cvmx_l2d_fsyn1_s cn58xxp1;
679 typedef union cvmx_l2d_fsyn1 cvmx_l2d_fsyn1_t;
684 * L2D_FUS0 = L2C Data Store QUAD0 Fuse Register
690 struct cvmx_l2d_fus0_s
692 #if __BYTE_ORDER == __BIG_ENDIAN
693 uint64_t reserved_34_63 : 30;
694 uint64_t q0fus : 34; /**< Fuse Register for QUAD0
695 This is purely for debug and not needed in the general
697 Note that the fuse are complementary (Assigning a
698 fuse to 1 will read as a zero). This means the case
699 where no fuses are blown result in these csr's showing
701 Failure \#1 Fuse Mapping
703 [13:7] bad high column
705 Failure \#2 Fuse Mapping
707 [30:24] bad high column
708 [23:17] bad low column */
711 uint64_t reserved_34_63 : 30;
714 struct cvmx_l2d_fus0_s cn30xx;
715 struct cvmx_l2d_fus0_s cn31xx;
716 struct cvmx_l2d_fus0_s cn38xx;
717 struct cvmx_l2d_fus0_s cn38xxp2;
718 struct cvmx_l2d_fus0_s cn50xx;
719 struct cvmx_l2d_fus0_s cn52xx;
720 struct cvmx_l2d_fus0_s cn52xxp1;
721 struct cvmx_l2d_fus0_s cn56xx;
722 struct cvmx_l2d_fus0_s cn56xxp1;
723 struct cvmx_l2d_fus0_s cn58xx;
724 struct cvmx_l2d_fus0_s cn58xxp1;
726 typedef union cvmx_l2d_fus0 cvmx_l2d_fus0_t;
731 * L2D_FUS1 = L2C Data Store QUAD1 Fuse Register
737 struct cvmx_l2d_fus1_s
739 #if __BYTE_ORDER == __BIG_ENDIAN
740 uint64_t reserved_34_63 : 30;
741 uint64_t q1fus : 34; /**< Fuse Register for QUAD1
742 This is purely for debug and not needed in the general
744 Note that the fuse are complementary (Assigning a
745 fuse to 1 will read as a zero). This means the case
746 where no fuses are blown result in these csr's showing
748 Failure \#1 Fuse Mapping
750 [13:7] bad high column
752 Failure \#2 Fuse Mapping
754 [30:24] bad high column
755 [23:17] bad low column */
758 uint64_t reserved_34_63 : 30;
761 struct cvmx_l2d_fus1_s cn30xx;
762 struct cvmx_l2d_fus1_s cn31xx;
763 struct cvmx_l2d_fus1_s cn38xx;
764 struct cvmx_l2d_fus1_s cn38xxp2;
765 struct cvmx_l2d_fus1_s cn50xx;
766 struct cvmx_l2d_fus1_s cn52xx;
767 struct cvmx_l2d_fus1_s cn52xxp1;
768 struct cvmx_l2d_fus1_s cn56xx;
769 struct cvmx_l2d_fus1_s cn56xxp1;
770 struct cvmx_l2d_fus1_s cn58xx;
771 struct cvmx_l2d_fus1_s cn58xxp1;
773 typedef union cvmx_l2d_fus1 cvmx_l2d_fus1_t;
778 * L2D_FUS2 = L2C Data Store QUAD2 Fuse Register
784 struct cvmx_l2d_fus2_s
786 #if __BYTE_ORDER == __BIG_ENDIAN
787 uint64_t reserved_34_63 : 30;
788 uint64_t q2fus : 34; /**< Fuse Register for QUAD2
789 This is purely for debug and not needed in the general
791 Note that the fuse are complementary (Assigning a
792 fuse to 1 will read as a zero). This means the case
793 where no fuses are blown result in these csr's showing
795 Failure \#1 Fuse Mapping
797 [13:7] bad high column
799 Failure \#2 Fuse Mapping
801 [30:24] bad high column
802 [23:17] bad low column */
805 uint64_t reserved_34_63 : 30;
808 struct cvmx_l2d_fus2_s cn30xx;
809 struct cvmx_l2d_fus2_s cn31xx;
810 struct cvmx_l2d_fus2_s cn38xx;
811 struct cvmx_l2d_fus2_s cn38xxp2;
812 struct cvmx_l2d_fus2_s cn50xx;
813 struct cvmx_l2d_fus2_s cn52xx;
814 struct cvmx_l2d_fus2_s cn52xxp1;
815 struct cvmx_l2d_fus2_s cn56xx;
816 struct cvmx_l2d_fus2_s cn56xxp1;
817 struct cvmx_l2d_fus2_s cn58xx;
818 struct cvmx_l2d_fus2_s cn58xxp1;
820 typedef union cvmx_l2d_fus2 cvmx_l2d_fus2_t;
825 * L2D_FUS3 = L2C Data Store QUAD3 Fuse Register
831 struct cvmx_l2d_fus3_s
833 #if __BYTE_ORDER == __BIG_ENDIAN
834 uint64_t reserved_40_63 : 24;
835 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
836 These bits are used to 'observe' the EMA[1:0] inputs
837 for the L2 Data Store RAMs which are controlled by
838 either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
839 From poweron (dc_ok), the EMA_CTL are driven from
840 FUSE[141:140]. However after the 1st CSR write to the
841 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
842 from the MIO_FUSE_EMA[EMA] register permanently
844 uint64_t reserved_34_36 : 3;
845 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
846 This is purely for debug and not needed in the general
848 Note that the fuses are complementary (Assigning a
849 fuse to 1 will read as a zero). This means the case
850 where no fuses are blown result in these csr's showing
852 Failure \#1 Fuse Mapping
854 [13:7] bad high column
856 Failure \#2 Fuse Mapping
858 [30:24] bad high column
859 [23:17] bad low column */
862 uint64_t reserved_34_36 : 3;
863 uint64_t ema_ctl : 3;
864 uint64_t reserved_40_63 : 24;
867 struct cvmx_l2d_fus3_cn30xx
869 #if __BYTE_ORDER == __BIG_ENDIAN
870 uint64_t reserved_35_63 : 29;
871 uint64_t crip_64k : 1; /**< This is purely for debug and not needed in the general
873 If the FUSE is not-blown, then this bit should read
874 as 0. If the FUSE is blown, then this bit should read
876 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
877 This is purely for debug and not needed in the general
879 Note that the fuses are complementary (Assigning a
880 fuse to 1 will read as a zero). This means the case
881 where no fuses are blown result in these csr's showing
883 Failure \#1 Fuse Mapping
886 [13:7] bad high column
888 Failure \#2 Fuse Mapping
891 [30:24] bad high column
892 [23:17] bad low column */
895 uint64_t crip_64k : 1;
896 uint64_t reserved_35_63 : 29;
899 struct cvmx_l2d_fus3_cn31xx
901 #if __BYTE_ORDER == __BIG_ENDIAN
902 uint64_t reserved_35_63 : 29;
903 uint64_t crip_128k : 1; /**< This is purely for debug and not needed in the general
905 If the FUSE is not-blown, then this bit should read
906 as 0. If the FUSE is blown, then this bit should read
908 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
909 This is purely for debug and not needed in the general
911 Note that the fuses are complementary (Assigning a
912 fuse to 1 will read as a zero). This means the case
913 where no fuses are blown result in these csr's showing
915 Failure \#1 Fuse Mapping
918 [13:7] bad high column
920 Failure \#2 Fuse Mapping
923 [30:24] bad high column
924 [23:17] bad low column */
927 uint64_t crip_128k : 1;
928 uint64_t reserved_35_63 : 29;
931 struct cvmx_l2d_fus3_cn38xx
933 #if __BYTE_ORDER == __BIG_ENDIAN
934 uint64_t reserved_36_63 : 28;
935 uint64_t crip_256k : 1; /**< This is purely for debug and not needed in the general
937 If the FUSE is not-blown, then this bit should read
938 as 0. If the FUSE is blown, then this bit should read
940 *** NOTE: Pass2 Addition */
941 uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general
943 If the FUSE is not-blown, then this bit should read
944 as 0. If the FUSE is blown, then this bit should read
946 *** NOTE: Pass2 Addition */
947 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
948 This is purely for debug and not needed in the general
950 Note that the fuses are complementary (Assigning a
951 fuse to 1 will read as a zero). This means the case
952 where no fuses are blown result in these csr's showing
954 Failure \#1 Fuse Mapping
956 [13:7] bad high column
958 Failure \#2 Fuse Mapping
960 [30:24] bad high column
961 [23:17] bad low column */
964 uint64_t crip_512k : 1;
965 uint64_t crip_256k : 1;
966 uint64_t reserved_36_63 : 28;
969 struct cvmx_l2d_fus3_cn38xx cn38xxp2;
970 struct cvmx_l2d_fus3_cn50xx
972 #if __BYTE_ORDER == __BIG_ENDIAN
973 uint64_t reserved_40_63 : 24;
974 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
975 These bits are used to 'observe' the EMA[2:0] inputs
976 for the L2 Data Store RAMs which are controlled by
977 either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
978 From poweron (dc_ok), the EMA_CTL are driven from
979 FUSE[141:140]. However after the 1st CSR write to the
980 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
981 from the MIO_FUSE_EMA[EMA] register permanently
983 uint64_t reserved_36_36 : 1;
984 uint64_t crip_32k : 1; /**< This is purely for debug and not needed in the general
986 If the FUSE is not-blown, then this bit should read
987 as 0. If the FUSE is blown, then this bit should read
989 uint64_t crip_64k : 1; /**< This is purely for debug and not needed in the general
991 If the FUSE is not-blown, then this bit should read
992 as 0. If the FUSE is blown, then this bit should read
994 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
995 This is purely for debug and not needed in the general
997 Note that the fuses are complementary (Assigning a
998 fuse to 1 will read as a zero). This means the case
999 where no fuses are blown result in these csr's showing
1001 Failure \#1 Fuse Mapping
1002 [16:14] UNUSED (5020 uses single physical bank per quad)
1003 [13:7] bad high column
1004 [6:0] bad low column
1005 Failure \#2 Fuse Mapping
1006 [33:31] UNUSED (5020 uses single physical bank per quad)
1007 [30:24] bad high column
1008 [23:17] bad low column */
1010 uint64_t q3fus : 34;
1011 uint64_t crip_64k : 1;
1012 uint64_t crip_32k : 1;
1013 uint64_t reserved_36_36 : 1;
1014 uint64_t ema_ctl : 3;
1015 uint64_t reserved_40_63 : 24;
1018 struct cvmx_l2d_fus3_cn52xx
1020 #if __BYTE_ORDER == __BIG_ENDIAN
1021 uint64_t reserved_40_63 : 24;
1022 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
1023 These bits are used to 'observe' the EMA[2:0] inputs
1024 for the L2 Data Store RAMs which are controlled by
1025 either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
1026 From poweron (dc_ok), the EMA_CTL are driven from
1027 FUSE[141:140]. However after the 1st CSR write to the
1028 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
1029 from the MIO_FUSE_EMA[EMA] register permanently
1031 uint64_t reserved_36_36 : 1;
1032 uint64_t crip_128k : 1; /**< This is purely for debug and not needed in the general
1034 If the FUSE is not-blown, then this bit should read
1035 as 0. If the FUSE is blown, then this bit should read
1037 uint64_t crip_256k : 1; /**< This is purely for debug and not needed in the general
1039 If the FUSE is not-blown, then this bit should read
1040 as 0. If the FUSE is blown, then this bit should read
1042 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
1043 This is purely for debug and not needed in the general
1045 Note that the fuses are complementary (Assigning a
1046 fuse to 1 will read as a zero). This means the case
1047 where no fuses are blown result in these csr's showing
1049 Failure \#1 Fuse Mapping
1050 [16:14] UNUSED (5020 uses single physical bank per quad)
1051 [13:7] bad high column
1052 [6:0] bad low column
1053 Failure \#2 Fuse Mapping
1054 [33:31] UNUSED (5020 uses single physical bank per quad)
1055 [30:24] bad high column
1056 [23:17] bad low column */
1058 uint64_t q3fus : 34;
1059 uint64_t crip_256k : 1;
1060 uint64_t crip_128k : 1;
1061 uint64_t reserved_36_36 : 1;
1062 uint64_t ema_ctl : 3;
1063 uint64_t reserved_40_63 : 24;
1066 struct cvmx_l2d_fus3_cn52xx cn52xxp1;
1067 struct cvmx_l2d_fus3_cn56xx
1069 #if __BYTE_ORDER == __BIG_ENDIAN
1070 uint64_t reserved_40_63 : 24;
1071 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
1072 These bits are used to 'observe' the EMA[2:0] inputs
1073 for the L2 Data Store RAMs which are controlled by
1074 either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
1075 From poweron (dc_ok), the EMA_CTL are driven from
1076 FUSE[141:140]. However after the 1st CSR write to the
1077 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
1078 from the MIO_FUSE_EMA[EMA] register permanently
1080 uint64_t reserved_36_36 : 1;
1081 uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general
1083 If the FUSE is not-blown, then this bit should read
1084 as 0. If the FUSE is blown, then this bit should read
1086 *** NOTE: Pass2 Addition */
1087 uint64_t crip_1024k : 1; /**< This is purely for debug and not needed in the general
1089 If the FUSE is not-blown, then this bit should read
1090 as 0. If the FUSE is blown, then this bit should read
1092 *** NOTE: Pass2 Addition */
1093 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
1094 This is purely for debug and not needed in the general
1096 Note that the fuses are complementary (Assigning a
1097 fuse to 1 will read as a zero). This means the case
1098 where no fuses are blown result in these csr's showing
1100 Failure \#1 Fuse Mapping
1102 [13:7] bad high column
1103 [6:0] bad low column
1104 Failure \#2 Fuse Mapping
1106 [30:24] bad high column
1107 [23:17] bad low column */
1109 uint64_t q3fus : 34;
1110 uint64_t crip_1024k : 1;
1111 uint64_t crip_512k : 1;
1112 uint64_t reserved_36_36 : 1;
1113 uint64_t ema_ctl : 3;
1114 uint64_t reserved_40_63 : 24;
1117 struct cvmx_l2d_fus3_cn56xx cn56xxp1;
1118 struct cvmx_l2d_fus3_cn58xx
1120 #if __BYTE_ORDER == __BIG_ENDIAN
1121 uint64_t reserved_39_63 : 25;
1122 uint64_t ema_ctl : 2; /**< L2 Data Store EMA Control
1123 These bits are used to 'observe' the EMA[1:0] inputs
1124 for the L2 Data Store RAMs which are controlled by
1125 either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
1126 From poweron (dc_ok), the EMA_CTL are driven from
1127 FUSE[141:140]. However after the 1st CSR write to the
1128 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
1129 from the MIO_FUSE_EMA[EMA] register permanently
1131 uint64_t reserved_36_36 : 1;
1132 uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general
1134 If the FUSE is not-blown, then this bit should read
1135 as 0. If the FUSE is blown, then this bit should read
1137 *** NOTE: Pass2 Addition */
1138 uint64_t crip_1024k : 1; /**< This is purely for debug and not needed in the general
1140 If the FUSE is not-blown, then this bit should read
1141 as 0. If the FUSE is blown, then this bit should read
1143 *** NOTE: Pass2 Addition */
1144 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
1145 This is purely for debug and not needed in the general
1147 Note that the fuses are complementary (Assigning a
1148 fuse to 1 will read as a zero). This means the case
1149 where no fuses are blown result in these csr's showing
1151 Failure \#1 Fuse Mapping
1153 [13:7] bad high column
1154 [6:0] bad low column
1155 Failure \#2 Fuse Mapping
1157 [30:24] bad high column
1158 [23:17] bad low column */
1160 uint64_t q3fus : 34;
1161 uint64_t crip_1024k : 1;
1162 uint64_t crip_512k : 1;
1163 uint64_t reserved_36_36 : 1;
1164 uint64_t ema_ctl : 2;
1165 uint64_t reserved_39_63 : 25;
1168 struct cvmx_l2d_fus3_cn58xx cn58xxp1;
1170 typedef union cvmx_l2d_fus3 cvmx_l2d_fus3_t;