1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
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14 * copyright notice, this list of conditions and the following
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16 * with the distribution.
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37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_MIO_TYPEDEFS_H__
53 #define __CVMX_MIO_TYPEDEFS_H__
55 #define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
56 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
57 #define CVMX_MIO_BOOT_COMP CVMX_MIO_BOOT_COMP_FUNC()
58 static inline uint64_t CVMX_MIO_BOOT_COMP_FUNC(void)
60 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
61 cvmx_warn("CVMX_MIO_BOOT_COMP not supported on this chip\n");
62 return CVMX_ADD_IO_SEG(0x00011800000000B8ull);
65 #define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
67 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
68 static inline uint64_t CVMX_MIO_BOOT_DMA_CFGX(unsigned long offset)
71 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
72 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
73 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
74 cvmx_warn("CVMX_MIO_BOOT_DMA_CFGX(%lu) is invalid on this chip\n", offset);
75 return CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8;
78 #define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
80 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
81 static inline uint64_t CVMX_MIO_BOOT_DMA_INTX(unsigned long offset)
84 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
85 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
86 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
87 cvmx_warn("CVMX_MIO_BOOT_DMA_INTX(%lu) is invalid on this chip\n", offset);
88 return CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8;
91 #define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
93 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
94 static inline uint64_t CVMX_MIO_BOOT_DMA_INT_ENX(unsigned long offset)
97 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
98 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
99 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
100 cvmx_warn("CVMX_MIO_BOOT_DMA_INT_ENX(%lu) is invalid on this chip\n", offset);
101 return CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8;
104 #define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
106 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
107 static inline uint64_t CVMX_MIO_BOOT_DMA_TIMX(unsigned long offset)
110 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
111 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
112 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
113 cvmx_warn("CVMX_MIO_BOOT_DMA_TIMX(%lu) is invalid on this chip\n", offset);
114 return CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8;
117 #define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
119 #define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
120 #define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
121 #define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
122 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
123 static inline uint64_t CVMX_MIO_BOOT_LOC_CFGX(unsigned long offset)
126 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
127 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
128 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
129 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
130 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
131 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
132 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
133 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
134 cvmx_warn("CVMX_MIO_BOOT_LOC_CFGX(%lu) is invalid on this chip\n", offset);
135 return CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8;
138 #define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
140 #define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
141 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
142 #define CVMX_MIO_BOOT_PIN_DEFS CVMX_MIO_BOOT_PIN_DEFS_FUNC()
143 static inline uint64_t CVMX_MIO_BOOT_PIN_DEFS_FUNC(void)
145 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
146 cvmx_warn("CVMX_MIO_BOOT_PIN_DEFS not supported on this chip\n");
147 return CVMX_ADD_IO_SEG(0x00011800000000C0ull);
150 #define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
152 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
153 static inline uint64_t CVMX_MIO_BOOT_REG_CFGX(unsigned long offset)
156 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
157 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
158 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
159 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
160 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
161 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
162 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
163 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
164 cvmx_warn("CVMX_MIO_BOOT_REG_CFGX(%lu) is invalid on this chip\n", offset);
165 return CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8;
168 #define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
170 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
171 static inline uint64_t CVMX_MIO_BOOT_REG_TIMX(unsigned long offset)
174 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
175 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
176 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
177 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
178 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
179 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
181 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7)))))
182 cvmx_warn("CVMX_MIO_BOOT_REG_TIMX(%lu) is invalid on this chip\n", offset);
183 return CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8;
186 #define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
188 #define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
189 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
190 static inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset)
193 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
194 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
195 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
196 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
197 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
198 cvmx_warn("CVMX_MIO_FUS_BNK_DATX(%lu) is invalid on this chip\n", offset);
199 return CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8;
202 #define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
204 #define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
205 #define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
206 #define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
207 #define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
208 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
209 #define CVMX_MIO_FUS_EMA CVMX_MIO_FUS_EMA_FUNC()
210 static inline uint64_t CVMX_MIO_FUS_EMA_FUNC(void)
212 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
213 cvmx_warn("CVMX_MIO_FUS_EMA not supported on this chip\n");
214 return CVMX_ADD_IO_SEG(0x0001180000001550ull);
217 #define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
219 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
220 #define CVMX_MIO_FUS_PDF CVMX_MIO_FUS_PDF_FUNC()
221 static inline uint64_t CVMX_MIO_FUS_PDF_FUNC(void)
223 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
224 cvmx_warn("CVMX_MIO_FUS_PDF not supported on this chip\n");
225 return CVMX_ADD_IO_SEG(0x0001180000001420ull);
228 #define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
230 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
231 #define CVMX_MIO_FUS_PLL CVMX_MIO_FUS_PLL_FUNC()
232 static inline uint64_t CVMX_MIO_FUS_PLL_FUNC(void)
234 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
235 cvmx_warn("CVMX_MIO_FUS_PLL not supported on this chip\n");
236 return CVMX_ADD_IO_SEG(0x0001180000001580ull);
239 #define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
241 #define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
242 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
243 #define CVMX_MIO_FUS_PROG_TIMES CVMX_MIO_FUS_PROG_TIMES_FUNC()
244 static inline uint64_t CVMX_MIO_FUS_PROG_TIMES_FUNC(void)
246 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
247 cvmx_warn("CVMX_MIO_FUS_PROG_TIMES not supported on this chip\n");
248 return CVMX_ADD_IO_SEG(0x0001180000001518ull);
251 #define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
253 #define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
254 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
255 #define CVMX_MIO_FUS_READ_TIMES CVMX_MIO_FUS_READ_TIMES_FUNC()
256 static inline uint64_t CVMX_MIO_FUS_READ_TIMES_FUNC(void)
258 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
259 cvmx_warn("CVMX_MIO_FUS_READ_TIMES not supported on this chip\n");
260 return CVMX_ADD_IO_SEG(0x0001180000001570ull);
263 #define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
265 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
266 #define CVMX_MIO_FUS_REPAIR_RES0 CVMX_MIO_FUS_REPAIR_RES0_FUNC()
267 static inline uint64_t CVMX_MIO_FUS_REPAIR_RES0_FUNC(void)
269 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
270 cvmx_warn("CVMX_MIO_FUS_REPAIR_RES0 not supported on this chip\n");
271 return CVMX_ADD_IO_SEG(0x0001180000001558ull);
274 #define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
276 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
277 #define CVMX_MIO_FUS_REPAIR_RES1 CVMX_MIO_FUS_REPAIR_RES1_FUNC()
278 static inline uint64_t CVMX_MIO_FUS_REPAIR_RES1_FUNC(void)
280 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
281 cvmx_warn("CVMX_MIO_FUS_REPAIR_RES1 not supported on this chip\n");
282 return CVMX_ADD_IO_SEG(0x0001180000001560ull);
285 #define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
287 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
288 #define CVMX_MIO_FUS_REPAIR_RES2 CVMX_MIO_FUS_REPAIR_RES2_FUNC()
289 static inline uint64_t CVMX_MIO_FUS_REPAIR_RES2_FUNC(void)
291 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
292 cvmx_warn("CVMX_MIO_FUS_REPAIR_RES2 not supported on this chip\n");
293 return CVMX_ADD_IO_SEG(0x0001180000001568ull);
296 #define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
298 #define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
299 #define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
300 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
301 #define CVMX_MIO_FUS_UNLOCK CVMX_MIO_FUS_UNLOCK_FUNC()
302 static inline uint64_t CVMX_MIO_FUS_UNLOCK_FUNC(void)
304 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
305 cvmx_warn("CVMX_MIO_FUS_UNLOCK not supported on this chip\n");
306 return CVMX_ADD_IO_SEG(0x0001180000001578ull);
309 #define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
311 #define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
312 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
313 #define CVMX_MIO_GPIO_COMP CVMX_MIO_GPIO_COMP_FUNC()
314 static inline uint64_t CVMX_MIO_GPIO_COMP_FUNC(void)
316 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
317 cvmx_warn("CVMX_MIO_GPIO_COMP not supported on this chip\n");
318 return CVMX_ADD_IO_SEG(0x00011800000000C8ull);
321 #define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
323 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
324 #define CVMX_MIO_NDF_DMA_CFG CVMX_MIO_NDF_DMA_CFG_FUNC()
325 static inline uint64_t CVMX_MIO_NDF_DMA_CFG_FUNC(void)
327 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
328 cvmx_warn("CVMX_MIO_NDF_DMA_CFG not supported on this chip\n");
329 return CVMX_ADD_IO_SEG(0x0001180000000168ull);
332 #define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
334 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
335 #define CVMX_MIO_NDF_DMA_INT CVMX_MIO_NDF_DMA_INT_FUNC()
336 static inline uint64_t CVMX_MIO_NDF_DMA_INT_FUNC(void)
338 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
339 cvmx_warn("CVMX_MIO_NDF_DMA_INT not supported on this chip\n");
340 return CVMX_ADD_IO_SEG(0x0001180000000170ull);
343 #define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
345 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
346 #define CVMX_MIO_NDF_DMA_INT_EN CVMX_MIO_NDF_DMA_INT_EN_FUNC()
347 static inline uint64_t CVMX_MIO_NDF_DMA_INT_EN_FUNC(void)
349 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
350 cvmx_warn("CVMX_MIO_NDF_DMA_INT_EN not supported on this chip\n");
351 return CVMX_ADD_IO_SEG(0x0001180000000178ull);
354 #define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
356 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
357 #define CVMX_MIO_PLL_CTL CVMX_MIO_PLL_CTL_FUNC()
358 static inline uint64_t CVMX_MIO_PLL_CTL_FUNC(void)
360 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
361 cvmx_warn("CVMX_MIO_PLL_CTL not supported on this chip\n");
362 return CVMX_ADD_IO_SEG(0x0001180000001448ull);
365 #define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
367 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
368 #define CVMX_MIO_PLL_SETTING CVMX_MIO_PLL_SETTING_FUNC()
369 static inline uint64_t CVMX_MIO_PLL_SETTING_FUNC(void)
371 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
372 cvmx_warn("CVMX_MIO_PLL_SETTING not supported on this chip\n");
373 return CVMX_ADD_IO_SEG(0x0001180000001440ull);
376 #define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
378 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
379 #define CVMX_MIO_PTP_CLOCK_CFG CVMX_MIO_PTP_CLOCK_CFG_FUNC()
380 static inline uint64_t CVMX_MIO_PTP_CLOCK_CFG_FUNC(void)
382 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
383 cvmx_warn("CVMX_MIO_PTP_CLOCK_CFG not supported on this chip\n");
384 return CVMX_ADD_IO_SEG(0x0001070000000F00ull);
387 #define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
389 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
390 #define CVMX_MIO_PTP_CLOCK_COMP CVMX_MIO_PTP_CLOCK_COMP_FUNC()
391 static inline uint64_t CVMX_MIO_PTP_CLOCK_COMP_FUNC(void)
393 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
394 cvmx_warn("CVMX_MIO_PTP_CLOCK_COMP not supported on this chip\n");
395 return CVMX_ADD_IO_SEG(0x0001070000000F18ull);
398 #define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
400 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
401 #define CVMX_MIO_PTP_CLOCK_HI CVMX_MIO_PTP_CLOCK_HI_FUNC()
402 static inline uint64_t CVMX_MIO_PTP_CLOCK_HI_FUNC(void)
404 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
405 cvmx_warn("CVMX_MIO_PTP_CLOCK_HI not supported on this chip\n");
406 return CVMX_ADD_IO_SEG(0x0001070000000F10ull);
409 #define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
411 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
412 #define CVMX_MIO_PTP_CLOCK_LO CVMX_MIO_PTP_CLOCK_LO_FUNC()
413 static inline uint64_t CVMX_MIO_PTP_CLOCK_LO_FUNC(void)
415 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
416 cvmx_warn("CVMX_MIO_PTP_CLOCK_LO not supported on this chip\n");
417 return CVMX_ADD_IO_SEG(0x0001070000000F08ull);
420 #define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
422 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
423 #define CVMX_MIO_PTP_EVT_CNT CVMX_MIO_PTP_EVT_CNT_FUNC()
424 static inline uint64_t CVMX_MIO_PTP_EVT_CNT_FUNC(void)
426 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
427 cvmx_warn("CVMX_MIO_PTP_EVT_CNT not supported on this chip\n");
428 return CVMX_ADD_IO_SEG(0x0001070000000F28ull);
431 #define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
433 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
434 #define CVMX_MIO_PTP_TIMESTAMP CVMX_MIO_PTP_TIMESTAMP_FUNC()
435 static inline uint64_t CVMX_MIO_PTP_TIMESTAMP_FUNC(void)
437 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
438 cvmx_warn("CVMX_MIO_PTP_TIMESTAMP not supported on this chip\n");
439 return CVMX_ADD_IO_SEG(0x0001070000000F20ull);
442 #define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
444 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
445 #define CVMX_MIO_RST_BOOT CVMX_MIO_RST_BOOT_FUNC()
446 static inline uint64_t CVMX_MIO_RST_BOOT_FUNC(void)
448 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
449 cvmx_warn("CVMX_MIO_RST_BOOT not supported on this chip\n");
450 return CVMX_ADD_IO_SEG(0x0001180000001600ull);
453 #define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
455 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
456 #define CVMX_MIO_RST_CFG CVMX_MIO_RST_CFG_FUNC()
457 static inline uint64_t CVMX_MIO_RST_CFG_FUNC(void)
459 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
460 cvmx_warn("CVMX_MIO_RST_CFG not supported on this chip\n");
461 return CVMX_ADD_IO_SEG(0x0001180000001610ull);
464 #define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
466 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
467 static inline uint64_t CVMX_MIO_RST_CTLX(unsigned long offset)
470 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
471 cvmx_warn("CVMX_MIO_RST_CTLX(%lu) is invalid on this chip\n", offset);
472 return CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8;
475 #define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
477 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
478 #define CVMX_MIO_RST_DELAY CVMX_MIO_RST_DELAY_FUNC()
479 static inline uint64_t CVMX_MIO_RST_DELAY_FUNC(void)
481 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
482 cvmx_warn("CVMX_MIO_RST_DELAY not supported on this chip\n");
483 return CVMX_ADD_IO_SEG(0x0001180000001608ull);
486 #define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
488 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
489 #define CVMX_MIO_RST_INT CVMX_MIO_RST_INT_FUNC()
490 static inline uint64_t CVMX_MIO_RST_INT_FUNC(void)
492 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
493 cvmx_warn("CVMX_MIO_RST_INT not supported on this chip\n");
494 return CVMX_ADD_IO_SEG(0x0001180000001628ull);
497 #define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
499 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
500 #define CVMX_MIO_RST_INT_EN CVMX_MIO_RST_INT_EN_FUNC()
501 static inline uint64_t CVMX_MIO_RST_INT_EN_FUNC(void)
503 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
504 cvmx_warn("CVMX_MIO_RST_INT_EN not supported on this chip\n");
505 return CVMX_ADD_IO_SEG(0x0001180000001630ull);
508 #define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
510 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
511 static inline uint64_t CVMX_MIO_TWSX_INT(unsigned long offset)
514 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
515 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
516 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
517 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
518 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
519 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
520 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
521 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
522 cvmx_warn("CVMX_MIO_TWSX_INT(%lu) is invalid on this chip\n", offset);
523 return CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512;
526 #define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
528 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
529 static inline uint64_t CVMX_MIO_TWSX_SW_TWSI(unsigned long offset)
532 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
533 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
534 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
535 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
536 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
537 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
538 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
539 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
540 cvmx_warn("CVMX_MIO_TWSX_SW_TWSI(%lu) is invalid on this chip\n", offset);
541 return CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512;
544 #define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
546 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
547 static inline uint64_t CVMX_MIO_TWSX_SW_TWSI_EXT(unsigned long offset)
550 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
551 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
552 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
553 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
554 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
555 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
556 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
557 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
558 cvmx_warn("CVMX_MIO_TWSX_SW_TWSI_EXT(%lu) is invalid on this chip\n", offset);
559 return CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512;
562 #define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
564 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
565 static inline uint64_t CVMX_MIO_TWSX_TWSI_SW(unsigned long offset)
568 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
569 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
570 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
571 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
572 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
573 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
574 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
575 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
576 cvmx_warn("CVMX_MIO_TWSX_TWSI_SW(%lu) is invalid on this chip\n", offset);
577 return CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512;
580 #define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
582 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
583 #define CVMX_MIO_UART2_DLH CVMX_MIO_UART2_DLH_FUNC()
584 static inline uint64_t CVMX_MIO_UART2_DLH_FUNC(void)
586 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
587 cvmx_warn("CVMX_MIO_UART2_DLH not supported on this chip\n");
588 return CVMX_ADD_IO_SEG(0x0001180000000488ull);
591 #define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
593 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
594 #define CVMX_MIO_UART2_DLL CVMX_MIO_UART2_DLL_FUNC()
595 static inline uint64_t CVMX_MIO_UART2_DLL_FUNC(void)
597 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
598 cvmx_warn("CVMX_MIO_UART2_DLL not supported on this chip\n");
599 return CVMX_ADD_IO_SEG(0x0001180000000480ull);
602 #define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
604 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
605 #define CVMX_MIO_UART2_FAR CVMX_MIO_UART2_FAR_FUNC()
606 static inline uint64_t CVMX_MIO_UART2_FAR_FUNC(void)
608 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
609 cvmx_warn("CVMX_MIO_UART2_FAR not supported on this chip\n");
610 return CVMX_ADD_IO_SEG(0x0001180000000520ull);
613 #define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
615 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
616 #define CVMX_MIO_UART2_FCR CVMX_MIO_UART2_FCR_FUNC()
617 static inline uint64_t CVMX_MIO_UART2_FCR_FUNC(void)
619 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
620 cvmx_warn("CVMX_MIO_UART2_FCR not supported on this chip\n");
621 return CVMX_ADD_IO_SEG(0x0001180000000450ull);
624 #define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
626 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
627 #define CVMX_MIO_UART2_HTX CVMX_MIO_UART2_HTX_FUNC()
628 static inline uint64_t CVMX_MIO_UART2_HTX_FUNC(void)
630 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
631 cvmx_warn("CVMX_MIO_UART2_HTX not supported on this chip\n");
632 return CVMX_ADD_IO_SEG(0x0001180000000708ull);
635 #define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
637 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
638 #define CVMX_MIO_UART2_IER CVMX_MIO_UART2_IER_FUNC()
639 static inline uint64_t CVMX_MIO_UART2_IER_FUNC(void)
641 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
642 cvmx_warn("CVMX_MIO_UART2_IER not supported on this chip\n");
643 return CVMX_ADD_IO_SEG(0x0001180000000408ull);
646 #define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
648 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
649 #define CVMX_MIO_UART2_IIR CVMX_MIO_UART2_IIR_FUNC()
650 static inline uint64_t CVMX_MIO_UART2_IIR_FUNC(void)
652 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
653 cvmx_warn("CVMX_MIO_UART2_IIR not supported on this chip\n");
654 return CVMX_ADD_IO_SEG(0x0001180000000410ull);
657 #define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
659 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
660 #define CVMX_MIO_UART2_LCR CVMX_MIO_UART2_LCR_FUNC()
661 static inline uint64_t CVMX_MIO_UART2_LCR_FUNC(void)
663 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
664 cvmx_warn("CVMX_MIO_UART2_LCR not supported on this chip\n");
665 return CVMX_ADD_IO_SEG(0x0001180000000418ull);
668 #define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
670 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
671 #define CVMX_MIO_UART2_LSR CVMX_MIO_UART2_LSR_FUNC()
672 static inline uint64_t CVMX_MIO_UART2_LSR_FUNC(void)
674 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
675 cvmx_warn("CVMX_MIO_UART2_LSR not supported on this chip\n");
676 return CVMX_ADD_IO_SEG(0x0001180000000428ull);
679 #define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
681 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
682 #define CVMX_MIO_UART2_MCR CVMX_MIO_UART2_MCR_FUNC()
683 static inline uint64_t CVMX_MIO_UART2_MCR_FUNC(void)
685 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
686 cvmx_warn("CVMX_MIO_UART2_MCR not supported on this chip\n");
687 return CVMX_ADD_IO_SEG(0x0001180000000420ull);
690 #define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
692 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
693 #define CVMX_MIO_UART2_MSR CVMX_MIO_UART2_MSR_FUNC()
694 static inline uint64_t CVMX_MIO_UART2_MSR_FUNC(void)
696 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
697 cvmx_warn("CVMX_MIO_UART2_MSR not supported on this chip\n");
698 return CVMX_ADD_IO_SEG(0x0001180000000430ull);
701 #define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
703 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
704 #define CVMX_MIO_UART2_RBR CVMX_MIO_UART2_RBR_FUNC()
705 static inline uint64_t CVMX_MIO_UART2_RBR_FUNC(void)
707 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
708 cvmx_warn("CVMX_MIO_UART2_RBR not supported on this chip\n");
709 return CVMX_ADD_IO_SEG(0x0001180000000400ull);
712 #define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
714 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
715 #define CVMX_MIO_UART2_RFL CVMX_MIO_UART2_RFL_FUNC()
716 static inline uint64_t CVMX_MIO_UART2_RFL_FUNC(void)
718 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
719 cvmx_warn("CVMX_MIO_UART2_RFL not supported on this chip\n");
720 return CVMX_ADD_IO_SEG(0x0001180000000608ull);
723 #define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
725 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
726 #define CVMX_MIO_UART2_RFW CVMX_MIO_UART2_RFW_FUNC()
727 static inline uint64_t CVMX_MIO_UART2_RFW_FUNC(void)
729 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
730 cvmx_warn("CVMX_MIO_UART2_RFW not supported on this chip\n");
731 return CVMX_ADD_IO_SEG(0x0001180000000530ull);
734 #define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
736 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
737 #define CVMX_MIO_UART2_SBCR CVMX_MIO_UART2_SBCR_FUNC()
738 static inline uint64_t CVMX_MIO_UART2_SBCR_FUNC(void)
740 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
741 cvmx_warn("CVMX_MIO_UART2_SBCR not supported on this chip\n");
742 return CVMX_ADD_IO_SEG(0x0001180000000620ull);
745 #define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
747 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
748 #define CVMX_MIO_UART2_SCR CVMX_MIO_UART2_SCR_FUNC()
749 static inline uint64_t CVMX_MIO_UART2_SCR_FUNC(void)
751 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
752 cvmx_warn("CVMX_MIO_UART2_SCR not supported on this chip\n");
753 return CVMX_ADD_IO_SEG(0x0001180000000438ull);
756 #define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
758 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
759 #define CVMX_MIO_UART2_SFE CVMX_MIO_UART2_SFE_FUNC()
760 static inline uint64_t CVMX_MIO_UART2_SFE_FUNC(void)
762 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
763 cvmx_warn("CVMX_MIO_UART2_SFE not supported on this chip\n");
764 return CVMX_ADD_IO_SEG(0x0001180000000630ull);
767 #define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
769 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
770 #define CVMX_MIO_UART2_SRR CVMX_MIO_UART2_SRR_FUNC()
771 static inline uint64_t CVMX_MIO_UART2_SRR_FUNC(void)
773 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
774 cvmx_warn("CVMX_MIO_UART2_SRR not supported on this chip\n");
775 return CVMX_ADD_IO_SEG(0x0001180000000610ull);
778 #define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
780 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
781 #define CVMX_MIO_UART2_SRT CVMX_MIO_UART2_SRT_FUNC()
782 static inline uint64_t CVMX_MIO_UART2_SRT_FUNC(void)
784 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
785 cvmx_warn("CVMX_MIO_UART2_SRT not supported on this chip\n");
786 return CVMX_ADD_IO_SEG(0x0001180000000638ull);
789 #define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
791 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
792 #define CVMX_MIO_UART2_SRTS CVMX_MIO_UART2_SRTS_FUNC()
793 static inline uint64_t CVMX_MIO_UART2_SRTS_FUNC(void)
795 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
796 cvmx_warn("CVMX_MIO_UART2_SRTS not supported on this chip\n");
797 return CVMX_ADD_IO_SEG(0x0001180000000618ull);
800 #define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
802 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
803 #define CVMX_MIO_UART2_STT CVMX_MIO_UART2_STT_FUNC()
804 static inline uint64_t CVMX_MIO_UART2_STT_FUNC(void)
806 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
807 cvmx_warn("CVMX_MIO_UART2_STT not supported on this chip\n");
808 return CVMX_ADD_IO_SEG(0x0001180000000700ull);
811 #define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
813 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
814 #define CVMX_MIO_UART2_TFL CVMX_MIO_UART2_TFL_FUNC()
815 static inline uint64_t CVMX_MIO_UART2_TFL_FUNC(void)
817 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
818 cvmx_warn("CVMX_MIO_UART2_TFL not supported on this chip\n");
819 return CVMX_ADD_IO_SEG(0x0001180000000600ull);
822 #define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
824 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
825 #define CVMX_MIO_UART2_TFR CVMX_MIO_UART2_TFR_FUNC()
826 static inline uint64_t CVMX_MIO_UART2_TFR_FUNC(void)
828 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
829 cvmx_warn("CVMX_MIO_UART2_TFR not supported on this chip\n");
830 return CVMX_ADD_IO_SEG(0x0001180000000528ull);
833 #define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
835 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
836 #define CVMX_MIO_UART2_THR CVMX_MIO_UART2_THR_FUNC()
837 static inline uint64_t CVMX_MIO_UART2_THR_FUNC(void)
839 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
840 cvmx_warn("CVMX_MIO_UART2_THR not supported on this chip\n");
841 return CVMX_ADD_IO_SEG(0x0001180000000440ull);
844 #define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
846 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
847 #define CVMX_MIO_UART2_USR CVMX_MIO_UART2_USR_FUNC()
848 static inline uint64_t CVMX_MIO_UART2_USR_FUNC(void)
850 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
851 cvmx_warn("CVMX_MIO_UART2_USR not supported on this chip\n");
852 return CVMX_ADD_IO_SEG(0x0001180000000538ull);
855 #define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
857 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
858 static inline uint64_t CVMX_MIO_UARTX_DLH(unsigned long offset)
861 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
862 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
863 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
864 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
865 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
866 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
867 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
868 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
869 cvmx_warn("CVMX_MIO_UARTX_DLH(%lu) is invalid on this chip\n", offset);
870 return CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024;
873 #define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
875 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
876 static inline uint64_t CVMX_MIO_UARTX_DLL(unsigned long offset)
879 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
880 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
881 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
882 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
883 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
884 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
885 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
886 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
887 cvmx_warn("CVMX_MIO_UARTX_DLL(%lu) is invalid on this chip\n", offset);
888 return CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024;
891 #define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
893 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
894 static inline uint64_t CVMX_MIO_UARTX_FAR(unsigned long offset)
897 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
898 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
899 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
900 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
901 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
902 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
903 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
904 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
905 cvmx_warn("CVMX_MIO_UARTX_FAR(%lu) is invalid on this chip\n", offset);
906 return CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024;
909 #define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
911 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
912 static inline uint64_t CVMX_MIO_UARTX_FCR(unsigned long offset)
915 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
916 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
917 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
918 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
919 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
920 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
921 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
922 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
923 cvmx_warn("CVMX_MIO_UARTX_FCR(%lu) is invalid on this chip\n", offset);
924 return CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024;
927 #define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
929 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
930 static inline uint64_t CVMX_MIO_UARTX_HTX(unsigned long offset)
933 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
934 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
935 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
936 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
937 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
938 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
939 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
940 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
941 cvmx_warn("CVMX_MIO_UARTX_HTX(%lu) is invalid on this chip\n", offset);
942 return CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024;
945 #define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
947 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
948 static inline uint64_t CVMX_MIO_UARTX_IER(unsigned long offset)
951 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
952 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
953 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
954 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
955 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
956 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
957 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
958 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
959 cvmx_warn("CVMX_MIO_UARTX_IER(%lu) is invalid on this chip\n", offset);
960 return CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024;
963 #define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
965 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
966 static inline uint64_t CVMX_MIO_UARTX_IIR(unsigned long offset)
969 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
970 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
971 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
972 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
973 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
974 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
975 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
976 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
977 cvmx_warn("CVMX_MIO_UARTX_IIR(%lu) is invalid on this chip\n", offset);
978 return CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024;
981 #define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
983 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
984 static inline uint64_t CVMX_MIO_UARTX_LCR(unsigned long offset)
987 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
988 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
989 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
990 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
991 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
992 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
993 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
994 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
995 cvmx_warn("CVMX_MIO_UARTX_LCR(%lu) is invalid on this chip\n", offset);
996 return CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024;
999 #define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
1001 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1002 static inline uint64_t CVMX_MIO_UARTX_LSR(unsigned long offset)
1005 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1006 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1007 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1008 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1009 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1010 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1011 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1012 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1013 cvmx_warn("CVMX_MIO_UARTX_LSR(%lu) is invalid on this chip\n", offset);
1014 return CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024;
1017 #define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
1019 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1020 static inline uint64_t CVMX_MIO_UARTX_MCR(unsigned long offset)
1023 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1024 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1025 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1026 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1027 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1028 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1029 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1030 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1031 cvmx_warn("CVMX_MIO_UARTX_MCR(%lu) is invalid on this chip\n", offset);
1032 return CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024;
1035 #define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
1037 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1038 static inline uint64_t CVMX_MIO_UARTX_MSR(unsigned long offset)
1041 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1042 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1043 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1044 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1045 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1046 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1047 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1048 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1049 cvmx_warn("CVMX_MIO_UARTX_MSR(%lu) is invalid on this chip\n", offset);
1050 return CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024;
1053 #define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
1055 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1056 static inline uint64_t CVMX_MIO_UARTX_RBR(unsigned long offset)
1059 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1060 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1061 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1062 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1063 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1064 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1065 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1066 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1067 cvmx_warn("CVMX_MIO_UARTX_RBR(%lu) is invalid on this chip\n", offset);
1068 return CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024;
1071 #define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
1073 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1074 static inline uint64_t CVMX_MIO_UARTX_RFL(unsigned long offset)
1077 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1078 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1079 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1080 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1081 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1082 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1083 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1084 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1085 cvmx_warn("CVMX_MIO_UARTX_RFL(%lu) is invalid on this chip\n", offset);
1086 return CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024;
1089 #define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
1091 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1092 static inline uint64_t CVMX_MIO_UARTX_RFW(unsigned long offset)
1095 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1096 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1097 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1098 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1099 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1100 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1101 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1102 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1103 cvmx_warn("CVMX_MIO_UARTX_RFW(%lu) is invalid on this chip\n", offset);
1104 return CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024;
1107 #define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
1109 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1110 static inline uint64_t CVMX_MIO_UARTX_SBCR(unsigned long offset)
1113 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1114 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1115 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1116 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1117 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1118 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1119 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1120 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1121 cvmx_warn("CVMX_MIO_UARTX_SBCR(%lu) is invalid on this chip\n", offset);
1122 return CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024;
1125 #define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
1127 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1128 static inline uint64_t CVMX_MIO_UARTX_SCR(unsigned long offset)
1131 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1132 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1133 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1134 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1135 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1136 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1137 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1138 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1139 cvmx_warn("CVMX_MIO_UARTX_SCR(%lu) is invalid on this chip\n", offset);
1140 return CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024;
1143 #define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
1145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1146 static inline uint64_t CVMX_MIO_UARTX_SFE(unsigned long offset)
1149 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1150 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1151 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1152 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1153 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1154 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1155 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1156 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1157 cvmx_warn("CVMX_MIO_UARTX_SFE(%lu) is invalid on this chip\n", offset);
1158 return CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024;
1161 #define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
1163 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1164 static inline uint64_t CVMX_MIO_UARTX_SRR(unsigned long offset)
1167 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1168 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1169 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1170 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1171 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1172 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1173 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1174 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1175 cvmx_warn("CVMX_MIO_UARTX_SRR(%lu) is invalid on this chip\n", offset);
1176 return CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024;
1179 #define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
1181 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1182 static inline uint64_t CVMX_MIO_UARTX_SRT(unsigned long offset)
1185 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1186 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1187 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1188 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1189 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1190 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1191 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1192 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1193 cvmx_warn("CVMX_MIO_UARTX_SRT(%lu) is invalid on this chip\n", offset);
1194 return CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024;
1197 #define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
1199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1200 static inline uint64_t CVMX_MIO_UARTX_SRTS(unsigned long offset)
1203 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1204 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1205 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1206 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1207 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1208 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1209 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1210 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1211 cvmx_warn("CVMX_MIO_UARTX_SRTS(%lu) is invalid on this chip\n", offset);
1212 return CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024;
1215 #define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
1217 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1218 static inline uint64_t CVMX_MIO_UARTX_STT(unsigned long offset)
1221 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1222 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1223 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1224 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1225 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1226 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1227 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1228 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1229 cvmx_warn("CVMX_MIO_UARTX_STT(%lu) is invalid on this chip\n", offset);
1230 return CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024;
1233 #define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
1235 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1236 static inline uint64_t CVMX_MIO_UARTX_TFL(unsigned long offset)
1239 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1241 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1242 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1243 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1244 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1245 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1246 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1247 cvmx_warn("CVMX_MIO_UARTX_TFL(%lu) is invalid on this chip\n", offset);
1248 return CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024;
1251 #define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
1253 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1254 static inline uint64_t CVMX_MIO_UARTX_TFR(unsigned long offset)
1257 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1258 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1259 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1260 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1261 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1262 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1263 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1264 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1265 cvmx_warn("CVMX_MIO_UARTX_TFR(%lu) is invalid on this chip\n", offset);
1266 return CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024;
1269 #define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
1271 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1272 static inline uint64_t CVMX_MIO_UARTX_THR(unsigned long offset)
1275 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1276 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1277 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1278 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1279 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1280 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1281 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1282 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1283 cvmx_warn("CVMX_MIO_UARTX_THR(%lu) is invalid on this chip\n", offset);
1284 return CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024;
1287 #define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
1289 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1290 static inline uint64_t CVMX_MIO_UARTX_USR(unsigned long offset)
1293 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1294 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1295 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1296 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1297 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1298 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1299 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1300 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1301 cvmx_warn("CVMX_MIO_UARTX_USR(%lu) is invalid on this chip\n", offset);
1302 return CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024;
1305 #define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
1309 * cvmx_mio_boot_bist_stat
1311 * MIO_BOOT_BIST_STAT = MIO Boot BIST Status Register
1313 * Contains the BIST status for the MIO boot memories. '0' = pass, '1' = fail.
1315 union cvmx_mio_boot_bist_stat
1318 struct cvmx_mio_boot_bist_stat_s
1320 #if __BYTE_ORDER == __BIG_ENDIAN
1321 uint64_t reserved_0_63 : 64;
1323 uint64_t reserved_0_63 : 64;
1326 struct cvmx_mio_boot_bist_stat_cn30xx
1328 #if __BYTE_ORDER == __BIG_ENDIAN
1329 uint64_t reserved_4_63 : 60;
1330 uint64_t ncbo_1 : 1; /**< NCB output FIFO 1 BIST status */
1331 uint64_t ncbo_0 : 1; /**< NCB output FIFO 0 BIST status */
1332 uint64_t loc : 1; /**< Local memory BIST status */
1333 uint64_t ncbi : 1; /**< NCB input FIFO BIST status */
1337 uint64_t ncbo_0 : 1;
1338 uint64_t ncbo_1 : 1;
1339 uint64_t reserved_4_63 : 60;
1342 struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
1343 struct cvmx_mio_boot_bist_stat_cn38xx
1345 #if __BYTE_ORDER == __BIG_ENDIAN
1346 uint64_t reserved_3_63 : 61;
1347 uint64_t ncbo_0 : 1; /**< NCB output FIFO BIST status */
1348 uint64_t loc : 1; /**< Local memory BIST status */
1349 uint64_t ncbi : 1; /**< NCB input FIFO BIST status */
1353 uint64_t ncbo_0 : 1;
1354 uint64_t reserved_3_63 : 61;
1357 struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
1358 struct cvmx_mio_boot_bist_stat_cn50xx
1360 #if __BYTE_ORDER == __BIG_ENDIAN
1361 uint64_t reserved_6_63 : 58;
1362 uint64_t pcm_1 : 1; /**< PCM memory 1 BIST status */
1363 uint64_t pcm_0 : 1; /**< PCM memory 0 BIST status */
1364 uint64_t ncbo_1 : 1; /**< NCB output FIFO 1 BIST status */
1365 uint64_t ncbo_0 : 1; /**< NCB output FIFO 0 BIST status */
1366 uint64_t loc : 1; /**< Local memory BIST status */
1367 uint64_t ncbi : 1; /**< NCB input FIFO BIST status */
1371 uint64_t ncbo_0 : 1;
1372 uint64_t ncbo_1 : 1;
1375 uint64_t reserved_6_63 : 58;
1378 struct cvmx_mio_boot_bist_stat_cn52xx
1380 #if __BYTE_ORDER == __BIG_ENDIAN
1381 uint64_t reserved_6_63 : 58;
1382 uint64_t ndf : 2; /**< NAND flash BIST status */
1383 uint64_t ncbo_0 : 1; /**< NCB output FIFO BIST status */
1384 uint64_t dma : 1; /**< DMA memory BIST status */
1385 uint64_t loc : 1; /**< Local memory BIST status */
1386 uint64_t ncbi : 1; /**< NCB input FIFO BIST status */
1391 uint64_t ncbo_0 : 1;
1393 uint64_t reserved_6_63 : 58;
1396 struct cvmx_mio_boot_bist_stat_cn52xxp1
1398 #if __BYTE_ORDER == __BIG_ENDIAN
1399 uint64_t reserved_4_63 : 60;
1400 uint64_t ncbo_0 : 1; /**< NCB output FIFO BIST status */
1401 uint64_t dma : 1; /**< DMA memory BIST status */
1402 uint64_t loc : 1; /**< Local memory BIST status */
1403 uint64_t ncbi : 1; /**< NCB input FIFO BIST status */
1408 uint64_t ncbo_0 : 1;
1409 uint64_t reserved_4_63 : 60;
1412 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx;
1413 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
1414 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
1415 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
1416 struct cvmx_mio_boot_bist_stat_cn63xx
1418 #if __BYTE_ORDER == __BIG_ENDIAN
1419 uint64_t reserved_9_63 : 55;
1420 uint64_t stat : 9; /**< BIST status */
1423 uint64_t reserved_9_63 : 55;
1426 struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
1428 typedef union cvmx_mio_boot_bist_stat cvmx_mio_boot_bist_stat_t;
1431 * cvmx_mio_boot_comp
1433 * MIO_BOOT_COMP = MIO Boot Compensation Register
1435 * Reset value is as follows:
1437 * no pullups, PCTL=38, NCTL=30 (25 ohm termination)
1438 * pullup on boot_ad[9], PCTL=19, NCTL=15 (50 ohm termination)
1439 * pullup on boot_ad[10], PCTL=15, NCTL=12 (65 ohm termination)
1440 * pullups on boot_ad[10:9], PCTL=15, NCTL=12 (65 ohm termination)
1442 union cvmx_mio_boot_comp
1445 struct cvmx_mio_boot_comp_s
1447 #if __BYTE_ORDER == __BIG_ENDIAN
1448 uint64_t reserved_0_63 : 64;
1450 uint64_t reserved_0_63 : 64;
1453 struct cvmx_mio_boot_comp_cn50xx
1455 #if __BYTE_ORDER == __BIG_ENDIAN
1456 uint64_t reserved_10_63 : 54;
1457 uint64_t pctl : 5; /**< Boot bus PCTL */
1458 uint64_t nctl : 5; /**< Boot bus NCTL */
1462 uint64_t reserved_10_63 : 54;
1465 struct cvmx_mio_boot_comp_cn50xx cn52xx;
1466 struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
1467 struct cvmx_mio_boot_comp_cn50xx cn56xx;
1468 struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
1469 struct cvmx_mio_boot_comp_cn63xx
1471 #if __BYTE_ORDER == __BIG_ENDIAN
1472 uint64_t reserved_12_63 : 52;
1473 uint64_t pctl : 6; /**< Boot bus PCTL */
1474 uint64_t nctl : 6; /**< Boot bus NCTL */
1478 uint64_t reserved_12_63 : 52;
1481 struct cvmx_mio_boot_comp_cn63xx cn63xxp1;
1483 typedef union cvmx_mio_boot_comp cvmx_mio_boot_comp_t;
1486 * cvmx_mio_boot_dma_cfg#
1488 * MIO_BOOT_DMA_CFG = MIO Boot DMA Config Register (1 per engine * 2 engines)
1490 * SIZE is specified in number of bus transfers, where one transfer is equal to the following number
1491 * of bytes dependent on MIO_BOOT_DMA_TIMn[WIDTH] and MIO_BOOT_DMA_TIMn[DDR]:
1493 * WIDTH DDR Transfer Size (bytes)
1494 * ----------------------------------------
1500 * Note: ADR must be aligned to the bus width (i.e. 16 bit aligned if WIDTH=0, 32 bit aligned if WIDTH=1).
1502 union cvmx_mio_boot_dma_cfgx
1505 struct cvmx_mio_boot_dma_cfgx_s
1507 #if __BYTE_ORDER == __BIG_ENDIAN
1508 uint64_t en : 1; /**< DMA Engine X enable */
1509 uint64_t rw : 1; /**< DMA Engine X R/W bit (0 = read, 1 = write) */
1510 uint64_t clr : 1; /**< DMA Engine X clear EN on device terminated burst */
1511 uint64_t reserved_60_60 : 1;
1512 uint64_t swap32 : 1; /**< DMA Engine X 32 bit swap */
1513 uint64_t swap16 : 1; /**< DMA Engine X 16 bit swap */
1514 uint64_t swap8 : 1; /**< DMA Engine X 8 bit swap */
1515 uint64_t endian : 1; /**< DMA Engine X NCB endian mode (0 = big, 1 = little) */
1516 uint64_t size : 20; /**< DMA Engine X size */
1517 uint64_t adr : 36; /**< DMA Engine X address */
1521 uint64_t endian : 1;
1523 uint64_t swap16 : 1;
1524 uint64_t swap32 : 1;
1525 uint64_t reserved_60_60 : 1;
1531 struct cvmx_mio_boot_dma_cfgx_s cn52xx;
1532 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
1533 struct cvmx_mio_boot_dma_cfgx_s cn56xx;
1534 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
1535 struct cvmx_mio_boot_dma_cfgx_s cn63xx;
1536 struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
1538 typedef union cvmx_mio_boot_dma_cfgx cvmx_mio_boot_dma_cfgx_t;
1541 * cvmx_mio_boot_dma_int#
1543 * MIO_BOOT_DMA_INT = MIO Boot DMA Interrupt Register (1 per engine * 2 engines)
1546 union cvmx_mio_boot_dma_intx
1549 struct cvmx_mio_boot_dma_intx_s
1551 #if __BYTE_ORDER == __BIG_ENDIAN
1552 uint64_t reserved_2_63 : 62;
1553 uint64_t dmarq : 1; /**< DMA Engine X DMARQ asserted interrupt */
1554 uint64_t done : 1; /**< DMA Engine X request completion interrupt */
1558 uint64_t reserved_2_63 : 62;
1561 struct cvmx_mio_boot_dma_intx_s cn52xx;
1562 struct cvmx_mio_boot_dma_intx_s cn52xxp1;
1563 struct cvmx_mio_boot_dma_intx_s cn56xx;
1564 struct cvmx_mio_boot_dma_intx_s cn56xxp1;
1565 struct cvmx_mio_boot_dma_intx_s cn63xx;
1566 struct cvmx_mio_boot_dma_intx_s cn63xxp1;
1568 typedef union cvmx_mio_boot_dma_intx cvmx_mio_boot_dma_intx_t;
1571 * cvmx_mio_boot_dma_int_en#
1573 * MIO_BOOT_DMA_INT_EN = MIO Boot DMA Interrupt Enable Register (1 per engine * 2 engines)
1576 union cvmx_mio_boot_dma_int_enx
1579 struct cvmx_mio_boot_dma_int_enx_s
1581 #if __BYTE_ORDER == __BIG_ENDIAN
1582 uint64_t reserved_2_63 : 62;
1583 uint64_t dmarq : 1; /**< DMA Engine X DMARQ asserted interrupt enable */
1584 uint64_t done : 1; /**< DMA Engine X request completion interrupt enable */
1588 uint64_t reserved_2_63 : 62;
1591 struct cvmx_mio_boot_dma_int_enx_s cn52xx;
1592 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
1593 struct cvmx_mio_boot_dma_int_enx_s cn56xx;
1594 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
1595 struct cvmx_mio_boot_dma_int_enx_s cn63xx;
1596 struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
1598 typedef union cvmx_mio_boot_dma_int_enx cvmx_mio_boot_dma_int_enx_t;
1601 * cvmx_mio_boot_dma_tim#
1603 * MIO_BOOT_DMA_TIM = MIO Boot DMA Timing Register (1 per engine * 2 engines)
1605 * DMACK_PI inverts the assertion level of boot_dmack[n]. The default polarity of boot_dmack[1:0] is
1606 * selected on the first de-assertion of reset by the values on boot_ad[12:11], where 0 is active high
1607 * and 1 is active low (see MIO_BOOT_PIN_DEFS for a read-only copy of the default polarity).
1608 * boot_ad[12:11] have internal pulldowns, so place a pullup on boot_ad[n+11] for active low default
1609 * polarity on engine n. To interface with CF cards in True IDE Mode, either a pullup should be placed
1610 * on boot_ad[n+11] OR the corresponding DMACK_PI[n] should be set.
1612 * DMARQ_PI inverts the assertion level of boot_dmarq[n]. The default polarity of boot_dmarq[1:0] is
1613 * active high, thus setting the polarity inversion bits changes the polarity to active low. To
1614 * interface with CF cards in True IDE Mode, the corresponding DMARQ_PI[n] should be clear.
1616 * TIM_MULT specifies the timing multiplier for an engine. The timing multiplier applies to all timing
1617 * parameters, except for DMARQ and RD_DLY, which simply count eclks. TIM_MULT is encoded as follows:
1618 * 0 = 4x, 1 = 1x, 2 = 2x, 3 = 8x.
1620 * RD_DLY specifies the read sample delay in eclk cycles for an engine. For reads, the data bus is
1621 * normally sampled on the same eclk edge that drives boot_oe_n high (and also low in DDR mode).
1622 * This parameter can delay that sampling edge by up to 7 eclks. Note: the number of eclk cycles
1623 * counted by the OE_A and DMACK_H + PAUSE timing parameters must be greater than RD_DLY.
1625 * If DDR is set, then WE_N must be less than WE_A.
1627 union cvmx_mio_boot_dma_timx
1630 struct cvmx_mio_boot_dma_timx_s
1632 #if __BYTE_ORDER == __BIG_ENDIAN
1633 uint64_t dmack_pi : 1; /**< DMA Engine X DMA ack polarity inversion */
1634 uint64_t dmarq_pi : 1; /**< DMA Engine X DMA request polarity inversion */
1635 uint64_t tim_mult : 2; /**< DMA Engine X timing multiplier */
1636 uint64_t rd_dly : 3; /**< DMA Engine X read sample delay */
1637 uint64_t ddr : 1; /**< DMA Engine X DDR mode */
1638 uint64_t width : 1; /**< DMA Engine X bus width (0 = 16 bits, 1 = 32 bits) */
1639 uint64_t reserved_48_54 : 7;
1640 uint64_t pause : 6; /**< DMA Engine X pause count */
1641 uint64_t dmack_h : 6; /**< DMA Engine X DMA ack hold count */
1642 uint64_t we_n : 6; /**< DMA Engine X write enable negated count */
1643 uint64_t we_a : 6; /**< DMA Engine X write enable asserted count */
1644 uint64_t oe_n : 6; /**< DMA Engine X output enable negated count */
1645 uint64_t oe_a : 6; /**< DMA Engine X output enable asserted count */
1646 uint64_t dmack_s : 6; /**< DMA Engine X DMA ack setup count */
1647 uint64_t dmarq : 6; /**< DMA Engine X DMA request count (must be non-zero) */
1650 uint64_t dmack_s : 6;
1655 uint64_t dmack_h : 6;
1657 uint64_t reserved_48_54 : 7;
1660 uint64_t rd_dly : 3;
1661 uint64_t tim_mult : 2;
1662 uint64_t dmarq_pi : 1;
1663 uint64_t dmack_pi : 1;
1666 struct cvmx_mio_boot_dma_timx_s cn52xx;
1667 struct cvmx_mio_boot_dma_timx_s cn52xxp1;
1668 struct cvmx_mio_boot_dma_timx_s cn56xx;
1669 struct cvmx_mio_boot_dma_timx_s cn56xxp1;
1670 struct cvmx_mio_boot_dma_timx_s cn63xx;
1671 struct cvmx_mio_boot_dma_timx_s cn63xxp1;
1673 typedef union cvmx_mio_boot_dma_timx cvmx_mio_boot_dma_timx_t;
1678 * MIO_BOOT_ERR = MIO Boot Error Register
1680 * Contains the address decode error and wait mode error bits. Address decode error is set when a
1681 * boot bus access does not hit in any of the 8 remote regions or 2 local regions. Wait mode error is
1682 * set when wait mode is enabled and the external wait signal is not de-asserted after 32k eclk cycles.
1684 union cvmx_mio_boot_err
1687 struct cvmx_mio_boot_err_s
1689 #if __BYTE_ORDER == __BIG_ENDIAN
1690 uint64_t reserved_2_63 : 62;
1691 uint64_t wait_err : 1; /**< Wait mode error */
1692 uint64_t adr_err : 1; /**< Address decode error */
1694 uint64_t adr_err : 1;
1695 uint64_t wait_err : 1;
1696 uint64_t reserved_2_63 : 62;
1699 struct cvmx_mio_boot_err_s cn30xx;
1700 struct cvmx_mio_boot_err_s cn31xx;
1701 struct cvmx_mio_boot_err_s cn38xx;
1702 struct cvmx_mio_boot_err_s cn38xxp2;
1703 struct cvmx_mio_boot_err_s cn50xx;
1704 struct cvmx_mio_boot_err_s cn52xx;
1705 struct cvmx_mio_boot_err_s cn52xxp1;
1706 struct cvmx_mio_boot_err_s cn56xx;
1707 struct cvmx_mio_boot_err_s cn56xxp1;
1708 struct cvmx_mio_boot_err_s cn58xx;
1709 struct cvmx_mio_boot_err_s cn58xxp1;
1710 struct cvmx_mio_boot_err_s cn63xx;
1711 struct cvmx_mio_boot_err_s cn63xxp1;
1713 typedef union cvmx_mio_boot_err cvmx_mio_boot_err_t;
1718 * MIO_BOOT_INT = MIO Boot Interrupt Register
1720 * Contains the interrupt enable bits for address decode error and wait mode error.
1722 union cvmx_mio_boot_int
1725 struct cvmx_mio_boot_int_s
1727 #if __BYTE_ORDER == __BIG_ENDIAN
1728 uint64_t reserved_2_63 : 62;
1729 uint64_t wait_int : 1; /**< Wait mode error interrupt enable */
1730 uint64_t adr_int : 1; /**< Address decode error interrupt enable */
1732 uint64_t adr_int : 1;
1733 uint64_t wait_int : 1;
1734 uint64_t reserved_2_63 : 62;
1737 struct cvmx_mio_boot_int_s cn30xx;
1738 struct cvmx_mio_boot_int_s cn31xx;
1739 struct cvmx_mio_boot_int_s cn38xx;
1740 struct cvmx_mio_boot_int_s cn38xxp2;
1741 struct cvmx_mio_boot_int_s cn50xx;
1742 struct cvmx_mio_boot_int_s cn52xx;
1743 struct cvmx_mio_boot_int_s cn52xxp1;
1744 struct cvmx_mio_boot_int_s cn56xx;
1745 struct cvmx_mio_boot_int_s cn56xxp1;
1746 struct cvmx_mio_boot_int_s cn58xx;
1747 struct cvmx_mio_boot_int_s cn58xxp1;
1748 struct cvmx_mio_boot_int_s cn63xx;
1749 struct cvmx_mio_boot_int_s cn63xxp1;
1751 typedef union cvmx_mio_boot_int cvmx_mio_boot_int_t;
1754 * cvmx_mio_boot_loc_adr
1756 * MIO_BOOT_LOC_ADR = MIO Boot Local Memory Address Register
1758 * Specifies the address for reading or writing the local memory. This address will post-increment
1759 * following an access to the MIO Boot Local Memory Data Register (MIO_BOOT_LOC_DAT).
1761 * Local memory region 0 exists from addresses 0x00 - 0x78.
1762 * Local memory region 1 exists from addresses 0x80 - 0xf8.
1764 union cvmx_mio_boot_loc_adr
1767 struct cvmx_mio_boot_loc_adr_s
1769 #if __BYTE_ORDER == __BIG_ENDIAN
1770 uint64_t reserved_8_63 : 56;
1771 uint64_t adr : 5; /**< Local memory address */
1772 uint64_t reserved_0_2 : 3;
1774 uint64_t reserved_0_2 : 3;
1776 uint64_t reserved_8_63 : 56;
1779 struct cvmx_mio_boot_loc_adr_s cn30xx;
1780 struct cvmx_mio_boot_loc_adr_s cn31xx;
1781 struct cvmx_mio_boot_loc_adr_s cn38xx;
1782 struct cvmx_mio_boot_loc_adr_s cn38xxp2;
1783 struct cvmx_mio_boot_loc_adr_s cn50xx;
1784 struct cvmx_mio_boot_loc_adr_s cn52xx;
1785 struct cvmx_mio_boot_loc_adr_s cn52xxp1;
1786 struct cvmx_mio_boot_loc_adr_s cn56xx;
1787 struct cvmx_mio_boot_loc_adr_s cn56xxp1;
1788 struct cvmx_mio_boot_loc_adr_s cn58xx;
1789 struct cvmx_mio_boot_loc_adr_s cn58xxp1;
1790 struct cvmx_mio_boot_loc_adr_s cn63xx;
1791 struct cvmx_mio_boot_loc_adr_s cn63xxp1;
1793 typedef union cvmx_mio_boot_loc_adr cvmx_mio_boot_loc_adr_t;
1796 * cvmx_mio_boot_loc_cfg#
1798 * MIO_BOOT_LOC_CFG = MIO Boot Local Region Config Register (1 per region * 2 regions)
1800 * Contains local region enable and local region base address parameters. Each local region is 128
1801 * bytes organized as 16 entries x 8 bytes.
1803 * Base address specifies address bits [31:7] of the region.
1805 union cvmx_mio_boot_loc_cfgx
1808 struct cvmx_mio_boot_loc_cfgx_s
1810 #if __BYTE_ORDER == __BIG_ENDIAN
1811 uint64_t reserved_32_63 : 32;
1812 uint64_t en : 1; /**< Local region X enable */
1813 uint64_t reserved_28_30 : 3;
1814 uint64_t base : 25; /**< Local region X base address */
1815 uint64_t reserved_0_2 : 3;
1817 uint64_t reserved_0_2 : 3;
1819 uint64_t reserved_28_30 : 3;
1821 uint64_t reserved_32_63 : 32;
1824 struct cvmx_mio_boot_loc_cfgx_s cn30xx;
1825 struct cvmx_mio_boot_loc_cfgx_s cn31xx;
1826 struct cvmx_mio_boot_loc_cfgx_s cn38xx;
1827 struct cvmx_mio_boot_loc_cfgx_s cn38xxp2;
1828 struct cvmx_mio_boot_loc_cfgx_s cn50xx;
1829 struct cvmx_mio_boot_loc_cfgx_s cn52xx;
1830 struct cvmx_mio_boot_loc_cfgx_s cn52xxp1;
1831 struct cvmx_mio_boot_loc_cfgx_s cn56xx;
1832 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
1833 struct cvmx_mio_boot_loc_cfgx_s cn58xx;
1834 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
1835 struct cvmx_mio_boot_loc_cfgx_s cn63xx;
1836 struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
1838 typedef union cvmx_mio_boot_loc_cfgx cvmx_mio_boot_loc_cfgx_t;
1841 * cvmx_mio_boot_loc_dat
1843 * MIO_BOOT_LOC_DAT = MIO Boot Local Memory Data Register
1845 * This is a pseudo-register that will read/write the local memory at the address specified by the MIO
1846 * Boot Local Address Register (MIO_BOOT_LOC_ADR) when accessed.
1848 union cvmx_mio_boot_loc_dat
1851 struct cvmx_mio_boot_loc_dat_s
1853 #if __BYTE_ORDER == __BIG_ENDIAN
1854 uint64_t data : 64; /**< Local memory data */
1859 struct cvmx_mio_boot_loc_dat_s cn30xx;
1860 struct cvmx_mio_boot_loc_dat_s cn31xx;
1861 struct cvmx_mio_boot_loc_dat_s cn38xx;
1862 struct cvmx_mio_boot_loc_dat_s cn38xxp2;
1863 struct cvmx_mio_boot_loc_dat_s cn50xx;
1864 struct cvmx_mio_boot_loc_dat_s cn52xx;
1865 struct cvmx_mio_boot_loc_dat_s cn52xxp1;
1866 struct cvmx_mio_boot_loc_dat_s cn56xx;
1867 struct cvmx_mio_boot_loc_dat_s cn56xxp1;
1868 struct cvmx_mio_boot_loc_dat_s cn58xx;
1869 struct cvmx_mio_boot_loc_dat_s cn58xxp1;
1870 struct cvmx_mio_boot_loc_dat_s cn63xx;
1871 struct cvmx_mio_boot_loc_dat_s cn63xxp1;
1873 typedef union cvmx_mio_boot_loc_dat cvmx_mio_boot_loc_dat_t;
1876 * cvmx_mio_boot_pin_defs
1878 * MIO_BOOT_PIN_DEFS = MIO Boot Pin Defaults Register
1881 union cvmx_mio_boot_pin_defs
1884 struct cvmx_mio_boot_pin_defs_s
1886 #if __BYTE_ORDER == __BIG_ENDIAN
1887 uint64_t reserved_16_63 : 48;
1888 uint64_t ale : 1; /**< Region 0 default ALE mode */
1889 uint64_t width : 1; /**< Region 0 default bus width */
1890 uint64_t dmack_p2 : 1; /**< boot_dmack[2] default polarity */
1891 uint64_t dmack_p1 : 1; /**< boot_dmack[1] default polarity */
1892 uint64_t dmack_p0 : 1; /**< boot_dmack[0] default polarity */
1893 uint64_t term : 2; /**< Selects default driver termination */
1894 uint64_t nand : 1; /**< Region 0 is NAND flash */
1895 uint64_t reserved_0_7 : 8;
1897 uint64_t reserved_0_7 : 8;
1900 uint64_t dmack_p0 : 1;
1901 uint64_t dmack_p1 : 1;
1902 uint64_t dmack_p2 : 1;
1905 uint64_t reserved_16_63 : 48;
1908 struct cvmx_mio_boot_pin_defs_cn52xx
1910 #if __BYTE_ORDER == __BIG_ENDIAN
1911 uint64_t reserved_16_63 : 48;
1912 uint64_t ale : 1; /**< Region 0 default ALE mode */
1913 uint64_t width : 1; /**< Region 0 default bus width */
1914 uint64_t reserved_13_13 : 1;
1915 uint64_t dmack_p1 : 1; /**< boot_dmack[1] default polarity */
1916 uint64_t dmack_p0 : 1; /**< boot_dmack[0] default polarity */
1917 uint64_t term : 2; /**< Selects default driver termination */
1918 uint64_t nand : 1; /**< Region 0 is NAND flash */
1919 uint64_t reserved_0_7 : 8;
1921 uint64_t reserved_0_7 : 8;
1924 uint64_t dmack_p0 : 1;
1925 uint64_t dmack_p1 : 1;
1926 uint64_t reserved_13_13 : 1;
1929 uint64_t reserved_16_63 : 48;
1932 struct cvmx_mio_boot_pin_defs_cn56xx
1934 #if __BYTE_ORDER == __BIG_ENDIAN
1935 uint64_t reserved_16_63 : 48;
1936 uint64_t ale : 1; /**< Region 0 default ALE mode */
1937 uint64_t width : 1; /**< Region 0 default bus width */
1938 uint64_t dmack_p2 : 1; /**< boot_dmack[2] default polarity */
1939 uint64_t dmack_p1 : 1; /**< boot_dmack[1] default polarity */
1940 uint64_t dmack_p0 : 1; /**< boot_dmack[0] default polarity */
1941 uint64_t term : 2; /**< Selects default driver termination */
1942 uint64_t reserved_0_8 : 9;
1944 uint64_t reserved_0_8 : 9;
1946 uint64_t dmack_p0 : 1;
1947 uint64_t dmack_p1 : 1;
1948 uint64_t dmack_p2 : 1;
1951 uint64_t reserved_16_63 : 48;
1954 struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
1955 struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
1957 typedef union cvmx_mio_boot_pin_defs cvmx_mio_boot_pin_defs_t;
1960 * cvmx_mio_boot_reg_cfg#
1962 union cvmx_mio_boot_reg_cfgx
1965 struct cvmx_mio_boot_reg_cfgx_s
1967 #if __BYTE_ORDER == __BIG_ENDIAN
1968 uint64_t reserved_44_63 : 20;
1969 uint64_t dmack : 2; /**< Region X DMACK */
1970 uint64_t tim_mult : 2; /**< Region X timing multiplier */
1971 uint64_t rd_dly : 3; /**< Region X read sample delay */
1972 uint64_t sam : 1; /**< Region X SAM mode */
1973 uint64_t we_ext : 2; /**< Region X write enable count extension */
1974 uint64_t oe_ext : 2; /**< Region X output enable count extension */
1975 uint64_t en : 1; /**< Region X enable */
1976 uint64_t orbit : 1; /**< Region X or bit */
1977 uint64_t ale : 1; /**< Region X ALE mode */
1978 uint64_t width : 1; /**< Region X bus width */
1979 uint64_t size : 12; /**< Region X size */
1980 uint64_t base : 16; /**< Region X base address */
1988 uint64_t oe_ext : 2;
1989 uint64_t we_ext : 2;
1991 uint64_t rd_dly : 3;
1992 uint64_t tim_mult : 2;
1994 uint64_t reserved_44_63 : 20;
1997 struct cvmx_mio_boot_reg_cfgx_cn30xx
1999 #if __BYTE_ORDER == __BIG_ENDIAN
2000 uint64_t reserved_37_63 : 27;
2001 uint64_t sam : 1; /**< Region X SAM mode */
2002 uint64_t we_ext : 2; /**< Region X write enable count extension */
2003 uint64_t oe_ext : 2; /**< Region X output enable count extension */
2004 uint64_t en : 1; /**< Region X enable */
2005 uint64_t orbit : 1; /**< Region X or bit */
2006 uint64_t ale : 1; /**< Region X ALE mode */
2007 uint64_t width : 1; /**< Region X bus width */
2008 uint64_t size : 12; /**< Region X size */
2009 uint64_t base : 16; /**< Region X base address */
2017 uint64_t oe_ext : 2;
2018 uint64_t we_ext : 2;
2020 uint64_t reserved_37_63 : 27;
2023 struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx;
2024 struct cvmx_mio_boot_reg_cfgx_cn38xx
2026 #if __BYTE_ORDER == __BIG_ENDIAN
2027 uint64_t reserved_32_63 : 32;
2028 uint64_t en : 1; /**< Region X enable */
2029 uint64_t orbit : 1; /**< Region X or bit */
2030 uint64_t reserved_28_29 : 2;
2031 uint64_t size : 12; /**< Region X size */
2032 uint64_t base : 16; /**< Region X base address */
2036 uint64_t reserved_28_29 : 2;
2039 uint64_t reserved_32_63 : 32;
2042 struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2;
2043 struct cvmx_mio_boot_reg_cfgx_cn50xx
2045 #if __BYTE_ORDER == __BIG_ENDIAN
2046 uint64_t reserved_42_63 : 22;
2047 uint64_t tim_mult : 2; /**< Region X timing multiplier */
2048 uint64_t rd_dly : 3; /**< Region X read sample delay */
2049 uint64_t sam : 1; /**< Region X SAM mode */
2050 uint64_t we_ext : 2; /**< Region X write enable count extension */
2051 uint64_t oe_ext : 2; /**< Region X output enable count extension */
2052 uint64_t en : 1; /**< Region X enable */
2053 uint64_t orbit : 1; /**< Region X or bit */
2054 uint64_t ale : 1; /**< Region X ALE mode */
2055 uint64_t width : 1; /**< Region X bus width */
2056 uint64_t size : 12; /**< Region X size */
2057 uint64_t base : 16; /**< Region X base address */
2065 uint64_t oe_ext : 2;
2066 uint64_t we_ext : 2;
2068 uint64_t rd_dly : 3;
2069 uint64_t tim_mult : 2;
2070 uint64_t reserved_42_63 : 22;
2073 struct cvmx_mio_boot_reg_cfgx_s cn52xx;
2074 struct cvmx_mio_boot_reg_cfgx_s cn52xxp1;
2075 struct cvmx_mio_boot_reg_cfgx_s cn56xx;
2076 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
2077 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
2078 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
2079 struct cvmx_mio_boot_reg_cfgx_s cn63xx;
2080 struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
2082 typedef union cvmx_mio_boot_reg_cfgx cvmx_mio_boot_reg_cfgx_t;
2085 * cvmx_mio_boot_reg_tim#
2087 union cvmx_mio_boot_reg_timx
2090 struct cvmx_mio_boot_reg_timx_s
2092 #if __BYTE_ORDER == __BIG_ENDIAN
2093 uint64_t pagem : 1; /**< Region X page mode */
2094 uint64_t waitm : 1; /**< Region X wait mode */
2095 uint64_t pages : 2; /**< Region X page size */
2096 uint64_t ale : 6; /**< Region X ALE count */
2097 uint64_t page : 6; /**< Region X page count */
2098 uint64_t wait : 6; /**< Region X wait count */
2099 uint64_t pause : 6; /**< Region X pause count */
2100 uint64_t wr_hld : 6; /**< Region X write hold count */
2101 uint64_t rd_hld : 6; /**< Region X read hold count */
2102 uint64_t we : 6; /**< Region X write enable count */
2103 uint64_t oe : 6; /**< Region X output enable count */
2104 uint64_t ce : 6; /**< Region X chip enable count */
2105 uint64_t adr : 6; /**< Region X address count */
2111 uint64_t rd_hld : 6;
2112 uint64_t wr_hld : 6;
2122 struct cvmx_mio_boot_reg_timx_s cn30xx;
2123 struct cvmx_mio_boot_reg_timx_s cn31xx;
2124 struct cvmx_mio_boot_reg_timx_cn38xx
2126 #if __BYTE_ORDER == __BIG_ENDIAN
2127 uint64_t pagem : 1; /**< Region X page mode */
2128 uint64_t waitm : 1; /**< Region X wait mode */
2129 uint64_t pages : 2; /**< Region X page size (NOT IN PASS 1) */
2130 uint64_t reserved_54_59 : 6;
2131 uint64_t page : 6; /**< Region X page count */
2132 uint64_t wait : 6; /**< Region X wait count */
2133 uint64_t pause : 6; /**< Region X pause count */
2134 uint64_t wr_hld : 6; /**< Region X write hold count */
2135 uint64_t rd_hld : 6; /**< Region X read hold count */
2136 uint64_t we : 6; /**< Region X write enable count */
2137 uint64_t oe : 6; /**< Region X output enable count */
2138 uint64_t ce : 6; /**< Region X chip enable count */
2139 uint64_t adr : 6; /**< Region X address count */
2145 uint64_t rd_hld : 6;
2146 uint64_t wr_hld : 6;
2150 uint64_t reserved_54_59 : 6;
2156 struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2;
2157 struct cvmx_mio_boot_reg_timx_s cn50xx;
2158 struct cvmx_mio_boot_reg_timx_s cn52xx;
2159 struct cvmx_mio_boot_reg_timx_s cn52xxp1;
2160 struct cvmx_mio_boot_reg_timx_s cn56xx;
2161 struct cvmx_mio_boot_reg_timx_s cn56xxp1;
2162 struct cvmx_mio_boot_reg_timx_s cn58xx;
2163 struct cvmx_mio_boot_reg_timx_s cn58xxp1;
2164 struct cvmx_mio_boot_reg_timx_s cn63xx;
2165 struct cvmx_mio_boot_reg_timx_s cn63xxp1;
2167 typedef union cvmx_mio_boot_reg_timx cvmx_mio_boot_reg_timx_t;
2172 * MIO_BOOT_THR = MIO Boot Threshold Register
2174 * Contains MIO Boot threshold values:
2176 * FIF_THR = Assert ncb__busy when the Boot NCB input FIFO reaches this level (not typically for
2179 * DMA_THR = When non-DMA accesses are pending, perform a DMA access after this value of non-DMA
2180 * accesses have completed. If set to zero, only perform a DMA access when non-DMA
2181 * accesses are not pending.
2183 union cvmx_mio_boot_thr
2186 struct cvmx_mio_boot_thr_s
2188 #if __BYTE_ORDER == __BIG_ENDIAN
2189 uint64_t reserved_22_63 : 42;
2190 uint64_t dma_thr : 6; /**< DMA threshold */
2191 uint64_t reserved_14_15 : 2;
2192 uint64_t fif_cnt : 6; /**< Current NCB FIFO count */
2193 uint64_t reserved_6_7 : 2;
2194 uint64_t fif_thr : 6; /**< NCB busy threshold */
2196 uint64_t fif_thr : 6;
2197 uint64_t reserved_6_7 : 2;
2198 uint64_t fif_cnt : 6;
2199 uint64_t reserved_14_15 : 2;
2200 uint64_t dma_thr : 6;
2201 uint64_t reserved_22_63 : 42;
2204 struct cvmx_mio_boot_thr_cn30xx
2206 #if __BYTE_ORDER == __BIG_ENDIAN
2207 uint64_t reserved_14_63 : 50;
2208 uint64_t fif_cnt : 6; /**< Current NCB FIFO count */
2209 uint64_t reserved_6_7 : 2;
2210 uint64_t fif_thr : 6; /**< NCB busy threshold */
2212 uint64_t fif_thr : 6;
2213 uint64_t reserved_6_7 : 2;
2214 uint64_t fif_cnt : 6;
2215 uint64_t reserved_14_63 : 50;
2218 struct cvmx_mio_boot_thr_cn30xx cn31xx;
2219 struct cvmx_mio_boot_thr_cn30xx cn38xx;
2220 struct cvmx_mio_boot_thr_cn30xx cn38xxp2;
2221 struct cvmx_mio_boot_thr_cn30xx cn50xx;
2222 struct cvmx_mio_boot_thr_s cn52xx;
2223 struct cvmx_mio_boot_thr_s cn52xxp1;
2224 struct cvmx_mio_boot_thr_s cn56xx;
2225 struct cvmx_mio_boot_thr_s cn56xxp1;
2226 struct cvmx_mio_boot_thr_cn30xx cn58xx;
2227 struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
2228 struct cvmx_mio_boot_thr_s cn63xx;
2229 struct cvmx_mio_boot_thr_s cn63xxp1;
2231 typedef union cvmx_mio_boot_thr cvmx_mio_boot_thr_t;
2234 * cvmx_mio_fus_bnk_dat#
2237 * The intial state of MIO_FUS_BNK_DAT* is as if bank6 was just read i.e. DAT* = fus[895:768]
2240 union cvmx_mio_fus_bnk_datx
2243 struct cvmx_mio_fus_bnk_datx_s
2245 #if __BYTE_ORDER == __BIG_ENDIAN
2246 uint64_t dat : 64; /**< Efuse bank store
2247 For reads, the DAT gets the fus bank last read
2248 For write, the DAT determines which fuses to blow */
2253 struct cvmx_mio_fus_bnk_datx_s cn50xx;
2254 struct cvmx_mio_fus_bnk_datx_s cn52xx;
2255 struct cvmx_mio_fus_bnk_datx_s cn52xxp1;
2256 struct cvmx_mio_fus_bnk_datx_s cn56xx;
2257 struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
2258 struct cvmx_mio_fus_bnk_datx_s cn58xx;
2259 struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
2260 struct cvmx_mio_fus_bnk_datx_s cn63xx;
2261 struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
2263 typedef union cvmx_mio_fus_bnk_datx cvmx_mio_fus_bnk_datx_t;
2268 union cvmx_mio_fus_dat0
2271 struct cvmx_mio_fus_dat0_s
2273 #if __BYTE_ORDER == __BIG_ENDIAN
2274 uint64_t reserved_32_63 : 32;
2275 uint64_t man_info : 32; /**< Fuse information - manufacturing info [31:0] */
2277 uint64_t man_info : 32;
2278 uint64_t reserved_32_63 : 32;
2281 struct cvmx_mio_fus_dat0_s cn30xx;
2282 struct cvmx_mio_fus_dat0_s cn31xx;
2283 struct cvmx_mio_fus_dat0_s cn38xx;
2284 struct cvmx_mio_fus_dat0_s cn38xxp2;
2285 struct cvmx_mio_fus_dat0_s cn50xx;
2286 struct cvmx_mio_fus_dat0_s cn52xx;
2287 struct cvmx_mio_fus_dat0_s cn52xxp1;
2288 struct cvmx_mio_fus_dat0_s cn56xx;
2289 struct cvmx_mio_fus_dat0_s cn56xxp1;
2290 struct cvmx_mio_fus_dat0_s cn58xx;
2291 struct cvmx_mio_fus_dat0_s cn58xxp1;
2292 struct cvmx_mio_fus_dat0_s cn63xx;
2293 struct cvmx_mio_fus_dat0_s cn63xxp1;
2295 typedef union cvmx_mio_fus_dat0 cvmx_mio_fus_dat0_t;
2300 union cvmx_mio_fus_dat1
2303 struct cvmx_mio_fus_dat1_s
2305 #if __BYTE_ORDER == __BIG_ENDIAN
2306 uint64_t reserved_32_63 : 32;
2307 uint64_t man_info : 32; /**< Fuse information - manufacturing info [63:32] */
2309 uint64_t man_info : 32;
2310 uint64_t reserved_32_63 : 32;
2313 struct cvmx_mio_fus_dat1_s cn30xx;
2314 struct cvmx_mio_fus_dat1_s cn31xx;
2315 struct cvmx_mio_fus_dat1_s cn38xx;
2316 struct cvmx_mio_fus_dat1_s cn38xxp2;
2317 struct cvmx_mio_fus_dat1_s cn50xx;
2318 struct cvmx_mio_fus_dat1_s cn52xx;
2319 struct cvmx_mio_fus_dat1_s cn52xxp1;
2320 struct cvmx_mio_fus_dat1_s cn56xx;
2321 struct cvmx_mio_fus_dat1_s cn56xxp1;
2322 struct cvmx_mio_fus_dat1_s cn58xx;
2323 struct cvmx_mio_fus_dat1_s cn58xxp1;
2324 struct cvmx_mio_fus_dat1_s cn63xx;
2325 struct cvmx_mio_fus_dat1_s cn63xxp1;
2327 typedef union cvmx_mio_fus_dat1 cvmx_mio_fus_dat1_t;
2333 * CHIP_ID is consumed in several places within Octeon.
2335 * * Core COP0 ProcessorIdentification[Revision]
2336 * * Core EJTAG DeviceIdentification[Version]
2340 * Note: The JTAG controller gets CHIP_ID[3:0] solely from the laser fuses.
2341 * Modification to the efuses will not change what the JTAG controller reports
2344 union cvmx_mio_fus_dat2
2347 struct cvmx_mio_fus_dat2_s
2349 #if __BYTE_ORDER == __BIG_ENDIAN
2350 uint64_t reserved_35_63 : 29;
2351 uint64_t dorm_crypto : 1; /**< Fuse information - Dormant Encryption enable */
2352 uint64_t fus318 : 1; /**< Fuse information - a copy of fuse318 */
2353 uint64_t raid_en : 1; /**< Fuse information - RAID enabled */
2354 uint64_t reserved_30_31 : 2;
2355 uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */
2356 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */
2357 uint64_t nomul : 1; /**< Fuse information - VMUL disable */
2358 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */
2359 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */
2360 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */
2361 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */
2362 uint64_t reserved_0_15 : 16;
2364 uint64_t reserved_0_15 : 16;
2365 uint64_t chip_id : 8;
2366 uint64_t bist_dis : 1;
2367 uint64_t rst_sht : 1;
2368 uint64_t nocrypto : 1;
2370 uint64_t nodfa_cp2 : 1;
2371 uint64_t nokasu : 1;
2372 uint64_t reserved_30_31 : 2;
2373 uint64_t raid_en : 1;
2374 uint64_t fus318 : 1;
2375 uint64_t dorm_crypto : 1;
2376 uint64_t reserved_35_63 : 29;
2379 struct cvmx_mio_fus_dat2_cn30xx
2381 #if __BYTE_ORDER == __BIG_ENDIAN
2382 uint64_t reserved_29_63 : 35;
2383 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */
2384 uint64_t nomul : 1; /**< Fuse information - VMUL disable */
2385 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */
2386 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */
2387 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */
2388 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */
2389 uint64_t pll_off : 4; /**< Fuse information - core pll offset
2390 Used to compute the base offset for the core pll.
2391 the offset will be (PLL_OFF ^ 8)
2392 Note, these fuses can only be set from laser fuse */
2393 uint64_t reserved_1_11 : 11;
2394 uint64_t pp_dis : 1; /**< Fuse information - PP_DISABLES */
2396 uint64_t pp_dis : 1;
2397 uint64_t reserved_1_11 : 11;
2398 uint64_t pll_off : 4;
2399 uint64_t chip_id : 8;
2400 uint64_t bist_dis : 1;
2401 uint64_t rst_sht : 1;
2402 uint64_t nocrypto : 1;
2404 uint64_t nodfa_cp2 : 1;
2405 uint64_t reserved_29_63 : 35;
2408 struct cvmx_mio_fus_dat2_cn31xx
2410 #if __BYTE_ORDER == __BIG_ENDIAN
2411 uint64_t reserved_29_63 : 35;
2412 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */
2413 uint64_t nomul : 1; /**< Fuse information - VMUL disable */
2414 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */
2415 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */
2416 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */
2417 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */
2418 uint64_t pll_off : 4; /**< Fuse information - core pll offset
2419 Used to compute the base offset for the core pll.
2420 the offset will be (PLL_OFF ^ 8)
2421 Note, these fuses can only be set from laser fuse */
2422 uint64_t reserved_2_11 : 10;
2423 uint64_t pp_dis : 2; /**< Fuse information - PP_DISABLES */
2425 uint64_t pp_dis : 2;
2426 uint64_t reserved_2_11 : 10;
2427 uint64_t pll_off : 4;
2428 uint64_t chip_id : 8;
2429 uint64_t bist_dis : 1;
2430 uint64_t rst_sht : 1;
2431 uint64_t nocrypto : 1;
2433 uint64_t nodfa_cp2 : 1;
2434 uint64_t reserved_29_63 : 35;
2437 struct cvmx_mio_fus_dat2_cn38xx
2439 #if __BYTE_ORDER == __BIG_ENDIAN
2440 uint64_t reserved_29_63 : 35;
2441 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2)
2443 uint64_t nomul : 1; /**< Fuse information - VMUL disable
2445 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable
2447 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */
2448 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */
2449 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */
2450 uint64_t pp_dis : 16; /**< Fuse information - PP_DISABLES */
2452 uint64_t pp_dis : 16;
2453 uint64_t chip_id : 8;
2454 uint64_t bist_dis : 1;
2455 uint64_t rst_sht : 1;
2456 uint64_t nocrypto : 1;
2458 uint64_t nodfa_cp2 : 1;
2459 uint64_t reserved_29_63 : 35;
2462 struct cvmx_mio_fus_dat2_cn38xx cn38xxp2;
2463 struct cvmx_mio_fus_dat2_cn50xx
2465 #if __BYTE_ORDER == __BIG_ENDIAN
2466 uint64_t reserved_34_63 : 30;
2467 uint64_t fus318 : 1; /**< Fuse information - a copy of fuse318 */
2468 uint64_t raid_en : 1; /**< Fuse information - RAID enabled
2469 (5020 does not have RAID co-processor) */
2470 uint64_t reserved_30_31 : 2;
2471 uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */
2472 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2)
2473 (5020 does not have DFA co-processor) */
2474 uint64_t nomul : 1; /**< Fuse information - VMUL disable */
2475 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */
2476 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */
2477 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */
2478 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */
2479 uint64_t reserved_2_15 : 14;
2480 uint64_t pp_dis : 2; /**< Fuse information - PP_DISABLES */
2482 uint64_t pp_dis : 2;
2483 uint64_t reserved_2_15 : 14;
2484 uint64_t chip_id : 8;
2485 uint64_t bist_dis : 1;
2486 uint64_t rst_sht : 1;
2487 uint64_t nocrypto : 1;
2489 uint64_t nodfa_cp2 : 1;
2490 uint64_t nokasu : 1;
2491 uint64_t reserved_30_31 : 2;
2492 uint64_t raid_en : 1;
2493 uint64_t fus318 : 1;
2494 uint64_t reserved_34_63 : 30;
2497 struct cvmx_mio_fus_dat2_cn52xx
2499 #if __BYTE_ORDER == __BIG_ENDIAN
2500 uint64_t reserved_34_63 : 30;
2501 uint64_t fus318 : 1; /**< Fuse information - a copy of fuse318 */
2502 uint64_t raid_en : 1; /**< Fuse information - RAID enabled */
2503 uint64_t reserved_30_31 : 2;
2504 uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */
2505 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */
2506 uint64_t nomul : 1; /**< Fuse information - VMUL disable */
2507 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */
2508 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */
2509 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */
2510 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */
2511 uint64_t reserved_4_15 : 12;
2512 uint64_t pp_dis : 4; /**< Fuse information - PP_DISABLES */
2514 uint64_t pp_dis : 4;
2515 uint64_t reserved_4_15 : 12;
2516 uint64_t chip_id : 8;
2517 uint64_t bist_dis : 1;
2518 uint64_t rst_sht : 1;
2519 uint64_t nocrypto : 1;
2521 uint64_t nodfa_cp2 : 1;
2522 uint64_t nokasu : 1;
2523 uint64_t reserved_30_31 : 2;
2524 uint64_t raid_en : 1;
2525 uint64_t fus318 : 1;
2526 uint64_t reserved_34_63 : 30;
2529 struct cvmx_mio_fus_dat2_cn52xx cn52xxp1;
2530 struct cvmx_mio_fus_dat2_cn56xx
2532 #if __BYTE_ORDER == __BIG_ENDIAN
2533 uint64_t reserved_34_63 : 30;
2534 uint64_t fus318 : 1; /**< Fuse information - a copy of fuse318 */
2535 uint64_t raid_en : 1; /**< Fuse information - RAID enabled */
2536 uint64_t reserved_30_31 : 2;
2537 uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */
2538 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */
2539 uint64_t nomul : 1; /**< Fuse information - VMUL disable */
2540 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */
2541 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */
2542 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */
2543 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */
2544 uint64_t reserved_12_15 : 4;
2545 uint64_t pp_dis : 12; /**< Fuse information - PP_DISABLES */
2547 uint64_t pp_dis : 12;
2548 uint64_t reserved_12_15 : 4;
2549 uint64_t chip_id : 8;
2550 uint64_t bist_dis : 1;
2551 uint64_t rst_sht : 1;
2552 uint64_t nocrypto : 1;
2554 uint64_t nodfa_cp2 : 1;
2555 uint64_t nokasu : 1;
2556 uint64_t reserved_30_31 : 2;
2557 uint64_t raid_en : 1;
2558 uint64_t fus318 : 1;
2559 uint64_t reserved_34_63 : 30;
2562 struct cvmx_mio_fus_dat2_cn56xx cn56xxp1;
2563 struct cvmx_mio_fus_dat2_cn58xx
2565 #if __BYTE_ORDER == __BIG_ENDIAN
2566 uint64_t reserved_30_63 : 34;
2567 uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */
2568 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */
2569 uint64_t nomul : 1; /**< Fuse information - VMUL disable */
2570 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */
2571 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */
2572 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */
2573 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */
2574 uint64_t pp_dis : 16; /**< Fuse information - PP_DISABLES */
2576 uint64_t pp_dis : 16;
2577 uint64_t chip_id : 8;
2578 uint64_t bist_dis : 1;
2579 uint64_t rst_sht : 1;
2580 uint64_t nocrypto : 1;
2582 uint64_t nodfa_cp2 : 1;
2583 uint64_t nokasu : 1;
2584 uint64_t reserved_30_63 : 34;
2587 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
2588 struct cvmx_mio_fus_dat2_cn63xx
2590 #if __BYTE_ORDER == __BIG_ENDIAN
2591 uint64_t reserved_35_63 : 29;
2592 uint64_t dorm_crypto : 1; /**< Fuse information - Dormant Encryption enable */
2593 uint64_t fus318 : 1; /**< Fuse information - a copy of fuse318 */
2594 uint64_t raid_en : 1; /**< Fuse information - RAID enabled */
2595 uint64_t reserved_29_31 : 3;
2596 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */
2597 uint64_t nomul : 1; /**< Fuse information - VMUL disable */
2598 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */
2599 uint64_t reserved_24_25 : 2;
2600 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */
2601 uint64_t reserved_6_15 : 10;
2602 uint64_t pp_dis : 6; /**< Fuse information - PP_DISABLES */
2604 uint64_t pp_dis : 6;
2605 uint64_t reserved_6_15 : 10;
2606 uint64_t chip_id : 8;
2607 uint64_t reserved_24_25 : 2;
2608 uint64_t nocrypto : 1;
2610 uint64_t nodfa_cp2 : 1;
2611 uint64_t reserved_29_31 : 3;
2612 uint64_t raid_en : 1;
2613 uint64_t fus318 : 1;
2614 uint64_t dorm_crypto : 1;
2615 uint64_t reserved_35_63 : 29;
2618 struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
2620 typedef union cvmx_mio_fus_dat2 cvmx_mio_fus_dat2_t;
2625 union cvmx_mio_fus_dat3
2628 struct cvmx_mio_fus_dat3_s
2630 #if __BYTE_ORDER == __BIG_ENDIAN
2631 uint64_t reserved_58_63 : 6;
2632 uint64_t pll_ctl : 10; /**< Fuse information - PLL control */
2633 uint64_t dfa_info_dte : 3; /**< Fuse information - DFA information (DTE) */
2634 uint64_t dfa_info_clm : 4; /**< Fuse information - DFA information (Cluster mask) */
2635 uint64_t reserved_40_40 : 1;
2636 uint64_t ema : 2; /**< Fuse information - EMA */
2637 uint64_t efus_lck_rsv : 1; /**< Fuse information - efuse lockdown */
2638 uint64_t efus_lck_man : 1; /**< Fuse information - efuse lockdown */
2639 uint64_t pll_half_dis : 1; /**< Fuse information - RCLK PLL control */
2640 uint64_t l2c_crip : 3; /**< Fuse information - L2C Cripple (1/8, 1/4, 1/2) */
2641 uint64_t pll_div4 : 1; /**< Fuse information - PLL DIV4 mode
2642 (laser fuse only) */
2643 uint64_t reserved_29_30 : 2;
2644 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Present (when blown '1') */
2645 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */
2646 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore */
2647 uint64_t nozip : 1; /**< Fuse information - ZIP disable */
2648 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */
2649 uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */
2651 uint64_t icache : 24;
2652 uint64_t nodfa_dte : 1;
2654 uint64_t efus_ign : 1;
2655 uint64_t efus_lck : 1;
2656 uint64_t bar2_en : 1;
2657 uint64_t reserved_29_30 : 2;
2658 uint64_t pll_div4 : 1;
2659 uint64_t l2c_crip : 3;
2660 uint64_t pll_half_dis : 1;
2661 uint64_t efus_lck_man : 1;
2662 uint64_t efus_lck_rsv : 1;
2664 uint64_t reserved_40_40 : 1;
2665 uint64_t dfa_info_clm : 4;
2666 uint64_t dfa_info_dte : 3;
2667 uint64_t pll_ctl : 10;
2668 uint64_t reserved_58_63 : 6;
2671 struct cvmx_mio_fus_dat3_cn30xx
2673 #if __BYTE_ORDER == __BIG_ENDIAN
2674 uint64_t reserved_32_63 : 32;
2675 uint64_t pll_div4 : 1; /**< Fuse information - PLL DIV4 mode
2676 (laser fuse only) */
2677 uint64_t reserved_29_30 : 2;
2678 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1') */
2679 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */
2680 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore
2681 This bit only has side effects when blown in
2682 the laser fuses. It is ignore if only set in
2684 uint64_t nozip : 1; /**< Fuse information - ZIP disable */
2685 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */
2686 uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */
2688 uint64_t icache : 24;
2689 uint64_t nodfa_dte : 1;
2691 uint64_t efus_ign : 1;
2692 uint64_t efus_lck : 1;
2693 uint64_t bar2_en : 1;
2694 uint64_t reserved_29_30 : 2;
2695 uint64_t pll_div4 : 1;
2696 uint64_t reserved_32_63 : 32;
2699 struct cvmx_mio_fus_dat3_cn31xx
2701 #if __BYTE_ORDER == __BIG_ENDIAN
2702 uint64_t reserved_32_63 : 32;
2703 uint64_t pll_div4 : 1; /**< Fuse information - PLL DIV4 mode
2704 (laser fuse only) */
2705 uint64_t zip_crip : 2; /**< Fuse information - Zip Cripple
2707 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1') */
2708 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */
2709 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore
2710 This bit only has side effects when blown in
2711 the laser fuses. It is ignore if only set in
2713 uint64_t nozip : 1; /**< Fuse information - ZIP disable */
2714 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */
2715 uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */
2717 uint64_t icache : 24;
2718 uint64_t nodfa_dte : 1;
2720 uint64_t efus_ign : 1;
2721 uint64_t efus_lck : 1;
2722 uint64_t bar2_en : 1;
2723 uint64_t zip_crip : 2;
2724 uint64_t pll_div4 : 1;
2725 uint64_t reserved_32_63 : 32;
2728 struct cvmx_mio_fus_dat3_cn38xx
2730 #if __BYTE_ORDER == __BIG_ENDIAN
2731 uint64_t reserved_31_63 : 33;
2732 uint64_t zip_crip : 2; /**< Fuse information - Zip Cripple
2734 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1')
2736 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown
2738 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore
2739 This bit only has side effects when blown in
2740 the laser fuses. It is ignore if only set in
2743 uint64_t nozip : 1; /**< Fuse information - ZIP disable
2745 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE)
2747 uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */
2749 uint64_t icache : 24;
2750 uint64_t nodfa_dte : 1;
2752 uint64_t efus_ign : 1;
2753 uint64_t efus_lck : 1;
2754 uint64_t bar2_en : 1;
2755 uint64_t zip_crip : 2;
2756 uint64_t reserved_31_63 : 33;
2759 struct cvmx_mio_fus_dat3_cn38xxp2
2761 #if __BYTE_ORDER == __BIG_ENDIAN
2762 uint64_t reserved_29_63 : 35;
2763 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1')
2765 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown
2767 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore
2768 This bit only has side effects when blown in
2769 the laser fuses. It is ignore if only set in
2772 uint64_t nozip : 1; /**< Fuse information - ZIP disable
2774 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE)
2776 uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */
2778 uint64_t icache : 24;
2779 uint64_t nodfa_dte : 1;
2781 uint64_t efus_ign : 1;
2782 uint64_t efus_lck : 1;
2783 uint64_t bar2_en : 1;
2784 uint64_t reserved_29_63 : 35;
2787 struct cvmx_mio_fus_dat3_cn38xx cn50xx;
2788 struct cvmx_mio_fus_dat3_cn38xx cn52xx;
2789 struct cvmx_mio_fus_dat3_cn38xx cn52xxp1;
2790 struct cvmx_mio_fus_dat3_cn38xx cn56xx;
2791 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
2792 struct cvmx_mio_fus_dat3_cn38xx cn58xx;
2793 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
2794 struct cvmx_mio_fus_dat3_cn63xx
2796 #if __BYTE_ORDER == __BIG_ENDIAN
2797 uint64_t reserved_58_63 : 6;
2798 uint64_t pll_ctl : 10; /**< Fuse information - PLL control */
2799 uint64_t dfa_info_dte : 3; /**< Fuse information - DFA information (DTE) */
2800 uint64_t dfa_info_clm : 4; /**< Fuse information - DFA information (Cluster mask) */
2801 uint64_t reserved_40_40 : 1;
2802 uint64_t ema : 2; /**< Fuse information - EMA */
2803 uint64_t efus_lck_rsv : 1; /**< Fuse information - efuse lockdown */
2804 uint64_t efus_lck_man : 1; /**< Fuse information - efuse lockdown */
2805 uint64_t pll_half_dis : 1; /**< Fuse information - RCLK PLL control */
2806 uint64_t l2c_crip : 3; /**< Fuse information - L2C Cripple (1/8, 1/4, 1/2) */
2807 uint64_t reserved_31_31 : 1;
2808 uint64_t zip_info : 2; /**< Fuse information - Zip information */
2809 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Present (when blown '1') */
2810 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */
2811 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore */
2812 uint64_t nozip : 1; /**< Fuse information - ZIP disable */
2813 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */
2814 uint64_t reserved_0_23 : 24;
2816 uint64_t reserved_0_23 : 24;
2817 uint64_t nodfa_dte : 1;
2819 uint64_t efus_ign : 1;
2820 uint64_t efus_lck : 1;
2821 uint64_t bar2_en : 1;
2822 uint64_t zip_info : 2;
2823 uint64_t reserved_31_31 : 1;
2824 uint64_t l2c_crip : 3;
2825 uint64_t pll_half_dis : 1;
2826 uint64_t efus_lck_man : 1;
2827 uint64_t efus_lck_rsv : 1;
2829 uint64_t reserved_40_40 : 1;
2830 uint64_t dfa_info_clm : 4;
2831 uint64_t dfa_info_dte : 3;
2832 uint64_t pll_ctl : 10;
2833 uint64_t reserved_58_63 : 6;
2836 struct cvmx_mio_fus_dat3_cn63xx cn63xxp1;
2838 typedef union cvmx_mio_fus_dat3 cvmx_mio_fus_dat3_t;
2843 union cvmx_mio_fus_ema
2846 struct cvmx_mio_fus_ema_s
2848 #if __BYTE_ORDER == __BIG_ENDIAN
2849 uint64_t reserved_7_63 : 57;
2850 uint64_t eff_ema : 3; /**< Reserved */
2851 uint64_t reserved_3_3 : 1;
2852 uint64_t ema : 3; /**< Reserved */
2855 uint64_t reserved_3_3 : 1;
2856 uint64_t eff_ema : 3;
2857 uint64_t reserved_7_63 : 57;
2860 struct cvmx_mio_fus_ema_s cn50xx;
2861 struct cvmx_mio_fus_ema_s cn52xx;
2862 struct cvmx_mio_fus_ema_s cn52xxp1;
2863 struct cvmx_mio_fus_ema_s cn56xx;
2864 struct cvmx_mio_fus_ema_s cn56xxp1;
2865 struct cvmx_mio_fus_ema_cn58xx
2867 #if __BYTE_ORDER == __BIG_ENDIAN
2868 uint64_t reserved_2_63 : 62;
2869 uint64_t ema : 2; /**< EMA Settings */
2872 uint64_t reserved_2_63 : 62;
2875 struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
2876 struct cvmx_mio_fus_ema_s cn63xx;
2877 struct cvmx_mio_fus_ema_s cn63xxp1;
2879 typedef union cvmx_mio_fus_ema cvmx_mio_fus_ema_t;
2884 union cvmx_mio_fus_pdf
2887 struct cvmx_mio_fus_pdf_s
2889 #if __BYTE_ORDER == __BIG_ENDIAN
2890 uint64_t pdf : 64; /**< Fuse information - Product Definition Field */
2895 struct cvmx_mio_fus_pdf_s cn50xx;
2896 struct cvmx_mio_fus_pdf_s cn52xx;
2897 struct cvmx_mio_fus_pdf_s cn52xxp1;
2898 struct cvmx_mio_fus_pdf_s cn56xx;
2899 struct cvmx_mio_fus_pdf_s cn56xxp1;
2900 struct cvmx_mio_fus_pdf_s cn58xx;
2901 struct cvmx_mio_fus_pdf_s cn63xx;
2902 struct cvmx_mio_fus_pdf_s cn63xxp1;
2904 typedef union cvmx_mio_fus_pdf cvmx_mio_fus_pdf_t;
2910 * The core clkout postscaler should be placed in reset at least 10 ref clocks prior to changing
2911 * the core clkout select. The core clkout postscaler should remain under reset for at least 10
2912 * ref clocks after the core clkout select changes.
2914 * The pnr clkout postscaler should be placed in reset at least 10 ref clocks prior to changing
2915 * the pnr clkout select. The pnr clkout postscaler should remain under reset for at least 10
2916 * ref clocks after the pnr clkout select changes.
2918 union cvmx_mio_fus_pll
2921 struct cvmx_mio_fus_pll_s
2923 #if __BYTE_ORDER == __BIG_ENDIAN
2924 uint64_t reserved_8_63 : 56;
2925 uint64_t c_cout_rst : 1; /**< Core clkout postscaler reset */
2926 uint64_t c_cout_sel : 2; /**< Core clkout select
2927 (0=RCLK,1=PS output,2=PLL output, 3=GND) | $PR */
2928 uint64_t pnr_cout_rst : 1; /**< PNR clkout postscaler reset */
2929 uint64_t pnr_cout_sel : 2; /**< PNR clkout select
2930 (0=SCLK,1=PS output,2=PLL output, 3=GND) | $PR */
2931 uint64_t rfslip : 1; /**< Reserved */
2932 uint64_t fbslip : 1; /**< Reserved */
2934 uint64_t fbslip : 1;
2935 uint64_t rfslip : 1;
2936 uint64_t pnr_cout_sel : 2;
2937 uint64_t pnr_cout_rst : 1;
2938 uint64_t c_cout_sel : 2;
2939 uint64_t c_cout_rst : 1;
2940 uint64_t reserved_8_63 : 56;
2943 struct cvmx_mio_fus_pll_cn50xx
2945 #if __BYTE_ORDER == __BIG_ENDIAN
2946 uint64_t reserved_2_63 : 62;
2947 uint64_t rfslip : 1; /**< PLL reference clock slip */
2948 uint64_t fbslip : 1; /**< PLL feedback clock slip */
2950 uint64_t fbslip : 1;
2951 uint64_t rfslip : 1;
2952 uint64_t reserved_2_63 : 62;
2955 struct cvmx_mio_fus_pll_cn50xx cn52xx;
2956 struct cvmx_mio_fus_pll_cn50xx cn52xxp1;
2957 struct cvmx_mio_fus_pll_cn50xx cn56xx;
2958 struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
2959 struct cvmx_mio_fus_pll_cn50xx cn58xx;
2960 struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
2961 struct cvmx_mio_fus_pll_s cn63xx;
2962 struct cvmx_mio_fus_pll_s cn63xxp1;
2964 typedef union cvmx_mio_fus_pll cvmx_mio_fus_pll_t;
2973 * This CSR is not present in the HRM.
2975 * To write a bank of fuses, SW must set MIO_FUS_WADR[ADDR] to the bank to be
2976 * programmed and then set each bit within MIO_FUS_BNK_DATX to indicate which
2977 * fuses to blow. Once ADDR, and DAT are setup, SW can write to
2978 * MIO_FUS_PROG[PROG] to start the bank write and poll on PROG. Once PROG is
2979 * clear, the bank write is complete.
2981 * A soft blow is still subject to lockdown fuses. After a soft/warm reset, the
2982 * chip will behave as though the fuses were actually blown. A cold reset restores
2983 * the actual fuse valuse.
2985 union cvmx_mio_fus_prog
2988 struct cvmx_mio_fus_prog_s
2990 #if __BYTE_ORDER == __BIG_ENDIAN
2991 uint64_t reserved_2_63 : 62;
2992 uint64_t soft : 1; /**< When set with PROG, causes only the local storeage
2993 to change. Will not really blow any fuses. HW
2994 will clear when the program operation is complete */
2995 uint64_t prog : 1; /**< Blow the fuse bank
2996 SW will set PROG, and then the HW will clear
2997 when the program operation is complete */
3001 uint64_t reserved_2_63 : 62;
3004 struct cvmx_mio_fus_prog_cn30xx
3006 #if __BYTE_ORDER == __BIG_ENDIAN
3007 uint64_t reserved_1_63 : 63;
3008 uint64_t prog : 1; /**< Blow the fuse
3009 SW will set PROG, hold it for 10us, then clear it */
3012 uint64_t reserved_1_63 : 63;
3015 struct cvmx_mio_fus_prog_cn30xx cn31xx;
3016 struct cvmx_mio_fus_prog_cn30xx cn38xx;
3017 struct cvmx_mio_fus_prog_cn30xx cn38xxp2;
3018 struct cvmx_mio_fus_prog_cn30xx cn50xx;
3019 struct cvmx_mio_fus_prog_cn30xx cn52xx;
3020 struct cvmx_mio_fus_prog_cn30xx cn52xxp1;
3021 struct cvmx_mio_fus_prog_cn30xx cn56xx;
3022 struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
3023 struct cvmx_mio_fus_prog_cn30xx cn58xx;
3024 struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
3025 struct cvmx_mio_fus_prog_s cn63xx;
3026 struct cvmx_mio_fus_prog_s cn63xxp1;
3028 typedef union cvmx_mio_fus_prog cvmx_mio_fus_prog_t;
3031 * cvmx_mio_fus_prog_times
3037 * This CSR is not present in the HRM.
3039 * All values must be > 0 for correct electrical operation.
3041 * IFB fuses are 0..1791
3042 * L6G fuses are 1792 to 2047
3044 * The reset values are for IFB fuses for ref_clk of 100MHZ
3046 union cvmx_mio_fus_prog_times
3049 struct cvmx_mio_fus_prog_times_s
3051 #if __BYTE_ORDER == __BIG_ENDIAN
3052 uint64_t reserved_35_63 : 29;
3053 uint64_t vgate_pin : 1; /**< efuse vgate pin (L6G) */
3054 uint64_t fsrc_pin : 1; /**< efuse fsource pin (L6G) */
3055 uint64_t prog_pin : 1; /**< efuse program pin (IFB) */
3056 uint64_t reserved_6_31 : 26;
3057 uint64_t setup : 6; /**< efuse timing param
3059 SETUP = (tWRS/refclk period)-1
3061 For IFB: tWRS = 20ns
3062 For L6G: tWRS = 20ns */
3065 uint64_t reserved_6_31 : 26;
3066 uint64_t prog_pin : 1;
3067 uint64_t fsrc_pin : 1;
3068 uint64_t vgate_pin : 1;
3069 uint64_t reserved_35_63 : 29;
3072 struct cvmx_mio_fus_prog_times_cn50xx
3074 #if __BYTE_ORDER == __BIG_ENDIAN
3075 uint64_t reserved_33_63 : 31;
3076 uint64_t prog_pin : 1; /**< efuse program pin */
3077 uint64_t out : 8; /**< efuse timing param (ref_clks to delay 10ns) */
3078 uint64_t sclk_lo : 4; /**< efuse timing param (ref_clks to delay 5ns) */
3079 uint64_t sclk_hi : 12; /**< efuse timing param (ref_clks to delay 1000ns) */
3080 uint64_t setup : 8; /**< efuse timing param (ref_clks to delay 10ns) */
3083 uint64_t sclk_hi : 12;
3084 uint64_t sclk_lo : 4;
3086 uint64_t prog_pin : 1;
3087 uint64_t reserved_33_63 : 31;
3090 struct cvmx_mio_fus_prog_times_cn50xx cn52xx;
3091 struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1;
3092 struct cvmx_mio_fus_prog_times_cn50xx cn56xx;
3093 struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
3094 struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
3095 struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
3096 struct cvmx_mio_fus_prog_times_cn63xx
3098 #if __BYTE_ORDER == __BIG_ENDIAN
3099 uint64_t reserved_35_63 : 29;
3100 uint64_t vgate_pin : 1; /**< efuse vgate pin (L6G) */
3101 uint64_t fsrc_pin : 1; /**< efuse fsource pin (L6G) */
3102 uint64_t prog_pin : 1; /**< efuse program pin (IFB) */
3103 uint64_t out : 7; /**< efuse timing param
3105 OUT = (tOUT/refclk period)-1
3107 For IFB: tOUT = 20ns
3108 For L6G: tOUT = 20ns */
3109 uint64_t sclk_lo : 4; /**< efuse timing param
3111 SCLK_LO=(tSLO/refclk period)-1
3113 For IFB: tSLO = 20ns
3114 For L6G: tSLO = 20ns */
3115 uint64_t sclk_hi : 15; /**< efuse timing param
3116 ***NOTE: Pass 1.x reset value is 20000
3118 SCLK_HI=(tSHI/refclk period)-1
3120 For IFB: tSHI = 200us
3121 For L6G: tSHI = 25us */
3122 uint64_t setup : 6; /**< efuse timing param
3124 SETUP = (tWRS/refclk period)-1
3126 For IFB: tWRS = 20ns
3127 For L6G: tWRS = 20ns */
3130 uint64_t sclk_hi : 15;
3131 uint64_t sclk_lo : 4;
3133 uint64_t prog_pin : 1;
3134 uint64_t fsrc_pin : 1;
3135 uint64_t vgate_pin : 1;
3136 uint64_t reserved_35_63 : 29;
3139 struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1;
3141 typedef union cvmx_mio_fus_prog_times cvmx_mio_fus_prog_times_t;
3147 * To read an efuse, SW writes MIO_FUS_RCMD[ADDR,PEND] with the byte address of
3148 * the fuse in question, then SW can poll MIO_FUS_RCMD[PEND]. When PEND is
3149 * clear, then MIO_FUS_RCMD[DAT] is valid. In addition, if the efuse read went
3150 * to the efuse banks (eg. ((ADDR/16) not [0,1,7]) || EFUSE) SW can read
3151 * MIO_FUS_BNK_DATX which contains all 128 fuses in the bank associated in
3154 union cvmx_mio_fus_rcmd
3157 struct cvmx_mio_fus_rcmd_s
3159 #if __BYTE_ORDER == __BIG_ENDIAN
3160 uint64_t reserved_24_63 : 40;
3161 uint64_t dat : 8; /**< 8bits of fuse data */
3162 uint64_t reserved_13_15 : 3;
3163 uint64_t pend : 1; /**< SW sets this bit on a write to start FUSE read
3164 operation. HW clears when read is complete and
3166 uint64_t reserved_9_11 : 3;
3167 uint64_t efuse : 1; /**< When set, return data from the efuse storage
3168 rather than the local storage */
3169 uint64_t addr : 8; /**< The byte address of the fuse to read */
3173 uint64_t reserved_9_11 : 3;
3175 uint64_t reserved_13_15 : 3;
3177 uint64_t reserved_24_63 : 40;
3180 struct cvmx_mio_fus_rcmd_cn30xx
3182 #if __BYTE_ORDER == __BIG_ENDIAN
3183 uint64_t reserved_24_63 : 40;
3184 uint64_t dat : 8; /**< 8bits of fuse data */
3185 uint64_t reserved_13_15 : 3;
3186 uint64_t pend : 1; /**< SW sets this bit on a write to start FUSE read
3187 operation. HW clears when read is complete and
3189 uint64_t reserved_9_11 : 3;
3190 uint64_t efuse : 1; /**< When set, return data from the efuse storage
3191 rather than the local storage for the 320 HW fuses */
3192 uint64_t reserved_7_7 : 1;
3193 uint64_t addr : 7; /**< The byte address of the fuse to read */
3196 uint64_t reserved_7_7 : 1;
3198 uint64_t reserved_9_11 : 3;
3200 uint64_t reserved_13_15 : 3;
3202 uint64_t reserved_24_63 : 40;
3205 struct cvmx_mio_fus_rcmd_cn30xx cn31xx;
3206 struct cvmx_mio_fus_rcmd_cn30xx cn38xx;
3207 struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2;
3208 struct cvmx_mio_fus_rcmd_cn30xx cn50xx;
3209 struct cvmx_mio_fus_rcmd_s cn52xx;
3210 struct cvmx_mio_fus_rcmd_s cn52xxp1;
3211 struct cvmx_mio_fus_rcmd_s cn56xx;
3212 struct cvmx_mio_fus_rcmd_s cn56xxp1;
3213 struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
3214 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
3215 struct cvmx_mio_fus_rcmd_s cn63xx;
3216 struct cvmx_mio_fus_rcmd_s cn63xxp1;
3218 typedef union cvmx_mio_fus_rcmd cvmx_mio_fus_rcmd_t;
3221 * cvmx_mio_fus_read_times
3224 * IFB fuses are 0..1791
3225 * L6G fuses are 1792 to 2047
3227 * The reset values are for IFB fuses for refclk up to 100MHZ when core PLL is enagaged
3228 * The reset values are for IFB fuses for refclk up to 500MHZ when core PLL is not enagaged
3230 * If any of the formulas above result in a value less than zero, the corresponding
3231 * timing parameter should be set to zero.
3233 * Prior to issuing a read to the fuse banks (via. MIO_FUS_RCMD), this register
3234 * should be written with the timing parameters which correspond to the fuse bank type (IFB vs L6G)
3235 * that will be read.
3237 * This register should not be written while MIO_FUS_RCMD[PEND]=1.
3239 union cvmx_mio_fus_read_times
3242 struct cvmx_mio_fus_read_times_s
3244 #if __BYTE_ORDER == __BIG_ENDIAN
3245 uint64_t reserved_26_63 : 38;
3246 uint64_t sch : 4; /**< Hold CS for (SCH+1) refclks after FSET desserts
3248 SCH = (tSCH/refclk period)-1
3250 For IFB: tSCH = 160ns
3251 For L6G: tSCH = 10ns */
3252 uint64_t fsh : 4; /**< Hold FSET for (FSH+1) refclks after PRCHG deasserts
3254 FSH = (tFSH/refclk period)-1
3256 For IFB: tFSH = 160ns
3257 For L6G: tFSH = 10ns */
3258 uint64_t prh : 4; /**< Assert PRCHG (PRH+1) refclks after SIGDEV deasserts
3260 PRH = (tPRH/refclk period)-1
3262 For IFB: tPRH = 70ns
3263 For L6G: tPRH = 10ns */
3264 uint64_t sdh : 4; /**< Hold SIGDEV for (SDH+1) refclks after FSET asserts
3266 SDH = (tSDH/refclk period)-1
3268 For IFB: tPRH = 10ns
3269 For L6G: tPRH = 10ns */
3270 uint64_t setup : 10; /**< Assert CS for (SETUP+1) refclks before asserting
3271 SIGDEV, FSET, or PRCHG
3273 SETUP=(tRDS/refclk period)-1
3275 For IFB: tRDS = 10000ns
3276 For L6G: tRDS = max(tSCS,tSDS,tPRS)
3281 uint64_t setup : 10;
3286 uint64_t reserved_26_63 : 38;
3289 struct cvmx_mio_fus_read_times_s cn63xx;
3290 struct cvmx_mio_fus_read_times_s cn63xxp1;
3292 typedef union cvmx_mio_fus_read_times cvmx_mio_fus_read_times_t;
3295 * cvmx_mio_fus_repair_res0
3297 union cvmx_mio_fus_repair_res0
3300 struct cvmx_mio_fus_repair_res0_s
3302 #if __BYTE_ORDER == __BIG_ENDIAN
3303 uint64_t reserved_55_63 : 9;
3304 uint64_t too_many : 1; /**< Too many defects */
3305 uint64_t repair2 : 18; /**< BISR Results */
3306 uint64_t repair1 : 18; /**< BISR Results */
3307 uint64_t repair0 : 18; /**< BISR Results */
3309 uint64_t repair0 : 18;
3310 uint64_t repair1 : 18;
3311 uint64_t repair2 : 18;
3312 uint64_t too_many : 1;
3313 uint64_t reserved_55_63 : 9;
3316 struct cvmx_mio_fus_repair_res0_s cn63xx;
3317 struct cvmx_mio_fus_repair_res0_s cn63xxp1;
3319 typedef union cvmx_mio_fus_repair_res0 cvmx_mio_fus_repair_res0_t;
3322 * cvmx_mio_fus_repair_res1
3324 union cvmx_mio_fus_repair_res1
3327 struct cvmx_mio_fus_repair_res1_s
3329 #if __BYTE_ORDER == __BIG_ENDIAN
3330 uint64_t reserved_54_63 : 10;
3331 uint64_t repair5 : 18; /**< BISR Results */
3332 uint64_t repair4 : 18; /**< BISR Results */
3333 uint64_t repair3 : 18; /**< BISR Results */
3335 uint64_t repair3 : 18;
3336 uint64_t repair4 : 18;
3337 uint64_t repair5 : 18;
3338 uint64_t reserved_54_63 : 10;
3341 struct cvmx_mio_fus_repair_res1_s cn63xx;
3342 struct cvmx_mio_fus_repair_res1_s cn63xxp1;
3344 typedef union cvmx_mio_fus_repair_res1 cvmx_mio_fus_repair_res1_t;
3347 * cvmx_mio_fus_repair_res2
3349 union cvmx_mio_fus_repair_res2
3352 struct cvmx_mio_fus_repair_res2_s
3354 #if __BYTE_ORDER == __BIG_ENDIAN
3355 uint64_t reserved_18_63 : 46;
3356 uint64_t repair6 : 18; /**< BISR Results */
3358 uint64_t repair6 : 18;
3359 uint64_t reserved_18_63 : 46;
3362 struct cvmx_mio_fus_repair_res2_s cn63xx;
3363 struct cvmx_mio_fus_repair_res2_s cn63xxp1;
3365 typedef union cvmx_mio_fus_repair_res2 cvmx_mio_fus_repair_res2_t;
3368 * cvmx_mio_fus_spr_repair_res
3374 union cvmx_mio_fus_spr_repair_res
3377 struct cvmx_mio_fus_spr_repair_res_s
3379 #if __BYTE_ORDER == __BIG_ENDIAN
3380 uint64_t reserved_42_63 : 22;
3381 uint64_t repair2 : 14; /**< Reserved (see MIO_FUS_REPAIR_RES*) */
3382 uint64_t repair1 : 14; /**< Reserved (see MIO_FUS_REPAIR_RES*) */
3383 uint64_t repair0 : 14; /**< Reserved (see MIO_FUS_REPAIR_RES*) */
3385 uint64_t repair0 : 14;
3386 uint64_t repair1 : 14;
3387 uint64_t repair2 : 14;
3388 uint64_t reserved_42_63 : 22;
3391 struct cvmx_mio_fus_spr_repair_res_s cn30xx;
3392 struct cvmx_mio_fus_spr_repair_res_s cn31xx;
3393 struct cvmx_mio_fus_spr_repair_res_s cn38xx;
3394 struct cvmx_mio_fus_spr_repair_res_s cn50xx;
3395 struct cvmx_mio_fus_spr_repair_res_s cn52xx;
3396 struct cvmx_mio_fus_spr_repair_res_s cn52xxp1;
3397 struct cvmx_mio_fus_spr_repair_res_s cn56xx;
3398 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
3399 struct cvmx_mio_fus_spr_repair_res_s cn58xx;
3400 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
3401 struct cvmx_mio_fus_spr_repair_res_s cn63xx;
3402 struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
3404 typedef union cvmx_mio_fus_spr_repair_res cvmx_mio_fus_spr_repair_res_t;
3407 * cvmx_mio_fus_spr_repair_sum
3413 union cvmx_mio_fus_spr_repair_sum
3416 struct cvmx_mio_fus_spr_repair_sum_s
3418 #if __BYTE_ORDER == __BIG_ENDIAN
3419 uint64_t reserved_1_63 : 63;
3420 uint64_t too_many : 1; /**< Reserved (see MIO_FUS_REPAIR_RES*) */
3422 uint64_t too_many : 1;
3423 uint64_t reserved_1_63 : 63;
3426 struct cvmx_mio_fus_spr_repair_sum_s cn30xx;
3427 struct cvmx_mio_fus_spr_repair_sum_s cn31xx;
3428 struct cvmx_mio_fus_spr_repair_sum_s cn38xx;
3429 struct cvmx_mio_fus_spr_repair_sum_s cn50xx;
3430 struct cvmx_mio_fus_spr_repair_sum_s cn52xx;
3431 struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1;
3432 struct cvmx_mio_fus_spr_repair_sum_s cn56xx;
3433 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
3434 struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
3435 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
3436 struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
3437 struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
3439 typedef union cvmx_mio_fus_spr_repair_sum cvmx_mio_fus_spr_repair_sum_t;
3442 * cvmx_mio_fus_unlock
3444 union cvmx_mio_fus_unlock
3447 struct cvmx_mio_fus_unlock_s
3449 #if __BYTE_ORDER == __BIG_ENDIAN
3450 uint64_t reserved_24_63 : 40;
3451 uint64_t key : 24; /**< When set to the typical value, allows SW to
3452 program the efuses */
3455 uint64_t reserved_24_63 : 40;
3458 struct cvmx_mio_fus_unlock_s cn30xx;
3459 struct cvmx_mio_fus_unlock_s cn31xx;
3461 typedef union cvmx_mio_fus_unlock cvmx_mio_fus_unlock_t;
3466 union cvmx_mio_fus_wadr
3469 struct cvmx_mio_fus_wadr_s
3471 #if __BYTE_ORDER == __BIG_ENDIAN
3472 uint64_t reserved_10_63 : 54;
3473 uint64_t addr : 10; /**< Which of the banks of 128 fuses to blow */
3476 uint64_t reserved_10_63 : 54;
3479 struct cvmx_mio_fus_wadr_s cn30xx;
3480 struct cvmx_mio_fus_wadr_s cn31xx;
3481 struct cvmx_mio_fus_wadr_s cn38xx;
3482 struct cvmx_mio_fus_wadr_s cn38xxp2;
3483 struct cvmx_mio_fus_wadr_cn50xx
3485 #if __BYTE_ORDER == __BIG_ENDIAN
3486 uint64_t reserved_2_63 : 62;
3487 uint64_t addr : 2; /**< Which of the four banks of 256 fuses to blow */
3490 uint64_t reserved_2_63 : 62;
3493 struct cvmx_mio_fus_wadr_cn52xx
3495 #if __BYTE_ORDER == __BIG_ENDIAN
3496 uint64_t reserved_3_63 : 61;
3497 uint64_t addr : 3; /**< Which of the four banks of 256 fuses to blow */
3500 uint64_t reserved_3_63 : 61;
3503 struct cvmx_mio_fus_wadr_cn52xx cn52xxp1;
3504 struct cvmx_mio_fus_wadr_cn52xx cn56xx;
3505 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
3506 struct cvmx_mio_fus_wadr_cn50xx cn58xx;
3507 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
3508 struct cvmx_mio_fus_wadr_cn63xx
3510 #if __BYTE_ORDER == __BIG_ENDIAN
3511 uint64_t reserved_4_63 : 60;
3512 uint64_t addr : 4; /**< Which of the banks of 128 fuses to blow */
3515 uint64_t reserved_4_63 : 60;
3518 struct cvmx_mio_fus_wadr_cn63xx cn63xxp1;
3520 typedef union cvmx_mio_fus_wadr cvmx_mio_fus_wadr_t;
3523 * cvmx_mio_gpio_comp
3525 * MIO_GPIO_COMP = MIO GPIO Compensation Register
3528 union cvmx_mio_gpio_comp
3531 struct cvmx_mio_gpio_comp_s
3533 #if __BYTE_ORDER == __BIG_ENDIAN
3534 uint64_t reserved_12_63 : 52;
3535 uint64_t pctl : 6; /**< GPIO bus PCTL */
3536 uint64_t nctl : 6; /**< GPIO bus NCTL */
3540 uint64_t reserved_12_63 : 52;
3543 struct cvmx_mio_gpio_comp_s cn63xx;
3544 struct cvmx_mio_gpio_comp_s cn63xxp1;
3546 typedef union cvmx_mio_gpio_comp cvmx_mio_gpio_comp_t;
3549 * cvmx_mio_ndf_dma_cfg
3551 * MIO_NDF_DMA_CFG = MIO NAND Flash DMA Config Register
3553 * SIZE is specified in number of 64 bit transfers (encoded in -1 notation).
3555 * ADR must be 64 bit aligned.
3557 union cvmx_mio_ndf_dma_cfg
3560 struct cvmx_mio_ndf_dma_cfg_s
3562 #if __BYTE_ORDER == __BIG_ENDIAN
3563 uint64_t en : 1; /**< DMA Engine enable */
3564 uint64_t rw : 1; /**< DMA Engine R/W bit (0 = read, 1 = write) */
3565 uint64_t clr : 1; /**< DMA Engine clear EN on device terminated burst */
3566 uint64_t reserved_60_60 : 1;
3567 uint64_t swap32 : 1; /**< DMA Engine 32 bit swap */
3568 uint64_t swap16 : 1; /**< DMA Engine 16 bit swap */
3569 uint64_t swap8 : 1; /**< DMA Engine 8 bit swap */
3570 uint64_t endian : 1; /**< DMA Engine NCB endian mode (0 = big, 1 = little) */
3571 uint64_t size : 20; /**< DMA Engine size */
3572 uint64_t adr : 36; /**< DMA Engine address */
3576 uint64_t endian : 1;
3578 uint64_t swap16 : 1;
3579 uint64_t swap32 : 1;
3580 uint64_t reserved_60_60 : 1;
3586 struct cvmx_mio_ndf_dma_cfg_s cn52xx;
3587 struct cvmx_mio_ndf_dma_cfg_s cn63xx;
3588 struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
3590 typedef union cvmx_mio_ndf_dma_cfg cvmx_mio_ndf_dma_cfg_t;
3593 * cvmx_mio_ndf_dma_int
3595 * MIO_NDF_DMA_INT = MIO NAND Flash DMA Interrupt Register
3598 union cvmx_mio_ndf_dma_int
3601 struct cvmx_mio_ndf_dma_int_s
3603 #if __BYTE_ORDER == __BIG_ENDIAN
3604 uint64_t reserved_1_63 : 63;
3605 uint64_t done : 1; /**< DMA Engine request completion interrupt */
3608 uint64_t reserved_1_63 : 63;
3611 struct cvmx_mio_ndf_dma_int_s cn52xx;
3612 struct cvmx_mio_ndf_dma_int_s cn63xx;
3613 struct cvmx_mio_ndf_dma_int_s cn63xxp1;
3615 typedef union cvmx_mio_ndf_dma_int cvmx_mio_ndf_dma_int_t;
3618 * cvmx_mio_ndf_dma_int_en
3620 * MIO_NDF_DMA_INT_EN = MIO NAND Flash DMA Interrupt Enable Register
3623 union cvmx_mio_ndf_dma_int_en
3626 struct cvmx_mio_ndf_dma_int_en_s
3628 #if __BYTE_ORDER == __BIG_ENDIAN
3629 uint64_t reserved_1_63 : 63;
3630 uint64_t done : 1; /**< DMA Engine request completion interrupt enable */
3633 uint64_t reserved_1_63 : 63;
3636 struct cvmx_mio_ndf_dma_int_en_s cn52xx;
3637 struct cvmx_mio_ndf_dma_int_en_s cn63xx;
3638 struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
3640 typedef union cvmx_mio_ndf_dma_int_en cvmx_mio_ndf_dma_int_en_t;
3645 union cvmx_mio_pll_ctl
3648 struct cvmx_mio_pll_ctl_s
3650 #if __BYTE_ORDER == __BIG_ENDIAN
3651 uint64_t reserved_5_63 : 59;
3652 uint64_t bw_ctl : 5; /**< Core PLL bandwidth control */
3654 uint64_t bw_ctl : 5;
3655 uint64_t reserved_5_63 : 59;
3658 struct cvmx_mio_pll_ctl_s cn30xx;
3659 struct cvmx_mio_pll_ctl_s cn31xx;
3661 typedef union cvmx_mio_pll_ctl cvmx_mio_pll_ctl_t;
3664 * cvmx_mio_pll_setting
3666 union cvmx_mio_pll_setting
3669 struct cvmx_mio_pll_setting_s
3671 #if __BYTE_ORDER == __BIG_ENDIAN
3672 uint64_t reserved_17_63 : 47;
3673 uint64_t setting : 17; /**< Core PLL setting */
3675 uint64_t setting : 17;
3676 uint64_t reserved_17_63 : 47;
3679 struct cvmx_mio_pll_setting_s cn30xx;
3680 struct cvmx_mio_pll_setting_s cn31xx;
3682 typedef union cvmx_mio_pll_setting cvmx_mio_pll_setting_t;
3685 * cvmx_mio_ptp_clock_cfg
3687 * MIO_PTP_CLOCK_CFG = Configuration
3690 union cvmx_mio_ptp_clock_cfg
3693 struct cvmx_mio_ptp_clock_cfg_s
3695 #if __BYTE_ORDER == __BIG_ENDIAN
3696 uint64_t reserved_24_63 : 40;
3697 uint64_t evcnt_in : 6; /**< Source for event counter input
3698 0x00-0x0f : GPIO[EVCNT_IN[3:0]]
3702 0x13-0x3f : Reserved */
3703 uint64_t evcnt_edge : 1; /**< Event counter input edge
3706 uint64_t evcnt_en : 1; /**< Enable event counter */
3707 uint64_t tstmp_in : 6; /**< Source for timestamp input
3708 0x00-0x0f : GPIO[TSTMP_IN[3:0]]
3712 0x13-0x3f : Reserved */
3713 uint64_t tstmp_edge : 1; /**< External timestamp input edge
3716 uint64_t tstmp_en : 1; /**< Enable external timestamp */
3717 uint64_t ext_clk_in : 6; /**< Source for external clock
3718 0x00-0x0f : GPIO[EXT_CLK_IN[3:0]]
3722 0x13-0x3f : Reserved */
3723 uint64_t ext_clk_en : 1; /**< Use positive edge of external clock */
3724 uint64_t ptp_en : 1; /**< Enable PTP Module */
3726 uint64_t ptp_en : 1;
3727 uint64_t ext_clk_en : 1;
3728 uint64_t ext_clk_in : 6;
3729 uint64_t tstmp_en : 1;
3730 uint64_t tstmp_edge : 1;
3731 uint64_t tstmp_in : 6;
3732 uint64_t evcnt_en : 1;
3733 uint64_t evcnt_edge : 1;
3734 uint64_t evcnt_in : 6;
3735 uint64_t reserved_24_63 : 40;
3738 struct cvmx_mio_ptp_clock_cfg_s cn63xx;
3739 struct cvmx_mio_ptp_clock_cfg_s cn63xxp1;
3741 typedef union cvmx_mio_ptp_clock_cfg cvmx_mio_ptp_clock_cfg_t;
3744 * cvmx_mio_ptp_clock_comp
3746 * MIO_PTP_CLOCK_COMP = Compensator
3749 union cvmx_mio_ptp_clock_comp
3752 struct cvmx_mio_ptp_clock_comp_s
3754 #if __BYTE_ORDER == __BIG_ENDIAN
3755 uint64_t nanosec : 32; /**< Nanoseconds */
3756 uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */
3758 uint64_t frnanosec : 32;
3759 uint64_t nanosec : 32;
3762 struct cvmx_mio_ptp_clock_comp_s cn63xx;
3763 struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
3765 typedef union cvmx_mio_ptp_clock_comp cvmx_mio_ptp_clock_comp_t;
3768 * cvmx_mio_ptp_clock_hi
3770 * MIO_PTP_CLOCK_HI = Hi bytes of CLOCK
3772 * Writes to MIO_PTP_CLOCK_HI also clear MIO_PTP_CLOCK_LO. To update all 96 bits, write MIO_PTP_CLOCK_HI followed
3773 * by MIO_PTP_CLOCK_LO
3775 union cvmx_mio_ptp_clock_hi
3778 struct cvmx_mio_ptp_clock_hi_s
3780 #if __BYTE_ORDER == __BIG_ENDIAN
3781 uint64_t nanosec : 64; /**< Nanoseconds */
3783 uint64_t nanosec : 64;
3786 struct cvmx_mio_ptp_clock_hi_s cn63xx;
3787 struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
3789 typedef union cvmx_mio_ptp_clock_hi cvmx_mio_ptp_clock_hi_t;
3792 * cvmx_mio_ptp_clock_lo
3794 * MIO_PTP_CLOCK_LO = Lo bytes of CLOCK
3797 union cvmx_mio_ptp_clock_lo
3800 struct cvmx_mio_ptp_clock_lo_s
3802 #if __BYTE_ORDER == __BIG_ENDIAN
3803 uint64_t reserved_32_63 : 32;
3804 uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */
3806 uint64_t frnanosec : 32;
3807 uint64_t reserved_32_63 : 32;
3810 struct cvmx_mio_ptp_clock_lo_s cn63xx;
3811 struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
3813 typedef union cvmx_mio_ptp_clock_lo cvmx_mio_ptp_clock_lo_t;
3816 * cvmx_mio_ptp_evt_cnt
3818 * MIO_PTP_EVT_CNT = Event Counter
3820 * Writes to MIO_PTP_EVT_CNT increment this register by the written data. The register counts down by
3821 * 1 for every MIO_PTP_CLOCK_CFG[EVCNT_EDGE] edge of MIO_PTP_CLOCK_CFG[EVCNT_IN]. When register equals
3822 * 0, an interrupt gets gerated
3824 union cvmx_mio_ptp_evt_cnt
3827 struct cvmx_mio_ptp_evt_cnt_s
3829 #if __BYTE_ORDER == __BIG_ENDIAN
3830 uint64_t cntr : 64; /**< Nanoseconds */
3835 struct cvmx_mio_ptp_evt_cnt_s cn63xx;
3836 struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
3838 typedef union cvmx_mio_ptp_evt_cnt cvmx_mio_ptp_evt_cnt_t;
3841 * cvmx_mio_ptp_timestamp
3843 * MIO_PTP_TIMESTAMP = Timestamp latched on MIO_PTP_CLOCK_CFG[TSTMP_EDGE] edge of MIO_PTP_CLOCK_CFG[TSTMP_IN]
3846 union cvmx_mio_ptp_timestamp
3849 struct cvmx_mio_ptp_timestamp_s
3851 #if __BYTE_ORDER == __BIG_ENDIAN
3852 uint64_t nanosec : 64; /**< Nanoseconds */
3854 uint64_t nanosec : 64;
3857 struct cvmx_mio_ptp_timestamp_s cn63xx;
3858 struct cvmx_mio_ptp_timestamp_s cn63xxp1;
3860 typedef union cvmx_mio_ptp_timestamp cvmx_mio_ptp_timestamp_t;
3865 union cvmx_mio_rst_boot
3868 struct cvmx_mio_rst_boot_s
3870 #if __BYTE_ORDER == __BIG_ENDIAN
3871 uint64_t reserved_36_63 : 28;
3872 uint64_t c_mul : 6; /**< Core clock multiplier:
3873 C_MUL = (core clk speed) / (ref clock speed)
3874 "ref clock speed" should always be 50MHz.
3875 If PLL_QLM_REF_CLK_EN=0, "ref clock" comes
3876 from PLL_REF_CLK pin.
3877 If PLL_QLM_REF_CLK_EN=1, "ref clock" is
3878 1/2 speed of QLMC_REF_CLK_* pins. */
3879 uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier:
3880 PNR_MUL = (coprocessor clk speed) /
3882 See C_MUL comments about ref clock. */
3883 uint64_t qlm2_spd : 4; /**< QLM2_SPD pins sampled at DCOK assertion */
3884 uint64_t qlm1_spd : 4; /**< QLM1_SPD pins sampled at DCOK assertion */
3885 uint64_t qlm0_spd : 4; /**< QLM0_SPD pins sampled at DCOK assertion */
3886 uint64_t lboot : 10; /**< Last boot cause mask, resets only with dock.
3888 bit9 - Soft reset due to watchdog
3889 bit8 - Soft reset due to CIU_SOFT_RST write
3890 bit7 - Warm reset due to cntl0 link-down or
3892 bit6 - Warm reset due to cntl1 link-down or
3894 bit5 - Cntl1 reset due to PERST1_L pin
3895 bit4 - Cntl0 reset due to PERST0_L pin
3896 bit3 - Warm reset due to PERST1_L pin
3897 bit2 - Warm reset due to PERST0_L pin
3898 bit1 - Warm reset due to CHIP_RESET_L pin
3899 bit0 - Cold reset due to DCOK pin */
3900 uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after
3901 after chip cold/warm/soft reset. */
3902 uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */
3904 uint64_t rboot_pin : 1;
3906 uint64_t lboot : 10;
3907 uint64_t qlm0_spd : 4;
3908 uint64_t qlm1_spd : 4;
3909 uint64_t qlm2_spd : 4;
3910 uint64_t pnr_mul : 6;
3912 uint64_t reserved_36_63 : 28;
3915 struct cvmx_mio_rst_boot_s cn63xx;
3916 struct cvmx_mio_rst_boot_s cn63xxp1;
3918 typedef union cvmx_mio_rst_boot cvmx_mio_rst_boot_t;
3924 * Cold reset will always performs a full bist.
3927 union cvmx_mio_rst_cfg
3930 struct cvmx_mio_rst_cfg_s
3932 #if __BYTE_ORDER == __BIG_ENDIAN
3933 uint64_t bist_delay : 58; /**< Reserved */
3934 uint64_t reserved_3_5 : 3;
3935 uint64_t cntl_clr_bist : 1; /**< Peform clear bist during cntl only reset,
3936 instead of a full bist. A warm/soft reset will
3937 not change this field. */
3938 uint64_t warm_clr_bist : 1; /**< Peform clear bist during warm reset, instead
3939 of a full bist. A warm/soft reset will not
3940 change this field. */
3941 uint64_t soft_clr_bist : 1; /**< Peform clear bist during soft reset, instead
3942 of a full bist. A warm/soft reset will not
3943 change this field. */
3945 uint64_t soft_clr_bist : 1;
3946 uint64_t warm_clr_bist : 1;
3947 uint64_t cntl_clr_bist : 1;
3948 uint64_t reserved_3_5 : 3;
3949 uint64_t bist_delay : 58;
3952 struct cvmx_mio_rst_cfg_s cn63xx;
3953 struct cvmx_mio_rst_cfg_cn63xxp1
3955 #if __BYTE_ORDER == __BIG_ENDIAN
3956 uint64_t bist_delay : 58; /**< Reserved */
3957 uint64_t reserved_2_5 : 4;
3958 uint64_t warm_clr_bist : 1; /**< Peform clear bist during warm reset, instead
3959 of a full bist. A warm/soft reset will not
3960 change this field. */
3961 uint64_t soft_clr_bist : 1; /**< Peform clear bist during soft reset, instead
3962 of a full bist. A warm/soft reset will not
3963 change this field. */
3965 uint64_t soft_clr_bist : 1;
3966 uint64_t warm_clr_bist : 1;
3967 uint64_t reserved_2_5 : 4;
3968 uint64_t bist_delay : 58;
3972 typedef union cvmx_mio_rst_cfg cvmx_mio_rst_cfg_t;
3977 union cvmx_mio_rst_ctlx
3980 struct cvmx_mio_rst_ctlx_s
3982 #if __BYTE_ORDER == __BIG_ENDIAN
3983 uint64_t reserved_10_63 : 54;
3984 uint64_t prst_link : 1; /**< Controls whether corresponding controller
3985 link-down or hot-reset causes the assertion of
3986 CIU_SOFT_PRST*[SOFT_PRST]
3988 A warm/soft reset will not change this field.
3989 On cold reset, this field is initialized to 0
3991 0 = when corresponding strap QLM*_HOST_MODE=1
3992 1 = when corresponding strap QLM*_HOST_MODE=0
3994 ***NOTE: Added in pass 2.0 */
3995 uint64_t rst_done : 1; /**< Read-only access to controller reset status
3997 RESET_DONE is always zero (i.e. the controller
3998 is held in reset) when:
3999 - CIU_SOFT_PRST*[SOFT_PRST]=1, or
4000 - RST_RCV==1 and PERST*_L pin is asserted */
4001 uint64_t rst_link : 1; /**< Controls whether corresponding controller
4002 link-down or hot-reset causes a warm chip reset
4003 On cold reset, this field is initialized as
4005 0 = when corresponding strap QLM*_HOST_MODE=1
4006 1 = when corresponding strap QLM*_HOST_MODE=0
4008 Note that a link-down or hot-reset event can
4009 never cause a warm chip reset when the
4010 controller is in reset (i.e. can never cause a
4011 warm reset when RST_DONE==0). */
4012 uint64_t host_mode : 1; /**< RO access to corresponding strap QLM*_HOST_MODE */
4013 uint64_t prtmode : 2; /**< Port mode
4017 A warm/soft reset will not change this field.
4018 On cold reset, this field is initialized as
4020 0 = when corresponding strap QLM*_HOST_MODE=0
4021 1 = when corresponding strap QLM*_HOST_MODE=1 */
4022 uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin
4023 is driven by the OCTEON. A warm/soft reset
4024 will not change this field. On cold reset,
4025 this field is initialized as follows:
4026 0 = when corresponding strap QLM*_HOST_MODE=0
4027 1 = when corresponding strap QLM*_HOST_MODE=1
4029 When set, OCTEON drives the corresponding
4030 PERST*_L pin. Otherwise, OCTEON does not drive
4031 the corresponding PERST*_L pin. */
4032 uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin
4033 is recieved by OCTEON. A warm/soft reset
4034 will not change this field. On cold reset,
4035 this field is initialized as follows:
4036 0 = when corresponding strap QLM*_HOST_MODE=1
4037 1 = when corresponding strap QLM*_HOST_MODE=0
4039 When RST_RCV==1, the PERST*_L value is
4040 received and may be used to reset the
4041 controller and (optionally, based on RST_CHIP)
4042 warm reset the chip.
4044 When RST_RCV==1 (and RST_CHIP=0),
4045 MIO_RST_INT[PERST*] gets set when the PERST*_L
4046 pin asserts. (This interrupt can alert SW
4047 whenever the external reset pin initiates a
4048 controller reset sequence.)
4050 RST_VAL gives the PERST*_L pin value when
4053 When RST_RCV==0, the PERST*_L pin value is
4055 uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip
4056 pin causes a chip warm reset like CHIP_RESET_L.
4057 A warm/soft reset will not change this field.
4058 On cold reset, this field is initialized to 0.
4060 RST_CHIP is not used when RST_RCV==0.
4062 When RST_RCV==0, RST_CHIP is ignored.
4064 When RST_RCV==1, RST_CHIP==1, and PERST*_L
4065 asserts, a chip warm reset will be generated. */
4066 uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin
4067 Unpredictable when RST_RCV==0. Reads as 1 when
4068 RST_RCV==1 and the PERST*_L pin is asserted.
4069 Reads as 0 when RST_RCV==1 and the PERST*_L
4070 pin is not asserted. */
4072 uint64_t rst_val : 1;
4073 uint64_t rst_chip : 1;
4074 uint64_t rst_rcv : 1;
4075 uint64_t rst_drv : 1;
4076 uint64_t prtmode : 2;
4077 uint64_t host_mode : 1;
4078 uint64_t rst_link : 1;
4079 uint64_t rst_done : 1;
4080 uint64_t prst_link : 1;
4081 uint64_t reserved_10_63 : 54;
4084 struct cvmx_mio_rst_ctlx_s cn63xx;
4085 struct cvmx_mio_rst_ctlx_cn63xxp1
4087 #if __BYTE_ORDER == __BIG_ENDIAN
4088 uint64_t reserved_9_63 : 55;
4089 uint64_t rst_done : 1; /**< Read-only access to controller reset status
4091 RESET_DONE is always zero (i.e. the controller
4092 is held in reset) when:
4093 - CIU_SOFT_PRST*[SOFT_PRST]=1, or
4094 - RST_RCV==1 and PERST*_L pin is asserted */
4095 uint64_t rst_link : 1; /**< Controls whether corresponding controller
4096 link-down or hot-reset causes a warm chip reset
4097 On cold reset, this field is initialized as
4099 0 = when corresponding strap QLM*_HOST_MODE=1
4100 1 = when corresponding strap QLM*_HOST_MODE=0
4102 Note that a link-down or hot-reset event can
4103 never cause a warm chip reset when the
4104 controller is in reset (i.e. can never cause a
4105 warm reset when RST_DONE==0). */
4106 uint64_t host_mode : 1; /**< RO access to corresponding strap QLM*_HOST_MODE */
4107 uint64_t prtmode : 2; /**< Port mode
4111 A warm/soft reset will not change this field.
4112 On cold reset, this field is initialized as
4114 0 = when corresponding strap QLM*_HOST_MODE=0
4115 1 = when corresponding strap QLM*_HOST_MODE=1 */
4116 uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin
4117 is driven by the OCTEON. A warm/soft reset
4118 will not change this field. On cold reset,
4119 this field is initialized as follows:
4120 0 = when corresponding strap QLM*_HOST_MODE=0
4121 1 = when corresponding strap QLM*_HOST_MODE=1
4123 When set, OCTEON drives the corresponding
4124 PERST*_L pin. Otherwise, OCTEON does not drive
4125 the corresponding PERST*_L pin. */
4126 uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin
4127 is recieved by OCTEON. A warm/soft reset
4128 will not change this field. On cold reset,
4129 this field is initialized as follows:
4130 0 = when corresponding strap QLM*_HOST_MODE=1
4131 1 = when corresponding strap QLM*_HOST_MODE=0
4133 When RST_RCV==1, the PERST*_L value is
4134 received and may be used to reset the
4135 controller and (optionally, based on RST_CHIP)
4136 warm reset the chip.
4138 When RST_RCV==1 (and RST_CHIP=0),
4139 MIO_RST_INT[PERST*] gets set when the PERST*_L
4140 pin asserts. (This interrupt can alert SW
4141 whenever the external reset pin initiates a
4142 controller reset sequence.)
4144 RST_VAL gives the PERST*_L pin value when
4147 When RST_RCV==0, the PERST*_L pin value is
4149 uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip
4150 pin causes a chip warm reset like CHIP_RESET_L.
4151 A warm/soft reset will not change this field.
4152 On cold reset, this field is initialized to 0.
4154 RST_CHIP is not used when RST_RCV==0.
4156 When RST_RCV==0, RST_CHIP is ignored.
4158 When RST_RCV==1, RST_CHIP==1, and PERST*_L
4159 asserts, a chip warm reset will be generated. */
4160 uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin
4161 Unpredictable when RST_RCV==0. Reads as 1 when
4162 RST_RCV==1 and the PERST*_L pin is asserted.
4163 Reads as 0 when RST_RCV==1 and the PERST*_L
4164 pin is not asserted. */
4166 uint64_t rst_val : 1;
4167 uint64_t rst_chip : 1;
4168 uint64_t rst_rcv : 1;
4169 uint64_t rst_drv : 1;
4170 uint64_t prtmode : 2;
4171 uint64_t host_mode : 1;
4172 uint64_t rst_link : 1;
4173 uint64_t rst_done : 1;
4174 uint64_t reserved_9_63 : 55;
4178 typedef union cvmx_mio_rst_ctlx cvmx_mio_rst_ctlx_t;
4181 * cvmx_mio_rst_delay
4183 union cvmx_mio_rst_delay
4186 struct cvmx_mio_rst_delay_s
4188 #if __BYTE_ORDER == __BIG_ENDIAN
4189 uint64_t reserved_32_63 : 32;
4190 uint64_t soft_rst_dly : 16; /**< A soft reset immediately causes an early soft
4191 reset notification. However, the assertion of
4192 soft reset will be delayed this many sclks.
4193 A warm/soft reset will not change this field.
4194 NOTE: This must be at least 500 dclks */
4195 uint64_t warm_rst_dly : 16; /**< A warm reset immediately causes an early warm
4196 reset notification. However, the assertion of
4197 warm reset will be delayed this many sclks.
4198 A warm/soft reset will not change this field.
4199 NOTE: This must be at least 500 dclks */
4201 uint64_t warm_rst_dly : 16;
4202 uint64_t soft_rst_dly : 16;
4203 uint64_t reserved_32_63 : 32;
4206 struct cvmx_mio_rst_delay_s cn63xx;
4207 struct cvmx_mio_rst_delay_s cn63xxp1;
4209 typedef union cvmx_mio_rst_delay cvmx_mio_rst_delay_t;
4214 * MIO_RST_INT = MIO Reset Interrupt Register
4217 union cvmx_mio_rst_int
4220 struct cvmx_mio_rst_int_s
4222 #if __BYTE_ORDER == __BIG_ENDIAN
4223 uint64_t reserved_10_63 : 54;
4224 uint64_t perst1 : 1; /**< PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1
4225 and MIO_RST_CTL1[RST_CHIP]=0 */
4226 uint64_t perst0 : 1; /**< PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1
4227 and MIO_RST_CTL0[RST_CHIP]=0 */
4228 uint64_t reserved_2_7 : 6;
4229 uint64_t rst_link1 : 1; /**< A controller1 link-down/hot-reset occurred while
4230 MIO_RST_CTL1[RST_LINK]=0. Software must assert
4231 then de-assert CIU_SOFT_PRST1[SOFT_PRST] */
4232 uint64_t rst_link0 : 1; /**< A controller0 link-down/hot-reset occurred while
4233 MIO_RST_CTL0[RST_LINK]=0. Software must assert
4234 then de-assert CIU_SOFT_PRST[SOFT_PRST] */
4236 uint64_t rst_link0 : 1;
4237 uint64_t rst_link1 : 1;
4238 uint64_t reserved_2_7 : 6;
4239 uint64_t perst0 : 1;
4240 uint64_t perst1 : 1;
4241 uint64_t reserved_10_63 : 54;
4244 struct cvmx_mio_rst_int_s cn63xx;
4245 struct cvmx_mio_rst_int_s cn63xxp1;
4247 typedef union cvmx_mio_rst_int cvmx_mio_rst_int_t;
4250 * cvmx_mio_rst_int_en
4252 * MIO_RST_INT_EN = MIO Reset Interrupt Enable Register
4255 union cvmx_mio_rst_int_en
4258 struct cvmx_mio_rst_int_en_s
4260 #if __BYTE_ORDER == __BIG_ENDIAN
4261 uint64_t reserved_10_63 : 54;
4262 uint64_t perst1 : 1; /**< Controller1 PERST reset interrupt enable */
4263 uint64_t perst0 : 1; /**< Controller0 PERST reset interrupt enable */
4264 uint64_t reserved_2_7 : 6;
4265 uint64_t rst_link1 : 1; /**< Controller1 link-down/hot reset interrupt enable */
4266 uint64_t rst_link0 : 1; /**< Controller0 link-down/hot reset interrupt enable */
4268 uint64_t rst_link0 : 1;
4269 uint64_t rst_link1 : 1;
4270 uint64_t reserved_2_7 : 6;
4271 uint64_t perst0 : 1;
4272 uint64_t perst1 : 1;
4273 uint64_t reserved_10_63 : 54;
4276 struct cvmx_mio_rst_int_en_s cn63xx;
4277 struct cvmx_mio_rst_int_en_s cn63xxp1;
4279 typedef union cvmx_mio_rst_int_en cvmx_mio_rst_int_en_t;
4284 * MIO_TWSX_INT = TWSX Interrupt Register
4286 * This register contains the TWSI interrupt enable mask and the interrupt source bits. Note: the
4287 * interrupt source bit for the TWSI core interrupt (CORE_INT) is read-only, the appropriate sequence
4288 * must be written to the TWSI core to clear this interrupt. The other interrupt source bits are write-
4289 * one-to-clear. TS_INT is set on the update of the MIO_TWS_TWSI_SW register (i.e. when it is written
4290 * by a TWSI device). ST_INT is set whenever the valid bit of the MIO_TWS_SW_TWSI is cleared (see above
4293 * Note: When using the high-level controller, CORE_EN should be clear and CORE_INT should be ignored.
4294 * Conversely, when the high-level controller is disabled, ST_EN / TS_EN should be clear and ST_INT /
4295 * TS_INT should be ignored.
4297 * This register also contains a read-only copy of the TWSI bus (SCL and SDA) as well as control bits to
4298 * override the current state of the TWSI bus (SCL_OVR and SDA_OVR). Setting an override bit high will
4299 * result in the open drain driver being activated, thus driving the corresponding signal low.
4301 union cvmx_mio_twsx_int
4304 struct cvmx_mio_twsx_int_s
4306 #if __BYTE_ORDER == __BIG_ENDIAN
4307 uint64_t reserved_12_63 : 52;
4308 uint64_t scl : 1; /**< SCL */
4309 uint64_t sda : 1; /**< SDA */
4310 uint64_t scl_ovr : 1; /**< SCL override */
4311 uint64_t sda_ovr : 1; /**< SDA override */
4312 uint64_t reserved_7_7 : 1;
4313 uint64_t core_en : 1; /**< TWSI core interrupt enable */
4314 uint64_t ts_en : 1; /**< MIO_TWS_TWSI_SW register update interrupt enable */
4315 uint64_t st_en : 1; /**< MIO_TWS_SW_TWSI register update interrupt enable */
4316 uint64_t reserved_3_3 : 1;
4317 uint64_t core_int : 1; /**< TWSI core interrupt */
4318 uint64_t ts_int : 1; /**< MIO_TWS_TWSI_SW register update interrupt */
4319 uint64_t st_int : 1; /**< MIO_TWS_SW_TWSI register update interrupt */
4321 uint64_t st_int : 1;
4322 uint64_t ts_int : 1;
4323 uint64_t core_int : 1;
4324 uint64_t reserved_3_3 : 1;
4327 uint64_t core_en : 1;
4328 uint64_t reserved_7_7 : 1;
4329 uint64_t sda_ovr : 1;
4330 uint64_t scl_ovr : 1;
4333 uint64_t reserved_12_63 : 52;
4336 struct cvmx_mio_twsx_int_s cn30xx;
4337 struct cvmx_mio_twsx_int_s cn31xx;
4338 struct cvmx_mio_twsx_int_s cn38xx;
4339 struct cvmx_mio_twsx_int_cn38xxp2
4341 #if __BYTE_ORDER == __BIG_ENDIAN
4342 uint64_t reserved_7_63 : 57;
4343 uint64_t core_en : 1; /**< TWSI core interrupt enable */
4344 uint64_t ts_en : 1; /**< MIO_TWS_TWSI_SW register update interrupt enable */
4345 uint64_t st_en : 1; /**< MIO_TWS_SW_TWSI register update interrupt enable */
4346 uint64_t reserved_3_3 : 1;
4347 uint64_t core_int : 1; /**< TWSI core interrupt */
4348 uint64_t ts_int : 1; /**< MIO_TWS_TWSI_SW register update interrupt */
4349 uint64_t st_int : 1; /**< MIO_TWS_SW_TWSI register update interrupt */
4351 uint64_t st_int : 1;
4352 uint64_t ts_int : 1;
4353 uint64_t core_int : 1;
4354 uint64_t reserved_3_3 : 1;
4357 uint64_t core_en : 1;
4358 uint64_t reserved_7_63 : 57;
4361 struct cvmx_mio_twsx_int_s cn50xx;
4362 struct cvmx_mio_twsx_int_s cn52xx;
4363 struct cvmx_mio_twsx_int_s cn52xxp1;
4364 struct cvmx_mio_twsx_int_s cn56xx;
4365 struct cvmx_mio_twsx_int_s cn56xxp1;
4366 struct cvmx_mio_twsx_int_s cn58xx;
4367 struct cvmx_mio_twsx_int_s cn58xxp1;
4368 struct cvmx_mio_twsx_int_s cn63xx;
4369 struct cvmx_mio_twsx_int_s cn63xxp1;
4371 typedef union cvmx_mio_twsx_int cvmx_mio_twsx_int_t;
4374 * cvmx_mio_tws#_sw_twsi
4376 * MIO_TWSX_SW_TWSI = TWSX Software to TWSI Register
4378 * This register allows software to
4379 * - initiate TWSI interface master-mode operations with a write and read the result with a read
4380 * - load four bytes for later retrieval (slave mode) with a write and check validity with a read
4381 * - launch a TWSI controller configuration read/write with a write and read the result with a read
4383 * This register should be read or written by software, and read by the TWSI device. The TWSI device can
4384 * use either two-byte or five-byte reads to reference this register.
4386 * The TWSI device considers this register valid when V==1 and SLONLY==1.
4388 union cvmx_mio_twsx_sw_twsi
4391 struct cvmx_mio_twsx_sw_twsi_s
4393 #if __BYTE_ORDER == __BIG_ENDIAN
4394 uint64_t v : 1; /**< Valid bit
4395 - Set on a write (should always be written with
4397 - Cleared when a TWSI master mode op completes
4398 - Cleared when a TWSI configuration register
4400 - Cleared when the TWSI device reads the
4401 register if SLONLY==1 */
4402 uint64_t slonly : 1; /**< Slave Only Mode
4403 - No operation is initiated with a write when
4404 this bit is set - only D field is updated in
4406 - When clear, a write initiates either a TWSI
4407 master-mode operation or a TWSI configuration
4409 uint64_t eia : 1; /**< Extended Internal Address - send additional
4410 internal address byte (MSB of IA is from IA field
4411 of MIO_TWS_SW_TWSI_EXT) */
4412 uint64_t op : 4; /**< Opcode field - When the register is written with
4413 SLONLY==0, initiate a read or write:
4414 0000 => 7-bit Byte Master Mode TWSI Op
4415 0001 => 7-bit Byte Combined Read Master Mode Op
4416 7-bit Byte Write w/ IA Master Mode Op
4417 0010 => 10-bit Byte Master Mode TWSI Op
4418 0011 => 10-bit Byte Combined Read Master Mode Op
4419 10-bit Byte Write w/ IA Master Mode Op
4420 0100 => TWSI Master Clock Register
4421 0110 => See EOP field
4422 1000 => 7-bit 4-byte Master Mode TWSI Op
4423 1001 => 7-bit 4-byte Comb. Read Master Mode Op
4424 7-bit 4-byte Write w/ IA Master Mode Op
4425 1010 => 10-bit 4-byte Master Mode TWSI Op
4426 1011 => 10-bit 4-byte Comb. Read Master Mode Op
4427 10-bit 4-byte Write w/ IA Master Mode Op */
4428 uint64_t r : 1; /**< Read bit or result
4429 - If set on a write when SLONLY==0, the
4431 - On a read, this bit returns the result
4432 indication for the most recent master mode
4433 operation (1 = success, 0 = fail) */
4434 uint64_t sovr : 1; /**< Size Override - if set, use the SIZE field to
4435 determine Master Mode Op size rather than what
4436 the Opcode field specifies. For operations
4437 greater than 4 bytes, the additional data will be
4438 contained in the D field of MIO_TWS_SW_TWSI_EXT */
4439 uint64_t size : 3; /**< Size in bytes of Master Mode Op if the Size
4440 Override bit is set. Specified in -1 notation
4441 (i.e. 0 = 1 byte, 1 = 2 bytes ... 7 = 8 bytes) */
4442 uint64_t scr : 2; /**< Scratch - unused, but retain state */
4443 uint64_t a : 10; /**< Address field
4444 - the address of the remote device for a master
4446 - A<9:7> are only used for 10-bit addressing
4447 Note that when mastering a 7-bit OP, A<6:0> should
4448 not take any of the values 0x78, 0x79, 0x7A nor
4449 0x7B (these 7-bit addresses are reserved to
4450 extend to 10-bit addressing). */
4451 uint64_t ia : 5; /**< Internal Address - Used when launching a master
4452 mode combined read / write with internal address
4453 (lower 3 bits are contained in the EOP_IA field) */
4454 uint64_t eop_ia : 3; /**< Extra opcode (when OP<3:0> == 0110 and SLONLY==0):
4455 000 => TWSI Slave Address Register
4456 001 => TWSI Data Register
4457 010 => TWSI Control Register
4458 011 => TWSI Clock Control Register (when R == 0)
4459 011 => TWSI Status Register (when R == 1)
4460 100 => TWSI Extended Slave Register
4461 111 => TWSI Soft Reset Register
4462 Also the lower 3 bits of Internal Address when
4463 launching a master mode combined read / write
4464 with internal address */
4465 uint64_t d : 32; /**< Data Field
4466 Used on a write when
4467 - initiating a master-mode write (SLONLY==0)
4468 - writing a TWSI config register (SLONLY==0)
4469 - a slave mode write (SLONLY==1)
4470 The read value is updated by
4471 - a write to this register
4472 - master mode completion (contains result or
4474 - TWSI config register read (contains result) */
4477 uint64_t eop_ia : 3;
4486 uint64_t slonly : 1;
4490 struct cvmx_mio_twsx_sw_twsi_s cn30xx;
4491 struct cvmx_mio_twsx_sw_twsi_s cn31xx;
4492 struct cvmx_mio_twsx_sw_twsi_s cn38xx;
4493 struct cvmx_mio_twsx_sw_twsi_s cn38xxp2;
4494 struct cvmx_mio_twsx_sw_twsi_s cn50xx;
4495 struct cvmx_mio_twsx_sw_twsi_s cn52xx;
4496 struct cvmx_mio_twsx_sw_twsi_s cn52xxp1;
4497 struct cvmx_mio_twsx_sw_twsi_s cn56xx;
4498 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
4499 struct cvmx_mio_twsx_sw_twsi_s cn58xx;
4500 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
4501 struct cvmx_mio_twsx_sw_twsi_s cn63xx;
4502 struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
4504 typedef union cvmx_mio_twsx_sw_twsi cvmx_mio_twsx_sw_twsi_t;
4507 * cvmx_mio_tws#_sw_twsi_ext
4509 * MIO_TWSX_SW_TWSI_EXT = TWSX Software to TWSI Extension Register
4511 * This register contains an additional byte of internal address and 4 additional bytes of data to be
4512 * used with TWSI master mode operations. IA will be sent as the first byte of internal address when
4513 * performing master mode combined read / write with internal address operations and the EIA bit of
4514 * MIO_TWS_SW_TWSI is set. D extends the data field of MIO_TWS_SW_TWSI for a total of 8 bytes (SOVR
4515 * must be set to perform operations greater than 4 bytes).
4517 union cvmx_mio_twsx_sw_twsi_ext
4520 struct cvmx_mio_twsx_sw_twsi_ext_s
4522 #if __BYTE_ORDER == __BIG_ENDIAN
4523 uint64_t reserved_40_63 : 24;
4524 uint64_t ia : 8; /**< Extended Internal Address */
4525 uint64_t d : 32; /**< Extended Data Field */
4529 uint64_t reserved_40_63 : 24;
4532 struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx;
4533 struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx;
4534 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx;
4535 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2;
4536 struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx;
4537 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx;
4538 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1;
4539 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx;
4540 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
4541 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
4542 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
4543 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
4544 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
4546 typedef union cvmx_mio_twsx_sw_twsi_ext cvmx_mio_twsx_sw_twsi_ext_t;
4549 * cvmx_mio_tws#_twsi_sw
4551 * MIO_TWSX_TWSI_SW = TWSX TWSI to Software Register
4553 * This register allows the TWSI device to transfer data to software and later check that software has
4554 * received the information.
4556 * This register should be read or written by the TWSI device, and read by software. The TWSI device can
4557 * use one-byte or four-byte payload writes, and two-byte payload reads.
4559 * The TWSI device considers this register valid when V==1.
4561 union cvmx_mio_twsx_twsi_sw
4564 struct cvmx_mio_twsx_twsi_sw_s
4566 #if __BYTE_ORDER == __BIG_ENDIAN
4567 uint64_t v : 2; /**< Valid Bits
4568 - Not directly writable
4569 - Set to 1 on any write by the TWSI device
4570 - Cleared on any read by software */
4571 uint64_t reserved_32_61 : 30;
4572 uint64_t d : 32; /**< Data Field - updated on a write by the TWSI device */
4575 uint64_t reserved_32_61 : 30;
4579 struct cvmx_mio_twsx_twsi_sw_s cn30xx;
4580 struct cvmx_mio_twsx_twsi_sw_s cn31xx;
4581 struct cvmx_mio_twsx_twsi_sw_s cn38xx;
4582 struct cvmx_mio_twsx_twsi_sw_s cn38xxp2;
4583 struct cvmx_mio_twsx_twsi_sw_s cn50xx;
4584 struct cvmx_mio_twsx_twsi_sw_s cn52xx;
4585 struct cvmx_mio_twsx_twsi_sw_s cn52xxp1;
4586 struct cvmx_mio_twsx_twsi_sw_s cn56xx;
4587 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
4588 struct cvmx_mio_twsx_twsi_sw_s cn58xx;
4589 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
4590 struct cvmx_mio_twsx_twsi_sw_s cn63xx;
4591 struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
4593 typedef union cvmx_mio_twsx_twsi_sw cvmx_mio_twsx_twsi_sw_t;
4596 * cvmx_mio_uart#_dlh
4598 * MIO_UARTX_DLH = MIO UARTX Divisor Latch High Register
4600 * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a
4601 * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is
4602 * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud
4603 * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as
4604 * follows: baud rate = eclk / (16 * divisor).
4606 * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this
4607 * register. BUSY bit is always clear in PASS3.
4609 * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled
4610 * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles
4611 * of eclk should be allowed to pass before transmitting or receiving data.
4613 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
4614 * IER and DLH registers are the same.
4616 union cvmx_mio_uartx_dlh
4619 struct cvmx_mio_uartx_dlh_s
4621 #if __BYTE_ORDER == __BIG_ENDIAN
4622 uint64_t reserved_8_63 : 56;
4623 uint64_t dlh : 8; /**< Divisor Latch High Register */
4626 uint64_t reserved_8_63 : 56;
4629 struct cvmx_mio_uartx_dlh_s cn30xx;
4630 struct cvmx_mio_uartx_dlh_s cn31xx;
4631 struct cvmx_mio_uartx_dlh_s cn38xx;
4632 struct cvmx_mio_uartx_dlh_s cn38xxp2;
4633 struct cvmx_mio_uartx_dlh_s cn50xx;
4634 struct cvmx_mio_uartx_dlh_s cn52xx;
4635 struct cvmx_mio_uartx_dlh_s cn52xxp1;
4636 struct cvmx_mio_uartx_dlh_s cn56xx;
4637 struct cvmx_mio_uartx_dlh_s cn56xxp1;
4638 struct cvmx_mio_uartx_dlh_s cn58xx;
4639 struct cvmx_mio_uartx_dlh_s cn58xxp1;
4640 struct cvmx_mio_uartx_dlh_s cn63xx;
4641 struct cvmx_mio_uartx_dlh_s cn63xxp1;
4643 typedef union cvmx_mio_uartx_dlh cvmx_mio_uartx_dlh_t;
4644 typedef cvmx_mio_uartx_dlh_t cvmx_uart_dlh_t;
4647 * cvmx_mio_uart#_dll
4649 * MIO_UARTX_DLL = MIO UARTX Divisor Latch Low Register
4651 * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a
4652 * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is
4653 * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud
4654 * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as
4655 * follows: baud rate = eclk / (16 * divisor).
4657 * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this
4658 * register. BUSY bit is always clear in PASS3.
4660 * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled
4661 * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles
4662 * of eclk should be allowed to pass before transmitting or receiving data.
4664 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
4665 * RBR, THR, and DLL registers are the same.
4667 union cvmx_mio_uartx_dll
4670 struct cvmx_mio_uartx_dll_s
4672 #if __BYTE_ORDER == __BIG_ENDIAN
4673 uint64_t reserved_8_63 : 56;
4674 uint64_t dll : 8; /**< Divisor Latch Low Register */
4677 uint64_t reserved_8_63 : 56;
4680 struct cvmx_mio_uartx_dll_s cn30xx;
4681 struct cvmx_mio_uartx_dll_s cn31xx;
4682 struct cvmx_mio_uartx_dll_s cn38xx;
4683 struct cvmx_mio_uartx_dll_s cn38xxp2;
4684 struct cvmx_mio_uartx_dll_s cn50xx;
4685 struct cvmx_mio_uartx_dll_s cn52xx;
4686 struct cvmx_mio_uartx_dll_s cn52xxp1;
4687 struct cvmx_mio_uartx_dll_s cn56xx;
4688 struct cvmx_mio_uartx_dll_s cn56xxp1;
4689 struct cvmx_mio_uartx_dll_s cn58xx;
4690 struct cvmx_mio_uartx_dll_s cn58xxp1;
4691 struct cvmx_mio_uartx_dll_s cn63xx;
4692 struct cvmx_mio_uartx_dll_s cn63xxp1;
4694 typedef union cvmx_mio_uartx_dll cvmx_mio_uartx_dll_t;
4695 typedef cvmx_mio_uartx_dll_t cvmx_uart_dll_t;
4698 * cvmx_mio_uart#_far
4700 * MIO_UARTX_FAR = MIO UARTX FIFO Access Register
4702 * The FIFO Access Register (FAR) is used to enable a FIFO access mode for testing, so that the receive
4703 * FIFO can be written by software and the transmit FIFO can be read by software when the FIFOs are
4704 * enabled. When FIFOs are not enabled it allows the RBR to be written by software and the THR to be read
4705 * by software. Note, that when the FIFO access mode is enabled/disabled, the control portion of the
4706 * receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty.
4708 union cvmx_mio_uartx_far
4711 struct cvmx_mio_uartx_far_s
4713 #if __BYTE_ORDER == __BIG_ENDIAN
4714 uint64_t reserved_1_63 : 63;
4715 uint64_t far : 1; /**< FIFO Access Register */
4718 uint64_t reserved_1_63 : 63;
4721 struct cvmx_mio_uartx_far_s cn30xx;
4722 struct cvmx_mio_uartx_far_s cn31xx;
4723 struct cvmx_mio_uartx_far_s cn38xx;
4724 struct cvmx_mio_uartx_far_s cn38xxp2;
4725 struct cvmx_mio_uartx_far_s cn50xx;
4726 struct cvmx_mio_uartx_far_s cn52xx;
4727 struct cvmx_mio_uartx_far_s cn52xxp1;
4728 struct cvmx_mio_uartx_far_s cn56xx;
4729 struct cvmx_mio_uartx_far_s cn56xxp1;
4730 struct cvmx_mio_uartx_far_s cn58xx;
4731 struct cvmx_mio_uartx_far_s cn58xxp1;
4732 struct cvmx_mio_uartx_far_s cn63xx;
4733 struct cvmx_mio_uartx_far_s cn63xxp1;
4735 typedef union cvmx_mio_uartx_far cvmx_mio_uartx_far_t;
4736 typedef cvmx_mio_uartx_far_t cvmx_uart_far_t;
4739 * cvmx_mio_uart#_fcr
4741 * MIO_UARTX_FCR = MIO UARTX FIFO Control Register
4743 * The FIFO Control Register (FCR) is a write-only register that controls the read and write data FIFO
4744 * operation. When FIFOs and Programmable THRE Interrupt mode are enabled, this register also controls
4745 * the THRE Interrupt empty threshold level.
4747 * Setting bit 0 of the FCR enables the transmit and receive FIFOs. Whenever the value of this bit is
4748 * changed both the TX and RX FIFOs will be reset.
4750 * Writing a '1' to bit 1 of the FCR resets and flushes data in the receive FIFO. Note that this bit is
4751 * self-clearing and it is not necessary to clear this bit.
4753 * Writing a '1' to bit 2 of the FCR resets and flushes data in the transmit FIFO. Note that this bit is
4754 * self-clearing and it is not necessary to clear this bit.
4756 * If the FIFOs and Programmable THRE Interrupt mode are enabled, bits 4 and 5 control the empty
4757 * threshold level at which THRE Interrupts are generated when the mode is active. See the following
4758 * table for encodings:
4763 * 01 = 2 chars in FIFO
4764 * 10 = FIFO 1/4 full
4765 * 11 = FIFO 1/2 full
4767 * If the FIFO mode is enabled (bit 0 of the FCR is set to '1') bits 6 and 7 are active. Bit 6 and bit 7
4768 * set the trigger level in the receiver FIFO for the Enable Received Data Available Interrupt (ERBFI).
4769 * In auto flow control mode the trigger is used to determine when the rts_n signal will be deasserted.
4770 * See the following table for encodings:
4774 * 00 = 1 char in FIFO
4775 * 01 = FIFO 1/4 full
4776 * 10 = FIFO 1/2 full
4777 * 11 = FIFO 2 chars less than full
4779 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
4780 * IIR and FCR registers are the same.
4782 union cvmx_mio_uartx_fcr
4785 struct cvmx_mio_uartx_fcr_s
4787 #if __BYTE_ORDER == __BIG_ENDIAN
4788 uint64_t reserved_8_63 : 56;
4789 uint64_t rxtrig : 2; /**< RX Trigger */
4790 uint64_t txtrig : 2; /**< TX Trigger */
4791 uint64_t reserved_3_3 : 1;
4792 uint64_t txfr : 1; /**< TX FIFO reset */
4793 uint64_t rxfr : 1; /**< RX FIFO reset */
4794 uint64_t en : 1; /**< FIFO enable */
4799 uint64_t reserved_3_3 : 1;
4800 uint64_t txtrig : 2;
4801 uint64_t rxtrig : 2;
4802 uint64_t reserved_8_63 : 56;
4805 struct cvmx_mio_uartx_fcr_s cn30xx;
4806 struct cvmx_mio_uartx_fcr_s cn31xx;
4807 struct cvmx_mio_uartx_fcr_s cn38xx;
4808 struct cvmx_mio_uartx_fcr_s cn38xxp2;
4809 struct cvmx_mio_uartx_fcr_s cn50xx;
4810 struct cvmx_mio_uartx_fcr_s cn52xx;
4811 struct cvmx_mio_uartx_fcr_s cn52xxp1;
4812 struct cvmx_mio_uartx_fcr_s cn56xx;
4813 struct cvmx_mio_uartx_fcr_s cn56xxp1;
4814 struct cvmx_mio_uartx_fcr_s cn58xx;
4815 struct cvmx_mio_uartx_fcr_s cn58xxp1;
4816 struct cvmx_mio_uartx_fcr_s cn63xx;
4817 struct cvmx_mio_uartx_fcr_s cn63xxp1;
4819 typedef union cvmx_mio_uartx_fcr cvmx_mio_uartx_fcr_t;
4820 typedef cvmx_mio_uartx_fcr_t cvmx_uart_fcr_t;
4823 * cvmx_mio_uart#_htx
4825 * MIO_UARTX_HTX = MIO UARTX Halt TX Register
4827 * The Halt TX Register (HTX) is used to halt transmissions for testing, so that the transmit FIFO can be
4828 * filled by software when FIFOs are enabled. If FIFOs are not enabled, setting the HTX register will
4831 union cvmx_mio_uartx_htx
4834 struct cvmx_mio_uartx_htx_s
4836 #if __BYTE_ORDER == __BIG_ENDIAN
4837 uint64_t reserved_1_63 : 63;
4838 uint64_t htx : 1; /**< Halt TX */
4841 uint64_t reserved_1_63 : 63;
4844 struct cvmx_mio_uartx_htx_s cn30xx;
4845 struct cvmx_mio_uartx_htx_s cn31xx;
4846 struct cvmx_mio_uartx_htx_s cn38xx;
4847 struct cvmx_mio_uartx_htx_s cn38xxp2;
4848 struct cvmx_mio_uartx_htx_s cn50xx;
4849 struct cvmx_mio_uartx_htx_s cn52xx;
4850 struct cvmx_mio_uartx_htx_s cn52xxp1;
4851 struct cvmx_mio_uartx_htx_s cn56xx;
4852 struct cvmx_mio_uartx_htx_s cn56xxp1;
4853 struct cvmx_mio_uartx_htx_s cn58xx;
4854 struct cvmx_mio_uartx_htx_s cn58xxp1;
4855 struct cvmx_mio_uartx_htx_s cn63xx;
4856 struct cvmx_mio_uartx_htx_s cn63xxp1;
4858 typedef union cvmx_mio_uartx_htx cvmx_mio_uartx_htx_t;
4859 typedef cvmx_mio_uartx_htx_t cvmx_uart_htx_t;
4862 * cvmx_mio_uart#_ier
4864 * MIO_UARTX_IER = MIO UARTX Interrupt Enable Register
4866 * Interrupt Enable Register (IER) is a read/write register that contains four bits that enable
4867 * the generation of interrupts. These four bits are the Enable Received Data Available Interrupt
4868 * (ERBFI), the Enable Transmitter Holding Register Empty Interrupt (ETBEI), the Enable Receiver Line
4869 * Status Interrupt (ELSI), and the Enable Modem Status Interrupt (EDSSI).
4871 * The IER also contains an enable bit (PTIME) for the Programmable THRE Interrupt mode.
4873 * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
4876 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
4877 * IER and DLH registers are the same.
4879 union cvmx_mio_uartx_ier
4882 struct cvmx_mio_uartx_ier_s
4884 #if __BYTE_ORDER == __BIG_ENDIAN
4885 uint64_t reserved_8_63 : 56;
4886 uint64_t ptime : 1; /**< Programmable THRE Interrupt mode enable */
4887 uint64_t reserved_4_6 : 3;
4888 uint64_t edssi : 1; /**< Enable Modem Status Interrupt */
4889 uint64_t elsi : 1; /**< Enable Receiver Line Status Interrupt */
4890 uint64_t etbei : 1; /**< Enable Transmitter Holding Register Empty Interrupt */
4891 uint64_t erbfi : 1; /**< Enable Received Data Available Interrupt */
4897 uint64_t reserved_4_6 : 3;
4899 uint64_t reserved_8_63 : 56;
4902 struct cvmx_mio_uartx_ier_s cn30xx;
4903 struct cvmx_mio_uartx_ier_s cn31xx;
4904 struct cvmx_mio_uartx_ier_s cn38xx;
4905 struct cvmx_mio_uartx_ier_s cn38xxp2;
4906 struct cvmx_mio_uartx_ier_s cn50xx;
4907 struct cvmx_mio_uartx_ier_s cn52xx;
4908 struct cvmx_mio_uartx_ier_s cn52xxp1;
4909 struct cvmx_mio_uartx_ier_s cn56xx;
4910 struct cvmx_mio_uartx_ier_s cn56xxp1;
4911 struct cvmx_mio_uartx_ier_s cn58xx;
4912 struct cvmx_mio_uartx_ier_s cn58xxp1;
4913 struct cvmx_mio_uartx_ier_s cn63xx;
4914 struct cvmx_mio_uartx_ier_s cn63xxp1;
4916 typedef union cvmx_mio_uartx_ier cvmx_mio_uartx_ier_t;
4917 typedef cvmx_mio_uartx_ier_t cvmx_uart_ier_t;
4920 * cvmx_mio_uart#_iir
4922 * MIO_UARTX_IIR = MIO UARTX Interrupt Identity Register
4924 * The Interrupt Identity Register (IIR) is a read-only register that identifies the source of an
4925 * interrupt. The upper two bits of the register are FIFO-enabled bits. These bits are '00' if the FIFOs
4926 * are disabled, and '11' if they are enabled. The lower four bits identify the highest priority pending
4927 * interrupt. The following table defines interrupt source decoding, interrupt priority, and interrupt
4930 * Interrupt Priority Interrupt Interrupt Interrupt
4931 * ID Level Type Source Reset By
4932 * ---------------------------------------------------------------------------------------------------------------------------------
4933 * 0001 - None None -
4935 * 0110 Highest Receiver Line Overrun, parity, or framing errors or break Reading the Line Status Register
4938 * 0100 Second Received Data Receiver data available (FIFOs disabled) or Reading the Receiver Buffer Register
4939 * Available RX FIFO trigger level reached (FIFOs (FIFOs disabled) or the FIFO drops below
4940 * enabled) the trigger level (FIFOs enabled)
4942 * 1100 Second Character No characters in or out of the RX FIFO Reading the Receiver Buffer Register
4943 * Timeout during the last 4 character times and there
4944 * Indication is at least 1 character in it during this
4947 * 0010 Third Transmitter Transmitter Holding Register Empty Reading the Interrupt Identity Register
4948 * Holding (Programmable THRE Mode disabled) or TX (if source of interrupt) or writing into
4949 * Register FIFO at or below threshold (Programmable THR (FIFOs or THRE Mode disabled) or TX
4950 * Empty THRE Mode enabled) FIFO above threshold (FIFOs and THRE
4953 * 0000 Fourth Modem Status Clear To Send (CTS) or Data Set Ready (DSR) Reading the Modem Status Register
4954 * Changed or Ring Indicator (RI) or Data Carrier
4955 * Detect (DCD) changed (note: if auto flow
4956 * control mode is enabled, a change in CTS
4957 * will not cause an interrupt)
4959 * 0111 Fifth Busy Detect Software has tried to write to the Line Reading the UART Status Register
4960 * Indication Control Register while the BUSY bit of the
4961 * UART Status Register was set
4963 * Note: The Busy Detect Indication interrupt has been removed from PASS3 and will never assert.
4965 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
4966 * IIR and FCR registers are the same.
4968 union cvmx_mio_uartx_iir
4971 struct cvmx_mio_uartx_iir_s
4973 #if __BYTE_ORDER == __BIG_ENDIAN
4974 uint64_t reserved_8_63 : 56;
4975 uint64_t fen : 2; /**< FIFO-enabled bits */
4976 uint64_t reserved_4_5 : 2;
4977 cvmx_uart_iid_t iid : 4; /**< Interrupt ID */
4979 cvmx_uart_iid_t iid : 4;
4980 uint64_t reserved_4_5 : 2;
4982 uint64_t reserved_8_63 : 56;
4985 struct cvmx_mio_uartx_iir_s cn30xx;
4986 struct cvmx_mio_uartx_iir_s cn31xx;
4987 struct cvmx_mio_uartx_iir_s cn38xx;
4988 struct cvmx_mio_uartx_iir_s cn38xxp2;
4989 struct cvmx_mio_uartx_iir_s cn50xx;
4990 struct cvmx_mio_uartx_iir_s cn52xx;
4991 struct cvmx_mio_uartx_iir_s cn52xxp1;
4992 struct cvmx_mio_uartx_iir_s cn56xx;
4993 struct cvmx_mio_uartx_iir_s cn56xxp1;
4994 struct cvmx_mio_uartx_iir_s cn58xx;
4995 struct cvmx_mio_uartx_iir_s cn58xxp1;
4996 struct cvmx_mio_uartx_iir_s cn63xx;
4997 struct cvmx_mio_uartx_iir_s cn63xxp1;
4999 typedef union cvmx_mio_uartx_iir cvmx_mio_uartx_iir_t;
5000 typedef cvmx_mio_uartx_iir_t cvmx_uart_iir_t;
5003 * cvmx_mio_uart#_lcr
5005 * MIO_UARTX_LCR = MIO UARTX Line Control Register
5007 * The Line Control Register (LCR) controls the format of the data that is transmitted and received by
5010 * LCR bits 0 and 1 are the Character Length Select field. This field is used to select the number of
5011 * data bits per character that are transmitted and received. See the following table for encodings:
5015 * 00 = 5 bits (bits 0-4 sent)
5016 * 01 = 6 bits (bits 0-5 sent)
5017 * 10 = 7 bits (bits 0-6 sent)
5018 * 11 = 8 bits (all bits sent)
5020 * LCR bit 2 controls the number of stop bits transmitted. If bit 2 is a '0', one stop bit is transmitted
5021 * in the serial data. If bit 2 is a '1' and the data bits are set to '00', one and a half stop bits are
5022 * generated. Otherwise, two stop bits are generated and transmitted in the serial data out. Note that
5023 * regardless of the number of stop bits selected the receiver will only check the first stop bit.
5025 * LCR bit 3 is the Parity Enable bit. This bit is used to enable and disable parity generation and
5026 * detection in transmitted and received serial character respectively.
5028 * LCR bit 4 is the Even Parity Select bit. If parity is enabled, bit 4 selects between even and odd
5029 * parity. If bit 4 is a '1', an even number of ones is transmitted or checked. If bit 4 is a '0', an odd
5030 * number of ones is transmitted or checked.
5032 * LCR bit 6 is the Break Control bit. Setting the Break bit sends a break signal by holding the sout
5033 * line low (when not in Loopback mode, as determined by Modem Control Register bit 4). When in Loopback
5034 * mode, the break condition is internally looped back to the receiver.
5036 * LCR bit 7 is the Divisor Latch Address bit. Setting this bit enables reading and writing of the
5037 * Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after
5038 * initial baud rate setup in order to access other registers.
5040 * Note: The LCR is writeable only when the UART is not busy (when the BUSY bit (bit 0) of the UART
5041 * Status Register (USR) is clear). The LCR is always readable. In PASS3, the LCR is always writable
5042 * because the BUSY bit is always clear.
5044 union cvmx_mio_uartx_lcr
5047 struct cvmx_mio_uartx_lcr_s
5049 #if __BYTE_ORDER == __BIG_ENDIAN
5050 uint64_t reserved_8_63 : 56;
5051 uint64_t dlab : 1; /**< Divisor Latch Address bit */
5052 uint64_t brk : 1; /**< Break Control bit */
5053 uint64_t reserved_5_5 : 1;
5054 uint64_t eps : 1; /**< Even Parity Select bit */
5055 uint64_t pen : 1; /**< Parity Enable bit */
5056 uint64_t stop : 1; /**< Stop Control bit */
5057 cvmx_uart_bits_t cls : 2; /**< Character Length Select */
5059 cvmx_uart_bits_t cls : 2;
5063 uint64_t reserved_5_5 : 1;
5066 uint64_t reserved_8_63 : 56;
5069 struct cvmx_mio_uartx_lcr_s cn30xx;
5070 struct cvmx_mio_uartx_lcr_s cn31xx;
5071 struct cvmx_mio_uartx_lcr_s cn38xx;
5072 struct cvmx_mio_uartx_lcr_s cn38xxp2;
5073 struct cvmx_mio_uartx_lcr_s cn50xx;
5074 struct cvmx_mio_uartx_lcr_s cn52xx;
5075 struct cvmx_mio_uartx_lcr_s cn52xxp1;
5076 struct cvmx_mio_uartx_lcr_s cn56xx;
5077 struct cvmx_mio_uartx_lcr_s cn56xxp1;
5078 struct cvmx_mio_uartx_lcr_s cn58xx;
5079 struct cvmx_mio_uartx_lcr_s cn58xxp1;
5080 struct cvmx_mio_uartx_lcr_s cn63xx;
5081 struct cvmx_mio_uartx_lcr_s cn63xxp1;
5083 typedef union cvmx_mio_uartx_lcr cvmx_mio_uartx_lcr_t;
5084 typedef cvmx_mio_uartx_lcr_t cvmx_uart_lcr_t;
5087 * cvmx_mio_uart#_lsr
5089 * MIO_UARTX_LSR = MIO UARTX Line Status Register
5091 * The Line Status Register (LSR) contains status of the receiver and transmitter data transfers. This
5092 * status can be read by the user at anytime.
5094 * LSR bit 0 is the Data Ready (DR) bit. When set, this bit indicates the receiver contains at least one
5095 * character in the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the non-FIFO
5096 * mode, or when the receiver FIFO is empty, in FIFO mode.
5098 * LSR bit 1 is the Overrun Error (OE) bit. When set, this bit indicates an overrun error has occurred
5099 * because a new data character was received before the previous data was read. In the non-FIFO mode, the
5100 * OE bit is set when a new character arrives in the receiver before the previous character was read from
5101 * the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error
5102 * occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is
5103 * retained and the data in the receive shift register is lost.
5105 * LSR bit 2 is the Parity Error (PE) bit. This bit is set whenever there is a parity error in the
5106 * receiver if the Parity Enable (PEN) bit in the LCR is set. In the FIFO mode, since the parity error is
5107 * associated with a character received, it is revealed when the character with the parity error arrives
5108 * at the top of the FIFO. It should be noted that the Parity Error (PE) bit will be set if a break
5109 * interrupt has occurred, as indicated by the Break Interrupt (BI) bit.
5111 * LSR bit 3 is the Framing Error (FE) bit. This bit is set whenever there is a framing error in the
5112 * receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received
5113 * data. In the FIFO mode, since the framing error is associated with a character received, it is
5114 * revealed when the character with the framing error is at the top of the FIFO. When a framing error
5115 * occurs the UART will try resynchronize. It does this by assuming that the error was due to the start
5116 * bit of the next character and then continues receiving the other bits (i.e. data and/or parity and
5117 * stop). It should be noted that the Framing Error (FE) bit will be set if a break interrupt has
5118 * occurred, as indicated by the Break Interrupt (BI) bit.
5120 * Note: The OE, PE, and FE bits are reset when a read of the LSR is performed.
5122 * LSR bit 4 is the Break Interrupt (BI) bit. This bit is set whenever the serial input (sin) is held in
5123 * a 0 state for longer than the sum of start time + data bits + parity + stop bits. A break condition on
5124 * sin causes one and only one character, consisting of all zeros, to be received by the UART. In the
5125 * FIFO mode, the character associated with the break condition is carried through the FIFO and is
5126 * revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-
5127 * FIFO mode, the BI indication occurs immediately and persists until the LSR is read.
5129 * LSR bit 5 is the Transmitter Holding Register Empty (THRE) bit. When Programmable THRE Interrupt mode
5130 * is disabled, this bit indicates that the UART can accept a new character for transmission. This bit is
5131 * set whenever data is transferred from the THR (or TX FIFO) to the transmitter shift register and no
5132 * new data has been written to the THR (or TX FIFO). This also causes a THRE Interrupt to occur, if the
5133 * THRE Interrupt is enabled. When FIFOs and Programmable THRE Interrupt mode are enabled, LSR bit 5
5134 * functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE
5135 * Interrupts, which are then controlled by the FCR[5:4] threshold setting.
5137 * LSR bit 6 is the Transmitter Empty (TEMT) bit. In the FIFO mode, this bit is set whenever the
5138 * Transmitter Shift Register and the FIFO are both empty. In the non-FIFO mode, this bit is set whenever
5139 * the Transmitter Holding Register and the Transmitter Shift Register are both empty. This bit is
5140 * typically used to make sure it is safe to change control registers. Changing control registers while
5141 * the transmitter is busy can result in corrupt data being transmitted.
5143 * LSR bit 7 is the Error in Receiver FIFO (FERR) bit. This bit is active only when FIFOs are enabled. It
5144 * is set when there is at least one parity error, framing error, or break indication in the FIFO. This
5145 * bit is cleared when the LSR is read and the character with the error is at the top of the receiver
5146 * FIFO and there are no subsequent errors in the FIFO.
5148 union cvmx_mio_uartx_lsr
5151 struct cvmx_mio_uartx_lsr_s
5153 #if __BYTE_ORDER == __BIG_ENDIAN
5154 uint64_t reserved_8_63 : 56;
5155 uint64_t ferr : 1; /**< Error in Receiver FIFO bit */
5156 uint64_t temt : 1; /**< Transmitter Empty bit */
5157 uint64_t thre : 1; /**< Transmitter Holding Register Empty bit */
5158 uint64_t bi : 1; /**< Break Interrupt bit */
5159 uint64_t fe : 1; /**< Framing Error bit */
5160 uint64_t pe : 1; /**< Parity Error bit */
5161 uint64_t oe : 1; /**< Overrun Error bit */
5162 uint64_t dr : 1; /**< Data Ready bit */
5172 uint64_t reserved_8_63 : 56;
5175 struct cvmx_mio_uartx_lsr_s cn30xx;
5176 struct cvmx_mio_uartx_lsr_s cn31xx;
5177 struct cvmx_mio_uartx_lsr_s cn38xx;
5178 struct cvmx_mio_uartx_lsr_s cn38xxp2;
5179 struct cvmx_mio_uartx_lsr_s cn50xx;
5180 struct cvmx_mio_uartx_lsr_s cn52xx;
5181 struct cvmx_mio_uartx_lsr_s cn52xxp1;
5182 struct cvmx_mio_uartx_lsr_s cn56xx;
5183 struct cvmx_mio_uartx_lsr_s cn56xxp1;
5184 struct cvmx_mio_uartx_lsr_s cn58xx;
5185 struct cvmx_mio_uartx_lsr_s cn58xxp1;
5186 struct cvmx_mio_uartx_lsr_s cn63xx;
5187 struct cvmx_mio_uartx_lsr_s cn63xxp1;
5189 typedef union cvmx_mio_uartx_lsr cvmx_mio_uartx_lsr_t;
5190 typedef cvmx_mio_uartx_lsr_t cvmx_uart_lsr_t;
5193 * cvmx_mio_uart#_mcr
5195 * MIO_UARTX_MCR = MIO UARTX Modem Control Register
5197 * The lower four bits of the Modem Control Register (MCR) directly manipulate the outputs of the UART.
5198 * The DTR (bit 0), RTS (bit 1), OUT1 (bit 2), and OUT2 (bit 3) bits are inverted and then drive the
5199 * corresponding UART outputs, dtr_n, rts_n, out1_n, and out2_n. In loopback mode, these outputs are
5200 * driven inactive high while the values in these locations are internally looped back to the inputs.
5202 * Note: When Auto RTS is enabled, the rts_n output is controlled in the same way, but is also gated
5203 * with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The
5204 * rts_n output will be de-asserted whenever RTS (bit 1) is set low.
5206 * Note: The UART0 out1_n and out2_n outputs are not present on the pins of the chip, but the UART0 OUT1
5207 * and OUT2 bits still function in Loopback mode. The UART1 dtr_n, out1_n, and out2_n outputs are not
5208 * present on the pins of the chip, but the UART1 DTR, OUT1, and OUT2 bits still function in Loopback
5211 * MCR bit 4 is the Loopback bit. When set, data on the sout line is held high, while serial data output
5212 * is looped back to the sin line, internally. In this mode all the interrupts are fully functional. This
5213 * feature is used for diagnostic purposes. Also, in loopback mode, the modem control inputs (dsr_n,
5214 * cts_n, ri_n, dcd_n) are disconnected and the four modem control outputs (dtr_n, rts_n, out1_n, out1_n)
5215 * are looped back to the inputs, internally.
5217 * MCR bit 5 is the Auto Flow Control Enable (AFCE) bit. When FIFOs are enabled and this bit is set,
5218 * 16750-compatible Auto RTS and Auto CTS serial data flow control features are enabled.
5220 * Auto RTS becomes active when the following occurs:
5221 * 1. MCR bit 1 is set
5222 * 2. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0
5223 * 3. MCR bit 5 is set (must be set after FCR bit 0)
5225 * When active, the rts_n output is forced inactive-high when the receiver FIFO level reaches the
5226 * threshold set by FCR[7:6]. When rts_n is connected to the cts_n input of another UART device, the
5227 * other UART stops sending serial data until the receiver FIFO has available space.
5229 * The selectable receiver FIFO threshold values are: 1, 1/4, 1/2, and 2 less than full. Since one
5230 * additional character may be transmitted to the UART after rts_n has become inactive (due to data
5231 * already having entered the transmitter block in the other UART), setting the threshold to 2 less
5232 * than full allows maximum use of the FIFO with a safety zone of one character.
5234 * Once the receiver FIFO becomes completely empty by reading the Receiver Buffer Register (RBR), rts_n
5235 * again becomes active-low, signalling the other UART to continue sending data. It is important to note
5236 * that, even if everything else is set to Enabled and the correct MCR bits are set, if the FIFOs are
5237 * disabled through FCR[0], Auto Flow Control is also disabled. When Auto RTS is disabled or inactive,
5238 * rts_n is controlled solely by MCR[1].
5240 * Auto CTS becomes active when the following occurs:
5241 * 1. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0
5242 * 2. MCR bit 5 is set (must be set after FCR bit 0)
5244 * When active, the UART transmitter is disabled whenever the cts_n input becomes inactive-high. This
5245 * prevents overflowing the FIFO of the receiving UART.
5247 * Note that, if the cts_n input is not inactivated before the middle of the last stop bit, another
5248 * character is transmitted before the transmitter is disabled. While the transmitter is disabled, the
5249 * transmitter FIFO can still be written to, and even overflowed. Therefore, when using this mode, either
5250 * the true FIFO depth (64 characters) must be known to software, or the Programmable THRE Interrupt mode
5251 * must be enabled to access the FIFO full status through the Line Status Register. When using the FIFO
5252 * full status, software can poll this before each write to the Transmitter FIFO.
5254 * Note: FIFO full status is also available in the UART Status Register (USR) or the actual level of the
5255 * FIFO may be read through the Transmit FIFO Level (TFL) register.
5257 * When the cts_n input becomes active-low again, transmission resumes. It is important to note that,
5258 * even if everything else is set to Enabled, Auto Flow Control is also disabled if the FIFOs are
5259 * disabled through FCR[0]. When Auto CTS is disabled or inactive, the transmitter is unaffected by
5262 union cvmx_mio_uartx_mcr
5265 struct cvmx_mio_uartx_mcr_s
5267 #if __BYTE_ORDER == __BIG_ENDIAN
5268 uint64_t reserved_6_63 : 58;
5269 uint64_t afce : 1; /**< Auto Flow Control Enable bit */
5270 uint64_t loop : 1; /**< Loopback bit */
5271 uint64_t out2 : 1; /**< OUT2 output bit */
5272 uint64_t out1 : 1; /**< OUT1 output bit */
5273 uint64_t rts : 1; /**< Request To Send output bit */
5274 uint64_t dtr : 1; /**< Data Terminal Ready output bit */
5282 uint64_t reserved_6_63 : 58;
5285 struct cvmx_mio_uartx_mcr_s cn30xx;
5286 struct cvmx_mio_uartx_mcr_s cn31xx;
5287 struct cvmx_mio_uartx_mcr_s cn38xx;
5288 struct cvmx_mio_uartx_mcr_s cn38xxp2;
5289 struct cvmx_mio_uartx_mcr_s cn50xx;
5290 struct cvmx_mio_uartx_mcr_s cn52xx;
5291 struct cvmx_mio_uartx_mcr_s cn52xxp1;
5292 struct cvmx_mio_uartx_mcr_s cn56xx;
5293 struct cvmx_mio_uartx_mcr_s cn56xxp1;
5294 struct cvmx_mio_uartx_mcr_s cn58xx;
5295 struct cvmx_mio_uartx_mcr_s cn58xxp1;
5296 struct cvmx_mio_uartx_mcr_s cn63xx;
5297 struct cvmx_mio_uartx_mcr_s cn63xxp1;
5299 typedef union cvmx_mio_uartx_mcr cvmx_mio_uartx_mcr_t;
5300 typedef cvmx_mio_uartx_mcr_t cvmx_uart_mcr_t;
5303 * cvmx_mio_uart#_msr
5305 * MIO_UARTX_MSR = MIO UARTX Modem Status Register
5307 * The Modem Status Register (MSR) contains the current status of the modem control input lines and if
5310 * DCTS (bit 0), DDSR (bit 1), and DDCD (bit 3) bits record whether the modem control lines (cts_n,
5311 * dsr_n, and dcd_n) have changed since the last time the user read the MSR. TERI (bit 2) indicates ri_n
5312 * has changed from an active-low, to an inactive-high state since the last time the MSR was read. In
5313 * Loopback mode, DCTS reflects changes on MCR bit 1 (RTS), DDSR reflects changes on MCR bit 0 (DTR), and
5314 * DDCD reflects changes on MCR bit 3 (Out2), while TERI reflects when MCR bit 2 (Out1) has changed state
5315 * from a high to a low.
5317 * Note: if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software
5318 * or otherwise), then the DCTS bit will get set when the reset is removed if the cts_n signal remains
5321 * The CTS, DSR, RI, and DCD Modem Status bits contain information on the current state of the modem
5322 * control lines. CTS (bit 4) is the compliment of cts_n, DSR (bit 5) is the compliment of dsr_n, RI
5323 * (bit 6) is the compliment of ri_n, and DCD (bit 7) is the compliment of dcd_n. In Loopback mode, CTS
5324 * is the same as MCR bit 1 (RTS), DSR is the same as MCR bit 0 (DTR), RI is the same as MCR bit 2
5325 * (Out1), and DCD is the same as MCR bit 3 (Out2).
5327 * Note: The UART0 dsr_n and ri_n inputs are internally tied to power and not present on the pins of chip.
5328 * Thus the UART0 DSR and RI bits will be '0' when not in Loopback mode. The UART1 dsr_n, ri_n, and dcd_n
5329 * inputs are internally tied to power and not present on the pins of chip. Thus the UART1 DSR, RI, and
5330 * DCD bits will be '0' when not in Loopback mode.
5332 union cvmx_mio_uartx_msr
5335 struct cvmx_mio_uartx_msr_s
5337 #if __BYTE_ORDER == __BIG_ENDIAN
5338 uint64_t reserved_8_63 : 56;
5339 uint64_t dcd : 1; /**< Data Carrier Detect input bit */
5340 uint64_t ri : 1; /**< Ring Indicator input bit */
5341 uint64_t dsr : 1; /**< Data Set Ready input bit */
5342 uint64_t cts : 1; /**< Clear To Send input bit */
5343 uint64_t ddcd : 1; /**< Delta Data Carrier Detect bit */
5344 uint64_t teri : 1; /**< Trailing Edge of Ring Indicator bit */
5345 uint64_t ddsr : 1; /**< Delta Data Set Ready bit */
5346 uint64_t dcts : 1; /**< Delta Clear To Send bit */
5356 uint64_t reserved_8_63 : 56;
5359 struct cvmx_mio_uartx_msr_s cn30xx;
5360 struct cvmx_mio_uartx_msr_s cn31xx;
5361 struct cvmx_mio_uartx_msr_s cn38xx;
5362 struct cvmx_mio_uartx_msr_s cn38xxp2;
5363 struct cvmx_mio_uartx_msr_s cn50xx;
5364 struct cvmx_mio_uartx_msr_s cn52xx;
5365 struct cvmx_mio_uartx_msr_s cn52xxp1;
5366 struct cvmx_mio_uartx_msr_s cn56xx;
5367 struct cvmx_mio_uartx_msr_s cn56xxp1;
5368 struct cvmx_mio_uartx_msr_s cn58xx;
5369 struct cvmx_mio_uartx_msr_s cn58xxp1;
5370 struct cvmx_mio_uartx_msr_s cn63xx;
5371 struct cvmx_mio_uartx_msr_s cn63xxp1;
5373 typedef union cvmx_mio_uartx_msr cvmx_mio_uartx_msr_t;
5374 typedef cvmx_mio_uartx_msr_t cvmx_uart_msr_t;
5377 * cvmx_mio_uart#_rbr
5379 * MIO_UARTX_RBR = MIO UARTX Receive Buffer Register
5381 * The Receive Buffer Register (RBR) is a read-only register that contains the data byte received on the
5382 * serial input port (sin). The data in this register is valid only if the Data Ready (DR) bit in the
5383 * Line status Register (LSR) is set. When the FIFOs are programmed OFF, the data in the RBR must be
5384 * read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. When
5385 * the FIFOs are programmed ON, this register accesses the head of the receive FIFO. If the receive FIFO
5386 * is full (64 characters) and this register is not read before the next data character arrives, then the
5387 * data already in the FIFO is preserved, but any incoming data is lost. An overrun error also occurs.
5389 * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
5392 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
5393 * RBR, THR, and DLL registers are the same.
5395 union cvmx_mio_uartx_rbr
5398 struct cvmx_mio_uartx_rbr_s
5400 #if __BYTE_ORDER == __BIG_ENDIAN
5401 uint64_t reserved_8_63 : 56;
5402 uint64_t rbr : 8; /**< Receive Buffer Register */
5405 uint64_t reserved_8_63 : 56;
5408 struct cvmx_mio_uartx_rbr_s cn30xx;
5409 struct cvmx_mio_uartx_rbr_s cn31xx;
5410 struct cvmx_mio_uartx_rbr_s cn38xx;
5411 struct cvmx_mio_uartx_rbr_s cn38xxp2;
5412 struct cvmx_mio_uartx_rbr_s cn50xx;
5413 struct cvmx_mio_uartx_rbr_s cn52xx;
5414 struct cvmx_mio_uartx_rbr_s cn52xxp1;
5415 struct cvmx_mio_uartx_rbr_s cn56xx;
5416 struct cvmx_mio_uartx_rbr_s cn56xxp1;
5417 struct cvmx_mio_uartx_rbr_s cn58xx;
5418 struct cvmx_mio_uartx_rbr_s cn58xxp1;
5419 struct cvmx_mio_uartx_rbr_s cn63xx;
5420 struct cvmx_mio_uartx_rbr_s cn63xxp1;
5422 typedef union cvmx_mio_uartx_rbr cvmx_mio_uartx_rbr_t;
5423 typedef cvmx_mio_uartx_rbr_t cvmx_uart_rbr_t;
5426 * cvmx_mio_uart#_rfl
5428 * MIO_UARTX_RFL = MIO UARTX Receive FIFO Level Register
5430 * The Receive FIFO Level Register (RFL) indicates the number of data entries in the receive FIFO.
5432 union cvmx_mio_uartx_rfl
5435 struct cvmx_mio_uartx_rfl_s
5437 #if __BYTE_ORDER == __BIG_ENDIAN
5438 uint64_t reserved_7_63 : 57;
5439 uint64_t rfl : 7; /**< Receive FIFO Level Register */
5442 uint64_t reserved_7_63 : 57;
5445 struct cvmx_mio_uartx_rfl_s cn30xx;
5446 struct cvmx_mio_uartx_rfl_s cn31xx;
5447 struct cvmx_mio_uartx_rfl_s cn38xx;
5448 struct cvmx_mio_uartx_rfl_s cn38xxp2;
5449 struct cvmx_mio_uartx_rfl_s cn50xx;
5450 struct cvmx_mio_uartx_rfl_s cn52xx;
5451 struct cvmx_mio_uartx_rfl_s cn52xxp1;
5452 struct cvmx_mio_uartx_rfl_s cn56xx;
5453 struct cvmx_mio_uartx_rfl_s cn56xxp1;
5454 struct cvmx_mio_uartx_rfl_s cn58xx;
5455 struct cvmx_mio_uartx_rfl_s cn58xxp1;
5456 struct cvmx_mio_uartx_rfl_s cn63xx;
5457 struct cvmx_mio_uartx_rfl_s cn63xxp1;
5459 typedef union cvmx_mio_uartx_rfl cvmx_mio_uartx_rfl_t;
5460 typedef cvmx_mio_uartx_rfl_t cvmx_uart_rfl_t;
5463 * cvmx_mio_uart#_rfw
5465 * MIO_UARTX_RFW = MIO UARTX Receive FIFO Write Register
5467 * The Receive FIFO Write Register (RFW) is only valid when FIFO access mode is enabled (FAR bit 0 is
5468 * set). When FIFOs are enabled, this register is used to write data to the receive FIFO. Each
5469 * consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are
5470 * not enabled, this register is used to write data to the RBR.
5472 union cvmx_mio_uartx_rfw
5475 struct cvmx_mio_uartx_rfw_s
5477 #if __BYTE_ORDER == __BIG_ENDIAN
5478 uint64_t reserved_10_63 : 54;
5479 uint64_t rffe : 1; /**< Receive FIFO Framing Error */
5480 uint64_t rfpe : 1; /**< Receive FIFO Parity Error */
5481 uint64_t rfwd : 8; /**< Receive FIFO Write Data */
5486 uint64_t reserved_10_63 : 54;
5489 struct cvmx_mio_uartx_rfw_s cn30xx;
5490 struct cvmx_mio_uartx_rfw_s cn31xx;
5491 struct cvmx_mio_uartx_rfw_s cn38xx;
5492 struct cvmx_mio_uartx_rfw_s cn38xxp2;
5493 struct cvmx_mio_uartx_rfw_s cn50xx;
5494 struct cvmx_mio_uartx_rfw_s cn52xx;
5495 struct cvmx_mio_uartx_rfw_s cn52xxp1;
5496 struct cvmx_mio_uartx_rfw_s cn56xx;
5497 struct cvmx_mio_uartx_rfw_s cn56xxp1;
5498 struct cvmx_mio_uartx_rfw_s cn58xx;
5499 struct cvmx_mio_uartx_rfw_s cn58xxp1;
5500 struct cvmx_mio_uartx_rfw_s cn63xx;
5501 struct cvmx_mio_uartx_rfw_s cn63xxp1;
5503 typedef union cvmx_mio_uartx_rfw cvmx_mio_uartx_rfw_t;
5504 typedef cvmx_mio_uartx_rfw_t cvmx_uart_rfw_t;
5507 * cvmx_mio_uart#_sbcr
5509 * MIO_UARTX_SBCR = MIO UARTX Shadow Break Control Register
5511 * The Shadow Break Control Register (SBCR) is a shadow register for the BREAK bit (LCR bit 6) that can
5512 * be used to remove the burden of having to perform a read-modify-write on the LCR.
5514 union cvmx_mio_uartx_sbcr
5517 struct cvmx_mio_uartx_sbcr_s
5519 #if __BYTE_ORDER == __BIG_ENDIAN
5520 uint64_t reserved_1_63 : 63;
5521 uint64_t sbcr : 1; /**< Shadow Break Control */
5524 uint64_t reserved_1_63 : 63;
5527 struct cvmx_mio_uartx_sbcr_s cn30xx;
5528 struct cvmx_mio_uartx_sbcr_s cn31xx;
5529 struct cvmx_mio_uartx_sbcr_s cn38xx;
5530 struct cvmx_mio_uartx_sbcr_s cn38xxp2;
5531 struct cvmx_mio_uartx_sbcr_s cn50xx;
5532 struct cvmx_mio_uartx_sbcr_s cn52xx;
5533 struct cvmx_mio_uartx_sbcr_s cn52xxp1;
5534 struct cvmx_mio_uartx_sbcr_s cn56xx;
5535 struct cvmx_mio_uartx_sbcr_s cn56xxp1;
5536 struct cvmx_mio_uartx_sbcr_s cn58xx;
5537 struct cvmx_mio_uartx_sbcr_s cn58xxp1;
5538 struct cvmx_mio_uartx_sbcr_s cn63xx;
5539 struct cvmx_mio_uartx_sbcr_s cn63xxp1;
5541 typedef union cvmx_mio_uartx_sbcr cvmx_mio_uartx_sbcr_t;
5542 typedef cvmx_mio_uartx_sbcr_t cvmx_uart_sbcr_t;
5545 * cvmx_mio_uart#_scr
5547 * MIO_UARTX_SCR = MIO UARTX Scratchpad Register
5549 * The Scratchpad Register (SCR) is an 8-bit read/write register for programmers to use as a temporary
5552 union cvmx_mio_uartx_scr
5555 struct cvmx_mio_uartx_scr_s
5557 #if __BYTE_ORDER == __BIG_ENDIAN
5558 uint64_t reserved_8_63 : 56;
5559 uint64_t scr : 8; /**< Scratchpad Register */
5562 uint64_t reserved_8_63 : 56;
5565 struct cvmx_mio_uartx_scr_s cn30xx;
5566 struct cvmx_mio_uartx_scr_s cn31xx;
5567 struct cvmx_mio_uartx_scr_s cn38xx;
5568 struct cvmx_mio_uartx_scr_s cn38xxp2;
5569 struct cvmx_mio_uartx_scr_s cn50xx;
5570 struct cvmx_mio_uartx_scr_s cn52xx;
5571 struct cvmx_mio_uartx_scr_s cn52xxp1;
5572 struct cvmx_mio_uartx_scr_s cn56xx;
5573 struct cvmx_mio_uartx_scr_s cn56xxp1;
5574 struct cvmx_mio_uartx_scr_s cn58xx;
5575 struct cvmx_mio_uartx_scr_s cn58xxp1;
5576 struct cvmx_mio_uartx_scr_s cn63xx;
5577 struct cvmx_mio_uartx_scr_s cn63xxp1;
5579 typedef union cvmx_mio_uartx_scr cvmx_mio_uartx_scr_t;
5580 typedef cvmx_mio_uartx_scr_t cvmx_uart_scr_t;
5583 * cvmx_mio_uart#_sfe
5585 * MIO_UARTX_SFE = MIO UARTX Shadow FIFO Enable Register
5587 * The Shadow FIFO Enable Register (SFE) is a shadow register for the FIFO enable bit (FCR bit 0) that
5588 * can be used to remove the burden of having to store the previously written value to the FCR in memory
5589 * and having to mask this value so that only the FIFO enable bit gets updated.
5591 union cvmx_mio_uartx_sfe
5594 struct cvmx_mio_uartx_sfe_s
5596 #if __BYTE_ORDER == __BIG_ENDIAN
5597 uint64_t reserved_1_63 : 63;
5598 uint64_t sfe : 1; /**< Shadow FIFO Enable */
5601 uint64_t reserved_1_63 : 63;
5604 struct cvmx_mio_uartx_sfe_s cn30xx;
5605 struct cvmx_mio_uartx_sfe_s cn31xx;
5606 struct cvmx_mio_uartx_sfe_s cn38xx;
5607 struct cvmx_mio_uartx_sfe_s cn38xxp2;
5608 struct cvmx_mio_uartx_sfe_s cn50xx;
5609 struct cvmx_mio_uartx_sfe_s cn52xx;
5610 struct cvmx_mio_uartx_sfe_s cn52xxp1;
5611 struct cvmx_mio_uartx_sfe_s cn56xx;
5612 struct cvmx_mio_uartx_sfe_s cn56xxp1;
5613 struct cvmx_mio_uartx_sfe_s cn58xx;
5614 struct cvmx_mio_uartx_sfe_s cn58xxp1;
5615 struct cvmx_mio_uartx_sfe_s cn63xx;
5616 struct cvmx_mio_uartx_sfe_s cn63xxp1;
5618 typedef union cvmx_mio_uartx_sfe cvmx_mio_uartx_sfe_t;
5619 typedef cvmx_mio_uartx_sfe_t cvmx_uart_sfe_t;
5622 * cvmx_mio_uart#_srr
5624 * MIO_UARTX_SRR = MIO UARTX Software Reset Register
5626 * The Software Reset Register (SRR) is a write-only register that resets the UART and/or the receive
5627 * FIFO and/or the transmit FIFO.
5629 * Bit 0 of the SRR is the UART Soft Reset (USR) bit. Setting this bit resets the UART.
5631 * Bit 1 of the SRR is a shadow copy of the RX FIFO Reset bit (FCR bit 1). This can be used to remove
5632 * the burden on software having to store previously written FCR values (which are pretty static) just
5633 * to reset the receive FIFO.
5635 * Bit 2 of the SRR is a shadow copy of the TX FIFO Reset bit (FCR bit 2). This can be used to remove
5636 * the burden on software having to store previously written FCR values (which are pretty static) just
5637 * to reset the transmit FIFO.
5639 union cvmx_mio_uartx_srr
5642 struct cvmx_mio_uartx_srr_s
5644 #if __BYTE_ORDER == __BIG_ENDIAN
5645 uint64_t reserved_3_63 : 61;
5646 uint64_t stfr : 1; /**< Shadow TX FIFO Reset */
5647 uint64_t srfr : 1; /**< Shadow RX FIFO Reset */
5648 uint64_t usr : 1; /**< UART Soft Reset */
5653 uint64_t reserved_3_63 : 61;
5656 struct cvmx_mio_uartx_srr_s cn30xx;
5657 struct cvmx_mio_uartx_srr_s cn31xx;
5658 struct cvmx_mio_uartx_srr_s cn38xx;
5659 struct cvmx_mio_uartx_srr_s cn38xxp2;
5660 struct cvmx_mio_uartx_srr_s cn50xx;
5661 struct cvmx_mio_uartx_srr_s cn52xx;
5662 struct cvmx_mio_uartx_srr_s cn52xxp1;
5663 struct cvmx_mio_uartx_srr_s cn56xx;
5664 struct cvmx_mio_uartx_srr_s cn56xxp1;
5665 struct cvmx_mio_uartx_srr_s cn58xx;
5666 struct cvmx_mio_uartx_srr_s cn58xxp1;
5667 struct cvmx_mio_uartx_srr_s cn63xx;
5668 struct cvmx_mio_uartx_srr_s cn63xxp1;
5670 typedef union cvmx_mio_uartx_srr cvmx_mio_uartx_srr_t;
5671 typedef cvmx_mio_uartx_srr_t cvmx_uart_srr_t;
5674 * cvmx_mio_uart#_srt
5676 * MIO_UARTX_SRT = MIO UARTX Shadow RX Trigger Register
5678 * The Shadow RX Trigger Register (SRT) is a shadow register for the RX Trigger bits (FCR bits 7:6) that
5679 * can be used to remove the burden of having to store the previously written value to the FCR in memory
5680 * and having to mask this value so that only the RX Trigger bits get updated.
5682 union cvmx_mio_uartx_srt
5685 struct cvmx_mio_uartx_srt_s
5687 #if __BYTE_ORDER == __BIG_ENDIAN
5688 uint64_t reserved_2_63 : 62;
5689 uint64_t srt : 2; /**< Shadow RX Trigger */
5692 uint64_t reserved_2_63 : 62;
5695 struct cvmx_mio_uartx_srt_s cn30xx;
5696 struct cvmx_mio_uartx_srt_s cn31xx;
5697 struct cvmx_mio_uartx_srt_s cn38xx;
5698 struct cvmx_mio_uartx_srt_s cn38xxp2;
5699 struct cvmx_mio_uartx_srt_s cn50xx;
5700 struct cvmx_mio_uartx_srt_s cn52xx;
5701 struct cvmx_mio_uartx_srt_s cn52xxp1;
5702 struct cvmx_mio_uartx_srt_s cn56xx;
5703 struct cvmx_mio_uartx_srt_s cn56xxp1;
5704 struct cvmx_mio_uartx_srt_s cn58xx;
5705 struct cvmx_mio_uartx_srt_s cn58xxp1;
5706 struct cvmx_mio_uartx_srt_s cn63xx;
5707 struct cvmx_mio_uartx_srt_s cn63xxp1;
5709 typedef union cvmx_mio_uartx_srt cvmx_mio_uartx_srt_t;
5710 typedef cvmx_mio_uartx_srt_t cvmx_uart_srt_t;
5713 * cvmx_mio_uart#_srts
5715 * MIO_UARTX_SRTS = MIO UARTX Shadow Request To Send Register
5717 * The Shadow Request To Send Register (SRTS) is a shadow register for the RTS bit (MCR bit 1) that can
5718 * be used to remove the burden of having to perform a read-modify-write on the MCR.
5720 union cvmx_mio_uartx_srts
5723 struct cvmx_mio_uartx_srts_s
5725 #if __BYTE_ORDER == __BIG_ENDIAN
5726 uint64_t reserved_1_63 : 63;
5727 uint64_t srts : 1; /**< Shadow Request To Send */
5730 uint64_t reserved_1_63 : 63;
5733 struct cvmx_mio_uartx_srts_s cn30xx;
5734 struct cvmx_mio_uartx_srts_s cn31xx;
5735 struct cvmx_mio_uartx_srts_s cn38xx;
5736 struct cvmx_mio_uartx_srts_s cn38xxp2;
5737 struct cvmx_mio_uartx_srts_s cn50xx;
5738 struct cvmx_mio_uartx_srts_s cn52xx;
5739 struct cvmx_mio_uartx_srts_s cn52xxp1;
5740 struct cvmx_mio_uartx_srts_s cn56xx;
5741 struct cvmx_mio_uartx_srts_s cn56xxp1;
5742 struct cvmx_mio_uartx_srts_s cn58xx;
5743 struct cvmx_mio_uartx_srts_s cn58xxp1;
5744 struct cvmx_mio_uartx_srts_s cn63xx;
5745 struct cvmx_mio_uartx_srts_s cn63xxp1;
5747 typedef union cvmx_mio_uartx_srts cvmx_mio_uartx_srts_t;
5748 typedef cvmx_mio_uartx_srts_t cvmx_uart_srts_t;
5751 * cvmx_mio_uart#_stt
5753 * MIO_UARTX_STT = MIO UARTX Shadow TX Trigger Register
5755 * The Shadow TX Trigger Register (STT) is a shadow register for the TX Trigger bits (FCR bits 5:4) that
5756 * can be used to remove the burden of having to store the previously written value to the FCR in memory
5757 * and having to mask this value so that only the TX Trigger bits get updated.
5759 union cvmx_mio_uartx_stt
5762 struct cvmx_mio_uartx_stt_s
5764 #if __BYTE_ORDER == __BIG_ENDIAN
5765 uint64_t reserved_2_63 : 62;
5766 uint64_t stt : 2; /**< Shadow TX Trigger */
5769 uint64_t reserved_2_63 : 62;
5772 struct cvmx_mio_uartx_stt_s cn30xx;
5773 struct cvmx_mio_uartx_stt_s cn31xx;
5774 struct cvmx_mio_uartx_stt_s cn38xx;
5775 struct cvmx_mio_uartx_stt_s cn38xxp2;
5776 struct cvmx_mio_uartx_stt_s cn50xx;
5777 struct cvmx_mio_uartx_stt_s cn52xx;
5778 struct cvmx_mio_uartx_stt_s cn52xxp1;
5779 struct cvmx_mio_uartx_stt_s cn56xx;
5780 struct cvmx_mio_uartx_stt_s cn56xxp1;
5781 struct cvmx_mio_uartx_stt_s cn58xx;
5782 struct cvmx_mio_uartx_stt_s cn58xxp1;
5783 struct cvmx_mio_uartx_stt_s cn63xx;
5784 struct cvmx_mio_uartx_stt_s cn63xxp1;
5786 typedef union cvmx_mio_uartx_stt cvmx_mio_uartx_stt_t;
5787 typedef cvmx_mio_uartx_stt_t cvmx_uart_stt_t;
5790 * cvmx_mio_uart#_tfl
5792 * MIO_UARTX_TFL = MIO UARTX Transmit FIFO Level Register
5794 * The Transmit FIFO Level Register (TFL) indicates the number of data entries in the transmit FIFO.
5796 union cvmx_mio_uartx_tfl
5799 struct cvmx_mio_uartx_tfl_s
5801 #if __BYTE_ORDER == __BIG_ENDIAN
5802 uint64_t reserved_7_63 : 57;
5803 uint64_t tfl : 7; /**< Transmit FIFO Level Register */
5806 uint64_t reserved_7_63 : 57;
5809 struct cvmx_mio_uartx_tfl_s cn30xx;
5810 struct cvmx_mio_uartx_tfl_s cn31xx;
5811 struct cvmx_mio_uartx_tfl_s cn38xx;
5812 struct cvmx_mio_uartx_tfl_s cn38xxp2;
5813 struct cvmx_mio_uartx_tfl_s cn50xx;
5814 struct cvmx_mio_uartx_tfl_s cn52xx;
5815 struct cvmx_mio_uartx_tfl_s cn52xxp1;
5816 struct cvmx_mio_uartx_tfl_s cn56xx;
5817 struct cvmx_mio_uartx_tfl_s cn56xxp1;
5818 struct cvmx_mio_uartx_tfl_s cn58xx;
5819 struct cvmx_mio_uartx_tfl_s cn58xxp1;
5820 struct cvmx_mio_uartx_tfl_s cn63xx;
5821 struct cvmx_mio_uartx_tfl_s cn63xxp1;
5823 typedef union cvmx_mio_uartx_tfl cvmx_mio_uartx_tfl_t;
5824 typedef cvmx_mio_uartx_tfl_t cvmx_uart_tfl_t;
5827 * cvmx_mio_uart#_tfr
5829 * MIO_UARTX_TFR = MIO UARTX Transmit FIFO Read Register
5831 * The Transmit FIFO Read Register (TFR) is only valid when FIFO access mode is enabled (FAR bit 0 is
5832 * set). When FIFOs are enabled, reading this register gives the data at the top of the transmit FIFO.
5833 * Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the
5834 * top of the FIFO. When FIFOs are not enabled, reading this register gives the data in the THR.
5836 union cvmx_mio_uartx_tfr
5839 struct cvmx_mio_uartx_tfr_s
5841 #if __BYTE_ORDER == __BIG_ENDIAN
5842 uint64_t reserved_8_63 : 56;
5843 uint64_t tfr : 8; /**< Transmit FIFO Read Register */
5846 uint64_t reserved_8_63 : 56;
5849 struct cvmx_mio_uartx_tfr_s cn30xx;
5850 struct cvmx_mio_uartx_tfr_s cn31xx;
5851 struct cvmx_mio_uartx_tfr_s cn38xx;
5852 struct cvmx_mio_uartx_tfr_s cn38xxp2;
5853 struct cvmx_mio_uartx_tfr_s cn50xx;
5854 struct cvmx_mio_uartx_tfr_s cn52xx;
5855 struct cvmx_mio_uartx_tfr_s cn52xxp1;
5856 struct cvmx_mio_uartx_tfr_s cn56xx;
5857 struct cvmx_mio_uartx_tfr_s cn56xxp1;
5858 struct cvmx_mio_uartx_tfr_s cn58xx;
5859 struct cvmx_mio_uartx_tfr_s cn58xxp1;
5860 struct cvmx_mio_uartx_tfr_s cn63xx;
5861 struct cvmx_mio_uartx_tfr_s cn63xxp1;
5863 typedef union cvmx_mio_uartx_tfr cvmx_mio_uartx_tfr_t;
5864 typedef cvmx_mio_uartx_tfr_t cvmx_uart_tfr_t;
5867 * cvmx_mio_uart#_thr
5869 * MIO_UARTX_THR = MIO UARTX Transmit Holding Register
5871 * Transmit Holding Register (THR) is a write-only register that contains data to be transmitted on the
5872 * serial output port (sout). Data can be written to the THR any time that the THR Empty (THRE) bit of
5873 * the Line Status Register (LSR) is set.
5875 * If FIFOs are not enabled and THRE is set, writing a single character to the THR clears the THRE. Any
5876 * additional writes to the THR before the THRE is set again causes the THR data to be overwritten.
5878 * If FIFOs are enabled and THRE is set (and Programmable THRE mode disabled), 64 characters of data may
5879 * be written to the THR before the FIFO is full. Any attempt to write data when the FIFO is full results
5880 * in the write data being lost.
5882 * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
5885 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
5886 * RBR, THR, and DLL registers are the same.
5888 union cvmx_mio_uartx_thr
5891 struct cvmx_mio_uartx_thr_s
5893 #if __BYTE_ORDER == __BIG_ENDIAN
5894 uint64_t reserved_8_63 : 56;
5895 uint64_t thr : 8; /**< Transmit Holding Register */
5898 uint64_t reserved_8_63 : 56;
5901 struct cvmx_mio_uartx_thr_s cn30xx;
5902 struct cvmx_mio_uartx_thr_s cn31xx;
5903 struct cvmx_mio_uartx_thr_s cn38xx;
5904 struct cvmx_mio_uartx_thr_s cn38xxp2;
5905 struct cvmx_mio_uartx_thr_s cn50xx;
5906 struct cvmx_mio_uartx_thr_s cn52xx;
5907 struct cvmx_mio_uartx_thr_s cn52xxp1;
5908 struct cvmx_mio_uartx_thr_s cn56xx;
5909 struct cvmx_mio_uartx_thr_s cn56xxp1;
5910 struct cvmx_mio_uartx_thr_s cn58xx;
5911 struct cvmx_mio_uartx_thr_s cn58xxp1;
5912 struct cvmx_mio_uartx_thr_s cn63xx;
5913 struct cvmx_mio_uartx_thr_s cn63xxp1;
5915 typedef union cvmx_mio_uartx_thr cvmx_mio_uartx_thr_t;
5916 typedef cvmx_mio_uartx_thr_t cvmx_uart_thr_t;
5919 * cvmx_mio_uart#_usr
5921 * MIO_UARTX_USR = MIO UARTX UART Status Register
5923 * The UART Status Register (USR) contains UART status information.
5925 * USR bit 0 is the BUSY bit. When set this bit indicates that a serial transfer is in progress, when
5926 * clear it indicates that the UART is idle or inactive.
5928 * Note: In PASS3, the BUSY bit will always be clear.
5930 * USR bits 1-4 indicate the following FIFO status: TX FIFO Not Full (TFNF), TX FIFO Empty (TFE), RX
5931 * FIFO Not Empty (RFNE), and RX FIFO Full (RFF).
5933 union cvmx_mio_uartx_usr
5936 struct cvmx_mio_uartx_usr_s
5938 #if __BYTE_ORDER == __BIG_ENDIAN
5939 uint64_t reserved_5_63 : 59;
5940 uint64_t rff : 1; /**< RX FIFO Full */
5941 uint64_t rfne : 1; /**< RX FIFO Not Empty */
5942 uint64_t tfe : 1; /**< TX FIFO Empty */
5943 uint64_t tfnf : 1; /**< TX FIFO Not Full */
5944 uint64_t busy : 1; /**< Busy bit (always 0 in PASS3) */
5951 uint64_t reserved_5_63 : 59;
5954 struct cvmx_mio_uartx_usr_s cn30xx;
5955 struct cvmx_mio_uartx_usr_s cn31xx;
5956 struct cvmx_mio_uartx_usr_s cn38xx;
5957 struct cvmx_mio_uartx_usr_s cn38xxp2;
5958 struct cvmx_mio_uartx_usr_s cn50xx;
5959 struct cvmx_mio_uartx_usr_s cn52xx;
5960 struct cvmx_mio_uartx_usr_s cn52xxp1;
5961 struct cvmx_mio_uartx_usr_s cn56xx;
5962 struct cvmx_mio_uartx_usr_s cn56xxp1;
5963 struct cvmx_mio_uartx_usr_s cn58xx;
5964 struct cvmx_mio_uartx_usr_s cn58xxp1;
5965 struct cvmx_mio_uartx_usr_s cn63xx;
5966 struct cvmx_mio_uartx_usr_s cn63xxp1;
5968 typedef union cvmx_mio_uartx_usr cvmx_mio_uartx_usr_t;
5969 typedef cvmx_mio_uartx_usr_t cvmx_uart_usr_t;
5972 * cvmx_mio_uart2_dlh
5974 union cvmx_mio_uart2_dlh
5977 struct cvmx_mio_uart2_dlh_s
5979 #if __BYTE_ORDER == __BIG_ENDIAN
5980 uint64_t reserved_8_63 : 56;
5981 uint64_t dlh : 8; /**< Divisor Latch High Register */
5984 uint64_t reserved_8_63 : 56;
5987 struct cvmx_mio_uart2_dlh_s cn52xx;
5988 struct cvmx_mio_uart2_dlh_s cn52xxp1;
5990 typedef union cvmx_mio_uart2_dlh cvmx_mio_uart2_dlh_t;
5993 * cvmx_mio_uart2_dll
5995 union cvmx_mio_uart2_dll
5998 struct cvmx_mio_uart2_dll_s
6000 #if __BYTE_ORDER == __BIG_ENDIAN
6001 uint64_t reserved_8_63 : 56;
6002 uint64_t dll : 8; /**< Divisor Latch Low Register */
6005 uint64_t reserved_8_63 : 56;
6008 struct cvmx_mio_uart2_dll_s cn52xx;
6009 struct cvmx_mio_uart2_dll_s cn52xxp1;
6011 typedef union cvmx_mio_uart2_dll cvmx_mio_uart2_dll_t;
6014 * cvmx_mio_uart2_far
6016 union cvmx_mio_uart2_far
6019 struct cvmx_mio_uart2_far_s
6021 #if __BYTE_ORDER == __BIG_ENDIAN
6022 uint64_t reserved_1_63 : 63;
6023 uint64_t far : 1; /**< FIFO Access Register */
6026 uint64_t reserved_1_63 : 63;
6029 struct cvmx_mio_uart2_far_s cn52xx;
6030 struct cvmx_mio_uart2_far_s cn52xxp1;
6032 typedef union cvmx_mio_uart2_far cvmx_mio_uart2_far_t;
6035 * cvmx_mio_uart2_fcr
6037 union cvmx_mio_uart2_fcr
6040 struct cvmx_mio_uart2_fcr_s
6042 #if __BYTE_ORDER == __BIG_ENDIAN
6043 uint64_t reserved_8_63 : 56;
6044 uint64_t rxtrig : 2; /**< RX Trigger */
6045 uint64_t txtrig : 2; /**< TX Trigger */
6046 uint64_t reserved_3_3 : 1;
6047 uint64_t txfr : 1; /**< TX FIFO reset */
6048 uint64_t rxfr : 1; /**< RX FIFO reset */
6049 uint64_t en : 1; /**< FIFO enable */
6054 uint64_t reserved_3_3 : 1;
6055 uint64_t txtrig : 2;
6056 uint64_t rxtrig : 2;
6057 uint64_t reserved_8_63 : 56;
6060 struct cvmx_mio_uart2_fcr_s cn52xx;
6061 struct cvmx_mio_uart2_fcr_s cn52xxp1;
6063 typedef union cvmx_mio_uart2_fcr cvmx_mio_uart2_fcr_t;
6066 * cvmx_mio_uart2_htx
6068 union cvmx_mio_uart2_htx
6071 struct cvmx_mio_uart2_htx_s
6073 #if __BYTE_ORDER == __BIG_ENDIAN
6074 uint64_t reserved_1_63 : 63;
6075 uint64_t htx : 1; /**< Halt TX */
6078 uint64_t reserved_1_63 : 63;
6081 struct cvmx_mio_uart2_htx_s cn52xx;
6082 struct cvmx_mio_uart2_htx_s cn52xxp1;
6084 typedef union cvmx_mio_uart2_htx cvmx_mio_uart2_htx_t;
6087 * cvmx_mio_uart2_ier
6089 union cvmx_mio_uart2_ier
6092 struct cvmx_mio_uart2_ier_s
6094 #if __BYTE_ORDER == __BIG_ENDIAN
6095 uint64_t reserved_8_63 : 56;
6096 uint64_t ptime : 1; /**< Programmable THRE Interrupt mode enable */
6097 uint64_t reserved_4_6 : 3;
6098 uint64_t edssi : 1; /**< Enable Modem Status Interrupt */
6099 uint64_t elsi : 1; /**< Enable Receiver Line Status Interrupt */
6100 uint64_t etbei : 1; /**< Enable Transmitter Holding Register Empty Interrupt */
6101 uint64_t erbfi : 1; /**< Enable Received Data Available Interrupt */
6107 uint64_t reserved_4_6 : 3;
6109 uint64_t reserved_8_63 : 56;
6112 struct cvmx_mio_uart2_ier_s cn52xx;
6113 struct cvmx_mio_uart2_ier_s cn52xxp1;
6115 typedef union cvmx_mio_uart2_ier cvmx_mio_uart2_ier_t;
6118 * cvmx_mio_uart2_iir
6120 union cvmx_mio_uart2_iir
6123 struct cvmx_mio_uart2_iir_s
6125 #if __BYTE_ORDER == __BIG_ENDIAN
6126 uint64_t reserved_8_63 : 56;
6127 uint64_t fen : 2; /**< FIFO-enabled bits */
6128 uint64_t reserved_4_5 : 2;
6129 uint64_t iid : 4; /**< Interrupt ID */
6132 uint64_t reserved_4_5 : 2;
6134 uint64_t reserved_8_63 : 56;
6137 struct cvmx_mio_uart2_iir_s cn52xx;
6138 struct cvmx_mio_uart2_iir_s cn52xxp1;
6140 typedef union cvmx_mio_uart2_iir cvmx_mio_uart2_iir_t;
6143 * cvmx_mio_uart2_lcr
6145 union cvmx_mio_uart2_lcr
6148 struct cvmx_mio_uart2_lcr_s
6150 #if __BYTE_ORDER == __BIG_ENDIAN
6151 uint64_t reserved_8_63 : 56;
6152 uint64_t dlab : 1; /**< Divisor Latch Address bit */
6153 uint64_t brk : 1; /**< Break Control bit */
6154 uint64_t reserved_5_5 : 1;
6155 uint64_t eps : 1; /**< Even Parity Select bit */
6156 uint64_t pen : 1; /**< Parity Enable bit */
6157 uint64_t stop : 1; /**< Stop Control bit */
6158 uint64_t cls : 2; /**< Character Length Select */
6164 uint64_t reserved_5_5 : 1;
6167 uint64_t reserved_8_63 : 56;
6170 struct cvmx_mio_uart2_lcr_s cn52xx;
6171 struct cvmx_mio_uart2_lcr_s cn52xxp1;
6173 typedef union cvmx_mio_uart2_lcr cvmx_mio_uart2_lcr_t;
6176 * cvmx_mio_uart2_lsr
6178 union cvmx_mio_uart2_lsr
6181 struct cvmx_mio_uart2_lsr_s
6183 #if __BYTE_ORDER == __BIG_ENDIAN
6184 uint64_t reserved_8_63 : 56;
6185 uint64_t ferr : 1; /**< Error in Receiver FIFO bit */
6186 uint64_t temt : 1; /**< Transmitter Empty bit */
6187 uint64_t thre : 1; /**< Transmitter Holding Register Empty bit */
6188 uint64_t bi : 1; /**< Break Interrupt bit */
6189 uint64_t fe : 1; /**< Framing Error bit */
6190 uint64_t pe : 1; /**< Parity Error bit */
6191 uint64_t oe : 1; /**< Overrun Error bit */
6192 uint64_t dr : 1; /**< Data Ready bit */
6202 uint64_t reserved_8_63 : 56;
6205 struct cvmx_mio_uart2_lsr_s cn52xx;
6206 struct cvmx_mio_uart2_lsr_s cn52xxp1;
6208 typedef union cvmx_mio_uart2_lsr cvmx_mio_uart2_lsr_t;
6211 * cvmx_mio_uart2_mcr
6213 union cvmx_mio_uart2_mcr
6216 struct cvmx_mio_uart2_mcr_s
6218 #if __BYTE_ORDER == __BIG_ENDIAN
6219 uint64_t reserved_6_63 : 58;
6220 uint64_t afce : 1; /**< Auto Flow Control Enable bit */
6221 uint64_t loop : 1; /**< Loopback bit */
6222 uint64_t out2 : 1; /**< OUT2 output bit */
6223 uint64_t out1 : 1; /**< OUT1 output bit */
6224 uint64_t rts : 1; /**< Request To Send output bit */
6225 uint64_t dtr : 1; /**< Data Terminal Ready output bit */
6233 uint64_t reserved_6_63 : 58;
6236 struct cvmx_mio_uart2_mcr_s cn52xx;
6237 struct cvmx_mio_uart2_mcr_s cn52xxp1;
6239 typedef union cvmx_mio_uart2_mcr cvmx_mio_uart2_mcr_t;
6242 * cvmx_mio_uart2_msr
6244 union cvmx_mio_uart2_msr
6247 struct cvmx_mio_uart2_msr_s
6249 #if __BYTE_ORDER == __BIG_ENDIAN
6250 uint64_t reserved_8_63 : 56;
6251 uint64_t dcd : 1; /**< Data Carrier Detect input bit */
6252 uint64_t ri : 1; /**< Ring Indicator input bit */
6253 uint64_t dsr : 1; /**< Data Set Ready input bit */
6254 uint64_t cts : 1; /**< Clear To Send input bit */
6255 uint64_t ddcd : 1; /**< Delta Data Carrier Detect bit */
6256 uint64_t teri : 1; /**< Trailing Edge of Ring Indicator bit */
6257 uint64_t ddsr : 1; /**< Delta Data Set Ready bit */
6258 uint64_t dcts : 1; /**< Delta Clear To Send bit */
6268 uint64_t reserved_8_63 : 56;
6271 struct cvmx_mio_uart2_msr_s cn52xx;
6272 struct cvmx_mio_uart2_msr_s cn52xxp1;
6274 typedef union cvmx_mio_uart2_msr cvmx_mio_uart2_msr_t;
6277 * cvmx_mio_uart2_rbr
6279 union cvmx_mio_uart2_rbr
6282 struct cvmx_mio_uart2_rbr_s
6284 #if __BYTE_ORDER == __BIG_ENDIAN
6285 uint64_t reserved_8_63 : 56;
6286 uint64_t rbr : 8; /**< Receive Buffer Register */
6289 uint64_t reserved_8_63 : 56;
6292 struct cvmx_mio_uart2_rbr_s cn52xx;
6293 struct cvmx_mio_uart2_rbr_s cn52xxp1;
6295 typedef union cvmx_mio_uart2_rbr cvmx_mio_uart2_rbr_t;
6298 * cvmx_mio_uart2_rfl
6300 union cvmx_mio_uart2_rfl
6303 struct cvmx_mio_uart2_rfl_s
6305 #if __BYTE_ORDER == __BIG_ENDIAN
6306 uint64_t reserved_7_63 : 57;
6307 uint64_t rfl : 7; /**< Receive FIFO Level Register */
6310 uint64_t reserved_7_63 : 57;
6313 struct cvmx_mio_uart2_rfl_s cn52xx;
6314 struct cvmx_mio_uart2_rfl_s cn52xxp1;
6316 typedef union cvmx_mio_uart2_rfl cvmx_mio_uart2_rfl_t;
6319 * cvmx_mio_uart2_rfw
6321 union cvmx_mio_uart2_rfw
6324 struct cvmx_mio_uart2_rfw_s
6326 #if __BYTE_ORDER == __BIG_ENDIAN
6327 uint64_t reserved_10_63 : 54;
6328 uint64_t rffe : 1; /**< Receive FIFO Framing Error */
6329 uint64_t rfpe : 1; /**< Receive FIFO Parity Error */
6330 uint64_t rfwd : 8; /**< Receive FIFO Write Data */
6335 uint64_t reserved_10_63 : 54;
6338 struct cvmx_mio_uart2_rfw_s cn52xx;
6339 struct cvmx_mio_uart2_rfw_s cn52xxp1;
6341 typedef union cvmx_mio_uart2_rfw cvmx_mio_uart2_rfw_t;
6344 * cvmx_mio_uart2_sbcr
6346 union cvmx_mio_uart2_sbcr
6349 struct cvmx_mio_uart2_sbcr_s
6351 #if __BYTE_ORDER == __BIG_ENDIAN
6352 uint64_t reserved_1_63 : 63;
6353 uint64_t sbcr : 1; /**< Shadow Break Control */
6356 uint64_t reserved_1_63 : 63;
6359 struct cvmx_mio_uart2_sbcr_s cn52xx;
6360 struct cvmx_mio_uart2_sbcr_s cn52xxp1;
6362 typedef union cvmx_mio_uart2_sbcr cvmx_mio_uart2_sbcr_t;
6365 * cvmx_mio_uart2_scr
6367 union cvmx_mio_uart2_scr
6370 struct cvmx_mio_uart2_scr_s
6372 #if __BYTE_ORDER == __BIG_ENDIAN
6373 uint64_t reserved_8_63 : 56;
6374 uint64_t scr : 8; /**< Scratchpad Register */
6377 uint64_t reserved_8_63 : 56;
6380 struct cvmx_mio_uart2_scr_s cn52xx;
6381 struct cvmx_mio_uart2_scr_s cn52xxp1;
6383 typedef union cvmx_mio_uart2_scr cvmx_mio_uart2_scr_t;
6386 * cvmx_mio_uart2_sfe
6388 union cvmx_mio_uart2_sfe
6391 struct cvmx_mio_uart2_sfe_s
6393 #if __BYTE_ORDER == __BIG_ENDIAN
6394 uint64_t reserved_1_63 : 63;
6395 uint64_t sfe : 1; /**< Shadow FIFO Enable */
6398 uint64_t reserved_1_63 : 63;
6401 struct cvmx_mio_uart2_sfe_s cn52xx;
6402 struct cvmx_mio_uart2_sfe_s cn52xxp1;
6404 typedef union cvmx_mio_uart2_sfe cvmx_mio_uart2_sfe_t;
6407 * cvmx_mio_uart2_srr
6409 union cvmx_mio_uart2_srr
6412 struct cvmx_mio_uart2_srr_s
6414 #if __BYTE_ORDER == __BIG_ENDIAN
6415 uint64_t reserved_3_63 : 61;
6416 uint64_t stfr : 1; /**< Shadow TX FIFO Reset */
6417 uint64_t srfr : 1; /**< Shadow RX FIFO Reset */
6418 uint64_t usr : 1; /**< UART Soft Reset */
6423 uint64_t reserved_3_63 : 61;
6426 struct cvmx_mio_uart2_srr_s cn52xx;
6427 struct cvmx_mio_uart2_srr_s cn52xxp1;
6429 typedef union cvmx_mio_uart2_srr cvmx_mio_uart2_srr_t;
6432 * cvmx_mio_uart2_srt
6434 union cvmx_mio_uart2_srt
6437 struct cvmx_mio_uart2_srt_s
6439 #if __BYTE_ORDER == __BIG_ENDIAN
6440 uint64_t reserved_2_63 : 62;
6441 uint64_t srt : 2; /**< Shadow RX Trigger */
6444 uint64_t reserved_2_63 : 62;
6447 struct cvmx_mio_uart2_srt_s cn52xx;
6448 struct cvmx_mio_uart2_srt_s cn52xxp1;
6450 typedef union cvmx_mio_uart2_srt cvmx_mio_uart2_srt_t;
6453 * cvmx_mio_uart2_srts
6455 union cvmx_mio_uart2_srts
6458 struct cvmx_mio_uart2_srts_s
6460 #if __BYTE_ORDER == __BIG_ENDIAN
6461 uint64_t reserved_1_63 : 63;
6462 uint64_t srts : 1; /**< Shadow Request To Send */
6465 uint64_t reserved_1_63 : 63;
6468 struct cvmx_mio_uart2_srts_s cn52xx;
6469 struct cvmx_mio_uart2_srts_s cn52xxp1;
6471 typedef union cvmx_mio_uart2_srts cvmx_mio_uart2_srts_t;
6474 * cvmx_mio_uart2_stt
6476 union cvmx_mio_uart2_stt
6479 struct cvmx_mio_uart2_stt_s
6481 #if __BYTE_ORDER == __BIG_ENDIAN
6482 uint64_t reserved_2_63 : 62;
6483 uint64_t stt : 2; /**< Shadow TX Trigger */
6486 uint64_t reserved_2_63 : 62;
6489 struct cvmx_mio_uart2_stt_s cn52xx;
6490 struct cvmx_mio_uart2_stt_s cn52xxp1;
6492 typedef union cvmx_mio_uart2_stt cvmx_mio_uart2_stt_t;
6495 * cvmx_mio_uart2_tfl
6497 union cvmx_mio_uart2_tfl
6500 struct cvmx_mio_uart2_tfl_s
6502 #if __BYTE_ORDER == __BIG_ENDIAN
6503 uint64_t reserved_7_63 : 57;
6504 uint64_t tfl : 7; /**< Transmit FIFO Level Register */
6507 uint64_t reserved_7_63 : 57;
6510 struct cvmx_mio_uart2_tfl_s cn52xx;
6511 struct cvmx_mio_uart2_tfl_s cn52xxp1;
6513 typedef union cvmx_mio_uart2_tfl cvmx_mio_uart2_tfl_t;
6516 * cvmx_mio_uart2_tfr
6518 union cvmx_mio_uart2_tfr
6521 struct cvmx_mio_uart2_tfr_s
6523 #if __BYTE_ORDER == __BIG_ENDIAN
6524 uint64_t reserved_8_63 : 56;
6525 uint64_t tfr : 8; /**< Transmit FIFO Read Register */
6528 uint64_t reserved_8_63 : 56;
6531 struct cvmx_mio_uart2_tfr_s cn52xx;
6532 struct cvmx_mio_uart2_tfr_s cn52xxp1;
6534 typedef union cvmx_mio_uart2_tfr cvmx_mio_uart2_tfr_t;
6537 * cvmx_mio_uart2_thr
6539 union cvmx_mio_uart2_thr
6542 struct cvmx_mio_uart2_thr_s
6544 #if __BYTE_ORDER == __BIG_ENDIAN
6545 uint64_t reserved_8_63 : 56;
6546 uint64_t thr : 8; /**< Transmit Holding Register */
6549 uint64_t reserved_8_63 : 56;
6552 struct cvmx_mio_uart2_thr_s cn52xx;
6553 struct cvmx_mio_uart2_thr_s cn52xxp1;
6555 typedef union cvmx_mio_uart2_thr cvmx_mio_uart2_thr_t;
6558 * cvmx_mio_uart2_usr
6560 union cvmx_mio_uart2_usr
6563 struct cvmx_mio_uart2_usr_s
6565 #if __BYTE_ORDER == __BIG_ENDIAN
6566 uint64_t reserved_5_63 : 59;
6567 uint64_t rff : 1; /**< RX FIFO Full */
6568 uint64_t rfne : 1; /**< RX FIFO Not Empty */
6569 uint64_t tfe : 1; /**< TX FIFO Empty */
6570 uint64_t tfnf : 1; /**< TX FIFO Not Full */
6571 uint64_t busy : 1; /**< Busy bit (always 0 in PASS3) */
6578 uint64_t reserved_5_63 : 59;
6581 struct cvmx_mio_uart2_usr_s cn52xx;
6582 struct cvmx_mio_uart2_usr_s cn52xxp1;
6584 typedef union cvmx_mio_uart2_usr cvmx_mio_uart2_usr_t;