1 /***********************license start***************
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_MPI_TYPEDEFS_H__
53 #define __CVMX_MPI_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC()
57 static inline uint64_t CVMX_MPI_CFG_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
60 cvmx_warn("CVMX_MPI_CFG not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001070000001000ull);
64 #define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
70 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) ||
71 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) ||
72 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8)))))
73 cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset);
74 return CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8;
77 #define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
79 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
80 #define CVMX_MPI_STS CVMX_MPI_STS_FUNC()
81 static inline uint64_t CVMX_MPI_STS_FUNC(void)
83 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
84 cvmx_warn("CVMX_MPI_STS not supported on this chip\n");
85 return CVMX_ADD_IO_SEG(0x0001070000001008ull);
88 #define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
90 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
91 #define CVMX_MPI_TX CVMX_MPI_TX_FUNC()
92 static inline uint64_t CVMX_MPI_TX_FUNC(void)
94 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
95 cvmx_warn("CVMX_MPI_TX not supported on this chip\n");
96 return CVMX_ADD_IO_SEG(0x0001070000001010ull);
99 #define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
108 struct cvmx_mpi_cfg_s
110 #if __BYTE_ORDER == __BIG_ENDIAN
111 uint64_t reserved_29_63 : 35;
112 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
113 CLKDIV = Feclk / (2 * Fsclk) */
114 uint64_t reserved_12_15 : 4;
115 uint64_t cslate : 1; /**< If 0, MPI_CS asserts 1/2 SCLK before transaction
116 1, MPI_CS assert coincident with transaction
117 NOTE: only used if CSENA == 1 */
118 uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not
119 expected to be driving
120 1, MPI_TX pin is tristated when not transmitting
121 NOTE: only used when WIREOR==1 */
122 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between
124 uint64_t cshi : 1; /**< If 0, CS is low asserted
125 1, CS is high asserted */
126 uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
127 1, CS is driven per MPI_TX intruction */
128 uint64_t int_ena : 1; /**< If 0, polling is required
129 1, MPI engine interrupts X end of transaction */
130 uint64_t lsbfirst : 1; /**< If 0, shift MSB first
131 1, shift LSB first */
132 uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
133 MPI_TX pin is always driven
134 1, MPI_TX/RX is all from MPI_TX pin (MPI)
135 MPI_TX pin is tristated when not transmitting
136 NOTE: if WIREOR==1, MPI_RX pin is not used by the
138 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after
139 completion of MPI transaction
140 1, clock never idles, requires CS deassertion
141 assertion between commands */
142 uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
143 1, MPI_CLK idles low, 1st transition is lo->hi */
144 uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs
145 1, MPI_CLK, MPI_CS, and MPI_TX are driven */
149 uint64_t clk_cont : 1;
151 uint64_t lsbfirst : 1;
152 uint64_t int_ena : 1;
155 uint64_t idleclks : 2;
158 uint64_t reserved_12_15 : 4;
159 uint64_t clkdiv : 13;
160 uint64_t reserved_29_63 : 35;
163 struct cvmx_mpi_cfg_s cn30xx;
164 struct cvmx_mpi_cfg_cn31xx
166 #if __BYTE_ORDER == __BIG_ENDIAN
167 uint64_t reserved_29_63 : 35;
168 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
169 CLKDIV = Feclk / (2 * Fsclk) */
170 uint64_t reserved_11_15 : 5;
171 uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not
172 expected to be driving
173 1, MPI_TX pin is tristated when not transmitting
174 NOTE: only used when WIREOR==1 */
175 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between
177 uint64_t cshi : 1; /**< If 0, CS is low asserted
178 1, CS is high asserted */
179 uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
180 1, CS is driven per MPI_TX intruction */
181 uint64_t int_ena : 1; /**< If 0, polling is required
182 1, MPI engine interrupts X end of transaction */
183 uint64_t lsbfirst : 1; /**< If 0, shift MSB first
184 1, shift LSB first */
185 uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
186 MPI_TX pin is always driven
187 1, MPI_TX/RX is all from MPI_TX pin (MPI)
188 MPI_TX pin is tristated when not transmitting
189 NOTE: if WIREOR==1, MPI_RX pin is not used by the
191 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after
192 completion of MPI transaction
193 1, clock never idles, requires CS deassertion
194 assertion between commands */
195 uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
196 1, MPI_CLK idles low, 1st transition is lo->hi */
197 uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs
198 1, MPI_CLK, MPI_CS, and MPI_TX are driven */
202 uint64_t clk_cont : 1;
204 uint64_t lsbfirst : 1;
205 uint64_t int_ena : 1;
208 uint64_t idleclks : 2;
210 uint64_t reserved_11_15 : 5;
211 uint64_t clkdiv : 13;
212 uint64_t reserved_29_63 : 35;
215 struct cvmx_mpi_cfg_s cn50xx;
217 typedef union cvmx_mpi_cfg cvmx_mpi_cfg_t;
225 struct cvmx_mpi_datx_s
227 #if __BYTE_ORDER == __BIG_ENDIAN
228 uint64_t reserved_8_63 : 56;
229 uint64_t data : 8; /**< Data to transmit/received */
232 uint64_t reserved_8_63 : 56;
235 struct cvmx_mpi_datx_s cn30xx;
236 struct cvmx_mpi_datx_s cn31xx;
237 struct cvmx_mpi_datx_s cn50xx;
239 typedef union cvmx_mpi_datx cvmx_mpi_datx_t;
247 struct cvmx_mpi_sts_s
249 #if __BYTE_ORDER == __BIG_ENDIAN
250 uint64_t reserved_13_63 : 51;
251 uint64_t rxnum : 5; /**< Number of bytes written for transaction */
252 uint64_t reserved_1_7 : 7;
253 uint64_t busy : 1; /**< If 0, no MPI transaction in progress
254 1, MPI engine is processing a transaction */
257 uint64_t reserved_1_7 : 7;
259 uint64_t reserved_13_63 : 51;
262 struct cvmx_mpi_sts_s cn30xx;
263 struct cvmx_mpi_sts_s cn31xx;
264 struct cvmx_mpi_sts_s cn50xx;
266 typedef union cvmx_mpi_sts cvmx_mpi_sts_t;
276 #if __BYTE_ORDER == __BIG_ENDIAN
277 uint64_t reserved_17_63 : 47;
278 uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done
279 1, leave CS asserted after transactrion is done */
280 uint64_t reserved_13_15 : 3;
281 uint64_t txnum : 5; /**< Number of bytes to transmit */
282 uint64_t reserved_5_7 : 3;
283 uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) */
286 uint64_t reserved_5_7 : 3;
288 uint64_t reserved_13_15 : 3;
289 uint64_t leavecs : 1;
290 uint64_t reserved_17_63 : 47;
293 struct cvmx_mpi_tx_s cn30xx;
294 struct cvmx_mpi_tx_s cn31xx;
295 struct cvmx_mpi_tx_s cn50xx;
297 typedef union cvmx_mpi_tx cvmx_mpi_tx_t;