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49 * Interface to PCIe as a host(RC) or target(EP)
51 * <hr>$Revision: 70030 $<hr>
54 #ifndef __CVMX_PCIE_H__
55 #define __CVMX_PCIE_H__
62 * The physical memory base mapped by BAR1. 256MB at the end of the
65 #define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
66 #define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
69 * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
70 * place BAR1 so it is the same for both.
72 #define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
79 uint64_t upper : 2; /* Normally 2 for XKPHYS */
80 uint64_t reserved_49_61 : 13; /* Must be zero */
81 uint64_t io : 1; /* 1 for IO space access */
82 uint64_t did : 5; /* PCIe DID = 3 */
83 uint64_t subdid : 3; /* PCIe SubDID = 1 */
84 uint64_t reserved_36_39 : 4; /* Must be zero */
85 uint64_t es : 2; /* Endian swap = 1 */
86 uint64_t port : 2; /* PCIe port 0,1 */
87 uint64_t reserved_29_31 : 3; /* Must be zero */
88 uint64_t ty : 1; /* Selects the type of the configuration request (0 = type 0, 1 = type 1). */
89 uint64_t bus : 8; /* Target bus number sent in the ID in the request. */
90 uint64_t dev : 5; /* Target device number sent in the ID in the request. Note that Dev must be
91 zero for type 0 configuration requests. */
92 uint64_t func : 3; /* Target function number sent in the ID in the request. */
93 uint64_t reg : 12; /* Selects a register in the configuration space of the target. */
97 uint64_t upper : 2; /* Normally 2 for XKPHYS */
98 uint64_t reserved_49_61 : 13; /* Must be zero */
99 uint64_t io : 1; /* 1 for IO space access */
100 uint64_t did : 5; /* PCIe DID = 3 */
101 uint64_t subdid : 3; /* PCIe SubDID = 2 */
102 uint64_t reserved_36_39 : 4; /* Must be zero */
103 uint64_t es : 2; /* Endian swap = 1 */
104 uint64_t port : 2; /* PCIe port 0,1 */
105 uint64_t address : 32; /* PCIe IO address */
109 uint64_t upper : 2; /* Normally 2 for XKPHYS */
110 uint64_t reserved_49_61 : 13; /* Must be zero */
111 uint64_t io : 1; /* 1 for IO space access */
112 uint64_t did : 5; /* PCIe DID = 3 */
113 uint64_t subdid : 3; /* PCIe SubDID = 3-6 */
114 uint64_t reserved_36_39 : 4; /* Must be zero */
115 uint64_t address : 36; /* PCIe Mem address */
117 } cvmx_pcie_address_t;
121 * Return the Core virtual base address for PCIe IO access. IOs are
122 * read/written as an offset from this address.
124 * @param pcie_port PCIe port the IO is for
126 * @return 64bit Octeon IO base address for read/write
128 uint64_t cvmx_pcie_get_io_base_address(int pcie_port);
131 * Size of the IO address region returned at address
132 * cvmx_pcie_get_io_base_address()
134 * @param pcie_port PCIe port the IO is for
136 * @return Size of the IO window
138 uint64_t cvmx_pcie_get_io_size(int pcie_port);
141 * Return the Core virtual base address for PCIe MEM access. Memory is
142 * read/written as an offset from this address.
144 * @param pcie_port PCIe port the IO is for
146 * @return 64bit Octeon IO base address for read/write
148 uint64_t cvmx_pcie_get_mem_base_address(int pcie_port);
151 * Size of the Mem address region returned at address
152 * cvmx_pcie_get_mem_base_address()
154 * @param pcie_port PCIe port the IO is for
156 * @return Size of the Mem window
158 uint64_t cvmx_pcie_get_mem_size(int pcie_port);
161 * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
163 * @param pcie_port PCIe port to initialize
165 * @return Zero on success
167 int cvmx_pcie_rc_initialize(int pcie_port);
170 * Shutdown a PCIe port and put it in reset
172 * @param pcie_port PCIe port to shutdown
174 * @return Zero on success
176 int cvmx_pcie_rc_shutdown(int pcie_port);
179 * Read 8bits from a Device's config space
181 * @param pcie_port PCIe port the device is on
183 * @param dev Device ID
184 * @param fn Device sub function
185 * @param reg Register to access
187 * @return Result of the read
189 uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn, int reg);
192 * Read 16bits from a Device's config space
194 * @param pcie_port PCIe port the device is on
196 * @param dev Device ID
197 * @param fn Device sub function
198 * @param reg Register to access
200 * @return Result of the read
202 uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn, int reg);
205 * Read 32bits from a Device's config space
207 * @param pcie_port PCIe port the device is on
209 * @param dev Device ID
210 * @param fn Device sub function
211 * @param reg Register to access
213 * @return Result of the read
215 uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn, int reg);
218 * Write 8bits to a Device's config space
220 * @param pcie_port PCIe port the device is on
222 * @param dev Device ID
223 * @param fn Device sub function
224 * @param reg Register to access
225 * @param val Value to write
227 void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg, uint8_t val);
230 * Write 16bits to a Device's config space
232 * @param pcie_port PCIe port the device is on
234 * @param dev Device ID
235 * @param fn Device sub function
236 * @param reg Register to access
237 * @param val Value to write
239 void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg, uint16_t val);
242 * Write 32bits to a Device's config space
244 * @param pcie_port PCIe port the device is on
246 * @param dev Device ID
247 * @param fn Device sub function
248 * @param reg Register to access
249 * @param val Value to write
251 void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg, uint32_t val);
254 * Read a PCIe config space register indirectly. This is used for
255 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
257 * @param pcie_port PCIe port to read from
258 * @param cfg_offset Address to read
262 uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset);
265 * Write a PCIe config space register indirectly. This is used for
266 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
268 * @param pcie_port PCIe port to write to
269 * @param cfg_offset Address to write
270 * @param val Value to write
272 void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val);
275 * Write a 32bit value to the Octeon NPEI register space
277 * @param address Address to write to
278 * @param val Value to write
280 static inline void cvmx_pcie_npei_write32(uint64_t address, uint32_t val)
282 cvmx_write64_uint32(address ^ 4, val);
283 cvmx_read64_uint32(address ^ 4);
287 * Read a 32bit value from the Octeon NPEI register space
289 * @param address Address to read
292 static inline uint32_t cvmx_pcie_npei_read32(uint64_t address)
294 return cvmx_read64_uint32(address ^ 4);
298 * Initialize a PCIe port for use in target(EP) mode.
300 * @param pcie_port PCIe port to initialize
302 * @return Zero on success
304 int cvmx_pcie_ep_initialize(int pcie_port);
307 * Wait for posted PCIe read/writes to reach the other side of
308 * the internal PCIe switch. This will insure that core
309 * read/writes are posted before anything after this function
310 * is called. This may be necessary when writing to memory that
311 * will later be read using the DMA/PKT engines.
313 * @param pcie_port PCIe port to wait for
315 void cvmx_pcie_wait_for_pending(int pcie_port);