1 /***********************license start***************
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_PCM_TYPEDEFS_H__
53 #define __CVMX_PCM_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
62 cvmx_warn("CVMX_PCM_CLKX_CFG(%lu) is invalid on this chip\n", offset);
63 return CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384;
66 #define CVMX_PCM_CLKX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384)
68 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
69 static inline uint64_t CVMX_PCM_CLKX_DBG(unsigned long offset)
72 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
73 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
74 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
75 cvmx_warn("CVMX_PCM_CLKX_DBG(%lu) is invalid on this chip\n", offset);
76 return CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384;
79 #define CVMX_PCM_CLKX_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384)
81 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
82 static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
85 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
86 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
87 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
88 cvmx_warn("CVMX_PCM_CLKX_GEN(%lu) is invalid on this chip\n", offset);
89 return CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384;
92 #define CVMX_PCM_CLKX_GEN(offset) (CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384)
98 union cvmx_pcm_clkx_cfg
101 struct cvmx_pcm_clkx_cfg_s
103 #if __BYTE_ORDER == __BIG_ENDIAN
104 uint64_t fsyncgood : 1; /**< FSYNC status
105 If 1, the last frame had a correctly positioned
107 If 0, none/extra fsync pulse seen on most recent
109 NOTE: this is intended for startup. the FSYNCEXTRA
110 and FSYNCMISSING interrupts are intended for
111 detecting loss of sync during normal operation. */
112 uint64_t reserved_48_62 : 15;
113 uint64_t fsyncsamp : 16; /**< Number of ECLKs from internal BCLK edge to
115 NOTE: used to sync to the start of a frame and to
116 check for FSYNC errors. */
117 uint64_t reserved_26_31 : 6;
118 uint64_t fsynclen : 5; /**< Number of 1/2 BCLKs FSYNC is asserted for
119 NOTE: only used when GEN==1 */
120 uint64_t fsyncloc : 5; /**< FSYNC location, in 1/2 BCLKS before timeslot 0,
122 NOTE: also used to detect framing errors and
123 therefore must have a correct value even if GEN==0 */
124 uint64_t numslots : 10; /**< Number of 8-bit slots in a frame
125 NOTE: this, along with EXTRABIT and Fbclk
126 determines FSYNC frequency when GEN == 1
127 NOTE: also used to detect framing errors and
128 therefore must have a correct value even if GEN==0 */
129 uint64_t extrabit : 1; /**< If 0, no frame bit
130 If 1, add one extra bit time for frame bit
131 NOTE: if GEN == 1, then FSYNC will be delayed one
133 NOTE: also used to detect framing errors and
134 therefore must have a correct value even if GEN==0
135 NOTE: the extra bit comes from the LSB/MSB of the
136 first byte of the frame in the transmit memory
137 region. LSB vs MSB is determined from the setting
138 of PCMn_TDM_CFG[LSBFIRST]. */
139 uint64_t bitlen : 2; /**< Number of BCLKs in a bit time.
143 3 : operation undefined */
144 uint64_t bclkpol : 1; /**< If 0, BCLK rise edge is start of bit time
145 If 1, BCLK fall edge is start of bit time
146 NOTE: also used to detect framing errors and
147 therefore must have a correct value even if GEN==0 */
148 uint64_t fsyncpol : 1; /**< If 0, FSYNC idles low, asserts high
149 If 1, FSYNC idles high, asserts low
150 NOTE: also used to detect framing errors and
151 therefore must have a correct value even if GEN==0 */
152 uint64_t ena : 1; /**< If 0, Clock receiving logic is doing nothing
153 1, Clock receiving logic is looking for sync */
156 uint64_t fsyncpol : 1;
157 uint64_t bclkpol : 1;
159 uint64_t extrabit : 1;
160 uint64_t numslots : 10;
161 uint64_t fsyncloc : 5;
162 uint64_t fsynclen : 5;
163 uint64_t reserved_26_31 : 6;
164 uint64_t fsyncsamp : 16;
165 uint64_t reserved_48_62 : 15;
166 uint64_t fsyncgood : 1;
169 struct cvmx_pcm_clkx_cfg_s cn30xx;
170 struct cvmx_pcm_clkx_cfg_s cn31xx;
171 struct cvmx_pcm_clkx_cfg_s cn50xx;
173 typedef union cvmx_pcm_clkx_cfg cvmx_pcm_clkx_cfg_t;
178 union cvmx_pcm_clkx_dbg
181 struct cvmx_pcm_clkx_dbg_s
183 #if __BYTE_ORDER == __BIG_ENDIAN
184 uint64_t debuginfo : 64; /**< Miscellaneous debug information */
186 uint64_t debuginfo : 64;
189 struct cvmx_pcm_clkx_dbg_s cn30xx;
190 struct cvmx_pcm_clkx_dbg_s cn31xx;
191 struct cvmx_pcm_clkx_dbg_s cn50xx;
193 typedef union cvmx_pcm_clkx_dbg cvmx_pcm_clkx_dbg_t;
198 union cvmx_pcm_clkx_gen
201 struct cvmx_pcm_clkx_gen_s
203 #if __BYTE_ORDER == __BIG_ENDIAN
204 uint64_t deltasamp : 16; /**< Signed number of ECLKs to move sampled BCLK edge
205 NOTE: the complete number of ECLKs to move is:
206 NUMSAMP + 2 + 1 + DELTASAMP
207 NUMSAMP to compensate for sampling delay
208 + 2 to compensate for dual-rank synchronizer
210 + DELTASAMP to CMA/debugging */
211 uint64_t numsamp : 16; /**< Number of ECLK samples to detect BCLK change when
213 uint64_t n : 32; /**< Determines BCLK frequency when generating clock
214 NOTE: Fbclk = Feclk * N / 2^32
215 N = (Fbclk / Feclk) * 2^32
216 NOTE: writing N == 0 stops the clock generator, and
217 causes bclk and fsync to be RECEIVED */
220 uint64_t numsamp : 16;
221 uint64_t deltasamp : 16;
224 struct cvmx_pcm_clkx_gen_s cn30xx;
225 struct cvmx_pcm_clkx_gen_s cn31xx;
226 struct cvmx_pcm_clkx_gen_s cn50xx;
228 typedef union cvmx_pcm_clkx_gen cvmx_pcm_clkx_gen_t;