1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_PCMX_TYPEDEFS_H__
53 #define __CVMX_PCMX_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
62 cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset);
63 return CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384;
66 #define CVMX_PCMX_DMA_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384)
68 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
69 static inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset)
72 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
73 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
74 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
75 cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset);
76 return CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384;
79 #define CVMX_PCMX_INT_ENA(offset) (CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384)
81 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
82 static inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset)
85 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
86 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
87 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
88 cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset);
89 return CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384;
92 #define CVMX_PCMX_INT_SUM(offset) (CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384)
94 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
95 static inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset)
98 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
99 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
100 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
101 cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset);
102 return CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384;
105 #define CVMX_PCMX_RXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384)
107 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
108 static inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset)
111 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
112 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
113 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
114 cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset);
115 return CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384;
118 #define CVMX_PCMX_RXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384)
120 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
121 static inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset)
124 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
125 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
126 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
127 cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset);
128 return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384;
131 #define CVMX_PCMX_RXMSK0(offset) (CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384)
133 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
134 static inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset)
137 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
138 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
139 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
140 cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset);
141 return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384;
144 #define CVMX_PCMX_RXMSK1(offset) (CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384)
146 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
147 static inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset)
150 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
151 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
152 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
153 cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset);
154 return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384;
157 #define CVMX_PCMX_RXMSK2(offset) (CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384)
159 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
160 static inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset)
163 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
164 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
166 cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset);
167 return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384;
170 #define CVMX_PCMX_RXMSK3(offset) (CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384)
172 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
173 static inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset)
176 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
177 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
178 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
179 cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset);
180 return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384;
183 #define CVMX_PCMX_RXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384)
185 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
186 static inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset)
189 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
190 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
191 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
192 cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n", offset);
193 return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384;
196 #define CVMX_PCMX_RXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384)
198 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
199 static inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset)
202 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
203 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
204 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
205 cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n", offset);
206 return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384;
209 #define CVMX_PCMX_RXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384)
211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
212 static inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset)
215 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
216 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
217 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
218 cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n", offset);
219 return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384;
222 #define CVMX_PCMX_RXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384)
224 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
225 static inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset)
228 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
229 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
230 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
231 cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n", offset);
232 return CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384;
235 #define CVMX_PCMX_RXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384)
237 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
238 static inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset)
241 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
242 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
243 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
244 cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n", offset);
245 return CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384;
248 #define CVMX_PCMX_TDM_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384)
250 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
251 static inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset)
254 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
255 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
256 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
257 cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n", offset);
258 return CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384;
261 #define CVMX_PCMX_TDM_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384)
263 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
264 static inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset)
267 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
268 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
269 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
270 cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n", offset);
271 return CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384;
274 #define CVMX_PCMX_TXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384)
276 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
277 static inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset)
280 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
281 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
282 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
283 cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n", offset);
284 return CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384;
287 #define CVMX_PCMX_TXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384)
289 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
290 static inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset)
293 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
294 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
295 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
296 cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n", offset);
297 return CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384;
300 #define CVMX_PCMX_TXMSK0(offset) (CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384)
302 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
303 static inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset)
306 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
307 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
308 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
309 cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n", offset);
310 return CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384;
313 #define CVMX_PCMX_TXMSK1(offset) (CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384)
315 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
316 static inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset)
319 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
320 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
321 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
322 cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n", offset);
323 return CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384;
326 #define CVMX_PCMX_TXMSK2(offset) (CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384)
328 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
329 static inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset)
332 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
333 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
334 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
335 cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n", offset);
336 return CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384;
339 #define CVMX_PCMX_TXMSK3(offset) (CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384)
341 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
342 static inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset)
345 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
346 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
347 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
348 cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n", offset);
349 return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384;
352 #define CVMX_PCMX_TXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384)
354 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
355 static inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset)
358 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
359 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
360 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
361 cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n", offset);
362 return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384;
365 #define CVMX_PCMX_TXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384)
367 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
368 static inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset)
371 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
372 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
373 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
374 cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n", offset);
375 return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384;
378 #define CVMX_PCMX_TXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384)
380 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
381 static inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset)
384 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
385 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
386 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
387 cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n", offset);
388 return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384;
391 #define CVMX_PCMX_TXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384)
393 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
394 static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
397 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
398 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
399 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
400 cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n", offset);
401 return CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384;
404 #define CVMX_PCMX_TXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384)
410 union cvmx_pcmx_dma_cfg
413 struct cvmx_pcmx_dma_cfg_s
415 #if __BYTE_ORDER == __BIG_ENDIAN
416 uint64_t rdpend : 1; /**< If 0, no L2C read responses pending
417 1, L2C read responses are outstanding
418 NOTE: When restarting after stopping a running TDM
419 engine, software must wait for RDPEND to read 0
420 before writing PCMn_TDM_CFG[ENABLE] to a 1 */
421 uint64_t reserved_54_62 : 9;
422 uint64_t rxslots : 10; /**< Number of 8-bit slots to receive per frame
423 (number of slots in a receive superframe) */
424 uint64_t reserved_42_43 : 2;
425 uint64_t txslots : 10; /**< Number of 8-bit slots to transmit per frame
426 (number of slots in a transmit superframe) */
427 uint64_t reserved_30_31 : 2;
428 uint64_t rxst : 10; /**< Number of frame writes for interrupt */
429 uint64_t reserved_19_19 : 1;
430 uint64_t useldt : 1; /**< If 0, use LDI command to read from L2C
431 1, use LDT command to read from L2C */
432 uint64_t txrd : 10; /**< Number of frame reads for interrupt */
433 uint64_t fetchsiz : 4; /**< FETCHSIZ+1 timeslots are read when threshold is
435 uint64_t thresh : 4; /**< If number of bytes remaining in the DMA fifo is <=
436 THRESH, initiate a fetch of timeslot data from the
437 transmit memory region.
438 NOTE: there are only 16B of buffer for each engine
439 so the seetings for FETCHSIZ and THRESH must be
440 such that the buffer will not be overrun:
442 THRESH + min(FETCHSIZ + 1,TXSLOTS) MUST BE <= 16 */
445 uint64_t fetchsiz : 4;
448 uint64_t reserved_19_19 : 1;
450 uint64_t reserved_30_31 : 2;
451 uint64_t txslots : 10;
452 uint64_t reserved_42_43 : 2;
453 uint64_t rxslots : 10;
454 uint64_t reserved_54_62 : 9;
458 struct cvmx_pcmx_dma_cfg_s cn30xx;
459 struct cvmx_pcmx_dma_cfg_s cn31xx;
460 struct cvmx_pcmx_dma_cfg_s cn50xx;
462 typedef union cvmx_pcmx_dma_cfg cvmx_pcmx_dma_cfg_t;
467 union cvmx_pcmx_int_ena
470 struct cvmx_pcmx_int_ena_s
472 #if __BYTE_ORDER == __BIG_ENDIAN
473 uint64_t reserved_8_63 : 56;
474 uint64_t rxovf : 1; /**< Enable interrupt if RX byte overflows */
475 uint64_t txempty : 1; /**< Enable interrupt on TX byte empty */
476 uint64_t txrd : 1; /**< Enable DMA engine frame read interrupts */
477 uint64_t txwrap : 1; /**< Enable TX region wrap interrupts */
478 uint64_t rxst : 1; /**< Enable DMA engine frame store interrupts */
479 uint64_t rxwrap : 1; /**< Enable RX region wrap interrupts */
480 uint64_t fsyncextra : 1; /**< Enable FSYNC extra interrupts
481 NOTE: FSYNCEXTRA errors are defined as an FSYNC
482 found in the "wrong" spot of a frame given the
483 programming of PCMn_CLK_CFG[NUMSLOTS] and
484 PCMn_CLK_CFG[EXTRABIT]. */
485 uint64_t fsyncmissed : 1; /**< Enable FSYNC missed interrupts
486 NOTE: FSYNCMISSED errors are defined as an FSYNC
487 missing from the correct spot in a frame given
488 the programming of PCMn_CLK_CFG[NUMSLOTS] and
489 PCMn_CLK_CFG[EXTRABIT]. */
491 uint64_t fsyncmissed : 1;
492 uint64_t fsyncextra : 1;
497 uint64_t txempty : 1;
499 uint64_t reserved_8_63 : 56;
502 struct cvmx_pcmx_int_ena_s cn30xx;
503 struct cvmx_pcmx_int_ena_s cn31xx;
504 struct cvmx_pcmx_int_ena_s cn50xx;
506 typedef union cvmx_pcmx_int_ena cvmx_pcmx_int_ena_t;
511 union cvmx_pcmx_int_sum
514 struct cvmx_pcmx_int_sum_s
516 #if __BYTE_ORDER == __BIG_ENDIAN
517 uint64_t reserved_8_63 : 56;
518 uint64_t rxovf : 1; /**< RX byte overflowed */
519 uint64_t txempty : 1; /**< TX byte was empty when sampled */
520 uint64_t txrd : 1; /**< DMA engine frame read interrupt occurred */
521 uint64_t txwrap : 1; /**< TX region wrap interrupt occurred */
522 uint64_t rxst : 1; /**< DMA engine frame store interrupt occurred */
523 uint64_t rxwrap : 1; /**< RX region wrap interrupt occurred */
524 uint64_t fsyncextra : 1; /**< FSYNC extra interrupt occurred */
525 uint64_t fsyncmissed : 1; /**< FSYNC missed interrupt occurred */
527 uint64_t fsyncmissed : 1;
528 uint64_t fsyncextra : 1;
533 uint64_t txempty : 1;
535 uint64_t reserved_8_63 : 56;
538 struct cvmx_pcmx_int_sum_s cn30xx;
539 struct cvmx_pcmx_int_sum_s cn31xx;
540 struct cvmx_pcmx_int_sum_s cn50xx;
542 typedef union cvmx_pcmx_int_sum cvmx_pcmx_int_sum_t;
547 union cvmx_pcmx_rxaddr
550 struct cvmx_pcmx_rxaddr_s
552 #if __BYTE_ORDER == __BIG_ENDIAN
553 uint64_t reserved_36_63 : 28;
554 uint64_t addr : 36; /**< Address of the next write to the receive memory
558 uint64_t reserved_36_63 : 28;
561 struct cvmx_pcmx_rxaddr_s cn30xx;
562 struct cvmx_pcmx_rxaddr_s cn31xx;
563 struct cvmx_pcmx_rxaddr_s cn50xx;
565 typedef union cvmx_pcmx_rxaddr cvmx_pcmx_rxaddr_t;
570 union cvmx_pcmx_rxcnt
573 struct cvmx_pcmx_rxcnt_s
575 #if __BYTE_ORDER == __BIG_ENDIAN
576 uint64_t reserved_16_63 : 48;
577 uint64_t cnt : 16; /**< Number of superframes in receive memory region */
580 uint64_t reserved_16_63 : 48;
583 struct cvmx_pcmx_rxcnt_s cn30xx;
584 struct cvmx_pcmx_rxcnt_s cn31xx;
585 struct cvmx_pcmx_rxcnt_s cn50xx;
587 typedef union cvmx_pcmx_rxcnt cvmx_pcmx_rxcnt_t;
592 union cvmx_pcmx_rxmsk0
595 struct cvmx_pcmx_rxmsk0_s
597 #if __BYTE_ORDER == __BIG_ENDIAN
598 uint64_t mask : 64; /**< Receive mask bits for slots 63 to 0
599 (1 means transmit, 0 means don't transmit) */
604 struct cvmx_pcmx_rxmsk0_s cn30xx;
605 struct cvmx_pcmx_rxmsk0_s cn31xx;
606 struct cvmx_pcmx_rxmsk0_s cn50xx;
608 typedef union cvmx_pcmx_rxmsk0 cvmx_pcmx_rxmsk0_t;
613 union cvmx_pcmx_rxmsk1
616 struct cvmx_pcmx_rxmsk1_s
618 #if __BYTE_ORDER == __BIG_ENDIAN
619 uint64_t mask : 64; /**< Receive mask bits for slots 127 to 64
620 (1 means transmit, 0 means don't transmit) */
625 struct cvmx_pcmx_rxmsk1_s cn30xx;
626 struct cvmx_pcmx_rxmsk1_s cn31xx;
627 struct cvmx_pcmx_rxmsk1_s cn50xx;
629 typedef union cvmx_pcmx_rxmsk1 cvmx_pcmx_rxmsk1_t;
634 union cvmx_pcmx_rxmsk2
637 struct cvmx_pcmx_rxmsk2_s
639 #if __BYTE_ORDER == __BIG_ENDIAN
640 uint64_t mask : 64; /**< Receive mask bits for slots 191 to 128
641 (1 means transmit, 0 means don't transmit) */
646 struct cvmx_pcmx_rxmsk2_s cn30xx;
647 struct cvmx_pcmx_rxmsk2_s cn31xx;
648 struct cvmx_pcmx_rxmsk2_s cn50xx;
650 typedef union cvmx_pcmx_rxmsk2 cvmx_pcmx_rxmsk2_t;
655 union cvmx_pcmx_rxmsk3
658 struct cvmx_pcmx_rxmsk3_s
660 #if __BYTE_ORDER == __BIG_ENDIAN
661 uint64_t mask : 64; /**< Receive mask bits for slots 255 to 192
662 (1 means transmit, 0 means don't transmit) */
667 struct cvmx_pcmx_rxmsk3_s cn30xx;
668 struct cvmx_pcmx_rxmsk3_s cn31xx;
669 struct cvmx_pcmx_rxmsk3_s cn50xx;
671 typedef union cvmx_pcmx_rxmsk3 cvmx_pcmx_rxmsk3_t;
676 union cvmx_pcmx_rxmsk4
679 struct cvmx_pcmx_rxmsk4_s
681 #if __BYTE_ORDER == __BIG_ENDIAN
682 uint64_t mask : 64; /**< Receive mask bits for slots 319 to 256
683 (1 means transmit, 0 means don't transmit) */
688 struct cvmx_pcmx_rxmsk4_s cn30xx;
689 struct cvmx_pcmx_rxmsk4_s cn31xx;
690 struct cvmx_pcmx_rxmsk4_s cn50xx;
692 typedef union cvmx_pcmx_rxmsk4 cvmx_pcmx_rxmsk4_t;
697 union cvmx_pcmx_rxmsk5
700 struct cvmx_pcmx_rxmsk5_s
702 #if __BYTE_ORDER == __BIG_ENDIAN
703 uint64_t mask : 64; /**< Receive mask bits for slots 383 to 320
704 (1 means transmit, 0 means don't transmit) */
709 struct cvmx_pcmx_rxmsk5_s cn30xx;
710 struct cvmx_pcmx_rxmsk5_s cn31xx;
711 struct cvmx_pcmx_rxmsk5_s cn50xx;
713 typedef union cvmx_pcmx_rxmsk5 cvmx_pcmx_rxmsk5_t;
718 union cvmx_pcmx_rxmsk6
721 struct cvmx_pcmx_rxmsk6_s
723 #if __BYTE_ORDER == __BIG_ENDIAN
724 uint64_t mask : 64; /**< Receive mask bits for slots 447 to 384
725 (1 means transmit, 0 means don't transmit) */
730 struct cvmx_pcmx_rxmsk6_s cn30xx;
731 struct cvmx_pcmx_rxmsk6_s cn31xx;
732 struct cvmx_pcmx_rxmsk6_s cn50xx;
734 typedef union cvmx_pcmx_rxmsk6 cvmx_pcmx_rxmsk6_t;
739 union cvmx_pcmx_rxmsk7
742 struct cvmx_pcmx_rxmsk7_s
744 #if __BYTE_ORDER == __BIG_ENDIAN
745 uint64_t mask : 64; /**< Receive mask bits for slots 511 to 448
746 (1 means transmit, 0 means don't transmit) */
751 struct cvmx_pcmx_rxmsk7_s cn30xx;
752 struct cvmx_pcmx_rxmsk7_s cn31xx;
753 struct cvmx_pcmx_rxmsk7_s cn50xx;
755 typedef union cvmx_pcmx_rxmsk7 cvmx_pcmx_rxmsk7_t;
760 union cvmx_pcmx_rxstart
763 struct cvmx_pcmx_rxstart_s
765 #if __BYTE_ORDER == __BIG_ENDIAN
766 uint64_t reserved_36_63 : 28;
767 uint64_t addr : 33; /**< Starting address for the receive memory region */
768 uint64_t reserved_0_2 : 3;
770 uint64_t reserved_0_2 : 3;
772 uint64_t reserved_36_63 : 28;
775 struct cvmx_pcmx_rxstart_s cn30xx;
776 struct cvmx_pcmx_rxstart_s cn31xx;
777 struct cvmx_pcmx_rxstart_s cn50xx;
779 typedef union cvmx_pcmx_rxstart cvmx_pcmx_rxstart_t;
784 union cvmx_pcmx_tdm_cfg
787 struct cvmx_pcmx_tdm_cfg_s
789 #if __BYTE_ORDER == __BIG_ENDIAN
790 uint64_t drvtim : 16; /**< Number of ECLKs from start of bit time to stop
791 driving last bit of timeslot (if not driving next
793 uint64_t samppt : 16; /**< Number of ECLKs from start of bit time to sample
795 uint64_t reserved_3_31 : 29;
796 uint64_t lsbfirst : 1; /**< If 0, shift/receive MSB first
797 1, shift/receive LSB first */
798 uint64_t useclk1 : 1; /**< If 0, this PCM is based on BCLK/FSYNC0
799 1, this PCM is based on BCLK/FSYNC1 */
800 uint64_t enable : 1; /**< If 1, PCM is enabled, otherwise pins are GPIOs
801 NOTE: when TDM is disabled by detection of an
802 FSYNC error all transmission and reception is
803 halted. In addition, PCMn_TX/RXADDR are updated
804 to point to the position at which the error was
808 uint64_t useclk1 : 1;
809 uint64_t lsbfirst : 1;
810 uint64_t reserved_3_31 : 29;
811 uint64_t samppt : 16;
812 uint64_t drvtim : 16;
815 struct cvmx_pcmx_tdm_cfg_s cn30xx;
816 struct cvmx_pcmx_tdm_cfg_s cn31xx;
817 struct cvmx_pcmx_tdm_cfg_s cn50xx;
819 typedef union cvmx_pcmx_tdm_cfg cvmx_pcmx_tdm_cfg_t;
824 union cvmx_pcmx_tdm_dbg
827 struct cvmx_pcmx_tdm_dbg_s
829 #if __BYTE_ORDER == __BIG_ENDIAN
830 uint64_t debuginfo : 64; /**< Miscellaneous debug information */
832 uint64_t debuginfo : 64;
835 struct cvmx_pcmx_tdm_dbg_s cn30xx;
836 struct cvmx_pcmx_tdm_dbg_s cn31xx;
837 struct cvmx_pcmx_tdm_dbg_s cn50xx;
839 typedef union cvmx_pcmx_tdm_dbg cvmx_pcmx_tdm_dbg_t;
844 union cvmx_pcmx_txaddr
847 struct cvmx_pcmx_txaddr_s
849 #if __BYTE_ORDER == __BIG_ENDIAN
850 uint64_t reserved_36_63 : 28;
851 uint64_t addr : 33; /**< Address of the next read from the transmit memory
853 uint64_t fram : 3; /**< Frame offset
854 NOTE: this is used to extract the correct byte from
855 each 64b word read from the transmit memory region */
859 uint64_t reserved_36_63 : 28;
862 struct cvmx_pcmx_txaddr_s cn30xx;
863 struct cvmx_pcmx_txaddr_s cn31xx;
864 struct cvmx_pcmx_txaddr_s cn50xx;
866 typedef union cvmx_pcmx_txaddr cvmx_pcmx_txaddr_t;
871 union cvmx_pcmx_txcnt
874 struct cvmx_pcmx_txcnt_s
876 #if __BYTE_ORDER == __BIG_ENDIAN
877 uint64_t reserved_16_63 : 48;
878 uint64_t cnt : 16; /**< Number of superframes in transmit memory region */
881 uint64_t reserved_16_63 : 48;
884 struct cvmx_pcmx_txcnt_s cn30xx;
885 struct cvmx_pcmx_txcnt_s cn31xx;
886 struct cvmx_pcmx_txcnt_s cn50xx;
888 typedef union cvmx_pcmx_txcnt cvmx_pcmx_txcnt_t;
893 union cvmx_pcmx_txmsk0
896 struct cvmx_pcmx_txmsk0_s
898 #if __BYTE_ORDER == __BIG_ENDIAN
899 uint64_t mask : 64; /**< Transmit mask bits for slots 63 to 0
900 (1 means transmit, 0 means don't transmit) */
905 struct cvmx_pcmx_txmsk0_s cn30xx;
906 struct cvmx_pcmx_txmsk0_s cn31xx;
907 struct cvmx_pcmx_txmsk0_s cn50xx;
909 typedef union cvmx_pcmx_txmsk0 cvmx_pcmx_txmsk0_t;
914 union cvmx_pcmx_txmsk1
917 struct cvmx_pcmx_txmsk1_s
919 #if __BYTE_ORDER == __BIG_ENDIAN
920 uint64_t mask : 64; /**< Transmit mask bits for slots 127 to 64
921 (1 means transmit, 0 means don't transmit) */
926 struct cvmx_pcmx_txmsk1_s cn30xx;
927 struct cvmx_pcmx_txmsk1_s cn31xx;
928 struct cvmx_pcmx_txmsk1_s cn50xx;
930 typedef union cvmx_pcmx_txmsk1 cvmx_pcmx_txmsk1_t;
935 union cvmx_pcmx_txmsk2
938 struct cvmx_pcmx_txmsk2_s
940 #if __BYTE_ORDER == __BIG_ENDIAN
941 uint64_t mask : 64; /**< Transmit mask bits for slots 191 to 128
942 (1 means transmit, 0 means don't transmit) */
947 struct cvmx_pcmx_txmsk2_s cn30xx;
948 struct cvmx_pcmx_txmsk2_s cn31xx;
949 struct cvmx_pcmx_txmsk2_s cn50xx;
951 typedef union cvmx_pcmx_txmsk2 cvmx_pcmx_txmsk2_t;
956 union cvmx_pcmx_txmsk3
959 struct cvmx_pcmx_txmsk3_s
961 #if __BYTE_ORDER == __BIG_ENDIAN
962 uint64_t mask : 64; /**< Transmit mask bits for slots 255 to 192
963 (1 means transmit, 0 means don't transmit) */
968 struct cvmx_pcmx_txmsk3_s cn30xx;
969 struct cvmx_pcmx_txmsk3_s cn31xx;
970 struct cvmx_pcmx_txmsk3_s cn50xx;
972 typedef union cvmx_pcmx_txmsk3 cvmx_pcmx_txmsk3_t;
977 union cvmx_pcmx_txmsk4
980 struct cvmx_pcmx_txmsk4_s
982 #if __BYTE_ORDER == __BIG_ENDIAN
983 uint64_t mask : 64; /**< Transmit mask bits for slots 319 to 256
984 (1 means transmit, 0 means don't transmit) */
989 struct cvmx_pcmx_txmsk4_s cn30xx;
990 struct cvmx_pcmx_txmsk4_s cn31xx;
991 struct cvmx_pcmx_txmsk4_s cn50xx;
993 typedef union cvmx_pcmx_txmsk4 cvmx_pcmx_txmsk4_t;
998 union cvmx_pcmx_txmsk5
1001 struct cvmx_pcmx_txmsk5_s
1003 #if __BYTE_ORDER == __BIG_ENDIAN
1004 uint64_t mask : 64; /**< Transmit mask bits for slots 383 to 320
1005 (1 means transmit, 0 means don't transmit) */
1010 struct cvmx_pcmx_txmsk5_s cn30xx;
1011 struct cvmx_pcmx_txmsk5_s cn31xx;
1012 struct cvmx_pcmx_txmsk5_s cn50xx;
1014 typedef union cvmx_pcmx_txmsk5 cvmx_pcmx_txmsk5_t;
1019 union cvmx_pcmx_txmsk6
1022 struct cvmx_pcmx_txmsk6_s
1024 #if __BYTE_ORDER == __BIG_ENDIAN
1025 uint64_t mask : 64; /**< Transmit mask bits for slots 447 to 384
1026 (1 means transmit, 0 means don't transmit) */
1031 struct cvmx_pcmx_txmsk6_s cn30xx;
1032 struct cvmx_pcmx_txmsk6_s cn31xx;
1033 struct cvmx_pcmx_txmsk6_s cn50xx;
1035 typedef union cvmx_pcmx_txmsk6 cvmx_pcmx_txmsk6_t;
1040 union cvmx_pcmx_txmsk7
1043 struct cvmx_pcmx_txmsk7_s
1045 #if __BYTE_ORDER == __BIG_ENDIAN
1046 uint64_t mask : 64; /**< Transmit mask bits for slots 511 to 448
1047 (1 means transmit, 0 means don't transmit) */
1052 struct cvmx_pcmx_txmsk7_s cn30xx;
1053 struct cvmx_pcmx_txmsk7_s cn31xx;
1054 struct cvmx_pcmx_txmsk7_s cn50xx;
1056 typedef union cvmx_pcmx_txmsk7 cvmx_pcmx_txmsk7_t;
1061 union cvmx_pcmx_txstart
1064 struct cvmx_pcmx_txstart_s
1066 #if __BYTE_ORDER == __BIG_ENDIAN
1067 uint64_t reserved_36_63 : 28;
1068 uint64_t addr : 33; /**< Starting address for the transmit memory region */
1069 uint64_t reserved_0_2 : 3;
1071 uint64_t reserved_0_2 : 3;
1073 uint64_t reserved_36_63 : 28;
1076 struct cvmx_pcmx_txstart_s cn30xx;
1077 struct cvmx_pcmx_txstart_s cn31xx;
1078 struct cvmx_pcmx_txstart_s cn50xx;
1080 typedef union cvmx_pcmx_txstart cvmx_pcmx_txstart_t;