1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_PESCX_TYPEDEFS_H__
53 #define __CVMX_PESCX_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_PESCX_BIST_STATUS(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
61 cvmx_warn("CVMX_PESCX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
62 return CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
67 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
68 static inline uint64_t CVMX_PESCX_BIST_STATUS2(unsigned long block_id)
71 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
72 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
73 cvmx_warn("CVMX_PESCX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id);
74 return CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
79 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
80 static inline uint64_t CVMX_PESCX_CFG_RD(unsigned long block_id)
83 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
84 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
85 cvmx_warn("CVMX_PESCX_CFG_RD(%lu) is invalid on this chip\n", block_id);
86 return CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull;
89 #define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
91 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
92 static inline uint64_t CVMX_PESCX_CFG_WR(unsigned long block_id)
95 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
96 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
97 cvmx_warn("CVMX_PESCX_CFG_WR(%lu) is invalid on this chip\n", block_id);
98 return CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
103 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
104 static inline uint64_t CVMX_PESCX_CPL_LUT_VALID(unsigned long block_id)
107 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
108 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
109 cvmx_warn("CVMX_PESCX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id);
110 return CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
115 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
116 static inline uint64_t CVMX_PESCX_CTL_STATUS(unsigned long block_id)
119 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
121 cvmx_warn("CVMX_PESCX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
122 return CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull;
125 #define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
127 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
128 static inline uint64_t CVMX_PESCX_CTL_STATUS2(unsigned long block_id)
131 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
132 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
133 cvmx_warn("CVMX_PESCX_CTL_STATUS2(%lu) is invalid on this chip\n", block_id);
134 return CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull;
137 #define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
139 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
140 static inline uint64_t CVMX_PESCX_DBG_INFO(unsigned long block_id)
143 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
144 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
145 cvmx_warn("CVMX_PESCX_DBG_INFO(%lu) is invalid on this chip\n", block_id);
146 return CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull;
149 #define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
151 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
152 static inline uint64_t CVMX_PESCX_DBG_INFO_EN(unsigned long block_id)
155 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
156 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
157 cvmx_warn("CVMX_PESCX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id);
158 return CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull;
161 #define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
163 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
164 static inline uint64_t CVMX_PESCX_DIAG_STATUS(unsigned long block_id)
167 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
168 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
169 cvmx_warn("CVMX_PESCX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id);
170 return CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull;
173 #define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
175 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
176 static inline uint64_t CVMX_PESCX_P2N_BAR0_START(unsigned long block_id)
179 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
181 cvmx_warn("CVMX_PESCX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id);
182 return CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull;
185 #define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
188 static inline uint64_t CVMX_PESCX_P2N_BAR1_START(unsigned long block_id)
191 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
192 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
193 cvmx_warn("CVMX_PESCX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id);
194 return CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull;
197 #define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
200 static inline uint64_t CVMX_PESCX_P2N_BAR2_START(unsigned long block_id)
203 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
204 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
205 cvmx_warn("CVMX_PESCX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id);
206 return CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull;
209 #define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
212 static inline uint64_t CVMX_PESCX_P2P_BARX_END(unsigned long offset, unsigned long block_id)
215 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
216 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1))))))
217 cvmx_warn("CVMX_PESCX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id);
218 return CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16;
221 #define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
223 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
224 static inline uint64_t CVMX_PESCX_P2P_BARX_START(unsigned long offset, unsigned long block_id)
227 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
228 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1))))))
229 cvmx_warn("CVMX_PESCX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id);
230 return CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16;
233 #define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
235 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
236 static inline uint64_t CVMX_PESCX_TLP_CREDITS(unsigned long block_id)
239 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
241 cvmx_warn("CVMX_PESCX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
242 return CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull;
245 #define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
249 * cvmx_pesc#_bist_status
251 * PESC_BIST_STATUS = PESC Bist Status
253 * Contains the diffrent interrupt summary bits of the PESC.
255 union cvmx_pescx_bist_status
258 struct cvmx_pescx_bist_status_s
260 #if __BYTE_ORDER == __BIG_ENDIAN
261 uint64_t reserved_13_63 : 51;
262 uint64_t rqdata5 : 1; /**< Rx Queue Data Memory5. */
263 uint64_t ctlp_or : 1; /**< C-TLP Order Fifo. */
264 uint64_t ntlp_or : 1; /**< N-TLP Order Fifo. */
265 uint64_t ptlp_or : 1; /**< P-TLP Order Fifo. */
266 uint64_t retry : 1; /**< Retry Buffer. */
267 uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */
268 uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */
269 uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */
270 uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */
271 uint64_t rqdata4 : 1; /**< Rx Queue Data Memory4. */
272 uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */
273 uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */
274 uint64_t sot : 1; /**< SOT Buffer. */
279 uint64_t rqdata4 : 1;
280 uint64_t rqdata3 : 1;
281 uint64_t rqdata2 : 1;
282 uint64_t rqdata1 : 1;
283 uint64_t rqdata0 : 1;
285 uint64_t ptlp_or : 1;
286 uint64_t ntlp_or : 1;
287 uint64_t ctlp_or : 1;
288 uint64_t rqdata5 : 1;
289 uint64_t reserved_13_63 : 51;
292 struct cvmx_pescx_bist_status_s cn52xx;
293 struct cvmx_pescx_bist_status_cn52xxp1
295 #if __BYTE_ORDER == __BIG_ENDIAN
296 uint64_t reserved_12_63 : 52;
297 uint64_t ctlp_or : 1; /**< C-TLP Order Fifo. */
298 uint64_t ntlp_or : 1; /**< N-TLP Order Fifo. */
299 uint64_t ptlp_or : 1; /**< P-TLP Order Fifo. */
300 uint64_t retry : 1; /**< Retry Buffer. */
301 uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */
302 uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */
303 uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */
304 uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */
305 uint64_t rqdata4 : 1; /**< Rx Queue Data Memory4. */
306 uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */
307 uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */
308 uint64_t sot : 1; /**< SOT Buffer. */
313 uint64_t rqdata4 : 1;
314 uint64_t rqdata3 : 1;
315 uint64_t rqdata2 : 1;
316 uint64_t rqdata1 : 1;
317 uint64_t rqdata0 : 1;
319 uint64_t ptlp_or : 1;
320 uint64_t ntlp_or : 1;
321 uint64_t ctlp_or : 1;
322 uint64_t reserved_12_63 : 52;
325 struct cvmx_pescx_bist_status_s cn56xx;
326 struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
328 typedef union cvmx_pescx_bist_status cvmx_pescx_bist_status_t;
331 * cvmx_pesc#_bist_status2
333 * PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register
335 * Results from BIST runs of PESC's memories.
337 union cvmx_pescx_bist_status2
340 struct cvmx_pescx_bist_status2_s
342 #if __BYTE_ORDER == __BIG_ENDIAN
343 uint64_t reserved_14_63 : 50;
344 uint64_t cto_p2e : 1; /**< BIST Status for the cto_p2e_fifo */
345 uint64_t e2p_cpl : 1; /**< BIST Status for the e2p_cpl_fifo */
346 uint64_t e2p_n : 1; /**< BIST Status for the e2p_n_fifo */
347 uint64_t e2p_p : 1; /**< BIST Status for the e2p_p_fifo */
348 uint64_t e2p_rsl : 1; /**< BIST Status for the e2p_rsl__fifo */
349 uint64_t dbg_p2e : 1; /**< BIST Status for the dbg_p2e_fifo */
350 uint64_t peai_p2e : 1; /**< BIST Status for the peai__pesc_fifo */
351 uint64_t rsl_p2e : 1; /**< BIST Status for the rsl_p2e_fifo */
352 uint64_t pef_tpf1 : 1; /**< BIST Status for the pef_tlp_p_fifo1 */
353 uint64_t pef_tpf0 : 1; /**< BIST Status for the pef_tlp_p_fifo0 */
354 uint64_t pef_tnf : 1; /**< BIST Status for the pef_tlp_n_fifo */
355 uint64_t pef_tcf1 : 1; /**< BIST Status for the pef_tlp_cpl_fifo1 */
356 uint64_t pef_tc0 : 1; /**< BIST Status for the pef_tlp_cpl_fifo0 */
357 uint64_t ppf : 1; /**< BIST Status for the ppf_fifo */
360 uint64_t pef_tc0 : 1;
361 uint64_t pef_tcf1 : 1;
362 uint64_t pef_tnf : 1;
363 uint64_t pef_tpf0 : 1;
364 uint64_t pef_tpf1 : 1;
365 uint64_t rsl_p2e : 1;
366 uint64_t peai_p2e : 1;
367 uint64_t dbg_p2e : 1;
368 uint64_t e2p_rsl : 1;
371 uint64_t e2p_cpl : 1;
372 uint64_t cto_p2e : 1;
373 uint64_t reserved_14_63 : 50;
376 struct cvmx_pescx_bist_status2_s cn52xx;
377 struct cvmx_pescx_bist_status2_s cn52xxp1;
378 struct cvmx_pescx_bist_status2_s cn56xx;
379 struct cvmx_pescx_bist_status2_s cn56xxp1;
381 typedef union cvmx_pescx_bist_status2 cvmx_pescx_bist_status2_t;
386 * PESC_CFG_RD = PESC Configuration Read
388 * Allows read access to the configuration in the PCIe Core.
390 union cvmx_pescx_cfg_rd
393 struct cvmx_pescx_cfg_rd_s
395 #if __BYTE_ORDER == __BIG_ENDIAN
396 uint64_t data : 32; /**< Data. */
397 uint64_t addr : 32; /**< Address to read. A write to this register
398 starts a read operation. */
404 struct cvmx_pescx_cfg_rd_s cn52xx;
405 struct cvmx_pescx_cfg_rd_s cn52xxp1;
406 struct cvmx_pescx_cfg_rd_s cn56xx;
407 struct cvmx_pescx_cfg_rd_s cn56xxp1;
409 typedef union cvmx_pescx_cfg_rd cvmx_pescx_cfg_rd_t;
414 * PESC_CFG_WR = PESC Configuration Write
416 * Allows write access to the configuration in the PCIe Core.
418 union cvmx_pescx_cfg_wr
421 struct cvmx_pescx_cfg_wr_s
423 #if __BYTE_ORDER == __BIG_ENDIAN
424 uint64_t data : 32; /**< Data to write. A write to this register starts
425 a write operation. */
426 uint64_t addr : 32; /**< Address to write. A write to this register starts
427 a write operation. */
433 struct cvmx_pescx_cfg_wr_s cn52xx;
434 struct cvmx_pescx_cfg_wr_s cn52xxp1;
435 struct cvmx_pescx_cfg_wr_s cn56xx;
436 struct cvmx_pescx_cfg_wr_s cn56xxp1;
438 typedef union cvmx_pescx_cfg_wr cvmx_pescx_cfg_wr_t;
441 * cvmx_pesc#_cpl_lut_valid
443 * PESC_CPL_LUT_VALID = PESC Cmpletion Lookup Table Valid
445 * Bit set for outstanding tag read.
447 union cvmx_pescx_cpl_lut_valid
450 struct cvmx_pescx_cpl_lut_valid_s
452 #if __BYTE_ORDER == __BIG_ENDIAN
453 uint64_t reserved_32_63 : 32;
454 uint64_t tag : 32; /**< Bit vector set cooresponds to an outstanding tag
455 expecting a completion. */
458 uint64_t reserved_32_63 : 32;
461 struct cvmx_pescx_cpl_lut_valid_s cn52xx;
462 struct cvmx_pescx_cpl_lut_valid_s cn52xxp1;
463 struct cvmx_pescx_cpl_lut_valid_s cn56xx;
464 struct cvmx_pescx_cpl_lut_valid_s cn56xxp1;
466 typedef union cvmx_pescx_cpl_lut_valid cvmx_pescx_cpl_lut_valid_t;
469 * cvmx_pesc#_ctl_status
471 * PESC_CTL_STATUS = PESC Control Status
473 * General control and status of the PESC.
475 union cvmx_pescx_ctl_status
478 struct cvmx_pescx_ctl_status_s
480 #if __BYTE_ORDER == __BIG_ENDIAN
481 uint64_t reserved_28_63 : 36;
482 uint64_t dnum : 5; /**< Primary bus device number. */
483 uint64_t pbus : 8; /**< Primary bus number. */
484 uint64_t qlm_cfg : 2; /**< The QLM configuration pad bits. */
485 uint64_t lane_swp : 1; /**< Lane Swap. For PEDC1, when 0 NO LANE SWAP when '1'
486 enables LANE SWAP. THis bit has no effect on PEDC0.
487 This bit should be set before enabling PEDC1. */
488 uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is
489 to the PCIe core pm_xmt_turnoff port. RC mode. */
490 uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is
491 to the PCIe core pm_xmt_pme port. EP mode. */
492 uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is
493 to the PCIe core outband_pwrup_cmd port. EP mode. */
494 uint64_t reserved_7_8 : 2;
495 uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */
496 uint64_t dly_one : 1; /**< When set the output client state machines will
497 wait one cycle before starting a new TLP out. */
498 uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the
499 link is disabled. This bit only is active when in
501 uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will
502 not wait for P-TLPs that normaly would be sent
504 uint64_t reserved_2_2 : 1;
505 uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */
506 uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */
508 uint64_t inv_lcrc : 1;
509 uint64_t inv_ecrc : 1;
510 uint64_t reserved_2_2 : 1;
511 uint64_t ro_ctlp : 1;
512 uint64_t lnk_enb : 1;
513 uint64_t dly_one : 1;
514 uint64_t nf_ecrc : 1;
515 uint64_t reserved_7_8 : 2;
516 uint64_t ob_p_cmd : 1;
517 uint64_t pm_xpme : 1;
518 uint64_t pm_xtoff : 1;
519 uint64_t lane_swp : 1;
520 uint64_t qlm_cfg : 2;
523 uint64_t reserved_28_63 : 36;
526 struct cvmx_pescx_ctl_status_s cn52xx;
527 struct cvmx_pescx_ctl_status_s cn52xxp1;
528 struct cvmx_pescx_ctl_status_cn56xx
530 #if __BYTE_ORDER == __BIG_ENDIAN
531 uint64_t reserved_28_63 : 36;
532 uint64_t dnum : 5; /**< Primary bus device number. */
533 uint64_t pbus : 8; /**< Primary bus number. */
534 uint64_t qlm_cfg : 2; /**< The QLM configuration pad bits. */
535 uint64_t reserved_12_12 : 1;
536 uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is
537 to the PCIe core pm_xmt_turnoff port. RC mode. */
538 uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is
539 to the PCIe core pm_xmt_pme port. EP mode. */
540 uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is
541 to the PCIe core outband_pwrup_cmd port. EP mode. */
542 uint64_t reserved_7_8 : 2;
543 uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */
544 uint64_t dly_one : 1; /**< When set the output client state machines will
545 wait one cycle before starting a new TLP out. */
546 uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the
547 link is disabled. This bit only is active when in
549 uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will
550 not wait for P-TLPs that normaly would be sent
552 uint64_t reserved_2_2 : 1;
553 uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */
554 uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */
556 uint64_t inv_lcrc : 1;
557 uint64_t inv_ecrc : 1;
558 uint64_t reserved_2_2 : 1;
559 uint64_t ro_ctlp : 1;
560 uint64_t lnk_enb : 1;
561 uint64_t dly_one : 1;
562 uint64_t nf_ecrc : 1;
563 uint64_t reserved_7_8 : 2;
564 uint64_t ob_p_cmd : 1;
565 uint64_t pm_xpme : 1;
566 uint64_t pm_xtoff : 1;
567 uint64_t reserved_12_12 : 1;
568 uint64_t qlm_cfg : 2;
571 uint64_t reserved_28_63 : 36;
574 struct cvmx_pescx_ctl_status_cn56xx cn56xxp1;
576 typedef union cvmx_pescx_ctl_status cvmx_pescx_ctl_status_t;
579 * cvmx_pesc#_ctl_status2
583 * PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register
585 * Results from BIST runs of PESC's memories.
587 union cvmx_pescx_ctl_status2
590 struct cvmx_pescx_ctl_status2_s
592 #if __BYTE_ORDER == __BIG_ENDIAN
593 uint64_t reserved_2_63 : 62;
594 uint64_t pclk_run : 1; /**< When the pce_clk is running this bit will be '1'.
595 Writing a '1' to this location will cause the
596 bit to be cleared, but if the pce_clk is running
597 this bit will be re-set. */
598 uint64_t pcierst : 1; /**< Set to '1' when PCIe is in reset. */
600 uint64_t pcierst : 1;
601 uint64_t pclk_run : 1;
602 uint64_t reserved_2_63 : 62;
605 struct cvmx_pescx_ctl_status2_s cn52xx;
606 struct cvmx_pescx_ctl_status2_cn52xxp1
608 #if __BYTE_ORDER == __BIG_ENDIAN
609 uint64_t reserved_1_63 : 63;
610 uint64_t pcierst : 1; /**< Set to '1' when PCIe is in reset. */
612 uint64_t pcierst : 1;
613 uint64_t reserved_1_63 : 63;
616 struct cvmx_pescx_ctl_status2_s cn56xx;
617 struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
619 typedef union cvmx_pescx_ctl_status2 cvmx_pescx_ctl_status2_t;
622 * cvmx_pesc#_dbg_info
624 * PESC(0..1)_DBG_INFO = PESC Debug Information
626 * General debug info.
628 union cvmx_pescx_dbg_info
631 struct cvmx_pescx_dbg_info_s
633 #if __BYTE_ORDER == __BIG_ENDIAN
634 uint64_t reserved_31_63 : 33;
635 uint64_t ecrc_e : 1; /**< Received a ECRC error.
637 uint64_t rawwpp : 1; /**< Received a write with poisoned payload
638 radm_rcvd_wreq_poisoned */
639 uint64_t racpp : 1; /**< Received a completion with poisoned payload
640 radm_rcvd_cpl_poisoned */
641 uint64_t ramtlp : 1; /**< Received a malformed TLP
643 uint64_t rarwdns : 1; /**< Recieved a request which device does not support
645 uint64_t caar : 1; /**< Completer aborted a request
647 This bit will never be set because Octeon does
648 not generate Completer Aborts. */
649 uint64_t racca : 1; /**< Received a completion with CA status
651 uint64_t racur : 1; /**< Received a completion with UR status
653 uint64_t rauc : 1; /**< Received an unexpected completion
654 radm_unexp_cpl_err */
655 uint64_t rqo : 1; /**< Receive queue overflow. Normally happens only when
656 flow control advertisements are ignored
658 uint64_t fcuv : 1; /**< Flow Control Update Violation (opt. checks)
659 int_xadm_fc_prot_err */
660 uint64_t rpe : 1; /**< When the PHY reports 8B/10B decode error
661 (RxStatus = 3b100) or disparity error
662 (RxStatus = 3b111), the signal rmlh_rcvd_err will
665 uint64_t fcpvwt : 1; /**< Flow Control Protocol Violation (Watchdog Timer)
667 uint64_t dpeoosd : 1; /**< DLLP protocol error (out of sequence DLLP)
669 uint64_t rtwdle : 1; /**< Received TLP with DataLink Layer Error
671 uint64_t rdwdle : 1; /**< Received DLLP with DataLink Layer Error
673 uint64_t mre : 1; /**< Max Retries Exceeded
674 xdlh_replay_num_rlover_err */
675 uint64_t rte : 1; /**< Replay Timer Expired
676 xdlh_replay_timeout_err
677 This bit is set when the REPLAY_TIMER expires in
678 the PCIE core. The probability of this bit being
679 set will increase with the traffic load. */
680 uint64_t acto : 1; /**< A Completion Timeout Occured
681 pedc_radm_cpl_timeout */
682 uint64_t rvdm : 1; /**< Received Vendor-Defined Message
683 pedc_radm_vendor_msg */
684 uint64_t rumep : 1; /**< Received Unlock Message (EP Mode Only)
685 pedc_radm_msg_unlock */
686 uint64_t rptamrc : 1; /**< Received PME Turnoff Acknowledge Message
688 pedc_radm_pm_to_ack */
689 uint64_t rpmerc : 1; /**< Received PME Message (RC Mode only)
691 uint64_t rfemrc : 1; /**< Received Fatal Error Message (RC Mode only)
693 Bit set when a message with ERR_FATAL is set. */
694 uint64_t rnfemrc : 1; /**< Received Non-Fatal Error Message (RC Mode only)
695 pedc_radm_nonfatal_err */
696 uint64_t rcemrc : 1; /**< Received Correctable Error Message (RC Mode only)
697 pedc_radm_correctable_err */
698 uint64_t rpoison : 1; /**< Received Poisoned TLP
699 pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */
700 uint64_t recrce : 1; /**< Received ECRC Error
701 pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */
702 uint64_t rtlplle : 1; /**< Received TLP has link layer error
703 pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */
704 uint64_t rtlpmal : 1; /**< Received TLP is malformed or a message.
705 pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot
706 If the core receives a MSG (or Vendor Message)
707 this bit will be set. */
708 uint64_t spoison : 1; /**< Poisoned TLP sent
709 peai__client0_tlp_ep & peai__client0_tlp_hv */
711 uint64_t spoison : 1;
712 uint64_t rtlpmal : 1;
713 uint64_t rtlplle : 1;
715 uint64_t rpoison : 1;
717 uint64_t rnfemrc : 1;
720 uint64_t rptamrc : 1;
728 uint64_t dpeoosd : 1;
737 uint64_t rarwdns : 1;
742 uint64_t reserved_31_63 : 33;
745 struct cvmx_pescx_dbg_info_s cn52xx;
746 struct cvmx_pescx_dbg_info_s cn52xxp1;
747 struct cvmx_pescx_dbg_info_s cn56xx;
748 struct cvmx_pescx_dbg_info_s cn56xxp1;
750 typedef union cvmx_pescx_dbg_info cvmx_pescx_dbg_info_t;
753 * cvmx_pesc#_dbg_info_en
755 * PESC(0..1)_DBG_INFO_EN = PESC Debug Information Enable
757 * Allows PESC_DBG_INFO to generate interrupts when cooresponding enable bit is set.
759 union cvmx_pescx_dbg_info_en
762 struct cvmx_pescx_dbg_info_en_s
764 #if __BYTE_ORDER == __BIG_ENDIAN
765 uint64_t reserved_31_63 : 33;
766 uint64_t ecrc_e : 1; /**< Allows PESC_DBG_INFO[30] to generate an interrupt. */
767 uint64_t rawwpp : 1; /**< Allows PESC_DBG_INFO[29] to generate an interrupt. */
768 uint64_t racpp : 1; /**< Allows PESC_DBG_INFO[28] to generate an interrupt. */
769 uint64_t ramtlp : 1; /**< Allows PESC_DBG_INFO[27] to generate an interrupt. */
770 uint64_t rarwdns : 1; /**< Allows PESC_DBG_INFO[26] to generate an interrupt. */
771 uint64_t caar : 1; /**< Allows PESC_DBG_INFO[25] to generate an interrupt. */
772 uint64_t racca : 1; /**< Allows PESC_DBG_INFO[24] to generate an interrupt. */
773 uint64_t racur : 1; /**< Allows PESC_DBG_INFO[23] to generate an interrupt. */
774 uint64_t rauc : 1; /**< Allows PESC_DBG_INFO[22] to generate an interrupt. */
775 uint64_t rqo : 1; /**< Allows PESC_DBG_INFO[21] to generate an interrupt. */
776 uint64_t fcuv : 1; /**< Allows PESC_DBG_INFO[20] to generate an interrupt. */
777 uint64_t rpe : 1; /**< Allows PESC_DBG_INFO[19] to generate an interrupt. */
778 uint64_t fcpvwt : 1; /**< Allows PESC_DBG_INFO[18] to generate an interrupt. */
779 uint64_t dpeoosd : 1; /**< Allows PESC_DBG_INFO[17] to generate an interrupt. */
780 uint64_t rtwdle : 1; /**< Allows PESC_DBG_INFO[16] to generate an interrupt. */
781 uint64_t rdwdle : 1; /**< Allows PESC_DBG_INFO[15] to generate an interrupt. */
782 uint64_t mre : 1; /**< Allows PESC_DBG_INFO[14] to generate an interrupt. */
783 uint64_t rte : 1; /**< Allows PESC_DBG_INFO[13] to generate an interrupt. */
784 uint64_t acto : 1; /**< Allows PESC_DBG_INFO[12] to generate an interrupt. */
785 uint64_t rvdm : 1; /**< Allows PESC_DBG_INFO[11] to generate an interrupt. */
786 uint64_t rumep : 1; /**< Allows PESC_DBG_INFO[10] to generate an interrupt. */
787 uint64_t rptamrc : 1; /**< Allows PESC_DBG_INFO[9] to generate an interrupt. */
788 uint64_t rpmerc : 1; /**< Allows PESC_DBG_INFO[8] to generate an interrupt. */
789 uint64_t rfemrc : 1; /**< Allows PESC_DBG_INFO[7] to generate an interrupt. */
790 uint64_t rnfemrc : 1; /**< Allows PESC_DBG_INFO[6] to generate an interrupt. */
791 uint64_t rcemrc : 1; /**< Allows PESC_DBG_INFO[5] to generate an interrupt. */
792 uint64_t rpoison : 1; /**< Allows PESC_DBG_INFO[4] to generate an interrupt. */
793 uint64_t recrce : 1; /**< Allows PESC_DBG_INFO[3] to generate an interrupt. */
794 uint64_t rtlplle : 1; /**< Allows PESC_DBG_INFO[2] to generate an interrupt. */
795 uint64_t rtlpmal : 1; /**< Allows PESC_DBG_INFO[1] to generate an interrupt. */
796 uint64_t spoison : 1; /**< Allows PESC_DBG_INFO[0] to generate an interrupt. */
798 uint64_t spoison : 1;
799 uint64_t rtlpmal : 1;
800 uint64_t rtlplle : 1;
802 uint64_t rpoison : 1;
804 uint64_t rnfemrc : 1;
807 uint64_t rptamrc : 1;
815 uint64_t dpeoosd : 1;
824 uint64_t rarwdns : 1;
829 uint64_t reserved_31_63 : 33;
832 struct cvmx_pescx_dbg_info_en_s cn52xx;
833 struct cvmx_pescx_dbg_info_en_s cn52xxp1;
834 struct cvmx_pescx_dbg_info_en_s cn56xx;
835 struct cvmx_pescx_dbg_info_en_s cn56xxp1;
837 typedef union cvmx_pescx_dbg_info_en cvmx_pescx_dbg_info_en_t;
840 * cvmx_pesc#_diag_status
842 * PESC_DIAG_STATUS = PESC Diagnostic Status
844 * Selection control for the cores diagnostic bus.
846 union cvmx_pescx_diag_status
849 struct cvmx_pescx_diag_status_s
851 #if __BYTE_ORDER == __BIG_ENDIAN
852 uint64_t reserved_4_63 : 60;
853 uint64_t pm_dst : 1; /**< Current power management DSTATE. */
854 uint64_t pm_stat : 1; /**< Power Management Status. */
855 uint64_t pm_en : 1; /**< Power Management Event Enable. */
856 uint64_t aux_en : 1; /**< Auxilary Power Enable. */
860 uint64_t pm_stat : 1;
862 uint64_t reserved_4_63 : 60;
865 struct cvmx_pescx_diag_status_s cn52xx;
866 struct cvmx_pescx_diag_status_s cn52xxp1;
867 struct cvmx_pescx_diag_status_s cn56xx;
868 struct cvmx_pescx_diag_status_s cn56xxp1;
870 typedef union cvmx_pescx_diag_status cvmx_pescx_diag_status_t;
873 * cvmx_pesc#_p2n_bar0_start
875 * PESC_P2N_BAR0_START = PESC PCIe to Npei BAR0 Start
877 * The starting address for addresses to forwarded to the NPEI in RC Mode.
879 union cvmx_pescx_p2n_bar0_start
882 struct cvmx_pescx_p2n_bar0_start_s
884 #if __BYTE_ORDER == __BIG_ENDIAN
885 uint64_t addr : 50; /**< The starting address of the 16KB address space that
886 is the BAR0 address space. */
887 uint64_t reserved_0_13 : 14;
889 uint64_t reserved_0_13 : 14;
893 struct cvmx_pescx_p2n_bar0_start_s cn52xx;
894 struct cvmx_pescx_p2n_bar0_start_s cn52xxp1;
895 struct cvmx_pescx_p2n_bar0_start_s cn56xx;
896 struct cvmx_pescx_p2n_bar0_start_s cn56xxp1;
898 typedef union cvmx_pescx_p2n_bar0_start cvmx_pescx_p2n_bar0_start_t;
901 * cvmx_pesc#_p2n_bar1_start
903 * PESC_P2N_BAR1_START = PESC PCIe to Npei BAR1 Start
905 * The starting address for addresses to forwarded to the NPEI in RC Mode.
907 union cvmx_pescx_p2n_bar1_start
910 struct cvmx_pescx_p2n_bar1_start_s
912 #if __BYTE_ORDER == __BIG_ENDIAN
913 uint64_t addr : 38; /**< The starting address of the 64KB address space
914 that is the BAR1 address space. */
915 uint64_t reserved_0_25 : 26;
917 uint64_t reserved_0_25 : 26;
921 struct cvmx_pescx_p2n_bar1_start_s cn52xx;
922 struct cvmx_pescx_p2n_bar1_start_s cn52xxp1;
923 struct cvmx_pescx_p2n_bar1_start_s cn56xx;
924 struct cvmx_pescx_p2n_bar1_start_s cn56xxp1;
926 typedef union cvmx_pescx_p2n_bar1_start cvmx_pescx_p2n_bar1_start_t;
929 * cvmx_pesc#_p2n_bar2_start
931 * PESC_P2N_BAR2_START = PESC PCIe to Npei BAR2 Start
933 * The starting address for addresses to forwarded to the NPEI in RC Mode.
935 union cvmx_pescx_p2n_bar2_start
938 struct cvmx_pescx_p2n_bar2_start_s
940 #if __BYTE_ORDER == __BIG_ENDIAN
941 uint64_t addr : 25; /**< The starting address of the 2^39 address space
942 that is the BAR2 address space. */
943 uint64_t reserved_0_38 : 39;
945 uint64_t reserved_0_38 : 39;
949 struct cvmx_pescx_p2n_bar2_start_s cn52xx;
950 struct cvmx_pescx_p2n_bar2_start_s cn52xxp1;
951 struct cvmx_pescx_p2n_bar2_start_s cn56xx;
952 struct cvmx_pescx_p2n_bar2_start_s cn56xxp1;
954 typedef union cvmx_pescx_p2n_bar2_start cvmx_pescx_p2n_bar2_start_t;
957 * cvmx_pesc#_p2p_bar#_end
959 * PESC_P2P_BAR#_END = PESC Peer-To-Peer BAR0 End
961 * The ending address for addresses to forwarded to the PCIe peer port.
963 union cvmx_pescx_p2p_barx_end
966 struct cvmx_pescx_p2p_barx_end_s
968 #if __BYTE_ORDER == __BIG_ENDIAN
969 uint64_t addr : 52; /**< The ending address of the address window created
970 this field and the PESC_P2P_BAR0_START[63:12]
971 field. The full 64-bits of address are created by:
972 [ADDR[63:12], 12'b0]. */
973 uint64_t reserved_0_11 : 12;
975 uint64_t reserved_0_11 : 12;
979 struct cvmx_pescx_p2p_barx_end_s cn52xx;
980 struct cvmx_pescx_p2p_barx_end_s cn52xxp1;
981 struct cvmx_pescx_p2p_barx_end_s cn56xx;
982 struct cvmx_pescx_p2p_barx_end_s cn56xxp1;
984 typedef union cvmx_pescx_p2p_barx_end cvmx_pescx_p2p_barx_end_t;
987 * cvmx_pesc#_p2p_bar#_start
989 * PESC_P2P_BAR#_START = PESC Peer-To-Peer BAR0 Start
991 * The starting address and enable for addresses to forwarded to the PCIe peer port.
993 union cvmx_pescx_p2p_barx_start
996 struct cvmx_pescx_p2p_barx_start_s
998 #if __BYTE_ORDER == __BIG_ENDIAN
999 uint64_t addr : 52; /**< The starting address of the address window created
1000 this field and the PESC_P2P_BAR0_END[63:12] field.
1001 The full 64-bits of address are created by:
1002 [ADDR[63:12], 12'b0]. */
1003 uint64_t reserved_0_11 : 12;
1005 uint64_t reserved_0_11 : 12;
1009 struct cvmx_pescx_p2p_barx_start_s cn52xx;
1010 struct cvmx_pescx_p2p_barx_start_s cn52xxp1;
1011 struct cvmx_pescx_p2p_barx_start_s cn56xx;
1012 struct cvmx_pescx_p2p_barx_start_s cn56xxp1;
1014 typedef union cvmx_pescx_p2p_barx_start cvmx_pescx_p2p_barx_start_t;
1017 * cvmx_pesc#_tlp_credits
1019 * PESC_TLP_CREDITS = PESC TLP Credits
1021 * Specifies the number of credits the PESC for use in moving TLPs. When this register is written the credit values are
1022 * reset to the register value. A write to this register should take place BEFORE traffic flow starts.
1024 union cvmx_pescx_tlp_credits
1027 struct cvmx_pescx_tlp_credits_s
1029 #if __BYTE_ORDER == __BIG_ENDIAN
1030 uint64_t reserved_0_63 : 64;
1032 uint64_t reserved_0_63 : 64;
1035 struct cvmx_pescx_tlp_credits_cn52xx
1037 #if __BYTE_ORDER == __BIG_ENDIAN
1038 uint64_t reserved_56_63 : 8;
1039 uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer.
1040 Legal values are 0x24 to 0x80. */
1041 uint64_t pesc_cpl : 8; /**< TLP credits for Completion TLPs in the Peer.
1042 Legal values are 0x24 to 0x80. */
1043 uint64_t pesc_np : 8; /**< TLP credits for Non-Posted TLPs in the Peer.
1044 Legal values are 0x4 to 0x10. */
1045 uint64_t pesc_p : 8; /**< TLP credits for Posted TLPs in the Peer.
1046 Legal values are 0x24 to 0x80. */
1047 uint64_t npei_cpl : 8; /**< TLP credits for Completion TLPs in the NPEI.
1048 Legal values are 0x24 to 0x80. */
1049 uint64_t npei_np : 8; /**< TLP credits for Non-Posted TLPs in the NPEI.
1050 Legal values are 0x4 to 0x10. */
1051 uint64_t npei_p : 8; /**< TLP credits for Posted TLPs in the NPEI.
1052 Legal values are 0x24 to 0x80. */
1054 uint64_t npei_p : 8;
1055 uint64_t npei_np : 8;
1056 uint64_t npei_cpl : 8;
1057 uint64_t pesc_p : 8;
1058 uint64_t pesc_np : 8;
1059 uint64_t pesc_cpl : 8;
1060 uint64_t peai_ppf : 8;
1061 uint64_t reserved_56_63 : 8;
1064 struct cvmx_pescx_tlp_credits_cn52xxp1
1066 #if __BYTE_ORDER == __BIG_ENDIAN
1067 uint64_t reserved_38_63 : 26;
1068 uint64_t peai_ppf : 8; /**< TLP credits in core clk pre-buffer that holds TLPs
1069 being sent from PCIe Core to NPEI or PEER. */
1070 uint64_t pesc_cpl : 5; /**< TLP credits for Completion TLPs in the Peer. */
1071 uint64_t pesc_np : 5; /**< TLP credits for Non-Posted TLPs in the Peer. */
1072 uint64_t pesc_p : 5; /**< TLP credits for Posted TLPs in the Peer. */
1073 uint64_t npei_cpl : 5; /**< TLP credits for Completion TLPs in the NPEI. */
1074 uint64_t npei_np : 5; /**< TLP credits for Non-Posted TLPs in the NPEI. */
1075 uint64_t npei_p : 5; /**< TLP credits for Posted TLPs in the NPEI. */
1077 uint64_t npei_p : 5;
1078 uint64_t npei_np : 5;
1079 uint64_t npei_cpl : 5;
1080 uint64_t pesc_p : 5;
1081 uint64_t pesc_np : 5;
1082 uint64_t pesc_cpl : 5;
1083 uint64_t peai_ppf : 8;
1084 uint64_t reserved_38_63 : 26;
1087 struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
1088 struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
1090 typedef union cvmx_pescx_tlp_credits cvmx_pescx_tlp_credits_t;