1 /***********************license start***************
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) definitions for
49 #ifndef __CVMX_PEXP_DEFS_H__
50 #define __CVMX_PEXP_DEFS_H__
52 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
53 static inline uint64_t CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset)
56 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
57 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
58 cvmx_warn("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
59 return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16;
62 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
64 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
65 #define CVMX_PEXP_NPEI_BIST_STATUS CVMX_PEXP_NPEI_BIST_STATUS_FUNC()
66 static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS_FUNC(void)
68 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
69 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS not supported on this chip\n");
70 return CVMX_ADD_IO_SEG(0x00011F0000008580ull);
73 #define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
75 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
76 #define CVMX_PEXP_NPEI_BIST_STATUS2 CVMX_PEXP_NPEI_BIST_STATUS2_FUNC()
77 static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS2_FUNC(void)
79 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
80 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS2 not supported on this chip\n");
81 return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
84 #define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
86 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
87 #define CVMX_PEXP_NPEI_CTL_PORT0 CVMX_PEXP_NPEI_CTL_PORT0_FUNC()
88 static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT0_FUNC(void)
90 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
91 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT0 not supported on this chip\n");
92 return CVMX_ADD_IO_SEG(0x00011F0000008250ull);
95 #define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
97 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
98 #define CVMX_PEXP_NPEI_CTL_PORT1 CVMX_PEXP_NPEI_CTL_PORT1_FUNC()
99 static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT1_FUNC(void)
101 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
102 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT1 not supported on this chip\n");
103 return CVMX_ADD_IO_SEG(0x00011F0000008260ull);
106 #define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
108 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
109 #define CVMX_PEXP_NPEI_CTL_STATUS CVMX_PEXP_NPEI_CTL_STATUS_FUNC()
110 static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS_FUNC(void)
112 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
113 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS not supported on this chip\n");
114 return CVMX_ADD_IO_SEG(0x00011F0000008570ull);
117 #define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
119 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
120 #define CVMX_PEXP_NPEI_CTL_STATUS2 CVMX_PEXP_NPEI_CTL_STATUS2_FUNC()
121 static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS2_FUNC(void)
123 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
124 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS2 not supported on this chip\n");
125 return CVMX_ADD_IO_SEG(0x00011F000000BC00ull);
128 #define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
130 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
131 #define CVMX_PEXP_NPEI_DATA_OUT_CNT CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC()
132 static inline uint64_t CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC(void)
134 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
135 cvmx_warn("CVMX_PEXP_NPEI_DATA_OUT_CNT not supported on this chip\n");
136 return CVMX_ADD_IO_SEG(0x00011F00000085F0ull);
139 #define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
141 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
142 #define CVMX_PEXP_NPEI_DBG_DATA CVMX_PEXP_NPEI_DBG_DATA_FUNC()
143 static inline uint64_t CVMX_PEXP_NPEI_DBG_DATA_FUNC(void)
145 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
146 cvmx_warn("CVMX_PEXP_NPEI_DBG_DATA not supported on this chip\n");
147 return CVMX_ADD_IO_SEG(0x00011F0000008510ull);
150 #define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
152 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
153 #define CVMX_PEXP_NPEI_DBG_SELECT CVMX_PEXP_NPEI_DBG_SELECT_FUNC()
154 static inline uint64_t CVMX_PEXP_NPEI_DBG_SELECT_FUNC(void)
156 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
157 cvmx_warn("CVMX_PEXP_NPEI_DBG_SELECT not supported on this chip\n");
158 return CVMX_ADD_IO_SEG(0x00011F0000008500ull);
161 #define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
163 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
164 #define CVMX_PEXP_NPEI_DMA0_INT_LEVEL CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC()
165 static inline uint64_t CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC(void)
167 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
168 cvmx_warn("CVMX_PEXP_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
169 return CVMX_ADD_IO_SEG(0x00011F00000085C0ull);
172 #define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
174 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
175 #define CVMX_PEXP_NPEI_DMA1_INT_LEVEL CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC()
176 static inline uint64_t CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC(void)
178 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
179 cvmx_warn("CVMX_PEXP_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
180 return CVMX_ADD_IO_SEG(0x00011F00000085D0ull);
183 #define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
185 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
186 static inline uint64_t CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset)
189 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
190 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
191 cvmx_warn("CVMX_PEXP_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
192 return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16;
195 #define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
197 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
198 static inline uint64_t CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset)
201 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
202 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
203 cvmx_warn("CVMX_PEXP_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
204 return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16;
207 #define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
209 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
210 static inline uint64_t CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
213 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
214 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
215 cvmx_warn("CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
216 return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16;
219 #define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
222 static inline uint64_t CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset)
225 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
227 cvmx_warn("CVMX_PEXP_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
228 return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16;
231 #define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
233 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
234 #define CVMX_PEXP_NPEI_DMA_CNTS CVMX_PEXP_NPEI_DMA_CNTS_FUNC()
235 static inline uint64_t CVMX_PEXP_NPEI_DMA_CNTS_FUNC(void)
237 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
238 cvmx_warn("CVMX_PEXP_NPEI_DMA_CNTS not supported on this chip\n");
239 return CVMX_ADD_IO_SEG(0x00011F00000085E0ull);
242 #define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
244 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
245 #define CVMX_PEXP_NPEI_DMA_CONTROL CVMX_PEXP_NPEI_DMA_CONTROL_FUNC()
246 static inline uint64_t CVMX_PEXP_NPEI_DMA_CONTROL_FUNC(void)
248 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
249 cvmx_warn("CVMX_PEXP_NPEI_DMA_CONTROL not supported on this chip\n");
250 return CVMX_ADD_IO_SEG(0x00011F00000083A0ull);
253 #define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
255 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
256 #define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC()
257 static inline uint64_t CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
259 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
260 cvmx_warn("CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
261 return CVMX_ADD_IO_SEG(0x00011F00000085B0ull);
264 #define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
266 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
267 #define CVMX_PEXP_NPEI_DMA_STATE1 CVMX_PEXP_NPEI_DMA_STATE1_FUNC()
268 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_FUNC(void)
270 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
271 cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE1 not supported on this chip\n");
272 return CVMX_ADD_IO_SEG(0x00011F00000086C0ull);
275 #define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
277 #define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
278 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
279 #define CVMX_PEXP_NPEI_DMA_STATE2 CVMX_PEXP_NPEI_DMA_STATE2_FUNC()
280 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_FUNC(void)
282 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
283 cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE2 not supported on this chip\n");
284 return CVMX_ADD_IO_SEG(0x00011F00000086D0ull);
287 #define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
289 #define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
290 #define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
291 #define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
292 #define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
293 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
294 #define CVMX_PEXP_NPEI_INT_A_ENB CVMX_PEXP_NPEI_INT_A_ENB_FUNC()
295 static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB_FUNC(void)
297 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
298 cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB not supported on this chip\n");
299 return CVMX_ADD_IO_SEG(0x00011F0000008560ull);
302 #define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
304 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
305 #define CVMX_PEXP_NPEI_INT_A_ENB2 CVMX_PEXP_NPEI_INT_A_ENB2_FUNC()
306 static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB2_FUNC(void)
308 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
309 cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB2 not supported on this chip\n");
310 return CVMX_ADD_IO_SEG(0x00011F000000BCE0ull);
313 #define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
315 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
316 #define CVMX_PEXP_NPEI_INT_A_SUM CVMX_PEXP_NPEI_INT_A_SUM_FUNC()
317 static inline uint64_t CVMX_PEXP_NPEI_INT_A_SUM_FUNC(void)
319 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
320 cvmx_warn("CVMX_PEXP_NPEI_INT_A_SUM not supported on this chip\n");
321 return CVMX_ADD_IO_SEG(0x00011F0000008550ull);
324 #define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
326 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
327 #define CVMX_PEXP_NPEI_INT_ENB CVMX_PEXP_NPEI_INT_ENB_FUNC()
328 static inline uint64_t CVMX_PEXP_NPEI_INT_ENB_FUNC(void)
330 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
331 cvmx_warn("CVMX_PEXP_NPEI_INT_ENB not supported on this chip\n");
332 return CVMX_ADD_IO_SEG(0x00011F0000008540ull);
335 #define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
337 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
338 #define CVMX_PEXP_NPEI_INT_ENB2 CVMX_PEXP_NPEI_INT_ENB2_FUNC()
339 static inline uint64_t CVMX_PEXP_NPEI_INT_ENB2_FUNC(void)
341 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
342 cvmx_warn("CVMX_PEXP_NPEI_INT_ENB2 not supported on this chip\n");
343 return CVMX_ADD_IO_SEG(0x00011F000000BCD0ull);
346 #define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
348 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
349 #define CVMX_PEXP_NPEI_INT_INFO CVMX_PEXP_NPEI_INT_INFO_FUNC()
350 static inline uint64_t CVMX_PEXP_NPEI_INT_INFO_FUNC(void)
352 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
353 cvmx_warn("CVMX_PEXP_NPEI_INT_INFO not supported on this chip\n");
354 return CVMX_ADD_IO_SEG(0x00011F0000008590ull);
357 #define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
359 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
360 #define CVMX_PEXP_NPEI_INT_SUM CVMX_PEXP_NPEI_INT_SUM_FUNC()
361 static inline uint64_t CVMX_PEXP_NPEI_INT_SUM_FUNC(void)
363 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
364 cvmx_warn("CVMX_PEXP_NPEI_INT_SUM not supported on this chip\n");
365 return CVMX_ADD_IO_SEG(0x00011F0000008530ull);
368 #define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
370 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
371 #define CVMX_PEXP_NPEI_INT_SUM2 CVMX_PEXP_NPEI_INT_SUM2_FUNC()
372 static inline uint64_t CVMX_PEXP_NPEI_INT_SUM2_FUNC(void)
374 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
375 cvmx_warn("CVMX_PEXP_NPEI_INT_SUM2 not supported on this chip\n");
376 return CVMX_ADD_IO_SEG(0x00011F000000BCC0ull);
379 #define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
381 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
382 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC()
383 static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC(void)
385 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
386 cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
387 return CVMX_ADD_IO_SEG(0x00011F0000008600ull);
390 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
392 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
393 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC()
394 static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC(void)
396 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
397 cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
398 return CVMX_ADD_IO_SEG(0x00011F0000008610ull);
401 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
403 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
404 #define CVMX_PEXP_NPEI_MEM_ACCESS_CTL CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC()
405 static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC(void)
407 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
408 cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
409 return CVMX_ADD_IO_SEG(0x00011F00000084F0ull);
412 #define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
414 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
415 static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
418 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) ||
419 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27))))))
420 cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
421 return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12;
424 #define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
426 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
427 #define CVMX_PEXP_NPEI_MSI_ENB0 CVMX_PEXP_NPEI_MSI_ENB0_FUNC()
428 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB0_FUNC(void)
430 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
431 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB0 not supported on this chip\n");
432 return CVMX_ADD_IO_SEG(0x00011F000000BC50ull);
435 #define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
437 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
438 #define CVMX_PEXP_NPEI_MSI_ENB1 CVMX_PEXP_NPEI_MSI_ENB1_FUNC()
439 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB1_FUNC(void)
441 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
442 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB1 not supported on this chip\n");
443 return CVMX_ADD_IO_SEG(0x00011F000000BC60ull);
446 #define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
448 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
449 #define CVMX_PEXP_NPEI_MSI_ENB2 CVMX_PEXP_NPEI_MSI_ENB2_FUNC()
450 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB2_FUNC(void)
452 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
453 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB2 not supported on this chip\n");
454 return CVMX_ADD_IO_SEG(0x00011F000000BC70ull);
457 #define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
459 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
460 #define CVMX_PEXP_NPEI_MSI_ENB3 CVMX_PEXP_NPEI_MSI_ENB3_FUNC()
461 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB3_FUNC(void)
463 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
464 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB3 not supported on this chip\n");
465 return CVMX_ADD_IO_SEG(0x00011F000000BC80ull);
468 #define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
470 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
471 #define CVMX_PEXP_NPEI_MSI_RCV0 CVMX_PEXP_NPEI_MSI_RCV0_FUNC()
472 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV0_FUNC(void)
474 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
475 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV0 not supported on this chip\n");
476 return CVMX_ADD_IO_SEG(0x00011F000000BC10ull);
479 #define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
481 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
482 #define CVMX_PEXP_NPEI_MSI_RCV1 CVMX_PEXP_NPEI_MSI_RCV1_FUNC()
483 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV1_FUNC(void)
485 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
486 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV1 not supported on this chip\n");
487 return CVMX_ADD_IO_SEG(0x00011F000000BC20ull);
490 #define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
492 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
493 #define CVMX_PEXP_NPEI_MSI_RCV2 CVMX_PEXP_NPEI_MSI_RCV2_FUNC()
494 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV2_FUNC(void)
496 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
497 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV2 not supported on this chip\n");
498 return CVMX_ADD_IO_SEG(0x00011F000000BC30ull);
501 #define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
503 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
504 #define CVMX_PEXP_NPEI_MSI_RCV3 CVMX_PEXP_NPEI_MSI_RCV3_FUNC()
505 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV3_FUNC(void)
507 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
508 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV3 not supported on this chip\n");
509 return CVMX_ADD_IO_SEG(0x00011F000000BC40ull);
512 #define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
514 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
515 #define CVMX_PEXP_NPEI_MSI_RD_MAP CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC()
516 static inline uint64_t CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC(void)
518 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
519 cvmx_warn("CVMX_PEXP_NPEI_MSI_RD_MAP not supported on this chip\n");
520 return CVMX_ADD_IO_SEG(0x00011F000000BCA0ull);
523 #define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
525 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
526 #define CVMX_PEXP_NPEI_MSI_W1C_ENB0 CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC()
527 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC(void)
529 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
530 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
531 return CVMX_ADD_IO_SEG(0x00011F000000BCF0ull);
534 #define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
536 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
537 #define CVMX_PEXP_NPEI_MSI_W1C_ENB1 CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC()
538 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC(void)
540 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
541 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
542 return CVMX_ADD_IO_SEG(0x00011F000000BD00ull);
545 #define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
547 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
548 #define CVMX_PEXP_NPEI_MSI_W1C_ENB2 CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC()
549 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC(void)
551 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
552 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
553 return CVMX_ADD_IO_SEG(0x00011F000000BD10ull);
556 #define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
558 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
559 #define CVMX_PEXP_NPEI_MSI_W1C_ENB3 CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC()
560 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC(void)
562 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
563 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
564 return CVMX_ADD_IO_SEG(0x00011F000000BD20ull);
567 #define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
569 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
570 #define CVMX_PEXP_NPEI_MSI_W1S_ENB0 CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC()
571 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC(void)
573 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
574 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
575 return CVMX_ADD_IO_SEG(0x00011F000000BD30ull);
578 #define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
580 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
581 #define CVMX_PEXP_NPEI_MSI_W1S_ENB1 CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC()
582 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC(void)
584 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
585 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
586 return CVMX_ADD_IO_SEG(0x00011F000000BD40ull);
589 #define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
591 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
592 #define CVMX_PEXP_NPEI_MSI_W1S_ENB2 CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC()
593 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC(void)
595 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
596 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
597 return CVMX_ADD_IO_SEG(0x00011F000000BD50ull);
600 #define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
602 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
603 #define CVMX_PEXP_NPEI_MSI_W1S_ENB3 CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC()
604 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC(void)
606 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
607 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
608 return CVMX_ADD_IO_SEG(0x00011F000000BD60ull);
611 #define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
613 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
614 #define CVMX_PEXP_NPEI_MSI_WR_MAP CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC()
615 static inline uint64_t CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC(void)
617 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
618 cvmx_warn("CVMX_PEXP_NPEI_MSI_WR_MAP not supported on this chip\n");
619 return CVMX_ADD_IO_SEG(0x00011F000000BC90ull);
622 #define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
624 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
625 #define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC()
626 static inline uint64_t CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC(void)
628 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
629 cvmx_warn("CVMX_PEXP_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
630 return CVMX_ADD_IO_SEG(0x00011F000000BD70ull);
633 #define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
635 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
636 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC()
637 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC(void)
639 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
640 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV not supported on this chip\n");
641 return CVMX_ADD_IO_SEG(0x00011F000000BCB0ull);
644 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
646 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
647 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC()
648 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
650 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
651 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
652 return CVMX_ADD_IO_SEG(0x00011F0000008650ull);
655 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
657 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
658 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC()
659 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
661 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
662 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
663 return CVMX_ADD_IO_SEG(0x00011F0000008660ull);
666 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
668 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
669 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC()
670 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
672 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
673 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
674 return CVMX_ADD_IO_SEG(0x00011F0000008670ull);
677 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
679 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
680 static inline uint64_t CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset)
683 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
684 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
685 cvmx_warn("CVMX_PEXP_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
686 return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16;
689 #define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
691 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
692 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
695 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
696 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
697 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
698 return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16;
701 #define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
703 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
704 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
707 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
708 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
709 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
710 return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16;
713 #define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
715 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
716 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
719 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
720 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
721 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
722 return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16;
725 #define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
727 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
728 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
731 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
732 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
733 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
734 return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16;
737 #define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
739 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
740 static inline uint64_t CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset)
743 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
744 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
745 cvmx_warn("CVMX_PEXP_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
746 return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16;
749 #define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
751 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
752 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
755 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
756 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
757 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
758 return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16;
761 #define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
763 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
764 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
767 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
768 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
769 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
770 return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16;
773 #define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
775 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
776 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
779 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
780 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
781 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
782 return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16;
785 #define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
787 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
788 #define CVMX_PEXP_NPEI_PKT_CNT_INT CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC()
789 static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC(void)
791 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
792 cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT not supported on this chip\n");
793 return CVMX_ADD_IO_SEG(0x00011F0000009110ull);
796 #define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
798 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
799 #define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC()
800 static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC(void)
802 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
803 cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
804 return CVMX_ADD_IO_SEG(0x00011F0000009130ull);
807 #define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
809 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
810 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC()
811 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC(void)
813 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
814 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
815 return CVMX_ADD_IO_SEG(0x00011F00000090B0ull);
818 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
820 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
821 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC()
822 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC(void)
824 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
825 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
826 return CVMX_ADD_IO_SEG(0x00011F00000090A0ull);
829 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
831 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
832 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC()
833 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
835 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
836 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
837 return CVMX_ADD_IO_SEG(0x00011F0000009090ull);
840 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
842 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
843 #define CVMX_PEXP_NPEI_PKT_DPADDR CVMX_PEXP_NPEI_PKT_DPADDR_FUNC()
844 static inline uint64_t CVMX_PEXP_NPEI_PKT_DPADDR_FUNC(void)
846 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
847 cvmx_warn("CVMX_PEXP_NPEI_PKT_DPADDR not supported on this chip\n");
848 return CVMX_ADD_IO_SEG(0x00011F0000009080ull);
851 #define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
853 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
854 #define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC()
855 static inline uint64_t CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC(void)
857 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
858 cvmx_warn("CVMX_PEXP_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
859 return CVMX_ADD_IO_SEG(0x00011F0000009150ull);
862 #define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
864 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
865 #define CVMX_PEXP_NPEI_PKT_INSTR_ENB CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC()
866 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC(void)
868 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
869 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_ENB not supported on this chip\n");
870 return CVMX_ADD_IO_SEG(0x00011F0000009000ull);
873 #define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
875 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
876 #define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC()
877 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
879 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
880 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
881 return CVMX_ADD_IO_SEG(0x00011F0000009190ull);
884 #define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
886 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
887 #define CVMX_PEXP_NPEI_PKT_INSTR_SIZE CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC()
888 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC(void)
890 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
891 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
892 return CVMX_ADD_IO_SEG(0x00011F0000009020ull);
895 #define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
897 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
898 #define CVMX_PEXP_NPEI_PKT_INT_LEVELS CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC()
899 static inline uint64_t CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC(void)
901 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
902 cvmx_warn("CVMX_PEXP_NPEI_PKT_INT_LEVELS not supported on this chip\n");
903 return CVMX_ADD_IO_SEG(0x00011F0000009100ull);
906 #define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
908 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
909 #define CVMX_PEXP_NPEI_PKT_IN_BP CVMX_PEXP_NPEI_PKT_IN_BP_FUNC()
910 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_BP_FUNC(void)
912 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
913 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_BP not supported on this chip\n");
914 return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
917 #define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
919 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
920 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
923 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
924 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
925 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
926 return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16;
929 #define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
931 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
932 #define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
933 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
935 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
936 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
937 return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
940 #define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
942 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
943 #define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC()
944 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
946 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
947 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
948 return CVMX_ADD_IO_SEG(0x00011F00000091A0ull);
951 #define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
953 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
954 #define CVMX_PEXP_NPEI_PKT_IPTR CVMX_PEXP_NPEI_PKT_IPTR_FUNC()
955 static inline uint64_t CVMX_PEXP_NPEI_PKT_IPTR_FUNC(void)
957 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
958 cvmx_warn("CVMX_PEXP_NPEI_PKT_IPTR not supported on this chip\n");
959 return CVMX_ADD_IO_SEG(0x00011F0000009070ull);
962 #define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
964 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
965 #define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC()
966 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
968 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
969 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
970 return CVMX_ADD_IO_SEG(0x00011F0000009160ull);
973 #define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
975 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
976 #define CVMX_PEXP_NPEI_PKT_OUT_BMODE CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC()
977 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC(void)
979 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
980 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_BMODE not supported on this chip\n");
981 return CVMX_ADD_IO_SEG(0x00011F00000090D0ull);
984 #define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
986 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
987 #define CVMX_PEXP_NPEI_PKT_OUT_ENB CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC()
988 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC(void)
990 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
991 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_ENB not supported on this chip\n");
992 return CVMX_ADD_IO_SEG(0x00011F0000009010ull);
995 #define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
997 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
998 #define CVMX_PEXP_NPEI_PKT_PCIE_PORT CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC()
999 static inline uint64_t CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC(void)
1001 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1002 cvmx_warn("CVMX_PEXP_NPEI_PKT_PCIE_PORT not supported on this chip\n");
1003 return CVMX_ADD_IO_SEG(0x00011F00000090E0ull);
1006 #define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
1008 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1009 #define CVMX_PEXP_NPEI_PKT_PORT_IN_RST CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC()
1010 static inline uint64_t CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC(void)
1012 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1013 cvmx_warn("CVMX_PEXP_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
1014 return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
1017 #define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
1019 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1020 #define CVMX_PEXP_NPEI_PKT_SLIST_ES CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC()
1021 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC(void)
1023 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1024 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ES not supported on this chip\n");
1025 return CVMX_ADD_IO_SEG(0x00011F0000009050ull);
1028 #define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
1030 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1031 #define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC()
1032 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
1034 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1035 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
1036 return CVMX_ADD_IO_SEG(0x00011F0000009180ull);
1039 #define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
1041 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1042 #define CVMX_PEXP_NPEI_PKT_SLIST_NS CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC()
1043 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC(void)
1045 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1046 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_NS not supported on this chip\n");
1047 return CVMX_ADD_IO_SEG(0x00011F0000009040ull);
1050 #define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
1052 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1053 #define CVMX_PEXP_NPEI_PKT_SLIST_ROR CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC()
1054 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC(void)
1056 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1057 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ROR not supported on this chip\n");
1058 return CVMX_ADD_IO_SEG(0x00011F0000009030ull);
1061 #define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
1063 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1064 #define CVMX_PEXP_NPEI_PKT_TIME_INT CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC()
1065 static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC(void)
1067 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1068 cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT not supported on this chip\n");
1069 return CVMX_ADD_IO_SEG(0x00011F0000009120ull);
1072 #define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
1074 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1075 #define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC()
1076 static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC(void)
1078 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1079 cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
1080 return CVMX_ADD_IO_SEG(0x00011F0000009140ull);
1083 #define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
1085 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1086 #define CVMX_PEXP_NPEI_RSL_INT_BLOCKS CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC()
1087 static inline uint64_t CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC(void)
1089 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1090 cvmx_warn("CVMX_PEXP_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
1091 return CVMX_ADD_IO_SEG(0x00011F0000008520ull);
1094 #define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
1096 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1097 #define CVMX_PEXP_NPEI_SCRATCH_1 CVMX_PEXP_NPEI_SCRATCH_1_FUNC()
1098 static inline uint64_t CVMX_PEXP_NPEI_SCRATCH_1_FUNC(void)
1100 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1101 cvmx_warn("CVMX_PEXP_NPEI_SCRATCH_1 not supported on this chip\n");
1102 return CVMX_ADD_IO_SEG(0x00011F0000008270ull);
1105 #define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
1107 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1108 #define CVMX_PEXP_NPEI_STATE1 CVMX_PEXP_NPEI_STATE1_FUNC()
1109 static inline uint64_t CVMX_PEXP_NPEI_STATE1_FUNC(void)
1111 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1112 cvmx_warn("CVMX_PEXP_NPEI_STATE1 not supported on this chip\n");
1113 return CVMX_ADD_IO_SEG(0x00011F0000008620ull);
1116 #define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
1118 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1119 #define CVMX_PEXP_NPEI_STATE2 CVMX_PEXP_NPEI_STATE2_FUNC()
1120 static inline uint64_t CVMX_PEXP_NPEI_STATE2_FUNC(void)
1122 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1123 cvmx_warn("CVMX_PEXP_NPEI_STATE2 not supported on this chip\n");
1124 return CVMX_ADD_IO_SEG(0x00011F0000008630ull);
1127 #define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
1129 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1130 #define CVMX_PEXP_NPEI_STATE3 CVMX_PEXP_NPEI_STATE3_FUNC()
1131 static inline uint64_t CVMX_PEXP_NPEI_STATE3_FUNC(void)
1133 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1134 cvmx_warn("CVMX_PEXP_NPEI_STATE3 not supported on this chip\n");
1135 return CVMX_ADD_IO_SEG(0x00011F0000008640ull);
1138 #define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
1140 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1141 #define CVMX_PEXP_NPEI_WINDOW_CTL CVMX_PEXP_NPEI_WINDOW_CTL_FUNC()
1142 static inline uint64_t CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void)
1144 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1145 cvmx_warn("CVMX_PEXP_NPEI_WINDOW_CTL not supported on this chip\n");
1146 return CVMX_ADD_IO_SEG(0x00011F0000008380ull);
1149 #define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
1151 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1152 #define CVMX_PEXP_SLI_BIST_STATUS CVMX_PEXP_SLI_BIST_STATUS_FUNC()
1153 static inline uint64_t CVMX_PEXP_SLI_BIST_STATUS_FUNC(void)
1155 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1156 cvmx_warn("CVMX_PEXP_SLI_BIST_STATUS not supported on this chip\n");
1157 return CVMX_ADD_IO_SEG(0x00011F0000010580ull);
1160 #define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
1162 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1163 static inline uint64_t CVMX_PEXP_SLI_CTL_PORTX(unsigned long offset)
1166 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1167 cvmx_warn("CVMX_PEXP_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
1168 return CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16;
1171 #define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
1173 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1174 #define CVMX_PEXP_SLI_CTL_STATUS CVMX_PEXP_SLI_CTL_STATUS_FUNC()
1175 static inline uint64_t CVMX_PEXP_SLI_CTL_STATUS_FUNC(void)
1177 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1178 cvmx_warn("CVMX_PEXP_SLI_CTL_STATUS not supported on this chip\n");
1179 return CVMX_ADD_IO_SEG(0x00011F0000010570ull);
1182 #define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
1184 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1185 #define CVMX_PEXP_SLI_DATA_OUT_CNT CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC()
1186 static inline uint64_t CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC(void)
1188 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1189 cvmx_warn("CVMX_PEXP_SLI_DATA_OUT_CNT not supported on this chip\n");
1190 return CVMX_ADD_IO_SEG(0x00011F00000105F0ull);
1193 #define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
1195 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1196 #define CVMX_PEXP_SLI_DBG_DATA CVMX_PEXP_SLI_DBG_DATA_FUNC()
1197 static inline uint64_t CVMX_PEXP_SLI_DBG_DATA_FUNC(void)
1199 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1200 cvmx_warn("CVMX_PEXP_SLI_DBG_DATA not supported on this chip\n");
1201 return CVMX_ADD_IO_SEG(0x00011F0000010310ull);
1204 #define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
1206 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1207 #define CVMX_PEXP_SLI_DBG_SELECT CVMX_PEXP_SLI_DBG_SELECT_FUNC()
1208 static inline uint64_t CVMX_PEXP_SLI_DBG_SELECT_FUNC(void)
1210 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1211 cvmx_warn("CVMX_PEXP_SLI_DBG_SELECT not supported on this chip\n");
1212 return CVMX_ADD_IO_SEG(0x00011F0000010300ull);
1215 #define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
1217 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1218 static inline uint64_t CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset)
1221 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1222 cvmx_warn("CVMX_PEXP_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
1223 return CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16;
1226 #define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
1228 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1229 static inline uint64_t CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset)
1232 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1233 cvmx_warn("CVMX_PEXP_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
1234 return CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16;
1237 #define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
1239 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1240 static inline uint64_t CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset)
1243 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1244 cvmx_warn("CVMX_PEXP_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
1245 return CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16;
1248 #define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
1250 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1251 #define CVMX_PEXP_SLI_INT_ENB_CIU CVMX_PEXP_SLI_INT_ENB_CIU_FUNC()
1252 static inline uint64_t CVMX_PEXP_SLI_INT_ENB_CIU_FUNC(void)
1254 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1255 cvmx_warn("CVMX_PEXP_SLI_INT_ENB_CIU not supported on this chip\n");
1256 return CVMX_ADD_IO_SEG(0x00011F0000013CD0ull);
1259 #define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
1261 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1262 static inline uint64_t CVMX_PEXP_SLI_INT_ENB_PORTX(unsigned long offset)
1265 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1266 cvmx_warn("CVMX_PEXP_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
1267 return CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16;
1270 #define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
1272 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1273 #define CVMX_PEXP_SLI_INT_SUM CVMX_PEXP_SLI_INT_SUM_FUNC()
1274 static inline uint64_t CVMX_PEXP_SLI_INT_SUM_FUNC(void)
1276 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1277 cvmx_warn("CVMX_PEXP_SLI_INT_SUM not supported on this chip\n");
1278 return CVMX_ADD_IO_SEG(0x00011F0000010330ull);
1281 #define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
1283 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1284 #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC()
1285 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC(void)
1287 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1288 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA0 not supported on this chip\n");
1289 return CVMX_ADD_IO_SEG(0x00011F0000010600ull);
1292 #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
1294 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1295 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC()
1296 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC(void)
1298 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1299 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA1 not supported on this chip\n");
1300 return CVMX_ADD_IO_SEG(0x00011F0000010610ull);
1303 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
1305 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1306 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC()
1307 static inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC(void)
1309 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1310 cvmx_warn("CVMX_PEXP_SLI_MAC_CREDIT_CNT not supported on this chip\n");
1311 return CVMX_ADD_IO_SEG(0x00011F0000013D70ull);
1314 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
1316 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1317 #define CVMX_PEXP_SLI_MEM_ACCESS_CTL CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC()
1318 static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC(void)
1320 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1321 cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_CTL not supported on this chip\n");
1322 return CVMX_ADD_IO_SEG(0x00011F00000102F0ull);
1325 #define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
1327 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1328 static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
1331 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27))))))
1332 cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
1333 return CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12;
1336 #define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
1338 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1339 #define CVMX_PEXP_SLI_MSI_ENB0 CVMX_PEXP_SLI_MSI_ENB0_FUNC()
1340 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB0_FUNC(void)
1342 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1343 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB0 not supported on this chip\n");
1344 return CVMX_ADD_IO_SEG(0x00011F0000013C50ull);
1347 #define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
1349 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1350 #define CVMX_PEXP_SLI_MSI_ENB1 CVMX_PEXP_SLI_MSI_ENB1_FUNC()
1351 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB1_FUNC(void)
1353 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1354 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB1 not supported on this chip\n");
1355 return CVMX_ADD_IO_SEG(0x00011F0000013C60ull);
1358 #define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
1360 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1361 #define CVMX_PEXP_SLI_MSI_ENB2 CVMX_PEXP_SLI_MSI_ENB2_FUNC()
1362 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB2_FUNC(void)
1364 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1365 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB2 not supported on this chip\n");
1366 return CVMX_ADD_IO_SEG(0x00011F0000013C70ull);
1369 #define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
1371 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1372 #define CVMX_PEXP_SLI_MSI_ENB3 CVMX_PEXP_SLI_MSI_ENB3_FUNC()
1373 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB3_FUNC(void)
1375 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1376 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB3 not supported on this chip\n");
1377 return CVMX_ADD_IO_SEG(0x00011F0000013C80ull);
1380 #define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
1382 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1383 #define CVMX_PEXP_SLI_MSI_RCV0 CVMX_PEXP_SLI_MSI_RCV0_FUNC()
1384 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV0_FUNC(void)
1386 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1387 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV0 not supported on this chip\n");
1388 return CVMX_ADD_IO_SEG(0x00011F0000013C10ull);
1391 #define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
1393 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1394 #define CVMX_PEXP_SLI_MSI_RCV1 CVMX_PEXP_SLI_MSI_RCV1_FUNC()
1395 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV1_FUNC(void)
1397 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1398 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV1 not supported on this chip\n");
1399 return CVMX_ADD_IO_SEG(0x00011F0000013C20ull);
1402 #define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
1404 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1405 #define CVMX_PEXP_SLI_MSI_RCV2 CVMX_PEXP_SLI_MSI_RCV2_FUNC()
1406 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV2_FUNC(void)
1408 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1409 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV2 not supported on this chip\n");
1410 return CVMX_ADD_IO_SEG(0x00011F0000013C30ull);
1413 #define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
1415 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1416 #define CVMX_PEXP_SLI_MSI_RCV3 CVMX_PEXP_SLI_MSI_RCV3_FUNC()
1417 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV3_FUNC(void)
1419 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1420 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV3 not supported on this chip\n");
1421 return CVMX_ADD_IO_SEG(0x00011F0000013C40ull);
1424 #define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
1426 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1427 #define CVMX_PEXP_SLI_MSI_RD_MAP CVMX_PEXP_SLI_MSI_RD_MAP_FUNC()
1428 static inline uint64_t CVMX_PEXP_SLI_MSI_RD_MAP_FUNC(void)
1430 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1431 cvmx_warn("CVMX_PEXP_SLI_MSI_RD_MAP not supported on this chip\n");
1432 return CVMX_ADD_IO_SEG(0x00011F0000013CA0ull);
1435 #define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
1437 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1438 #define CVMX_PEXP_SLI_MSI_W1C_ENB0 CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC()
1439 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC(void)
1441 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1442 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB0 not supported on this chip\n");
1443 return CVMX_ADD_IO_SEG(0x00011F0000013CF0ull);
1446 #define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
1448 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1449 #define CVMX_PEXP_SLI_MSI_W1C_ENB1 CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC()
1450 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC(void)
1452 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1453 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB1 not supported on this chip\n");
1454 return CVMX_ADD_IO_SEG(0x00011F0000013D00ull);
1457 #define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
1459 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1460 #define CVMX_PEXP_SLI_MSI_W1C_ENB2 CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC()
1461 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC(void)
1463 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1464 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB2 not supported on this chip\n");
1465 return CVMX_ADD_IO_SEG(0x00011F0000013D10ull);
1468 #define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
1470 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1471 #define CVMX_PEXP_SLI_MSI_W1C_ENB3 CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC()
1472 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC(void)
1474 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1475 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB3 not supported on this chip\n");
1476 return CVMX_ADD_IO_SEG(0x00011F0000013D20ull);
1479 #define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
1481 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1482 #define CVMX_PEXP_SLI_MSI_W1S_ENB0 CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC()
1483 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC(void)
1485 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1486 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB0 not supported on this chip\n");
1487 return CVMX_ADD_IO_SEG(0x00011F0000013D30ull);
1490 #define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
1492 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1493 #define CVMX_PEXP_SLI_MSI_W1S_ENB1 CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC()
1494 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC(void)
1496 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1497 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB1 not supported on this chip\n");
1498 return CVMX_ADD_IO_SEG(0x00011F0000013D40ull);
1501 #define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
1503 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1504 #define CVMX_PEXP_SLI_MSI_W1S_ENB2 CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC()
1505 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC(void)
1507 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1508 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB2 not supported on this chip\n");
1509 return CVMX_ADD_IO_SEG(0x00011F0000013D50ull);
1512 #define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
1514 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1515 #define CVMX_PEXP_SLI_MSI_W1S_ENB3 CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC()
1516 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC(void)
1518 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1519 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB3 not supported on this chip\n");
1520 return CVMX_ADD_IO_SEG(0x00011F0000013D60ull);
1523 #define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
1525 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1526 #define CVMX_PEXP_SLI_MSI_WR_MAP CVMX_PEXP_SLI_MSI_WR_MAP_FUNC()
1527 static inline uint64_t CVMX_PEXP_SLI_MSI_WR_MAP_FUNC(void)
1529 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1530 cvmx_warn("CVMX_PEXP_SLI_MSI_WR_MAP not supported on this chip\n");
1531 return CVMX_ADD_IO_SEG(0x00011F0000013C90ull);
1534 #define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
1536 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1537 #define CVMX_PEXP_SLI_PCIE_MSI_RCV CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC()
1538 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC(void)
1540 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1541 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV not supported on this chip\n");
1542 return CVMX_ADD_IO_SEG(0x00011F0000013CB0ull);
1545 #define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
1547 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1548 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC()
1549 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC(void)
1551 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1552 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n");
1553 return CVMX_ADD_IO_SEG(0x00011F0000010650ull);
1556 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
1558 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1559 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC()
1560 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC(void)
1562 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1563 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n");
1564 return CVMX_ADD_IO_SEG(0x00011F0000010660ull);
1567 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
1569 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1570 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC()
1571 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC(void)
1573 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1574 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n");
1575 return CVMX_ADD_IO_SEG(0x00011F0000010670ull);
1578 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
1580 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1581 static inline uint64_t CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset)
1584 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
1585 cvmx_warn("CVMX_PEXP_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
1586 return CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16;
1589 #define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
1591 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1592 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset)
1595 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
1596 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
1597 return CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16;
1600 #define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
1602 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1603 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
1606 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
1607 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
1608 return CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16;
1611 #define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
1613 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1614 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
1617 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
1618 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
1619 return CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16;
1622 #define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
1624 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1625 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_HEADER(unsigned long offset)
1628 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
1629 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
1630 return CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16;
1633 #define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
1635 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1636 static inline uint64_t CVMX_PEXP_SLI_PKTX_IN_BP(unsigned long offset)
1639 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
1640 cvmx_warn("CVMX_PEXP_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
1641 return CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16;
1644 #define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
1646 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1647 static inline uint64_t CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset)
1650 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
1651 cvmx_warn("CVMX_PEXP_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
1652 return CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16;
1655 #define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
1657 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1658 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset)
1661 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
1662 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
1663 return CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16;
1666 #define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
1668 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1669 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
1672 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
1673 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
1674 return CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16;
1677 #define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
1679 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1680 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
1683 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
1684 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
1685 return CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16;
1688 #define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
1690 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1691 #define CVMX_PEXP_SLI_PKT_CNT_INT CVMX_PEXP_SLI_PKT_CNT_INT_FUNC()
1692 static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_FUNC(void)
1694 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1695 cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT not supported on this chip\n");
1696 return CVMX_ADD_IO_SEG(0x00011F0000011130ull);
1699 #define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
1701 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1702 #define CVMX_PEXP_SLI_PKT_CNT_INT_ENB CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC()
1703 static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC(void)
1705 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1706 cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT_ENB not supported on this chip\n");
1707 return CVMX_ADD_IO_SEG(0x00011F0000011150ull);
1710 #define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
1712 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1713 #define CVMX_PEXP_SLI_PKT_CTL CVMX_PEXP_SLI_PKT_CTL_FUNC()
1714 static inline uint64_t CVMX_PEXP_SLI_PKT_CTL_FUNC(void)
1716 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1717 cvmx_warn("CVMX_PEXP_SLI_PKT_CTL not supported on this chip\n");
1718 return CVMX_ADD_IO_SEG(0x00011F0000011220ull);
1721 #define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
1723 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1724 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ES CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC()
1725 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC(void)
1727 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1728 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ES not supported on this chip\n");
1729 return CVMX_ADD_IO_SEG(0x00011F00000110B0ull);
1732 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
1734 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1735 #define CVMX_PEXP_SLI_PKT_DATA_OUT_NS CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC()
1736 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC(void)
1738 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1739 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_NS not supported on this chip\n");
1740 return CVMX_ADD_IO_SEG(0x00011F00000110A0ull);
1743 #define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
1745 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1746 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC()
1747 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC(void)
1749 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1750 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ROR not supported on this chip\n");
1751 return CVMX_ADD_IO_SEG(0x00011F0000011090ull);
1754 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
1756 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1757 #define CVMX_PEXP_SLI_PKT_DPADDR CVMX_PEXP_SLI_PKT_DPADDR_FUNC()
1758 static inline uint64_t CVMX_PEXP_SLI_PKT_DPADDR_FUNC(void)
1760 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1761 cvmx_warn("CVMX_PEXP_SLI_PKT_DPADDR not supported on this chip\n");
1762 return CVMX_ADD_IO_SEG(0x00011F0000011080ull);
1765 #define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
1767 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1768 #define CVMX_PEXP_SLI_PKT_INPUT_CONTROL CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC()
1769 static inline uint64_t CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC(void)
1771 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1772 cvmx_warn("CVMX_PEXP_SLI_PKT_INPUT_CONTROL not supported on this chip\n");
1773 return CVMX_ADD_IO_SEG(0x00011F0000011170ull);
1776 #define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
1778 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1779 #define CVMX_PEXP_SLI_PKT_INSTR_ENB CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC()
1780 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC(void)
1782 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1783 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_ENB not supported on this chip\n");
1784 return CVMX_ADD_IO_SEG(0x00011F0000011000ull);
1787 #define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
1789 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1790 #define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC()
1791 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
1793 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1794 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n");
1795 return CVMX_ADD_IO_SEG(0x00011F00000111A0ull);
1798 #define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
1800 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1801 #define CVMX_PEXP_SLI_PKT_INSTR_SIZE CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC()
1802 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC(void)
1804 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1805 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_SIZE not supported on this chip\n");
1806 return CVMX_ADD_IO_SEG(0x00011F0000011020ull);
1809 #define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
1811 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1812 #define CVMX_PEXP_SLI_PKT_INT_LEVELS CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC()
1813 static inline uint64_t CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC(void)
1815 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1816 cvmx_warn("CVMX_PEXP_SLI_PKT_INT_LEVELS not supported on this chip\n");
1817 return CVMX_ADD_IO_SEG(0x00011F0000011120ull);
1820 #define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
1822 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1823 #define CVMX_PEXP_SLI_PKT_IN_BP CVMX_PEXP_SLI_PKT_IN_BP_FUNC()
1824 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_BP_FUNC(void)
1826 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1827 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_BP not supported on this chip\n");
1828 return CVMX_ADD_IO_SEG(0x00011F0000011210ull);
1831 #define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
1833 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1834 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
1837 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
1838 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
1839 return CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16;
1842 #define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
1844 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1845 #define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC()
1846 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
1848 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1849 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
1850 return CVMX_ADD_IO_SEG(0x00011F0000011200ull);
1853 #define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
1855 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1856 #define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC()
1857 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC(void)
1859 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1860 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_PCIE_PORT not supported on this chip\n");
1861 return CVMX_ADD_IO_SEG(0x00011F00000111B0ull);
1864 #define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
1866 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1867 #define CVMX_PEXP_SLI_PKT_IPTR CVMX_PEXP_SLI_PKT_IPTR_FUNC()
1868 static inline uint64_t CVMX_PEXP_SLI_PKT_IPTR_FUNC(void)
1870 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1871 cvmx_warn("CVMX_PEXP_SLI_PKT_IPTR not supported on this chip\n");
1872 return CVMX_ADD_IO_SEG(0x00011F0000011070ull);
1875 #define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
1877 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1878 #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC()
1879 static inline uint64_t CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC(void)
1881 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1882 cvmx_warn("CVMX_PEXP_SLI_PKT_OUTPUT_WMARK not supported on this chip\n");
1883 return CVMX_ADD_IO_SEG(0x00011F0000011180ull);
1886 #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
1888 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1889 #define CVMX_PEXP_SLI_PKT_OUT_BMODE CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC()
1890 static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC(void)
1892 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1893 cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_BMODE not supported on this chip\n");
1894 return CVMX_ADD_IO_SEG(0x00011F00000110D0ull);
1897 #define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
1899 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1900 #define CVMX_PEXP_SLI_PKT_OUT_ENB CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC()
1901 static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC(void)
1903 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1904 cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_ENB not supported on this chip\n");
1905 return CVMX_ADD_IO_SEG(0x00011F0000011010ull);
1908 #define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
1910 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1911 #define CVMX_PEXP_SLI_PKT_PCIE_PORT CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC()
1912 static inline uint64_t CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC(void)
1914 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1915 cvmx_warn("CVMX_PEXP_SLI_PKT_PCIE_PORT not supported on this chip\n");
1916 return CVMX_ADD_IO_SEG(0x00011F00000110E0ull);
1919 #define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
1921 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1922 #define CVMX_PEXP_SLI_PKT_PORT_IN_RST CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC()
1923 static inline uint64_t CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC(void)
1925 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1926 cvmx_warn("CVMX_PEXP_SLI_PKT_PORT_IN_RST not supported on this chip\n");
1927 return CVMX_ADD_IO_SEG(0x00011F00000111F0ull);
1930 #define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
1932 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1933 #define CVMX_PEXP_SLI_PKT_SLIST_ES CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC()
1934 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC(void)
1936 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1937 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ES not supported on this chip\n");
1938 return CVMX_ADD_IO_SEG(0x00011F0000011050ull);
1941 #define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
1943 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1944 #define CVMX_PEXP_SLI_PKT_SLIST_NS CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC()
1945 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC(void)
1947 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1948 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_NS not supported on this chip\n");
1949 return CVMX_ADD_IO_SEG(0x00011F0000011040ull);
1952 #define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
1954 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1955 #define CVMX_PEXP_SLI_PKT_SLIST_ROR CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC()
1956 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC(void)
1958 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1959 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ROR not supported on this chip\n");
1960 return CVMX_ADD_IO_SEG(0x00011F0000011030ull);
1963 #define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
1965 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1966 #define CVMX_PEXP_SLI_PKT_TIME_INT CVMX_PEXP_SLI_PKT_TIME_INT_FUNC()
1967 static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_FUNC(void)
1969 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1970 cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT not supported on this chip\n");
1971 return CVMX_ADD_IO_SEG(0x00011F0000011140ull);
1974 #define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
1976 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1977 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC()
1978 static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC(void)
1980 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
1981 cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT_ENB not supported on this chip\n");
1982 return CVMX_ADD_IO_SEG(0x00011F0000011160ull);
1985 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
1987 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1988 static inline uint64_t CVMX_PEXP_SLI_S2M_PORTX_CTL(unsigned long offset)
1991 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
1992 cvmx_warn("CVMX_PEXP_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
1993 return CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16;
1996 #define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
1998 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1999 #define CVMX_PEXP_SLI_SCRATCH_1 CVMX_PEXP_SLI_SCRATCH_1_FUNC()
2000 static inline uint64_t CVMX_PEXP_SLI_SCRATCH_1_FUNC(void)
2002 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
2003 cvmx_warn("CVMX_PEXP_SLI_SCRATCH_1 not supported on this chip\n");
2004 return CVMX_ADD_IO_SEG(0x00011F00000103C0ull);
2007 #define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
2009 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2010 #define CVMX_PEXP_SLI_SCRATCH_2 CVMX_PEXP_SLI_SCRATCH_2_FUNC()
2011 static inline uint64_t CVMX_PEXP_SLI_SCRATCH_2_FUNC(void)
2013 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
2014 cvmx_warn("CVMX_PEXP_SLI_SCRATCH_2 not supported on this chip\n");
2015 return CVMX_ADD_IO_SEG(0x00011F00000103D0ull);
2018 #define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
2020 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2021 #define CVMX_PEXP_SLI_STATE1 CVMX_PEXP_SLI_STATE1_FUNC()
2022 static inline uint64_t CVMX_PEXP_SLI_STATE1_FUNC(void)
2024 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
2025 cvmx_warn("CVMX_PEXP_SLI_STATE1 not supported on this chip\n");
2026 return CVMX_ADD_IO_SEG(0x00011F0000010620ull);
2029 #define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
2031 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2032 #define CVMX_PEXP_SLI_STATE2 CVMX_PEXP_SLI_STATE2_FUNC()
2033 static inline uint64_t CVMX_PEXP_SLI_STATE2_FUNC(void)
2035 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
2036 cvmx_warn("CVMX_PEXP_SLI_STATE2 not supported on this chip\n");
2037 return CVMX_ADD_IO_SEG(0x00011F0000010630ull);
2040 #define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
2042 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2043 #define CVMX_PEXP_SLI_STATE3 CVMX_PEXP_SLI_STATE3_FUNC()
2044 static inline uint64_t CVMX_PEXP_SLI_STATE3_FUNC(void)
2046 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
2047 cvmx_warn("CVMX_PEXP_SLI_STATE3 not supported on this chip\n");
2048 return CVMX_ADD_IO_SEG(0x00011F0000010640ull);
2051 #define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
2053 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2054 #define CVMX_PEXP_SLI_WINDOW_CTL CVMX_PEXP_SLI_WINDOW_CTL_FUNC()
2055 static inline uint64_t CVMX_PEXP_SLI_WINDOW_CTL_FUNC(void)
2057 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
2058 cvmx_warn("CVMX_PEXP_SLI_WINDOW_CTL not supported on this chip\n");
2059 return CVMX_ADD_IO_SEG(0x00011F00000102E0ull);
2062 #define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))