1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
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14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_PKO_TYPEDEFS_H__
53 #define __CVMX_PKO_TYPEDEFS_H__
55 #define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull))
56 #define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull))
57 #define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull))
58 #define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull))
59 #define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull))
60 #define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull))
61 #define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull))
62 #define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull))
63 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
64 #define CVMX_PKO_MEM_DEBUG14 CVMX_PKO_MEM_DEBUG14_FUNC()
65 static inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void)
67 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
68 cvmx_warn("CVMX_PKO_MEM_DEBUG14 not supported on this chip\n");
69 return CVMX_ADD_IO_SEG(0x0001180050001170ull);
72 #define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull))
74 #define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull))
75 #define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull))
76 #define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull))
77 #define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull))
78 #define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull))
79 #define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull))
80 #define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull))
81 #define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull))
82 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
83 #define CVMX_PKO_MEM_PORT_PTRS CVMX_PKO_MEM_PORT_PTRS_FUNC()
84 static inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void)
86 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
87 cvmx_warn("CVMX_PKO_MEM_PORT_PTRS not supported on this chip\n");
88 return CVMX_ADD_IO_SEG(0x0001180050001010ull);
91 #define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull))
93 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
94 #define CVMX_PKO_MEM_PORT_QOS CVMX_PKO_MEM_PORT_QOS_FUNC()
95 static inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void)
97 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
98 cvmx_warn("CVMX_PKO_MEM_PORT_QOS not supported on this chip\n");
99 return CVMX_ADD_IO_SEG(0x0001180050001018ull);
102 #define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull))
104 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
105 #define CVMX_PKO_MEM_PORT_RATE0 CVMX_PKO_MEM_PORT_RATE0_FUNC()
106 static inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void)
108 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
109 cvmx_warn("CVMX_PKO_MEM_PORT_RATE0 not supported on this chip\n");
110 return CVMX_ADD_IO_SEG(0x0001180050001020ull);
113 #define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull))
115 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
116 #define CVMX_PKO_MEM_PORT_RATE1 CVMX_PKO_MEM_PORT_RATE1_FUNC()
117 static inline uint64_t CVMX_PKO_MEM_PORT_RATE1_FUNC(void)
119 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
120 cvmx_warn("CVMX_PKO_MEM_PORT_RATE1 not supported on this chip\n");
121 return CVMX_ADD_IO_SEG(0x0001180050001028ull);
124 #define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull))
126 #define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull))
127 #define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull))
128 #define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull))
129 #define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull))
130 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
131 static inline uint64_t CVMX_PKO_REG_CRC_CTLX(unsigned long offset)
134 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
135 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
136 cvmx_warn("CVMX_PKO_REG_CRC_CTLX(%lu) is invalid on this chip\n", offset);
137 return CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8;
140 #define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8)
142 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
143 #define CVMX_PKO_REG_CRC_ENABLE CVMX_PKO_REG_CRC_ENABLE_FUNC()
144 static inline uint64_t CVMX_PKO_REG_CRC_ENABLE_FUNC(void)
146 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
147 cvmx_warn("CVMX_PKO_REG_CRC_ENABLE not supported on this chip\n");
148 return CVMX_ADD_IO_SEG(0x0001180050000020ull);
151 #define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull))
153 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
154 static inline uint64_t CVMX_PKO_REG_CRC_IVX(unsigned long offset)
157 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
158 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
159 cvmx_warn("CVMX_PKO_REG_CRC_IVX(%lu) is invalid on this chip\n", offset);
160 return CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8;
163 #define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8)
165 #define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull))
166 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
167 #define CVMX_PKO_REG_DEBUG1 CVMX_PKO_REG_DEBUG1_FUNC()
168 static inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void)
170 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
171 cvmx_warn("CVMX_PKO_REG_DEBUG1 not supported on this chip\n");
172 return CVMX_ADD_IO_SEG(0x00011800500000A0ull);
175 #define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull))
177 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
178 #define CVMX_PKO_REG_DEBUG2 CVMX_PKO_REG_DEBUG2_FUNC()
179 static inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void)
181 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
182 cvmx_warn("CVMX_PKO_REG_DEBUG2 not supported on this chip\n");
183 return CVMX_ADD_IO_SEG(0x00011800500000A8ull);
186 #define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull))
188 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
189 #define CVMX_PKO_REG_DEBUG3 CVMX_PKO_REG_DEBUG3_FUNC()
190 static inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void)
192 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
193 cvmx_warn("CVMX_PKO_REG_DEBUG3 not supported on this chip\n");
194 return CVMX_ADD_IO_SEG(0x00011800500000B0ull);
197 #define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull))
199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
200 #define CVMX_PKO_REG_ENGINE_INFLIGHT CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC()
201 static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void)
203 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
204 cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT not supported on this chip\n");
205 return CVMX_ADD_IO_SEG(0x0001180050000050ull);
208 #define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull))
210 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
211 #define CVMX_PKO_REG_ENGINE_THRESH CVMX_PKO_REG_ENGINE_THRESH_FUNC()
212 static inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void)
214 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
215 cvmx_warn("CVMX_PKO_REG_ENGINE_THRESH not supported on this chip\n");
216 return CVMX_ADD_IO_SEG(0x0001180050000058ull);
219 #define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull))
221 #define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull))
222 #define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull))
223 #define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull))
224 #define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull))
225 #define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull))
226 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
227 #define CVMX_PKO_REG_QUEUE_PTRS1 CVMX_PKO_REG_QUEUE_PTRS1_FUNC()
228 static inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void)
230 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
231 cvmx_warn("CVMX_PKO_REG_QUEUE_PTRS1 not supported on this chip\n");
232 return CVMX_ADD_IO_SEG(0x0001180050000100ull);
235 #define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull))
237 #define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull))
238 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
239 #define CVMX_PKO_REG_TIMESTAMP CVMX_PKO_REG_TIMESTAMP_FUNC()
240 static inline uint64_t CVMX_PKO_REG_TIMESTAMP_FUNC(void)
242 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
243 cvmx_warn("CVMX_PKO_REG_TIMESTAMP not supported on this chip\n");
244 return CVMX_ADD_IO_SEG(0x0001180050000060ull);
247 #define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull))
251 * cvmx_pko_mem_count0
254 * Total number of packets seen by PKO, per port
255 * A write to this address will clear the entry whose index is specified as COUNT[5:0].
256 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
257 * CSR read operations to this address can be performed. A read of any entry that has not been
258 * previously written is illegal and will result in unpredictable CSR read data.
260 union cvmx_pko_mem_count0
263 struct cvmx_pko_mem_count0_s
265 #if __BYTE_ORDER == __BIG_ENDIAN
266 uint64_t reserved_32_63 : 32;
267 uint64_t count : 32; /**< Total number of packets seen by PKO */
270 uint64_t reserved_32_63 : 32;
273 struct cvmx_pko_mem_count0_s cn30xx;
274 struct cvmx_pko_mem_count0_s cn31xx;
275 struct cvmx_pko_mem_count0_s cn38xx;
276 struct cvmx_pko_mem_count0_s cn38xxp2;
277 struct cvmx_pko_mem_count0_s cn50xx;
278 struct cvmx_pko_mem_count0_s cn52xx;
279 struct cvmx_pko_mem_count0_s cn52xxp1;
280 struct cvmx_pko_mem_count0_s cn56xx;
281 struct cvmx_pko_mem_count0_s cn56xxp1;
282 struct cvmx_pko_mem_count0_s cn58xx;
283 struct cvmx_pko_mem_count0_s cn58xxp1;
284 struct cvmx_pko_mem_count0_s cn63xx;
285 struct cvmx_pko_mem_count0_s cn63xxp1;
287 typedef union cvmx_pko_mem_count0 cvmx_pko_mem_count0_t;
290 * cvmx_pko_mem_count1
293 * Total number of bytes seen by PKO, per port
294 * A write to this address will clear the entry whose index is specified as COUNT[5:0].
295 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
296 * CSR read operations to this address can be performed. A read of any entry that has not been
297 * previously written is illegal and will result in unpredictable CSR read data.
299 union cvmx_pko_mem_count1
302 struct cvmx_pko_mem_count1_s
304 #if __BYTE_ORDER == __BIG_ENDIAN
305 uint64_t reserved_48_63 : 16;
306 uint64_t count : 48; /**< Total number of bytes seen by PKO */
309 uint64_t reserved_48_63 : 16;
312 struct cvmx_pko_mem_count1_s cn30xx;
313 struct cvmx_pko_mem_count1_s cn31xx;
314 struct cvmx_pko_mem_count1_s cn38xx;
315 struct cvmx_pko_mem_count1_s cn38xxp2;
316 struct cvmx_pko_mem_count1_s cn50xx;
317 struct cvmx_pko_mem_count1_s cn52xx;
318 struct cvmx_pko_mem_count1_s cn52xxp1;
319 struct cvmx_pko_mem_count1_s cn56xx;
320 struct cvmx_pko_mem_count1_s cn56xxp1;
321 struct cvmx_pko_mem_count1_s cn58xx;
322 struct cvmx_pko_mem_count1_s cn58xxp1;
323 struct cvmx_pko_mem_count1_s cn63xx;
324 struct cvmx_pko_mem_count1_s cn63xxp1;
326 typedef union cvmx_pko_mem_count1 cvmx_pko_mem_count1_t;
329 * cvmx_pko_mem_debug0
332 * Internal per-port state intended for debug use only - pko_prt_psb.cmnd[63:0]
333 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
334 * CSR read operations to this address can be performed.
336 union cvmx_pko_mem_debug0
339 struct cvmx_pko_mem_debug0_s
341 #if __BYTE_ORDER == __BIG_ENDIAN
342 uint64_t fau : 28; /**< Fetch and add command words */
343 uint64_t cmd : 14; /**< Command word */
344 uint64_t segs : 6; /**< Number of segments/gather size */
345 uint64_t size : 16; /**< Packet length in bytes */
353 struct cvmx_pko_mem_debug0_s cn30xx;
354 struct cvmx_pko_mem_debug0_s cn31xx;
355 struct cvmx_pko_mem_debug0_s cn38xx;
356 struct cvmx_pko_mem_debug0_s cn38xxp2;
357 struct cvmx_pko_mem_debug0_s cn50xx;
358 struct cvmx_pko_mem_debug0_s cn52xx;
359 struct cvmx_pko_mem_debug0_s cn52xxp1;
360 struct cvmx_pko_mem_debug0_s cn56xx;
361 struct cvmx_pko_mem_debug0_s cn56xxp1;
362 struct cvmx_pko_mem_debug0_s cn58xx;
363 struct cvmx_pko_mem_debug0_s cn58xxp1;
364 struct cvmx_pko_mem_debug0_s cn63xx;
365 struct cvmx_pko_mem_debug0_s cn63xxp1;
367 typedef union cvmx_pko_mem_debug0 cvmx_pko_mem_debug0_t;
370 * cvmx_pko_mem_debug1
373 * Internal per-port state intended for debug use only - pko_prt_psb.curr[63:0]
374 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
375 * CSR read operations to this address can be performed.
377 union cvmx_pko_mem_debug1
380 struct cvmx_pko_mem_debug1_s
382 #if __BYTE_ORDER == __BIG_ENDIAN
383 uint64_t i : 1; /**< "I" value used for free operation */
384 uint64_t back : 4; /**< Back value used for free operation */
385 uint64_t pool : 3; /**< Pool value used for free operation */
386 uint64_t size : 16; /**< Size in bytes */
387 uint64_t ptr : 40; /**< Data pointer */
396 struct cvmx_pko_mem_debug1_s cn30xx;
397 struct cvmx_pko_mem_debug1_s cn31xx;
398 struct cvmx_pko_mem_debug1_s cn38xx;
399 struct cvmx_pko_mem_debug1_s cn38xxp2;
400 struct cvmx_pko_mem_debug1_s cn50xx;
401 struct cvmx_pko_mem_debug1_s cn52xx;
402 struct cvmx_pko_mem_debug1_s cn52xxp1;
403 struct cvmx_pko_mem_debug1_s cn56xx;
404 struct cvmx_pko_mem_debug1_s cn56xxp1;
405 struct cvmx_pko_mem_debug1_s cn58xx;
406 struct cvmx_pko_mem_debug1_s cn58xxp1;
407 struct cvmx_pko_mem_debug1_s cn63xx;
408 struct cvmx_pko_mem_debug1_s cn63xxp1;
410 typedef union cvmx_pko_mem_debug1 cvmx_pko_mem_debug1_t;
413 * cvmx_pko_mem_debug10
416 * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs1, pko.dat.ptr.ptrs2
417 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
418 * CSR read operations to this address can be performed.
420 union cvmx_pko_mem_debug10
423 struct cvmx_pko_mem_debug10_s
425 #if __BYTE_ORDER == __BIG_ENDIAN
426 uint64_t reserved_0_63 : 64;
428 uint64_t reserved_0_63 : 64;
431 struct cvmx_pko_mem_debug10_cn30xx
433 #if __BYTE_ORDER == __BIG_ENDIAN
434 uint64_t fau : 28; /**< Fetch and add command words */
435 uint64_t cmd : 14; /**< Command word */
436 uint64_t segs : 6; /**< Number of segments/gather size */
437 uint64_t size : 16; /**< Packet length in bytes */
445 struct cvmx_pko_mem_debug10_cn30xx cn31xx;
446 struct cvmx_pko_mem_debug10_cn30xx cn38xx;
447 struct cvmx_pko_mem_debug10_cn30xx cn38xxp2;
448 struct cvmx_pko_mem_debug10_cn50xx
450 #if __BYTE_ORDER == __BIG_ENDIAN
451 uint64_t reserved_49_63 : 15;
452 uint64_t ptrs1 : 17; /**< Internal state */
453 uint64_t reserved_17_31 : 15;
454 uint64_t ptrs2 : 17; /**< Internal state */
457 uint64_t reserved_17_31 : 15;
459 uint64_t reserved_49_63 : 15;
462 struct cvmx_pko_mem_debug10_cn50xx cn52xx;
463 struct cvmx_pko_mem_debug10_cn50xx cn52xxp1;
464 struct cvmx_pko_mem_debug10_cn50xx cn56xx;
465 struct cvmx_pko_mem_debug10_cn50xx cn56xxp1;
466 struct cvmx_pko_mem_debug10_cn50xx cn58xx;
467 struct cvmx_pko_mem_debug10_cn50xx cn58xxp1;
468 struct cvmx_pko_mem_debug10_cn50xx cn63xx;
469 struct cvmx_pko_mem_debug10_cn50xx cn63xxp1;
471 typedef union cvmx_pko_mem_debug10 cvmx_pko_mem_debug10_t;
474 * cvmx_pko_mem_debug11
477 * Internal per-port state intended for debug use only - pko.out.sta.state[22:0]
478 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
479 * CSR read operations to this address can be performed.
481 union cvmx_pko_mem_debug11
484 struct cvmx_pko_mem_debug11_s
486 #if __BYTE_ORDER == __BIG_ENDIAN
487 uint64_t i : 1; /**< "I" value used for free operation */
488 uint64_t back : 4; /**< Back value used for free operation */
489 uint64_t pool : 3; /**< Pool value used for free operation */
490 uint64_t size : 16; /**< Size in bytes */
491 uint64_t reserved_0_39 : 40;
493 uint64_t reserved_0_39 : 40;
500 struct cvmx_pko_mem_debug11_cn30xx
502 #if __BYTE_ORDER == __BIG_ENDIAN
503 uint64_t i : 1; /**< "I" value used for free operation */
504 uint64_t back : 4; /**< Back value used for free operation */
505 uint64_t pool : 3; /**< Pool value used for free operation */
506 uint64_t size : 16; /**< Size in bytes */
507 uint64_t ptr : 40; /**< Data pointer */
516 struct cvmx_pko_mem_debug11_cn30xx cn31xx;
517 struct cvmx_pko_mem_debug11_cn30xx cn38xx;
518 struct cvmx_pko_mem_debug11_cn30xx cn38xxp2;
519 struct cvmx_pko_mem_debug11_cn50xx
521 #if __BYTE_ORDER == __BIG_ENDIAN
522 uint64_t reserved_23_63 : 41;
523 uint64_t maj : 1; /**< Internal state */
524 uint64_t uid : 3; /**< Internal state */
525 uint64_t sop : 1; /**< Internal state */
526 uint64_t len : 1; /**< Internal state */
527 uint64_t chk : 1; /**< Internal state */
528 uint64_t cnt : 13; /**< Internal state */
529 uint64_t mod : 3; /**< Internal state */
538 uint64_t reserved_23_63 : 41;
541 struct cvmx_pko_mem_debug11_cn50xx cn52xx;
542 struct cvmx_pko_mem_debug11_cn50xx cn52xxp1;
543 struct cvmx_pko_mem_debug11_cn50xx cn56xx;
544 struct cvmx_pko_mem_debug11_cn50xx cn56xxp1;
545 struct cvmx_pko_mem_debug11_cn50xx cn58xx;
546 struct cvmx_pko_mem_debug11_cn50xx cn58xxp1;
547 struct cvmx_pko_mem_debug11_cn50xx cn63xx;
548 struct cvmx_pko_mem_debug11_cn50xx cn63xxp1;
550 typedef union cvmx_pko_mem_debug11 cvmx_pko_mem_debug11_t;
553 * cvmx_pko_mem_debug12
556 * Internal per-port state intended for debug use only - pko.out.ctl.cmnd[63:0]
557 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
558 * CSR read operations to this address can be performed.
560 union cvmx_pko_mem_debug12
563 struct cvmx_pko_mem_debug12_s
565 #if __BYTE_ORDER == __BIG_ENDIAN
566 uint64_t reserved_0_63 : 64;
568 uint64_t reserved_0_63 : 64;
571 struct cvmx_pko_mem_debug12_cn30xx
573 #if __BYTE_ORDER == __BIG_ENDIAN
574 uint64_t data : 64; /**< WorkQ data or Store0 pointer */
579 struct cvmx_pko_mem_debug12_cn30xx cn31xx;
580 struct cvmx_pko_mem_debug12_cn30xx cn38xx;
581 struct cvmx_pko_mem_debug12_cn30xx cn38xxp2;
582 struct cvmx_pko_mem_debug12_cn50xx
584 #if __BYTE_ORDER == __BIG_ENDIAN
585 uint64_t fau : 28; /**< Fetch and add command words */
586 uint64_t cmd : 14; /**< Command word */
587 uint64_t segs : 6; /**< Number of segments/gather size */
588 uint64_t size : 16; /**< Packet length in bytes */
596 struct cvmx_pko_mem_debug12_cn50xx cn52xx;
597 struct cvmx_pko_mem_debug12_cn50xx cn52xxp1;
598 struct cvmx_pko_mem_debug12_cn50xx cn56xx;
599 struct cvmx_pko_mem_debug12_cn50xx cn56xxp1;
600 struct cvmx_pko_mem_debug12_cn50xx cn58xx;
601 struct cvmx_pko_mem_debug12_cn50xx cn58xxp1;
602 struct cvmx_pko_mem_debug12_cn50xx cn63xx;
603 struct cvmx_pko_mem_debug12_cn50xx cn63xxp1;
605 typedef union cvmx_pko_mem_debug12 cvmx_pko_mem_debug12_t;
608 * cvmx_pko_mem_debug13
611 * Internal per-port state intended for debug use only - pko.out.ctl.head[63:0]
612 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
613 * CSR read operations to this address can be performed.
615 union cvmx_pko_mem_debug13
618 struct cvmx_pko_mem_debug13_s
620 #if __BYTE_ORDER == __BIG_ENDIAN
621 uint64_t i : 1; /**< "I" value used for free operation */
622 uint64_t back : 4; /**< Back value used for free operation */
623 uint64_t pool : 3; /**< Pool value used for free operation */
624 uint64_t reserved_0_55 : 56;
626 uint64_t reserved_0_55 : 56;
632 struct cvmx_pko_mem_debug13_cn30xx
634 #if __BYTE_ORDER == __BIG_ENDIAN
635 uint64_t reserved_51_63 : 13;
636 uint64_t widx : 17; /**< PDB widx */
637 uint64_t ridx2 : 17; /**< PDB ridx2 */
638 uint64_t widx2 : 17; /**< PDB widx2 */
643 uint64_t reserved_51_63 : 13;
646 struct cvmx_pko_mem_debug13_cn30xx cn31xx;
647 struct cvmx_pko_mem_debug13_cn30xx cn38xx;
648 struct cvmx_pko_mem_debug13_cn30xx cn38xxp2;
649 struct cvmx_pko_mem_debug13_cn50xx
651 #if __BYTE_ORDER == __BIG_ENDIAN
652 uint64_t i : 1; /**< "I" value used for free operation */
653 uint64_t back : 4; /**< Back value used for free operation */
654 uint64_t pool : 3; /**< Pool value used for free operation */
655 uint64_t size : 16; /**< Size in bytes */
656 uint64_t ptr : 40; /**< Data pointer */
665 struct cvmx_pko_mem_debug13_cn50xx cn52xx;
666 struct cvmx_pko_mem_debug13_cn50xx cn52xxp1;
667 struct cvmx_pko_mem_debug13_cn50xx cn56xx;
668 struct cvmx_pko_mem_debug13_cn50xx cn56xxp1;
669 struct cvmx_pko_mem_debug13_cn50xx cn58xx;
670 struct cvmx_pko_mem_debug13_cn50xx cn58xxp1;
671 struct cvmx_pko_mem_debug13_cn50xx cn63xx;
672 struct cvmx_pko_mem_debug13_cn50xx cn63xxp1;
674 typedef union cvmx_pko_mem_debug13 cvmx_pko_mem_debug13_t;
677 * cvmx_pko_mem_debug14
680 * Internal per-port state intended for debug use only - pko.prt.psb.save[63:0]
681 * This CSR is a memory of 132 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
682 * CSR read operations to this address can be performed.
684 union cvmx_pko_mem_debug14
687 struct cvmx_pko_mem_debug14_s
689 #if __BYTE_ORDER == __BIG_ENDIAN
690 uint64_t reserved_0_63 : 64;
692 uint64_t reserved_0_63 : 64;
695 struct cvmx_pko_mem_debug14_cn30xx
697 #if __BYTE_ORDER == __BIG_ENDIAN
698 uint64_t reserved_17_63 : 47;
699 uint64_t ridx : 17; /**< PDB ridx */
702 uint64_t reserved_17_63 : 47;
705 struct cvmx_pko_mem_debug14_cn30xx cn31xx;
706 struct cvmx_pko_mem_debug14_cn30xx cn38xx;
707 struct cvmx_pko_mem_debug14_cn30xx cn38xxp2;
708 struct cvmx_pko_mem_debug14_cn52xx
710 #if __BYTE_ORDER == __BIG_ENDIAN
711 uint64_t data : 64; /**< Command words */
716 struct cvmx_pko_mem_debug14_cn52xx cn52xxp1;
717 struct cvmx_pko_mem_debug14_cn52xx cn56xx;
718 struct cvmx_pko_mem_debug14_cn52xx cn56xxp1;
719 struct cvmx_pko_mem_debug14_cn52xx cn63xx;
720 struct cvmx_pko_mem_debug14_cn52xx cn63xxp1;
722 typedef union cvmx_pko_mem_debug14 cvmx_pko_mem_debug14_t;
725 * cvmx_pko_mem_debug2
728 * Internal per-port state intended for debug use only - pko_prt_psb.head[63:0]
729 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
730 * CSR read operations to this address can be performed.
732 union cvmx_pko_mem_debug2
735 struct cvmx_pko_mem_debug2_s
737 #if __BYTE_ORDER == __BIG_ENDIAN
738 uint64_t i : 1; /**< "I" value used for free operation */
739 uint64_t back : 4; /**< Back value used for free operation */
740 uint64_t pool : 3; /**< Pool value used for free operation */
741 uint64_t size : 16; /**< Size in bytes */
742 uint64_t ptr : 40; /**< Data pointer */
751 struct cvmx_pko_mem_debug2_s cn30xx;
752 struct cvmx_pko_mem_debug2_s cn31xx;
753 struct cvmx_pko_mem_debug2_s cn38xx;
754 struct cvmx_pko_mem_debug2_s cn38xxp2;
755 struct cvmx_pko_mem_debug2_s cn50xx;
756 struct cvmx_pko_mem_debug2_s cn52xx;
757 struct cvmx_pko_mem_debug2_s cn52xxp1;
758 struct cvmx_pko_mem_debug2_s cn56xx;
759 struct cvmx_pko_mem_debug2_s cn56xxp1;
760 struct cvmx_pko_mem_debug2_s cn58xx;
761 struct cvmx_pko_mem_debug2_s cn58xxp1;
762 struct cvmx_pko_mem_debug2_s cn63xx;
763 struct cvmx_pko_mem_debug2_s cn63xxp1;
765 typedef union cvmx_pko_mem_debug2 cvmx_pko_mem_debug2_t;
768 * cvmx_pko_mem_debug3
771 * Internal per-port state intended for debug use only - pko_prt_psb.resp[63:0]
772 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
773 * CSR read operations to this address can be performed.
775 union cvmx_pko_mem_debug3
778 struct cvmx_pko_mem_debug3_s
780 #if __BYTE_ORDER == __BIG_ENDIAN
781 uint64_t reserved_0_63 : 64;
783 uint64_t reserved_0_63 : 64;
786 struct cvmx_pko_mem_debug3_cn30xx
788 #if __BYTE_ORDER == __BIG_ENDIAN
789 uint64_t i : 1; /**< "I" value used for free operation */
790 uint64_t back : 4; /**< Back value used for free operation */
791 uint64_t pool : 3; /**< Pool value used for free operation */
792 uint64_t size : 16; /**< Size in bytes */
793 uint64_t ptr : 40; /**< Data pointer */
802 struct cvmx_pko_mem_debug3_cn30xx cn31xx;
803 struct cvmx_pko_mem_debug3_cn30xx cn38xx;
804 struct cvmx_pko_mem_debug3_cn30xx cn38xxp2;
805 struct cvmx_pko_mem_debug3_cn50xx
807 #if __BYTE_ORDER == __BIG_ENDIAN
808 uint64_t data : 64; /**< WorkQ data or Store0 pointer */
813 struct cvmx_pko_mem_debug3_cn50xx cn52xx;
814 struct cvmx_pko_mem_debug3_cn50xx cn52xxp1;
815 struct cvmx_pko_mem_debug3_cn50xx cn56xx;
816 struct cvmx_pko_mem_debug3_cn50xx cn56xxp1;
817 struct cvmx_pko_mem_debug3_cn50xx cn58xx;
818 struct cvmx_pko_mem_debug3_cn50xx cn58xxp1;
819 struct cvmx_pko_mem_debug3_cn50xx cn63xx;
820 struct cvmx_pko_mem_debug3_cn50xx cn63xxp1;
822 typedef union cvmx_pko_mem_debug3 cvmx_pko_mem_debug3_t;
825 * cvmx_pko_mem_debug4
828 * Internal per-port state intended for debug use only - pko_prt_psb.state[63:0]
829 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
830 * CSR read operations to this address can be performed.
832 union cvmx_pko_mem_debug4
835 struct cvmx_pko_mem_debug4_s
837 #if __BYTE_ORDER == __BIG_ENDIAN
838 uint64_t reserved_0_63 : 64;
840 uint64_t reserved_0_63 : 64;
843 struct cvmx_pko_mem_debug4_cn30xx
845 #if __BYTE_ORDER == __BIG_ENDIAN
846 uint64_t data : 64; /**< WorkQ data or Store0 pointer */
851 struct cvmx_pko_mem_debug4_cn30xx cn31xx;
852 struct cvmx_pko_mem_debug4_cn30xx cn38xx;
853 struct cvmx_pko_mem_debug4_cn30xx cn38xxp2;
854 struct cvmx_pko_mem_debug4_cn50xx
856 #if __BYTE_ORDER == __BIG_ENDIAN
857 uint64_t cmnd_segs : 3; /**< Internal state */
858 uint64_t cmnd_siz : 16; /**< Internal state */
859 uint64_t cmnd_off : 6; /**< Internal state */
860 uint64_t uid : 3; /**< Internal state */
861 uint64_t dread_sop : 1; /**< Internal state */
862 uint64_t init_dwrite : 1; /**< Internal state */
863 uint64_t chk_once : 1; /**< Internal state */
864 uint64_t chk_mode : 1; /**< Internal state */
865 uint64_t active : 1; /**< Internal state */
866 uint64_t static_p : 1; /**< Internal state */
867 uint64_t qos : 3; /**< Internal state */
868 uint64_t qcb_ridx : 5; /**< Internal state */
869 uint64_t qid_off_max : 4; /**< Internal state */
870 uint64_t qid_off : 4; /**< Internal state */
871 uint64_t qid_base : 8; /**< Internal state */
872 uint64_t wait : 1; /**< Internal state */
873 uint64_t minor : 2; /**< Internal state */
874 uint64_t major : 3; /**< Internal state */
879 uint64_t qid_base : 8;
880 uint64_t qid_off : 4;
881 uint64_t qid_off_max : 4;
882 uint64_t qcb_ridx : 5;
884 uint64_t static_p : 1;
886 uint64_t chk_mode : 1;
887 uint64_t chk_once : 1;
888 uint64_t init_dwrite : 1;
889 uint64_t dread_sop : 1;
891 uint64_t cmnd_off : 6;
892 uint64_t cmnd_siz : 16;
893 uint64_t cmnd_segs : 3;
896 struct cvmx_pko_mem_debug4_cn52xx
898 #if __BYTE_ORDER == __BIG_ENDIAN
899 uint64_t curr_siz : 8; /**< Internal state */
900 uint64_t curr_off : 16; /**< Internal state */
901 uint64_t cmnd_segs : 6; /**< Internal state */
902 uint64_t cmnd_siz : 16; /**< Internal state */
903 uint64_t cmnd_off : 6; /**< Internal state */
904 uint64_t uid : 2; /**< Internal state */
905 uint64_t dread_sop : 1; /**< Internal state */
906 uint64_t init_dwrite : 1; /**< Internal state */
907 uint64_t chk_once : 1; /**< Internal state */
908 uint64_t chk_mode : 1; /**< Internal state */
909 uint64_t wait : 1; /**< Internal state */
910 uint64_t minor : 2; /**< Internal state */
911 uint64_t major : 3; /**< Internal state */
916 uint64_t chk_mode : 1;
917 uint64_t chk_once : 1;
918 uint64_t init_dwrite : 1;
919 uint64_t dread_sop : 1;
921 uint64_t cmnd_off : 6;
922 uint64_t cmnd_siz : 16;
923 uint64_t cmnd_segs : 6;
924 uint64_t curr_off : 16;
925 uint64_t curr_siz : 8;
928 struct cvmx_pko_mem_debug4_cn52xx cn52xxp1;
929 struct cvmx_pko_mem_debug4_cn52xx cn56xx;
930 struct cvmx_pko_mem_debug4_cn52xx cn56xxp1;
931 struct cvmx_pko_mem_debug4_cn50xx cn58xx;
932 struct cvmx_pko_mem_debug4_cn50xx cn58xxp1;
933 struct cvmx_pko_mem_debug4_cn52xx cn63xx;
934 struct cvmx_pko_mem_debug4_cn52xx cn63xxp1;
936 typedef union cvmx_pko_mem_debug4 cvmx_pko_mem_debug4_t;
939 * cvmx_pko_mem_debug5
942 * Internal per-port state intended for debug use only - pko_prt_psb.state[127:64]
943 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
944 * CSR read operations to this address can be performed.
946 union cvmx_pko_mem_debug5
949 struct cvmx_pko_mem_debug5_s
951 #if __BYTE_ORDER == __BIG_ENDIAN
952 uint64_t reserved_0_63 : 64;
954 uint64_t reserved_0_63 : 64;
957 struct cvmx_pko_mem_debug5_cn30xx
959 #if __BYTE_ORDER == __BIG_ENDIAN
960 uint64_t dwri_mod : 1; /**< Dwrite mod */
961 uint64_t dwri_sop : 1; /**< Dwrite sop needed */
962 uint64_t dwri_len : 1; /**< Dwrite len */
963 uint64_t dwri_cnt : 13; /**< Dwrite count */
964 uint64_t cmnd_siz : 16; /**< Copy of cmnd.size */
965 uint64_t uid : 1; /**< UID */
966 uint64_t xfer_wor : 1; /**< Transfer work needed */
967 uint64_t xfer_dwr : 1; /**< Transfer dwrite needed */
968 uint64_t cbuf_fre : 1; /**< Cbuf needs free */
969 uint64_t reserved_27_27 : 1;
970 uint64_t chk_mode : 1; /**< Checksum mode */
971 uint64_t active : 1; /**< Port is active */
972 uint64_t qos : 3; /**< Current QOS round */
973 uint64_t qcb_ridx : 5; /**< Buffer read index for QCB */
974 uint64_t qid_off : 3; /**< Offset to be added to QID_BASE for current queue */
975 uint64_t qid_base : 7; /**< Absolute QID of the queue array base = &QUEUES[0] */
976 uint64_t wait : 1; /**< State wait when set */
977 uint64_t minor : 2; /**< State minor code */
978 uint64_t major : 4; /**< State major code */
983 uint64_t qid_base : 7;
984 uint64_t qid_off : 3;
985 uint64_t qcb_ridx : 5;
988 uint64_t chk_mode : 1;
989 uint64_t reserved_27_27 : 1;
990 uint64_t cbuf_fre : 1;
991 uint64_t xfer_dwr : 1;
992 uint64_t xfer_wor : 1;
994 uint64_t cmnd_siz : 16;
995 uint64_t dwri_cnt : 13;
996 uint64_t dwri_len : 1;
997 uint64_t dwri_sop : 1;
998 uint64_t dwri_mod : 1;
1001 struct cvmx_pko_mem_debug5_cn30xx cn31xx;
1002 struct cvmx_pko_mem_debug5_cn30xx cn38xx;
1003 struct cvmx_pko_mem_debug5_cn30xx cn38xxp2;
1004 struct cvmx_pko_mem_debug5_cn50xx
1006 #if __BYTE_ORDER == __BIG_ENDIAN
1007 uint64_t curr_ptr : 29; /**< Internal state */
1008 uint64_t curr_siz : 16; /**< Internal state */
1009 uint64_t curr_off : 16; /**< Internal state */
1010 uint64_t cmnd_segs : 3; /**< Internal state */
1012 uint64_t cmnd_segs : 3;
1013 uint64_t curr_off : 16;
1014 uint64_t curr_siz : 16;
1015 uint64_t curr_ptr : 29;
1018 struct cvmx_pko_mem_debug5_cn52xx
1020 #if __BYTE_ORDER == __BIG_ENDIAN
1021 uint64_t reserved_54_63 : 10;
1022 uint64_t nxt_inflt : 6; /**< Internal state */
1023 uint64_t curr_ptr : 40; /**< Internal state */
1024 uint64_t curr_siz : 8; /**< Internal state */
1026 uint64_t curr_siz : 8;
1027 uint64_t curr_ptr : 40;
1028 uint64_t nxt_inflt : 6;
1029 uint64_t reserved_54_63 : 10;
1032 struct cvmx_pko_mem_debug5_cn52xx cn52xxp1;
1033 struct cvmx_pko_mem_debug5_cn52xx cn56xx;
1034 struct cvmx_pko_mem_debug5_cn52xx cn56xxp1;
1035 struct cvmx_pko_mem_debug5_cn50xx cn58xx;
1036 struct cvmx_pko_mem_debug5_cn50xx cn58xxp1;
1037 struct cvmx_pko_mem_debug5_cn63xx
1039 #if __BYTE_ORDER == __BIG_ENDIAN
1040 uint64_t reserved_56_63 : 8;
1041 uint64_t ptp : 1; /**< Internal state */
1042 uint64_t major_3 : 1; /**< Internal state */
1043 uint64_t nxt_inflt : 6; /**< Internal state */
1044 uint64_t curr_ptr : 40; /**< Internal state */
1045 uint64_t curr_siz : 8; /**< Internal state */
1047 uint64_t curr_siz : 8;
1048 uint64_t curr_ptr : 40;
1049 uint64_t nxt_inflt : 6;
1050 uint64_t major_3 : 1;
1052 uint64_t reserved_56_63 : 8;
1055 struct cvmx_pko_mem_debug5_cn63xx cn63xxp1;
1057 typedef union cvmx_pko_mem_debug5 cvmx_pko_mem_debug5_t;
1060 * cvmx_pko_mem_debug6
1063 * Internal per-port state intended for debug use only - pko_prt_psb.port[63:0]
1064 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
1065 * CSR read operations to this address can be performed.
1067 union cvmx_pko_mem_debug6
1070 struct cvmx_pko_mem_debug6_s
1072 #if __BYTE_ORDER == __BIG_ENDIAN
1073 uint64_t reserved_37_63 : 27;
1074 uint64_t qid_offres : 4; /**< Internal state */
1075 uint64_t qid_offths : 4; /**< Internal state */
1076 uint64_t preempter : 1; /**< Internal state */
1077 uint64_t preemptee : 1; /**< Internal state */
1078 uint64_t preempted : 1; /**< Internal state */
1079 uint64_t active : 1; /**< Internal state */
1080 uint64_t statc : 1; /**< Internal state */
1081 uint64_t qos : 3; /**< Internal state */
1082 uint64_t qcb_ridx : 5; /**< Internal state */
1083 uint64_t qid_offmax : 4; /**< Internal state */
1084 uint64_t reserved_0_11 : 12;
1086 uint64_t reserved_0_11 : 12;
1087 uint64_t qid_offmax : 4;
1088 uint64_t qcb_ridx : 5;
1091 uint64_t active : 1;
1092 uint64_t preempted : 1;
1093 uint64_t preemptee : 1;
1094 uint64_t preempter : 1;
1095 uint64_t qid_offths : 4;
1096 uint64_t qid_offres : 4;
1097 uint64_t reserved_37_63 : 27;
1100 struct cvmx_pko_mem_debug6_cn30xx
1102 #if __BYTE_ORDER == __BIG_ENDIAN
1103 uint64_t reserved_11_63 : 53;
1104 uint64_t qid_offm : 3; /**< Qid offset max */
1105 uint64_t static_p : 1; /**< Static port when set */
1106 uint64_t work_min : 3; /**< Work minor */
1107 uint64_t dwri_chk : 1; /**< Dwrite checksum mode */
1108 uint64_t dwri_uid : 1; /**< Dwrite UID */
1109 uint64_t dwri_mod : 2; /**< Dwrite mod */
1111 uint64_t dwri_mod : 2;
1112 uint64_t dwri_uid : 1;
1113 uint64_t dwri_chk : 1;
1114 uint64_t work_min : 3;
1115 uint64_t static_p : 1;
1116 uint64_t qid_offm : 3;
1117 uint64_t reserved_11_63 : 53;
1120 struct cvmx_pko_mem_debug6_cn30xx cn31xx;
1121 struct cvmx_pko_mem_debug6_cn30xx cn38xx;
1122 struct cvmx_pko_mem_debug6_cn30xx cn38xxp2;
1123 struct cvmx_pko_mem_debug6_cn50xx
1125 #if __BYTE_ORDER == __BIG_ENDIAN
1126 uint64_t reserved_11_63 : 53;
1127 uint64_t curr_ptr : 11; /**< Internal state */
1129 uint64_t curr_ptr : 11;
1130 uint64_t reserved_11_63 : 53;
1133 struct cvmx_pko_mem_debug6_cn52xx
1135 #if __BYTE_ORDER == __BIG_ENDIAN
1136 uint64_t reserved_37_63 : 27;
1137 uint64_t qid_offres : 4; /**< Internal state */
1138 uint64_t qid_offths : 4; /**< Internal state */
1139 uint64_t preempter : 1; /**< Internal state */
1140 uint64_t preemptee : 1; /**< Internal state */
1141 uint64_t preempted : 1; /**< Internal state */
1142 uint64_t active : 1; /**< Internal state */
1143 uint64_t statc : 1; /**< Internal state */
1144 uint64_t qos : 3; /**< Internal state */
1145 uint64_t qcb_ridx : 5; /**< Internal state */
1146 uint64_t qid_offmax : 4; /**< Internal state */
1147 uint64_t qid_off : 4; /**< Internal state */
1148 uint64_t qid_base : 8; /**< Internal state */
1150 uint64_t qid_base : 8;
1151 uint64_t qid_off : 4;
1152 uint64_t qid_offmax : 4;
1153 uint64_t qcb_ridx : 5;
1156 uint64_t active : 1;
1157 uint64_t preempted : 1;
1158 uint64_t preemptee : 1;
1159 uint64_t preempter : 1;
1160 uint64_t qid_offths : 4;
1161 uint64_t qid_offres : 4;
1162 uint64_t reserved_37_63 : 27;
1165 struct cvmx_pko_mem_debug6_cn52xx cn52xxp1;
1166 struct cvmx_pko_mem_debug6_cn52xx cn56xx;
1167 struct cvmx_pko_mem_debug6_cn52xx cn56xxp1;
1168 struct cvmx_pko_mem_debug6_cn50xx cn58xx;
1169 struct cvmx_pko_mem_debug6_cn50xx cn58xxp1;
1170 struct cvmx_pko_mem_debug6_cn52xx cn63xx;
1171 struct cvmx_pko_mem_debug6_cn52xx cn63xxp1;
1173 typedef union cvmx_pko_mem_debug6 cvmx_pko_mem_debug6_t;
1176 * cvmx_pko_mem_debug7
1179 * Internal per-queue state intended for debug use only - pko_prt_qsb.state[63:0]
1180 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
1181 * CSR read operations to this address can be performed.
1183 union cvmx_pko_mem_debug7
1186 struct cvmx_pko_mem_debug7_s
1188 #if __BYTE_ORDER == __BIG_ENDIAN
1189 uint64_t qos : 5; /**< QOS mask to enable the queue when set */
1190 uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */
1191 uint64_t reserved_0_57 : 58;
1193 uint64_t reserved_0_57 : 58;
1198 struct cvmx_pko_mem_debug7_cn30xx
1200 #if __BYTE_ORDER == __BIG_ENDIAN
1201 uint64_t reserved_58_63 : 6;
1202 uint64_t dwb : 9; /**< Calculated DWB count used for free operation */
1203 uint64_t start : 33; /**< Calculated start address used for free operation */
1204 uint64_t size : 16; /**< Packet length in bytes */
1207 uint64_t start : 33;
1209 uint64_t reserved_58_63 : 6;
1212 struct cvmx_pko_mem_debug7_cn30xx cn31xx;
1213 struct cvmx_pko_mem_debug7_cn30xx cn38xx;
1214 struct cvmx_pko_mem_debug7_cn30xx cn38xxp2;
1215 struct cvmx_pko_mem_debug7_cn50xx
1217 #if __BYTE_ORDER == __BIG_ENDIAN
1218 uint64_t qos : 5; /**< QOS mask to enable the queue when set */
1219 uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */
1220 uint64_t buf_siz : 13; /**< Command buffer remaining size in words */
1221 uint64_t buf_ptr : 33; /**< Command word pointer */
1222 uint64_t qcb_widx : 6; /**< Buffer write index for QCB */
1223 uint64_t qcb_ridx : 6; /**< Buffer read index for QCB */
1225 uint64_t qcb_ridx : 6;
1226 uint64_t qcb_widx : 6;
1227 uint64_t buf_ptr : 33;
1228 uint64_t buf_siz : 13;
1233 struct cvmx_pko_mem_debug7_cn50xx cn52xx;
1234 struct cvmx_pko_mem_debug7_cn50xx cn52xxp1;
1235 struct cvmx_pko_mem_debug7_cn50xx cn56xx;
1236 struct cvmx_pko_mem_debug7_cn50xx cn56xxp1;
1237 struct cvmx_pko_mem_debug7_cn50xx cn58xx;
1238 struct cvmx_pko_mem_debug7_cn50xx cn58xxp1;
1239 struct cvmx_pko_mem_debug7_cn50xx cn63xx;
1240 struct cvmx_pko_mem_debug7_cn50xx cn63xxp1;
1242 typedef union cvmx_pko_mem_debug7 cvmx_pko_mem_debug7_t;
1245 * cvmx_pko_mem_debug8
1248 * Internal per-queue state intended for debug use only - pko_prt_qsb.state[91:64]
1249 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
1250 * CSR read operations to this address can be performed.
1252 union cvmx_pko_mem_debug8
1255 struct cvmx_pko_mem_debug8_s
1257 #if __BYTE_ORDER == __BIG_ENDIAN
1258 uint64_t reserved_59_63 : 5;
1259 uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */
1260 uint64_t buf_siz : 13; /**< Command buffer remaining size in words */
1261 uint64_t reserved_0_44 : 45;
1263 uint64_t reserved_0_44 : 45;
1264 uint64_t buf_siz : 13;
1266 uint64_t reserved_59_63 : 5;
1269 struct cvmx_pko_mem_debug8_cn30xx
1271 #if __BYTE_ORDER == __BIG_ENDIAN
1272 uint64_t qos : 5; /**< QOS mask to enable the queue when set */
1273 uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */
1274 uint64_t buf_siz : 13; /**< Command buffer remaining size in words */
1275 uint64_t buf_ptr : 33; /**< Command word pointer */
1276 uint64_t qcb_widx : 6; /**< Buffer write index for QCB */
1277 uint64_t qcb_ridx : 6; /**< Buffer read index for QCB */
1279 uint64_t qcb_ridx : 6;
1280 uint64_t qcb_widx : 6;
1281 uint64_t buf_ptr : 33;
1282 uint64_t buf_siz : 13;
1287 struct cvmx_pko_mem_debug8_cn30xx cn31xx;
1288 struct cvmx_pko_mem_debug8_cn30xx cn38xx;
1289 struct cvmx_pko_mem_debug8_cn30xx cn38xxp2;
1290 struct cvmx_pko_mem_debug8_cn50xx
1292 #if __BYTE_ORDER == __BIG_ENDIAN
1293 uint64_t reserved_28_63 : 36;
1294 uint64_t doorbell : 20; /**< Doorbell count */
1295 uint64_t reserved_6_7 : 2;
1296 uint64_t static_p : 1; /**< Static priority */
1297 uint64_t s_tail : 1; /**< Static tail */
1298 uint64_t static_q : 1; /**< Static priority */
1299 uint64_t qos : 3; /**< QOS mask to enable the queue when set */
1302 uint64_t static_q : 1;
1303 uint64_t s_tail : 1;
1304 uint64_t static_p : 1;
1305 uint64_t reserved_6_7 : 2;
1306 uint64_t doorbell : 20;
1307 uint64_t reserved_28_63 : 36;
1310 struct cvmx_pko_mem_debug8_cn52xx
1312 #if __BYTE_ORDER == __BIG_ENDIAN
1313 uint64_t reserved_29_63 : 35;
1314 uint64_t preempter : 1; /**< Preempter */
1315 uint64_t doorbell : 20; /**< Doorbell count */
1316 uint64_t reserved_7_7 : 1;
1317 uint64_t preemptee : 1; /**< Preemptee */
1318 uint64_t static_p : 1; /**< Static priority */
1319 uint64_t s_tail : 1; /**< Static tail */
1320 uint64_t static_q : 1; /**< Static priority */
1321 uint64_t qos : 3; /**< QOS mask to enable the queue when set */
1324 uint64_t static_q : 1;
1325 uint64_t s_tail : 1;
1326 uint64_t static_p : 1;
1327 uint64_t preemptee : 1;
1328 uint64_t reserved_7_7 : 1;
1329 uint64_t doorbell : 20;
1330 uint64_t preempter : 1;
1331 uint64_t reserved_29_63 : 35;
1334 struct cvmx_pko_mem_debug8_cn52xx cn52xxp1;
1335 struct cvmx_pko_mem_debug8_cn52xx cn56xx;
1336 struct cvmx_pko_mem_debug8_cn52xx cn56xxp1;
1337 struct cvmx_pko_mem_debug8_cn50xx cn58xx;
1338 struct cvmx_pko_mem_debug8_cn50xx cn58xxp1;
1339 struct cvmx_pko_mem_debug8_cn52xx cn63xx;
1340 struct cvmx_pko_mem_debug8_cn52xx cn63xxp1;
1342 typedef union cvmx_pko_mem_debug8 cvmx_pko_mem_debug8_t;
1345 * cvmx_pko_mem_debug9
1348 * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs0, pko.dat.ptr.ptrs3
1349 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
1350 * CSR read operations to this address can be performed.
1352 union cvmx_pko_mem_debug9
1355 struct cvmx_pko_mem_debug9_s
1357 #if __BYTE_ORDER == __BIG_ENDIAN
1358 uint64_t reserved_49_63 : 15;
1359 uint64_t ptrs0 : 17; /**< Internal state */
1360 uint64_t reserved_0_31 : 32;
1362 uint64_t reserved_0_31 : 32;
1363 uint64_t ptrs0 : 17;
1364 uint64_t reserved_49_63 : 15;
1367 struct cvmx_pko_mem_debug9_cn30xx
1369 #if __BYTE_ORDER == __BIG_ENDIAN
1370 uint64_t reserved_28_63 : 36;
1371 uint64_t doorbell : 20; /**< Doorbell count */
1372 uint64_t reserved_5_7 : 3;
1373 uint64_t s_tail : 1; /**< reads as zero (S_TAIL cannot be read) */
1374 uint64_t static_q : 1; /**< reads as zero (STATIC_Q cannot be read) */
1375 uint64_t qos : 3; /**< QOS mask to enable the queue when set */
1378 uint64_t static_q : 1;
1379 uint64_t s_tail : 1;
1380 uint64_t reserved_5_7 : 3;
1381 uint64_t doorbell : 20;
1382 uint64_t reserved_28_63 : 36;
1385 struct cvmx_pko_mem_debug9_cn30xx cn31xx;
1386 struct cvmx_pko_mem_debug9_cn38xx
1388 #if __BYTE_ORDER == __BIG_ENDIAN
1389 uint64_t reserved_28_63 : 36;
1390 uint64_t doorbell : 20; /**< Doorbell count */
1391 uint64_t reserved_6_7 : 2;
1392 uint64_t static_p : 1; /**< Static priority (port) */
1393 uint64_t s_tail : 1; /**< Static tail */
1394 uint64_t static_q : 1; /**< Static priority */
1395 uint64_t qos : 3; /**< QOS mask to enable the queue when set */
1398 uint64_t static_q : 1;
1399 uint64_t s_tail : 1;
1400 uint64_t static_p : 1;
1401 uint64_t reserved_6_7 : 2;
1402 uint64_t doorbell : 20;
1403 uint64_t reserved_28_63 : 36;
1406 struct cvmx_pko_mem_debug9_cn38xx cn38xxp2;
1407 struct cvmx_pko_mem_debug9_cn50xx
1409 #if __BYTE_ORDER == __BIG_ENDIAN
1410 uint64_t reserved_49_63 : 15;
1411 uint64_t ptrs0 : 17; /**< Internal state */
1412 uint64_t reserved_17_31 : 15;
1413 uint64_t ptrs3 : 17; /**< Internal state */
1415 uint64_t ptrs3 : 17;
1416 uint64_t reserved_17_31 : 15;
1417 uint64_t ptrs0 : 17;
1418 uint64_t reserved_49_63 : 15;
1421 struct cvmx_pko_mem_debug9_cn50xx cn52xx;
1422 struct cvmx_pko_mem_debug9_cn50xx cn52xxp1;
1423 struct cvmx_pko_mem_debug9_cn50xx cn56xx;
1424 struct cvmx_pko_mem_debug9_cn50xx cn56xxp1;
1425 struct cvmx_pko_mem_debug9_cn50xx cn58xx;
1426 struct cvmx_pko_mem_debug9_cn50xx cn58xxp1;
1427 struct cvmx_pko_mem_debug9_cn50xx cn63xx;
1428 struct cvmx_pko_mem_debug9_cn50xx cn63xxp1;
1430 typedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t;
1433 * cvmx_pko_mem_port_ptrs
1436 * Sets the port to engine mapping, per port. Ports marked as static priority need not be contiguous,
1437 * but they must be the lowest numbered PIDs mapped to this EID and must have QOS_MASK=0xff. If EID==8
1438 * or EID==9, then PID[1:0] is used to direct the packet to the correct port on that interface.
1439 * EID==15 can be used for unused PKO-internal ports.
1440 * BP_PORT==63 means that the PKO-internal port is not backpressured.
1441 * BP_PORTs are assumed to belong to an interface as follows:
1442 * 42 <= BP_PORT < 44 -> srio interface 1
1443 * 40 <= BP_PORT < 42 -> srio interface 0
1444 * 36 <= BP_PORT < 40 -> loopback interface
1445 * 32 <= BP_PORT < 36 -> PCIe interface
1446 * 0 <= BP_PORT < 16 -> SGMII/Xaui interface 0
1448 * Note that the SRIO interfaces do not actually provide backpressure. Thus, ports that use
1449 * 40 <= BP_PORT < 44 for backpressure will never be backpressured.
1451 * The reset configuration is the following:
1452 * PID EID(ext port) BP_PORT QOS_MASK STATIC_P
1453 * -------------------------------------------
1464 * 10 2( 2) 10 0xff 0
1465 * 11 3( 3) 11 0xff 0
1466 * 12 0( 0) 12 0xff 0
1467 * 13 1( 1) 13 0xff 0
1468 * 14 2( 2) 14 0xff 0
1469 * 15 3( 3) 15 0xff 0
1470 * -------------------------------------------
1481 * 26 2( 2) 10 0xff 0
1482 * 27 3( 3) 11 0xff 0
1483 * 28 0( 0) 12 0xff 0
1484 * 29 1( 1) 13 0xff 0
1485 * 30 2( 2) 14 0xff 0
1486 * 31 3( 3) 15 0xff 0
1487 * -------------------------------------------
1488 * 32 8(32) 32 0xff 0
1489 * 33 8(33) 33 0xff 0
1490 * 34 8(34) 34 0xff 0
1491 * 35 8(35) 35 0xff 0
1492 * -------------------------------------------
1493 * 36 9(36) 36 0xff 0
1494 * 37 9(37) 37 0xff 0
1495 * 38 9(38) 38 0xff 0
1496 * 39 9(39) 39 0xff 0
1497 * -------------------------------------------
1498 * 40 10(40) 40 0xff 0
1499 * 41 10(41) 41 0xff 0
1500 * -------------------------------------------
1501 * 42 11(42) 42 0xff 0
1502 * 43 11(43) 43 0xff 0
1504 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
1505 * CSR read operations to this address can be performed. A read of any entry that has not been
1506 * previously written is illegal and will result in unpredictable CSR read data.
1508 union cvmx_pko_mem_port_ptrs
1511 struct cvmx_pko_mem_port_ptrs_s
1513 #if __BYTE_ORDER == __BIG_ENDIAN
1514 uint64_t reserved_62_63 : 2;
1515 uint64_t static_p : 1; /**< Set if this PID has static priority */
1516 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */
1517 uint64_t reserved_16_52 : 37;
1518 uint64_t bp_port : 6; /**< PID listens to BP_PORT for per-packet backpressure
1519 Legal BP_PORTs: 0-15, 32-43, 63 (63 means no BP) */
1520 uint64_t eid : 4; /**< Engine ID to which this port is mapped
1521 Legal EIDs: 0-3, 8-11, 15 (15 only if port not used) */
1522 uint64_t pid : 6; /**< Port ID[5:0] */
1526 uint64_t bp_port : 6;
1527 uint64_t reserved_16_52 : 37;
1528 uint64_t qos_mask : 8;
1529 uint64_t static_p : 1;
1530 uint64_t reserved_62_63 : 2;
1533 struct cvmx_pko_mem_port_ptrs_s cn52xx;
1534 struct cvmx_pko_mem_port_ptrs_s cn52xxp1;
1535 struct cvmx_pko_mem_port_ptrs_s cn56xx;
1536 struct cvmx_pko_mem_port_ptrs_s cn56xxp1;
1537 struct cvmx_pko_mem_port_ptrs_s cn63xx;
1538 struct cvmx_pko_mem_port_ptrs_s cn63xxp1;
1540 typedef union cvmx_pko_mem_port_ptrs cvmx_pko_mem_port_ptrs_t;
1543 * cvmx_pko_mem_port_qos
1546 * Sets the QOS mask, per port. These QOS_MASK bits are logically and physically the same QOS_MASK
1547 * bits in PKO_MEM_PORT_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO
1548 * operation without affecting any other port state. The engine to which port PID is mapped is engine
1549 * EID. Note that the port to engine mapping must be the same as was previously programmed via the
1550 * PKO_MEM_PORT_PTRS CSR.
1551 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
1552 * CSR read operations to this address can be performed. A read of any entry that has not been
1553 * previously written is illegal and will result in unpredictable CSR read data.
1555 union cvmx_pko_mem_port_qos
1558 struct cvmx_pko_mem_port_qos_s
1560 #if __BYTE_ORDER == __BIG_ENDIAN
1561 uint64_t reserved_61_63 : 3;
1562 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */
1563 uint64_t reserved_10_52 : 43;
1564 uint64_t eid : 4; /**< Engine ID to which this port is mapped
1565 Legal EIDs: 0-3, 8-11 */
1566 uint64_t pid : 6; /**< Port ID[5:0] */
1570 uint64_t reserved_10_52 : 43;
1571 uint64_t qos_mask : 8;
1572 uint64_t reserved_61_63 : 3;
1575 struct cvmx_pko_mem_port_qos_s cn52xx;
1576 struct cvmx_pko_mem_port_qos_s cn52xxp1;
1577 struct cvmx_pko_mem_port_qos_s cn56xx;
1578 struct cvmx_pko_mem_port_qos_s cn56xxp1;
1579 struct cvmx_pko_mem_port_qos_s cn63xx;
1580 struct cvmx_pko_mem_port_qos_s cn63xxp1;
1582 typedef union cvmx_pko_mem_port_qos cvmx_pko_mem_port_qos_t;
1585 * cvmx_pko_mem_port_rate0
1588 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
1589 * CSR read operations to this address can be performed. A read of any entry that has not been
1590 * previously written is illegal and will result in unpredictable CSR read data.
1592 union cvmx_pko_mem_port_rate0
1595 struct cvmx_pko_mem_port_rate0_s
1597 #if __BYTE_ORDER == __BIG_ENDIAN
1598 uint64_t reserved_51_63 : 13;
1599 uint64_t rate_word : 19; /**< Rate limiting adder per 8 byte */
1600 uint64_t rate_pkt : 24; /**< Rate limiting adder per packet */
1601 uint64_t reserved_6_7 : 2;
1602 uint64_t pid : 6; /**< Port ID[5:0] */
1605 uint64_t reserved_6_7 : 2;
1606 uint64_t rate_pkt : 24;
1607 uint64_t rate_word : 19;
1608 uint64_t reserved_51_63 : 13;
1611 struct cvmx_pko_mem_port_rate0_s cn52xx;
1612 struct cvmx_pko_mem_port_rate0_s cn52xxp1;
1613 struct cvmx_pko_mem_port_rate0_s cn56xx;
1614 struct cvmx_pko_mem_port_rate0_s cn56xxp1;
1615 struct cvmx_pko_mem_port_rate0_s cn63xx;
1616 struct cvmx_pko_mem_port_rate0_s cn63xxp1;
1618 typedef union cvmx_pko_mem_port_rate0 cvmx_pko_mem_port_rate0_t;
1621 * cvmx_pko_mem_port_rate1
1624 * Writing PKO_MEM_PORT_RATE1[PID,RATE_LIM] has the side effect of setting the corresponding
1625 * accumulator to zero.
1626 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
1627 * CSR read operations to this address can be performed. A read of any entry that has not been
1628 * previously written is illegal and will result in unpredictable CSR read data.
1630 union cvmx_pko_mem_port_rate1
1633 struct cvmx_pko_mem_port_rate1_s
1635 #if __BYTE_ORDER == __BIG_ENDIAN
1636 uint64_t reserved_32_63 : 32;
1637 uint64_t rate_lim : 24; /**< Rate limiting accumulator limit */
1638 uint64_t reserved_6_7 : 2;
1639 uint64_t pid : 6; /**< Port ID[5:0] */
1642 uint64_t reserved_6_7 : 2;
1643 uint64_t rate_lim : 24;
1644 uint64_t reserved_32_63 : 32;
1647 struct cvmx_pko_mem_port_rate1_s cn52xx;
1648 struct cvmx_pko_mem_port_rate1_s cn52xxp1;
1649 struct cvmx_pko_mem_port_rate1_s cn56xx;
1650 struct cvmx_pko_mem_port_rate1_s cn56xxp1;
1651 struct cvmx_pko_mem_port_rate1_s cn63xx;
1652 struct cvmx_pko_mem_port_rate1_s cn63xxp1;
1654 typedef union cvmx_pko_mem_port_rate1 cvmx_pko_mem_port_rate1_t;
1657 * cvmx_pko_mem_queue_ptrs
1660 * Sets the queue to port mapping and the initial command buffer pointer, per queue
1661 * Each queue may map to at most one port. No more than 16 queues may map to a port. The set of
1662 * queues that is mapped to a port must be a contiguous array of queues. The port to which queue QID
1663 * is mapped is port PID. The index of queue QID in port PID's queue list is IDX. The last queue in
1664 * port PID's queue array must have its TAIL bit set. Unused queues must be mapped to port 63.
1665 * STATIC_Q marks queue QID as having static priority. STATIC_P marks the port PID to which QID is
1666 * mapped as having at least one queue with static priority. If any QID that maps to PID has static
1667 * priority, then all QID that map to PID must have STATIC_P set. Queues marked as static priority
1668 * must be contiguous and begin at IDX 0. The last queue that is marked as having static priority
1669 * must have its S_TAIL bit set.
1670 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
1671 * CSR read operations to this address can be performed. A read of any entry that has not been
1672 * previously written is illegal and will result in unpredictable CSR read data.
1674 union cvmx_pko_mem_queue_ptrs
1677 struct cvmx_pko_mem_queue_ptrs_s
1679 #if __BYTE_ORDER == __BIG_ENDIAN
1680 uint64_t s_tail : 1; /**< Set if this QID is the tail of the static queues */
1681 uint64_t static_p : 1; /**< Set if any QID in this PID has static priority */
1682 uint64_t static_q : 1; /**< Set if this QID has static priority */
1683 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */
1684 uint64_t buf_ptr : 36; /**< Command buffer pointer, <23:17> MBZ */
1685 uint64_t tail : 1; /**< Set if this QID is the tail of the queue array */
1686 uint64_t index : 3; /**< Index[2:0] (distance from head) in the queue array */
1687 uint64_t port : 6; /**< Port ID to which this queue is mapped */
1688 uint64_t queue : 7; /**< Queue ID[6:0] */
1694 uint64_t buf_ptr : 36;
1695 uint64_t qos_mask : 8;
1696 uint64_t static_q : 1;
1697 uint64_t static_p : 1;
1698 uint64_t s_tail : 1;
1701 struct cvmx_pko_mem_queue_ptrs_s cn30xx;
1702 struct cvmx_pko_mem_queue_ptrs_s cn31xx;
1703 struct cvmx_pko_mem_queue_ptrs_s cn38xx;
1704 struct cvmx_pko_mem_queue_ptrs_s cn38xxp2;
1705 struct cvmx_pko_mem_queue_ptrs_s cn50xx;
1706 struct cvmx_pko_mem_queue_ptrs_s cn52xx;
1707 struct cvmx_pko_mem_queue_ptrs_s cn52xxp1;
1708 struct cvmx_pko_mem_queue_ptrs_s cn56xx;
1709 struct cvmx_pko_mem_queue_ptrs_s cn56xxp1;
1710 struct cvmx_pko_mem_queue_ptrs_s cn58xx;
1711 struct cvmx_pko_mem_queue_ptrs_s cn58xxp1;
1712 struct cvmx_pko_mem_queue_ptrs_s cn63xx;
1713 struct cvmx_pko_mem_queue_ptrs_s cn63xxp1;
1715 typedef union cvmx_pko_mem_queue_ptrs cvmx_pko_mem_queue_ptrs_t;
1718 * cvmx_pko_mem_queue_qos
1721 * Sets the QOS mask, per queue. These QOS_MASK bits are logically and physically the same QOS_MASK
1722 * bits in PKO_MEM_QUEUE_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO
1723 * operation without affecting any other queue state. The port to which queue QID is mapped is port
1724 * PID. Note that the queue to port mapping must be the same as was previously programmed via the
1725 * PKO_MEM_QUEUE_PTRS CSR.
1726 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
1727 * CSR read operations to this address can be performed. A read of any entry that has not been
1728 * previously written is illegal and will result in unpredictable CSR read data.
1730 union cvmx_pko_mem_queue_qos
1733 struct cvmx_pko_mem_queue_qos_s
1735 #if __BYTE_ORDER == __BIG_ENDIAN
1736 uint64_t reserved_61_63 : 3;
1737 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */
1738 uint64_t reserved_13_52 : 40;
1739 uint64_t pid : 6; /**< Port ID to which this queue is mapped */
1740 uint64_t qid : 7; /**< Queue ID */
1744 uint64_t reserved_13_52 : 40;
1745 uint64_t qos_mask : 8;
1746 uint64_t reserved_61_63 : 3;
1749 struct cvmx_pko_mem_queue_qos_s cn30xx;
1750 struct cvmx_pko_mem_queue_qos_s cn31xx;
1751 struct cvmx_pko_mem_queue_qos_s cn38xx;
1752 struct cvmx_pko_mem_queue_qos_s cn38xxp2;
1753 struct cvmx_pko_mem_queue_qos_s cn50xx;
1754 struct cvmx_pko_mem_queue_qos_s cn52xx;
1755 struct cvmx_pko_mem_queue_qos_s cn52xxp1;
1756 struct cvmx_pko_mem_queue_qos_s cn56xx;
1757 struct cvmx_pko_mem_queue_qos_s cn56xxp1;
1758 struct cvmx_pko_mem_queue_qos_s cn58xx;
1759 struct cvmx_pko_mem_queue_qos_s cn58xxp1;
1760 struct cvmx_pko_mem_queue_qos_s cn63xx;
1761 struct cvmx_pko_mem_queue_qos_s cn63xxp1;
1763 typedef union cvmx_pko_mem_queue_qos cvmx_pko_mem_queue_qos_t;
1766 * cvmx_pko_reg_bist_result
1769 * Access to the internal BiST results
1770 * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
1772 union cvmx_pko_reg_bist_result
1775 struct cvmx_pko_reg_bist_result_s
1777 #if __BYTE_ORDER == __BIG_ENDIAN
1778 uint64_t reserved_0_63 : 64;
1780 uint64_t reserved_0_63 : 64;
1783 struct cvmx_pko_reg_bist_result_cn30xx
1785 #if __BYTE_ORDER == __BIG_ENDIAN
1786 uint64_t reserved_27_63 : 37;
1787 uint64_t psb2 : 5; /**< BiST result of the PSB memories (0=pass, !0=fail) */
1788 uint64_t count : 1; /**< BiST result of the COUNT memories (0=pass, !0=fail) */
1789 uint64_t rif : 1; /**< BiST result of the RIF memories (0=pass, !0=fail) */
1790 uint64_t wif : 1; /**< BiST result of the WIF memories (0=pass, !0=fail) */
1791 uint64_t ncb : 1; /**< BiST result of the NCB memories (0=pass, !0=fail) */
1792 uint64_t out : 1; /**< BiST result of the OUT memories (0=pass, !0=fail) */
1793 uint64_t crc : 1; /**< BiST result of the CRC memories (0=pass, !0=fail) */
1794 uint64_t chk : 1; /**< BiST result of the CHK memories (0=pass, !0=fail) */
1795 uint64_t qsb : 2; /**< BiST result of the QSB memories (0=pass, !0=fail) */
1796 uint64_t qcb : 2; /**< BiST result of the QCB memories (0=pass, !0=fail) */
1797 uint64_t pdb : 4; /**< BiST result of the PDB memories (0=pass, !0=fail) */
1798 uint64_t psb : 7; /**< BiST result of the PSB memories (0=pass, !0=fail) */
1812 uint64_t reserved_27_63 : 37;
1815 struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
1816 struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
1817 struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
1818 struct cvmx_pko_reg_bist_result_cn50xx
1820 #if __BYTE_ORDER == __BIG_ENDIAN
1821 uint64_t reserved_33_63 : 31;
1822 uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */
1823 uint64_t iob : 1; /**< BiST result of IOB memories (0=pass, !0=fail) */
1824 uint64_t out_crc : 1; /**< BiST result of OUT_CRC memories (0=pass, !0=fail) */
1825 uint64_t out_ctl : 3; /**< BiST result of OUT_CTL memories (0=pass, !0=fail) */
1826 uint64_t out_sta : 1; /**< BiST result of OUT_STA memories (0=pass, !0=fail) */
1827 uint64_t out_wif : 1; /**< BiST result of OUT_WIF memories (0=pass, !0=fail) */
1828 uint64_t prt_chk : 3; /**< BiST result of PRT_CHK memories (0=pass, !0=fail) */
1829 uint64_t prt_nxt : 1; /**< BiST result of PRT_NXT memories (0=pass, !0=fail) */
1830 uint64_t prt_psb : 6; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */
1831 uint64_t ncb_inb : 2; /**< BiST result of NCB_INB memories (0=pass, !0=fail) */
1832 uint64_t prt_qcb : 2; /**< BiST result of PRT_QCB memories (0=pass, !0=fail) */
1833 uint64_t prt_qsb : 3; /**< BiST result of PRT_QSB memories (0=pass, !0=fail) */
1834 uint64_t dat_dat : 4; /**< BiST result of DAT_DAT memories (0=pass, !0=fail) */
1835 uint64_t dat_ptr : 4; /**< BiST result of DAT_PTR memories (0=pass, !0=fail) */
1837 uint64_t dat_ptr : 4;
1838 uint64_t dat_dat : 4;
1839 uint64_t prt_qsb : 3;
1840 uint64_t prt_qcb : 2;
1841 uint64_t ncb_inb : 2;
1842 uint64_t prt_psb : 6;
1843 uint64_t prt_nxt : 1;
1844 uint64_t prt_chk : 3;
1845 uint64_t out_wif : 1;
1846 uint64_t out_sta : 1;
1847 uint64_t out_ctl : 3;
1848 uint64_t out_crc : 1;
1851 uint64_t reserved_33_63 : 31;
1854 struct cvmx_pko_reg_bist_result_cn52xx
1856 #if __BYTE_ORDER == __BIG_ENDIAN
1857 uint64_t reserved_35_63 : 29;
1858 uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */
1859 uint64_t iob : 1; /**< BiST result of IOB memories (0=pass, !0=fail) */
1860 uint64_t out_dat : 1; /**< BiST result of OUT_DAT memories (0=pass, !0=fail) */
1861 uint64_t out_ctl : 3; /**< BiST result of OUT_CTL memories (0=pass, !0=fail) */
1862 uint64_t out_sta : 1; /**< BiST result of OUT_STA memories (0=pass, !0=fail) */
1863 uint64_t out_wif : 1; /**< BiST result of OUT_WIF memories (0=pass, !0=fail) */
1864 uint64_t prt_chk : 3; /**< BiST result of PRT_CHK memories (0=pass, !0=fail) */
1865 uint64_t prt_nxt : 1; /**< BiST result of PRT_NXT memories (0=pass, !0=fail) */
1866 uint64_t prt_psb : 8; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */
1867 uint64_t ncb_inb : 2; /**< BiST result of NCB_INB memories (0=pass, !0=fail) */
1868 uint64_t prt_qcb : 2; /**< BiST result of PRT_QCB memories (0=pass, !0=fail) */
1869 uint64_t prt_qsb : 3; /**< BiST result of PRT_QSB memories (0=pass, !0=fail) */
1870 uint64_t prt_ctl : 2; /**< BiST result of PRT_CTL memories (0=pass, !0=fail) */
1871 uint64_t dat_dat : 2; /**< BiST result of DAT_DAT memories (0=pass, !0=fail) */
1872 uint64_t dat_ptr : 4; /**< BiST result of DAT_PTR memories (0=pass, !0=fail) */
1874 uint64_t dat_ptr : 4;
1875 uint64_t dat_dat : 2;
1876 uint64_t prt_ctl : 2;
1877 uint64_t prt_qsb : 3;
1878 uint64_t prt_qcb : 2;
1879 uint64_t ncb_inb : 2;
1880 uint64_t prt_psb : 8;
1881 uint64_t prt_nxt : 1;
1882 uint64_t prt_chk : 3;
1883 uint64_t out_wif : 1;
1884 uint64_t out_sta : 1;
1885 uint64_t out_ctl : 3;
1886 uint64_t out_dat : 1;
1889 uint64_t reserved_35_63 : 29;
1892 struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
1893 struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
1894 struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
1895 struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
1896 struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
1897 struct cvmx_pko_reg_bist_result_cn52xx cn63xx;
1898 struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1;
1900 typedef union cvmx_pko_reg_bist_result cvmx_pko_reg_bist_result_t;
1903 * cvmx_pko_reg_cmd_buf
1906 * Sets the command buffer parameters
1907 * The size of the command buffer segments is measured in uint64s. The pool specifies (1 of 8 free
1908 * lists to be used when freeing command buffer segments.
1910 union cvmx_pko_reg_cmd_buf
1913 struct cvmx_pko_reg_cmd_buf_s
1915 #if __BYTE_ORDER == __BIG_ENDIAN
1916 uint64_t reserved_23_63 : 41;
1917 uint64_t pool : 3; /**< Free list used to free command buffer segments */
1918 uint64_t reserved_13_19 : 7;
1919 uint64_t size : 13; /**< Number of uint64s per command buffer segment */
1922 uint64_t reserved_13_19 : 7;
1924 uint64_t reserved_23_63 : 41;
1927 struct cvmx_pko_reg_cmd_buf_s cn30xx;
1928 struct cvmx_pko_reg_cmd_buf_s cn31xx;
1929 struct cvmx_pko_reg_cmd_buf_s cn38xx;
1930 struct cvmx_pko_reg_cmd_buf_s cn38xxp2;
1931 struct cvmx_pko_reg_cmd_buf_s cn50xx;
1932 struct cvmx_pko_reg_cmd_buf_s cn52xx;
1933 struct cvmx_pko_reg_cmd_buf_s cn52xxp1;
1934 struct cvmx_pko_reg_cmd_buf_s cn56xx;
1935 struct cvmx_pko_reg_cmd_buf_s cn56xxp1;
1936 struct cvmx_pko_reg_cmd_buf_s cn58xx;
1937 struct cvmx_pko_reg_cmd_buf_s cn58xxp1;
1938 struct cvmx_pko_reg_cmd_buf_s cn63xx;
1939 struct cvmx_pko_reg_cmd_buf_s cn63xxp1;
1941 typedef union cvmx_pko_reg_cmd_buf cvmx_pko_reg_cmd_buf_t;
1944 * cvmx_pko_reg_crc_ctl#
1947 * Controls datapath reflection when calculating CRC
1950 union cvmx_pko_reg_crc_ctlx
1953 struct cvmx_pko_reg_crc_ctlx_s
1955 #if __BYTE_ORDER == __BIG_ENDIAN
1956 uint64_t reserved_2_63 : 62;
1957 uint64_t invres : 1; /**< Invert the result */
1958 uint64_t refin : 1; /**< Reflect the bits in each byte.
1959 Byte order does not change.
1960 - 0: CRC is calculated MSB to LSB
1961 - 1: CRC is calculated MLB to MSB */
1964 uint64_t invres : 1;
1965 uint64_t reserved_2_63 : 62;
1968 struct cvmx_pko_reg_crc_ctlx_s cn38xx;
1969 struct cvmx_pko_reg_crc_ctlx_s cn38xxp2;
1970 struct cvmx_pko_reg_crc_ctlx_s cn58xx;
1971 struct cvmx_pko_reg_crc_ctlx_s cn58xxp1;
1973 typedef union cvmx_pko_reg_crc_ctlx cvmx_pko_reg_crc_ctlx_t;
1976 * cvmx_pko_reg_crc_enable
1979 * Enables CRC for the GMX ports.
1982 union cvmx_pko_reg_crc_enable
1985 struct cvmx_pko_reg_crc_enable_s
1987 #if __BYTE_ORDER == __BIG_ENDIAN
1988 uint64_t reserved_32_63 : 32;
1989 uint64_t enable : 32; /**< Mask for ports 31-0 to enable CRC
1990 Mask bit==0 means CRC not enabled
1991 Mask bit==1 means CRC enabled
1992 Note that CRC should be enabled only when using SPI4.2 */
1994 uint64_t enable : 32;
1995 uint64_t reserved_32_63 : 32;
1998 struct cvmx_pko_reg_crc_enable_s cn38xx;
1999 struct cvmx_pko_reg_crc_enable_s cn38xxp2;
2000 struct cvmx_pko_reg_crc_enable_s cn58xx;
2001 struct cvmx_pko_reg_crc_enable_s cn58xxp1;
2003 typedef union cvmx_pko_reg_crc_enable cvmx_pko_reg_crc_enable_t;
2006 * cvmx_pko_reg_crc_iv#
2009 * Determines the IV used by the CRC algorithm
2011 * PKO_CRC_IV controls the initial state of the CRC algorithm. Octane can
2012 * support a wide range of CRC algorithms and as such, the IV must be
2013 * carefully constructed to meet the specific algorithm. The code below
2014 * determines the value to program into Octane based on the algorthim's IV
2015 * and width. In the case of Octane, the width should always be 32.
2017 * PKO_CRC_IV0 sets the IV for ports 0-15 while PKO_CRC_IV1 sets the IV for
2021 * unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w)
2025 * unsigned int current_val = algorithm_iv;
2027 * for(i = 0; i < w; i++) [
2028 * doit = current_val & 0x1;
2030 * if(doit) current_val ^= poly;
2031 * assert(!(current_val & 0x1));
2033 * current_val = (current_val >> 1) | (doit << (w-1));
2036 * return current_val;
2040 union cvmx_pko_reg_crc_ivx
2043 struct cvmx_pko_reg_crc_ivx_s
2045 #if __BYTE_ORDER == __BIG_ENDIAN
2046 uint64_t reserved_32_63 : 32;
2047 uint64_t iv : 32; /**< IV used by the CRC algorithm. Default is FCS32. */
2050 uint64_t reserved_32_63 : 32;
2053 struct cvmx_pko_reg_crc_ivx_s cn38xx;
2054 struct cvmx_pko_reg_crc_ivx_s cn38xxp2;
2055 struct cvmx_pko_reg_crc_ivx_s cn58xx;
2056 struct cvmx_pko_reg_crc_ivx_s cn58xxp1;
2058 typedef union cvmx_pko_reg_crc_ivx cvmx_pko_reg_crc_ivx_t;
2061 * cvmx_pko_reg_debug0
2064 * Note that this CSR is present only in chip revisions beginning with pass2.
2067 union cvmx_pko_reg_debug0
2070 struct cvmx_pko_reg_debug0_s
2072 #if __BYTE_ORDER == __BIG_ENDIAN
2073 uint64_t asserts : 64; /**< Various assertion checks */
2075 uint64_t asserts : 64;
2078 struct cvmx_pko_reg_debug0_cn30xx
2080 #if __BYTE_ORDER == __BIG_ENDIAN
2081 uint64_t reserved_17_63 : 47;
2082 uint64_t asserts : 17; /**< Various assertion checks */
2084 uint64_t asserts : 17;
2085 uint64_t reserved_17_63 : 47;
2088 struct cvmx_pko_reg_debug0_cn30xx cn31xx;
2089 struct cvmx_pko_reg_debug0_cn30xx cn38xx;
2090 struct cvmx_pko_reg_debug0_cn30xx cn38xxp2;
2091 struct cvmx_pko_reg_debug0_s cn50xx;
2092 struct cvmx_pko_reg_debug0_s cn52xx;
2093 struct cvmx_pko_reg_debug0_s cn52xxp1;
2094 struct cvmx_pko_reg_debug0_s cn56xx;
2095 struct cvmx_pko_reg_debug0_s cn56xxp1;
2096 struct cvmx_pko_reg_debug0_s cn58xx;
2097 struct cvmx_pko_reg_debug0_s cn58xxp1;
2098 struct cvmx_pko_reg_debug0_s cn63xx;
2099 struct cvmx_pko_reg_debug0_s cn63xxp1;
2101 typedef union cvmx_pko_reg_debug0 cvmx_pko_reg_debug0_t;
2104 * cvmx_pko_reg_debug1
2106 union cvmx_pko_reg_debug1
2109 struct cvmx_pko_reg_debug1_s
2111 #if __BYTE_ORDER == __BIG_ENDIAN
2112 uint64_t asserts : 64; /**< Various assertion checks */
2114 uint64_t asserts : 64;
2117 struct cvmx_pko_reg_debug1_s cn50xx;
2118 struct cvmx_pko_reg_debug1_s cn52xx;
2119 struct cvmx_pko_reg_debug1_s cn52xxp1;
2120 struct cvmx_pko_reg_debug1_s cn56xx;
2121 struct cvmx_pko_reg_debug1_s cn56xxp1;
2122 struct cvmx_pko_reg_debug1_s cn58xx;
2123 struct cvmx_pko_reg_debug1_s cn58xxp1;
2124 struct cvmx_pko_reg_debug1_s cn63xx;
2125 struct cvmx_pko_reg_debug1_s cn63xxp1;
2127 typedef union cvmx_pko_reg_debug1 cvmx_pko_reg_debug1_t;
2130 * cvmx_pko_reg_debug2
2132 union cvmx_pko_reg_debug2
2135 struct cvmx_pko_reg_debug2_s
2137 #if __BYTE_ORDER == __BIG_ENDIAN
2138 uint64_t asserts : 64; /**< Various assertion checks */
2140 uint64_t asserts : 64;
2143 struct cvmx_pko_reg_debug2_s cn50xx;
2144 struct cvmx_pko_reg_debug2_s cn52xx;
2145 struct cvmx_pko_reg_debug2_s cn52xxp1;
2146 struct cvmx_pko_reg_debug2_s cn56xx;
2147 struct cvmx_pko_reg_debug2_s cn56xxp1;
2148 struct cvmx_pko_reg_debug2_s cn58xx;
2149 struct cvmx_pko_reg_debug2_s cn58xxp1;
2150 struct cvmx_pko_reg_debug2_s cn63xx;
2151 struct cvmx_pko_reg_debug2_s cn63xxp1;
2153 typedef union cvmx_pko_reg_debug2 cvmx_pko_reg_debug2_t;
2156 * cvmx_pko_reg_debug3
2158 union cvmx_pko_reg_debug3
2161 struct cvmx_pko_reg_debug3_s
2163 #if __BYTE_ORDER == __BIG_ENDIAN
2164 uint64_t asserts : 64; /**< Various assertion checks */
2166 uint64_t asserts : 64;
2169 struct cvmx_pko_reg_debug3_s cn50xx;
2170 struct cvmx_pko_reg_debug3_s cn52xx;
2171 struct cvmx_pko_reg_debug3_s cn52xxp1;
2172 struct cvmx_pko_reg_debug3_s cn56xx;
2173 struct cvmx_pko_reg_debug3_s cn56xxp1;
2174 struct cvmx_pko_reg_debug3_s cn58xx;
2175 struct cvmx_pko_reg_debug3_s cn58xxp1;
2176 struct cvmx_pko_reg_debug3_s cn63xx;
2177 struct cvmx_pko_reg_debug3_s cn63xxp1;
2179 typedef union cvmx_pko_reg_debug3 cvmx_pko_reg_debug3_t;
2182 * cvmx_pko_reg_engine_inflight
2185 * Sets the maximum number of inflight packets, per engine. Values greater than 4 are illegal.
2186 * Setting an engine's value to 0 effectively stops the engine.
2187 * Note that engines 4-7 do not exist
2189 union cvmx_pko_reg_engine_inflight
2192 struct cvmx_pko_reg_engine_inflight_s
2194 #if __BYTE_ORDER == __BIG_ENDIAN
2195 uint64_t reserved_48_63 : 16;
2196 uint64_t engine11 : 4; /**< Maximum number of inflight packets for engine11 */
2197 uint64_t engine10 : 4; /**< Maximum number of inflight packets for engine10 */
2198 uint64_t engine9 : 4; /**< Maximum number of inflight packets for engine9 */
2199 uint64_t engine8 : 4; /**< Maximum number of inflight packets for engine8 */
2200 uint64_t engine7 : 4; /**< MBZ */
2201 uint64_t engine6 : 4; /**< MBZ */
2202 uint64_t engine5 : 4; /**< MBZ */
2203 uint64_t engine4 : 4; /**< MBZ */
2204 uint64_t engine3 : 4; /**< Maximum number of inflight packets for engine3 */
2205 uint64_t engine2 : 4; /**< Maximum number of inflight packets for engine2 */
2206 uint64_t engine1 : 4; /**< Maximum number of inflight packets for engine1 */
2207 uint64_t engine0 : 4; /**< Maximum number of inflight packets for engine0 */
2209 uint64_t engine0 : 4;
2210 uint64_t engine1 : 4;
2211 uint64_t engine2 : 4;
2212 uint64_t engine3 : 4;
2213 uint64_t engine4 : 4;
2214 uint64_t engine5 : 4;
2215 uint64_t engine6 : 4;
2216 uint64_t engine7 : 4;
2217 uint64_t engine8 : 4;
2218 uint64_t engine9 : 4;
2219 uint64_t engine10 : 4;
2220 uint64_t engine11 : 4;
2221 uint64_t reserved_48_63 : 16;
2224 struct cvmx_pko_reg_engine_inflight_cn52xx
2226 #if __BYTE_ORDER == __BIG_ENDIAN
2227 uint64_t reserved_40_63 : 24;
2228 uint64_t engine9 : 4; /**< Maximum number of inflight packets for engine9 */
2229 uint64_t engine8 : 4; /**< Maximum number of inflight packets for engine8 */
2230 uint64_t engine7 : 4; /**< MBZ */
2231 uint64_t engine6 : 4; /**< MBZ */
2232 uint64_t engine5 : 4; /**< MBZ */
2233 uint64_t engine4 : 4; /**< MBZ */
2234 uint64_t engine3 : 4; /**< Maximum number of inflight packets for engine3 */
2235 uint64_t engine2 : 4; /**< Maximum number of inflight packets for engine2 */
2236 uint64_t engine1 : 4; /**< Maximum number of inflight packets for engine1 */
2237 uint64_t engine0 : 4; /**< Maximum number of inflight packets for engine0 */
2239 uint64_t engine0 : 4;
2240 uint64_t engine1 : 4;
2241 uint64_t engine2 : 4;
2242 uint64_t engine3 : 4;
2243 uint64_t engine4 : 4;
2244 uint64_t engine5 : 4;
2245 uint64_t engine6 : 4;
2246 uint64_t engine7 : 4;
2247 uint64_t engine8 : 4;
2248 uint64_t engine9 : 4;
2249 uint64_t reserved_40_63 : 24;
2252 struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1;
2253 struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx;
2254 struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1;
2255 struct cvmx_pko_reg_engine_inflight_s cn63xx;
2256 struct cvmx_pko_reg_engine_inflight_s cn63xxp1;
2258 typedef union cvmx_pko_reg_engine_inflight cvmx_pko_reg_engine_inflight_t;
2261 * cvmx_pko_reg_engine_thresh
2264 * When not enabled, packet data may be sent as soon as it is written into PKO's internal buffers.
2265 * When enabled and the packet fits entirely in the PKO's internal buffer, none of the packet data will
2266 * be sent until all of it has been written into the PKO's internal buffer. Note that a packet is
2267 * considered to fit entirely only if the packet's size is <= BUFFER_SIZE-8. When enabled and the
2268 * packet does not fit entirely in the PKO's internal buffer, none of the packet data will be sent until
2269 * at least BUFFER_SIZE-256 bytes of the packet have been written into the PKO's internal buffer
2270 * (note that BUFFER_SIZE is a function of PKO_REG_GMX_PORT_MODE above)
2271 * Note that engines 4-7 do not exist, so MASK<7:4> MBZ
2273 union cvmx_pko_reg_engine_thresh
2276 struct cvmx_pko_reg_engine_thresh_s
2278 #if __BYTE_ORDER == __BIG_ENDIAN
2279 uint64_t reserved_12_63 : 52;
2280 uint64_t mask : 12; /**< Mask[n]=0 disables packet send threshold for engine n
2281 Mask[n]=1 enables packet send threshold for engine n $PR NS
2282 Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */
2285 uint64_t reserved_12_63 : 52;
2288 struct cvmx_pko_reg_engine_thresh_cn52xx
2290 #if __BYTE_ORDER == __BIG_ENDIAN
2291 uint64_t reserved_10_63 : 54;
2292 uint64_t mask : 10; /**< Mask[n]=0 disables packet send threshold for eng n
2293 Mask[n]=1 enables packet send threshold for eng n $PR NS
2294 Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */
2297 uint64_t reserved_10_63 : 54;
2300 struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1;
2301 struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx;
2302 struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1;
2303 struct cvmx_pko_reg_engine_thresh_s cn63xx;
2304 struct cvmx_pko_reg_engine_thresh_s cn63xxp1;
2306 typedef union cvmx_pko_reg_engine_thresh cvmx_pko_reg_engine_thresh_t;
2309 * cvmx_pko_reg_error
2312 * Note that this CSR is present only in chip revisions beginning with pass2.
2315 union cvmx_pko_reg_error
2318 struct cvmx_pko_reg_error_s
2320 #if __BYTE_ORDER == __BIG_ENDIAN
2321 uint64_t reserved_3_63 : 61;
2322 uint64_t currzero : 1; /**< A packet data pointer has size=0 */
2323 uint64_t doorbell : 1; /**< A doorbell count has overflowed */
2324 uint64_t parity : 1; /**< Read parity error at port data buffer */
2326 uint64_t parity : 1;
2327 uint64_t doorbell : 1;
2328 uint64_t currzero : 1;
2329 uint64_t reserved_3_63 : 61;
2332 struct cvmx_pko_reg_error_cn30xx
2334 #if __BYTE_ORDER == __BIG_ENDIAN
2335 uint64_t reserved_2_63 : 62;
2336 uint64_t doorbell : 1; /**< A doorbell count has overflowed */
2337 uint64_t parity : 1; /**< Read parity error at port data buffer */
2339 uint64_t parity : 1;
2340 uint64_t doorbell : 1;
2341 uint64_t reserved_2_63 : 62;
2344 struct cvmx_pko_reg_error_cn30xx cn31xx;
2345 struct cvmx_pko_reg_error_cn30xx cn38xx;
2346 struct cvmx_pko_reg_error_cn30xx cn38xxp2;
2347 struct cvmx_pko_reg_error_s cn50xx;
2348 struct cvmx_pko_reg_error_s cn52xx;
2349 struct cvmx_pko_reg_error_s cn52xxp1;
2350 struct cvmx_pko_reg_error_s cn56xx;
2351 struct cvmx_pko_reg_error_s cn56xxp1;
2352 struct cvmx_pko_reg_error_s cn58xx;
2353 struct cvmx_pko_reg_error_s cn58xxp1;
2354 struct cvmx_pko_reg_error_s cn63xx;
2355 struct cvmx_pko_reg_error_s cn63xxp1;
2357 typedef union cvmx_pko_reg_error cvmx_pko_reg_error_t;
2360 * cvmx_pko_reg_flags
2363 * When set, ENA_PKO enables the PKO picker and places the PKO in normal operation. When set, ENA_DWB
2364 * enables the use of DontWriteBacks during the buffer freeing operations. When not set, STORE_BE inverts
2365 * bits[2:0] of the STORE0 byte write address. When set, RESET causes a 4-cycle reset pulse to the
2368 union cvmx_pko_reg_flags
2371 struct cvmx_pko_reg_flags_s
2373 #if __BYTE_ORDER == __BIG_ENDIAN
2374 uint64_t reserved_4_63 : 60;
2375 uint64_t reset : 1; /**< Reset oneshot pulse */
2376 uint64_t store_be : 1; /**< Force STORE0 byte write address to big endian */
2377 uint64_t ena_dwb : 1; /**< Set to enable DontWriteBacks */
2378 uint64_t ena_pko : 1; /**< Set to enable the PKO picker */
2380 uint64_t ena_pko : 1;
2381 uint64_t ena_dwb : 1;
2382 uint64_t store_be : 1;
2384 uint64_t reserved_4_63 : 60;
2387 struct cvmx_pko_reg_flags_s cn30xx;
2388 struct cvmx_pko_reg_flags_s cn31xx;
2389 struct cvmx_pko_reg_flags_s cn38xx;
2390 struct cvmx_pko_reg_flags_s cn38xxp2;
2391 struct cvmx_pko_reg_flags_s cn50xx;
2392 struct cvmx_pko_reg_flags_s cn52xx;
2393 struct cvmx_pko_reg_flags_s cn52xxp1;
2394 struct cvmx_pko_reg_flags_s cn56xx;
2395 struct cvmx_pko_reg_flags_s cn56xxp1;
2396 struct cvmx_pko_reg_flags_s cn58xx;
2397 struct cvmx_pko_reg_flags_s cn58xxp1;
2398 struct cvmx_pko_reg_flags_s cn63xx;
2399 struct cvmx_pko_reg_flags_s cn63xxp1;
2401 typedef union cvmx_pko_reg_flags cvmx_pko_reg_flags_t;
2404 * cvmx_pko_reg_gmx_port_mode
2407 * The system has a total of 4 + 0 + 4 + 4 + 4 ports and 4 + 0 + 1 + 1 + 1 + 1 engines (GM0 + GM1 + PCI + LOOP + SRIO0 + SRIO1).
2408 * This CSR sets the number of GMX0 ports and amount of local storage per engine.
2409 * It has no effect on the number of ports or amount of local storage per engine for PCI, LOOP,
2410 * SRIO0, or SRIO1. When all GMX ports are used (MODE0=2), each GMX engine has 2.5kB of local
2411 * storage. Increasing the value of MODEn by 1 decreases the number of GMX ports by a power of 2 and
2412 * increases the local storage per PKO GMX engine by a power of 2.
2413 * Modes 0 and 1 are illegal and, if selected, are treated as mode 2.
2415 * MODE[n] GM[0] PCI LOOP GM[0] PCI LOOP SRIO0 SRIO1
2416 * ports ports ports storage/engine storage/engine storage/engine storage/engine storage/engine
2417 * 0 4 4 4 2.5kB 2.5kB 2.5kB 2.5kB 2.5kB
2418 * 1 4 4 4 2.5kB 2.5kB 2.5kB 2.5kB 2.5kB
2419 * 2 4 4 4 2.5kB 2.5kB 2.5kB 2.5kB 2.5kB
2420 * 3 2 4 4 5.0kB 2.5kB 2.5kB 2.5kB 2.5kB
2421 * 4 1 4 4 10.0kB 2.5kB 2.5kB 2.5kB 2.5kB
2423 union cvmx_pko_reg_gmx_port_mode
2426 struct cvmx_pko_reg_gmx_port_mode_s
2428 #if __BYTE_ORDER == __BIG_ENDIAN
2429 uint64_t reserved_6_63 : 58;
2430 uint64_t mode1 : 3; /**< MBZ */
2431 uint64_t mode0 : 3; /**< # of GM0 ports = 16 >> MODE0, 0 <= MODE0 <= 4 */
2435 uint64_t reserved_6_63 : 58;
2438 struct cvmx_pko_reg_gmx_port_mode_s cn30xx;
2439 struct cvmx_pko_reg_gmx_port_mode_s cn31xx;
2440 struct cvmx_pko_reg_gmx_port_mode_s cn38xx;
2441 struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2;
2442 struct cvmx_pko_reg_gmx_port_mode_s cn50xx;
2443 struct cvmx_pko_reg_gmx_port_mode_s cn52xx;
2444 struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1;
2445 struct cvmx_pko_reg_gmx_port_mode_s cn56xx;
2446 struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1;
2447 struct cvmx_pko_reg_gmx_port_mode_s cn58xx;
2448 struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1;
2449 struct cvmx_pko_reg_gmx_port_mode_s cn63xx;
2450 struct cvmx_pko_reg_gmx_port_mode_s cn63xxp1;
2452 typedef union cvmx_pko_reg_gmx_port_mode cvmx_pko_reg_gmx_port_mode_t;
2455 * cvmx_pko_reg_int_mask
2458 * When a mask bit is set, the corresponding interrupt is enabled.
2461 union cvmx_pko_reg_int_mask
2464 struct cvmx_pko_reg_int_mask_s
2466 #if __BYTE_ORDER == __BIG_ENDIAN
2467 uint64_t reserved_3_63 : 61;
2468 uint64_t currzero : 1; /**< Bit mask corresponding to PKO_REG_ERROR[2] above */
2469 uint64_t doorbell : 1; /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
2470 uint64_t parity : 1; /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
2472 uint64_t parity : 1;
2473 uint64_t doorbell : 1;
2474 uint64_t currzero : 1;
2475 uint64_t reserved_3_63 : 61;
2478 struct cvmx_pko_reg_int_mask_cn30xx
2480 #if __BYTE_ORDER == __BIG_ENDIAN
2481 uint64_t reserved_2_63 : 62;
2482 uint64_t doorbell : 1; /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
2483 uint64_t parity : 1; /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
2485 uint64_t parity : 1;
2486 uint64_t doorbell : 1;
2487 uint64_t reserved_2_63 : 62;
2490 struct cvmx_pko_reg_int_mask_cn30xx cn31xx;
2491 struct cvmx_pko_reg_int_mask_cn30xx cn38xx;
2492 struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2;
2493 struct cvmx_pko_reg_int_mask_s cn50xx;
2494 struct cvmx_pko_reg_int_mask_s cn52xx;
2495 struct cvmx_pko_reg_int_mask_s cn52xxp1;
2496 struct cvmx_pko_reg_int_mask_s cn56xx;
2497 struct cvmx_pko_reg_int_mask_s cn56xxp1;
2498 struct cvmx_pko_reg_int_mask_s cn58xx;
2499 struct cvmx_pko_reg_int_mask_s cn58xxp1;
2500 struct cvmx_pko_reg_int_mask_s cn63xx;
2501 struct cvmx_pko_reg_int_mask_s cn63xxp1;
2503 typedef union cvmx_pko_reg_int_mask cvmx_pko_reg_int_mask_t;
2506 * cvmx_pko_reg_queue_mode
2509 * Sets the number of queues and amount of local storage per queue
2510 * The system has a total of 256 queues and (256*8) words of local command storage. This CSR sets the
2511 * number of queues that are used. Increasing the value of MODE by 1 decreases the number of queues
2512 * by a power of 2 and increases the local storage per queue by a power of 2.
2513 * MODEn queues storage/queue
2514 * 0 256 64B ( 8 words)
2515 * 1 128 128B (16 words)
2516 * 2 64 256B (32 words)
2518 union cvmx_pko_reg_queue_mode
2521 struct cvmx_pko_reg_queue_mode_s
2523 #if __BYTE_ORDER == __BIG_ENDIAN
2524 uint64_t reserved_2_63 : 62;
2525 uint64_t mode : 2; /**< # of queues = 256 >> MODE, 0 <= MODE <=2 */
2528 uint64_t reserved_2_63 : 62;
2531 struct cvmx_pko_reg_queue_mode_s cn30xx;
2532 struct cvmx_pko_reg_queue_mode_s cn31xx;
2533 struct cvmx_pko_reg_queue_mode_s cn38xx;
2534 struct cvmx_pko_reg_queue_mode_s cn38xxp2;
2535 struct cvmx_pko_reg_queue_mode_s cn50xx;
2536 struct cvmx_pko_reg_queue_mode_s cn52xx;
2537 struct cvmx_pko_reg_queue_mode_s cn52xxp1;
2538 struct cvmx_pko_reg_queue_mode_s cn56xx;
2539 struct cvmx_pko_reg_queue_mode_s cn56xxp1;
2540 struct cvmx_pko_reg_queue_mode_s cn58xx;
2541 struct cvmx_pko_reg_queue_mode_s cn58xxp1;
2542 struct cvmx_pko_reg_queue_mode_s cn63xx;
2543 struct cvmx_pko_reg_queue_mode_s cn63xxp1;
2545 typedef union cvmx_pko_reg_queue_mode cvmx_pko_reg_queue_mode_t;
2548 * cvmx_pko_reg_queue_ptrs1
2551 * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS to allow access to queues 128-255
2552 * and to allow up mapping of up to 16 queues per port. When programming queues 128-255, the
2553 * programming sequence must first write PKO_REG_QUEUE_PTRS1 and then write PKO_MEM_QUEUE_PTRS or
2554 * PKO_MEM_QUEUE_QOS for each queue.
2555 * See the descriptions of PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS for further explanation of queue
2558 union cvmx_pko_reg_queue_ptrs1
2561 struct cvmx_pko_reg_queue_ptrs1_s
2563 #if __BYTE_ORDER == __BIG_ENDIAN
2564 uint64_t reserved_2_63 : 62;
2565 uint64_t idx3 : 1; /**< [3] of Index (distance from head) in the queue array */
2566 uint64_t qid7 : 1; /**< [7] of Queue ID */
2570 uint64_t reserved_2_63 : 62;
2573 struct cvmx_pko_reg_queue_ptrs1_s cn50xx;
2574 struct cvmx_pko_reg_queue_ptrs1_s cn52xx;
2575 struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1;
2576 struct cvmx_pko_reg_queue_ptrs1_s cn56xx;
2577 struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1;
2578 struct cvmx_pko_reg_queue_ptrs1_s cn58xx;
2579 struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1;
2580 struct cvmx_pko_reg_queue_ptrs1_s cn63xx;
2581 struct cvmx_pko_reg_queue_ptrs1_s cn63xxp1;
2583 typedef union cvmx_pko_reg_queue_ptrs1 cvmx_pko_reg_queue_ptrs1_t;
2586 * cvmx_pko_reg_read_idx
2589 * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
2590 * as memories. The names of these CSRs begin with the prefix "PKO_MEM_".
2591 * IDX[7:0] is the read index. INC[7:0] is an increment that is added to IDX[7:0] after any CSR read.
2592 * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire
2593 * contents of a CSR memory can be read with consecutive CSR read commands.
2595 union cvmx_pko_reg_read_idx
2598 struct cvmx_pko_reg_read_idx_s
2600 #if __BYTE_ORDER == __BIG_ENDIAN
2601 uint64_t reserved_16_63 : 48;
2602 uint64_t inc : 8; /**< Increment to add to current index for next index */
2603 uint64_t index : 8; /**< Index to use for next memory CSR read */
2607 uint64_t reserved_16_63 : 48;
2610 struct cvmx_pko_reg_read_idx_s cn30xx;
2611 struct cvmx_pko_reg_read_idx_s cn31xx;
2612 struct cvmx_pko_reg_read_idx_s cn38xx;
2613 struct cvmx_pko_reg_read_idx_s cn38xxp2;
2614 struct cvmx_pko_reg_read_idx_s cn50xx;
2615 struct cvmx_pko_reg_read_idx_s cn52xx;
2616 struct cvmx_pko_reg_read_idx_s cn52xxp1;
2617 struct cvmx_pko_reg_read_idx_s cn56xx;
2618 struct cvmx_pko_reg_read_idx_s cn56xxp1;
2619 struct cvmx_pko_reg_read_idx_s cn58xx;
2620 struct cvmx_pko_reg_read_idx_s cn58xxp1;
2621 struct cvmx_pko_reg_read_idx_s cn63xx;
2622 struct cvmx_pko_reg_read_idx_s cn63xxp1;
2624 typedef union cvmx_pko_reg_read_idx cvmx_pko_reg_read_idx_t;
2627 * cvmx_pko_reg_timestamp
2633 union cvmx_pko_reg_timestamp
2636 struct cvmx_pko_reg_timestamp_s
2638 #if __BYTE_ORDER == __BIG_ENDIAN
2639 uint64_t reserved_4_63 : 60;
2640 uint64_t wqe_word : 4; /**< Specifies the 8-byte word in the WQE to which a PTP
2641 timestamp is written. Values 0 and 1 are illegal. */
2643 uint64_t wqe_word : 4;
2644 uint64_t reserved_4_63 : 60;
2647 struct cvmx_pko_reg_timestamp_s cn63xx;
2648 struct cvmx_pko_reg_timestamp_s cn63xxp1;
2650 typedef union cvmx_pko_reg_timestamp cvmx_pko_reg_timestamp_t;