1 /***********************license start***************
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_SMI_TYPEDEFS_H__
53 #define __CVMX_SMI_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_SMI_DRV_CTL CVMX_SMI_DRV_CTL_FUNC()
57 static inline uint64_t CVMX_SMI_DRV_CTL_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
60 cvmx_warn("CVMX_SMI_DRV_CTL not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180000001828ull);
64 #define CVMX_SMI_DRV_CTL (CVMX_ADD_IO_SEG(0x0001180000001828ull))
70 * SMI_DRV_CTL = SMI Drive Strength Control
73 union cvmx_smi_drv_ctl
76 struct cvmx_smi_drv_ctl_s
78 #if __BYTE_ORDER == __BIG_ENDIAN
79 uint64_t reserved_14_63 : 50;
80 uint64_t pctl : 6; /**< PCTL Drive strength control bits
81 Assuming a 50ohm termination
84 uint64_t reserved_6_7 : 2;
85 uint64_t nctl : 6; /**< NCTL Drive strength control bits
86 Assuming a 50ohm termination
91 uint64_t reserved_6_7 : 2;
93 uint64_t reserved_14_63 : 50;
96 struct cvmx_smi_drv_ctl_s cn63xx;
97 struct cvmx_smi_drv_ctl_s cn63xxp1;
99 typedef union cvmx_smi_drv_ctl cvmx_smi_drv_ctl_t;