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47 * <hr>$Revision: 41586 $<hr>
50 #ifndef __CVMX_SRIO_H__
51 #define __CVMX_SRIO_H__
58 * Enumeration of the type of operations that can be performed
59 * by a mapped write operation.
63 CVMX_SRIO_WRITE_MODE_NWRITE = 0, /**< Only create NWrite operations */
64 CVMX_SRIO_WRITE_MODE_NWRITE_RESP = 1, /**< Create NWrite with response */
65 CVMX_SRIO_WRITE_MODE_AUTO = 2, /**< Intelligently breaks writes into multiple transactions based on alignment */
66 CVMX_SRIO_WRITE_MODE_AUTO_RESP = 3, /**< CVMX_SRIO_WRITE_MODE_WRITE followed with a response */
67 CVMX_SRIO_WRITE_MODE_MAINTENANCE = 6, /**< Create a MAINTENANCE transaction. Use cvmx_srio_config_write32() instead */
68 CVMX_SRIO_WRITE_MODE_PORT = 7 /**< Port Write? */
69 } cvmx_srio_write_mode_t;
72 * Enumeration of the type of operations that can be performed
73 * by a mapped read operation.
77 CVMX_SRIO_READ_MODE_NORMAL = 0, /**< Perform a normal read */
78 CVMX_SRIO_READ_MODE_ATOMIC_SET = 2, /**< Atomically sets bits in data on remote device */
79 CVMX_SRIO_READ_MODE_ATOMIC_CLEAR = 3, /**< Atomically clears bits in data on remote device */
80 CVMX_SRIO_READ_MODE_ATOMIC_INCREMENT = 4,/**< Atomically increments data on remote device */
81 CVMX_SRIO_READ_MODE_ATOMIC_DECREMENT = 5,/**< Atomically decrements data on remote device */
82 CVMX_SRIO_READ_MODE_MAINTENANCE = 6 /**< Create a MAINTENANCE transaction. Use cvmx_srio_config_read32() instead */
83 } cvmx_srio_read_mode_t;
86 * Initialization flags for SRIO
90 CVMX_SRIO_INITIALIZE_DEBUG = 1,
91 } cvmx_srio_initialize_flags_t;
94 * The possible results from a doorbell operation
98 CVMX_SRIO_DOORBELL_DONE, /**< The doorbell is complete */
99 CVMX_SRIO_DOORBELL_NONE, /**< There wasn't an outstanding doorbell */
100 CVMX_SRIO_DOORBELL_BUSY, /**< The doorbell is still processing */
101 CVMX_SRIO_DOORBELL_RETRY, /**< The doorbell needs to be retried */
102 CVMX_SRIO_DOORBELL_ERROR /**< The doorbell failed with an error */
103 } cvmx_srio_doorbell_status_t;
106 * This structure represents the SRIO header received from SRIO on
107 * the top of every received message. This header passes through
108 * IPD/PIP unmodified.
117 #if __BYTE_ORDER == __BIG_ENDIAN
118 uint64_t prio : 2; /**< The sRIO prio (priority) field in the
119 first sRIO message segment received for the
121 uint64_t tt : 1; /**< When set, indicates that the first sRIO
122 message segment received for the message had
123 16-bit source and destination ID's. When
124 clear, indicates 8-bit ID were present. */
125 uint64_t dis : 1; /**< When set, indicates that the destination
126 ID in the first sRIO message segment received
127 for the message matched the 63xx's secondary
128 ID. When clear, indicates that the destination
129 ID in the first sRIO message segment
130 received for the message matched the 63xx's
131 primary ID. Note that the full destination
132 ID in the received sRIO message can be
133 determined via the combination of
134 WORD0[DIS] in the sRIO inbound message
135 header and WORD1[iprt] in the work queue
136 entry created by PIP/IPD. */
137 uint64_t ssize : 4; /**< The RIO ssize (standard message packet data
138 size) field used for the message. */
139 uint64_t sid : 16; /**< The source ID in the first sRIO message
140 segment received for the message. When TT is
141 clear, the most-significant 8 bits are zero. */
142 uint64_t xmbox : 4; /**< The RIO xmbox (recipient mailbox extension)
143 field in the first sRIO message segment
144 received for the message. Always zero for
145 multi-segment messages. */
146 uint64_t mbox : 2; /**< The RIO mbox (recipient mailbox) field in
147 the first sRIO message segment received for
149 uint64_t letter : 2; /**< The RIO letter (slot within a mailbox)
150 field in the first sRIO message segment
151 received for the message. */
152 uint64_t seq : 32; /**< A sequence number. Whenever the OCTEON
153 63xx sRIO hardware accepts the first sRIO
154 segment of either a message or doorbell, it
155 samples the current value of a counter
156 register and increments the counter
157 register. SEQ is the value sampled for the
158 message. The counter increments once per
159 message/doorbell. SEQ can be used to
160 determine the relative order of
161 packets/doorbells. Note that the SEQ-implied
162 order may differ from the order that the
163 WQE's are received by software for a number
164 of reasons, including the fact that the WQE
165 is not created until the end of the message,
166 while SEQ is sampled when the first segment. */
185 #if __BYTE_ORDER == __BIG_ENDIAN
186 uint64_t r : 1; /**< When set, WORD1[R]/PKT_INST_HDR[R] selects
187 either RAWFULL or RAWSCHED special PIP
188 instruction form. WORD1[R] may commonly be
189 set so that WORD1[QOS,GRP] will be directly
190 used by the PIP hardware. */
191 uint64_t reserved_62_58 : 5;
192 uint64_t pm : 2; /**< WORD1[PM]/PKT_INST_HDR[PM] selects the PIP
193 parse mode (uninterpreted, skip-to-L2,
194 skip-to-IP), and chooses between
195 RAWFULL/RAWSCHED when WORD1[R] is set. */
196 uint64_t reserved_55 : 1;
197 uint64_t sl : 7; /**< WORD1[SL]/PKT_INST_HDR[SL] selects the
198 skip II length. WORD1[SL] may typically be
199 set to 8 (or larger) so that PIP skips this
201 uint64_t reserved_47_46 : 2;
202 uint64_t nqos : 1; /**< WORD1[NQOS] must not be set when WORD1[R]
203 is clear and PIP interprets WORD1 as a
204 PKT_INST_HDR. When set, WORD1[NQOS]/PKT_INST_HDR[NQOS]
205 prevents PIP from directly using
206 WORD1[QOS]/PKT_INST_HDR[QOS] for the QOS
207 value in the work queue entry created by
208 PIP. WORD1[NQOS] may commonly be clear so
209 that WORD1[QOS] will be directly used by the
210 PIP hardware. PKT_INST_HDR[NQOS] is new to
211 63xx - this functionality did not exist in
213 uint64_t ngrp : 1; /**< WORD1[NGRP] must not be set when WORD1[R]
214 is clear and PIP interprets WORD1 as a
215 PKT_INST_HDR. When set, WORD1[NGRP]/PKT_INST_HDR[NGRP]
216 prevents PIP from directly using
217 WORD1[GRP]/PKT_INST_HDR[GRP] for the GRP
218 value in the work queue entry created by
219 PIP. WORD1[NGRP] may commonly be clear so
220 that WORD1[GRP] will be directly used by the
221 PIP hardware. PKT_INST_HDR[NGRP] is new to
222 63xx - this functionality did not exist in
224 uint64_t ntt : 1; /**< WORD1[NTT] must not be set when WORD1[R]
225 is clear and PIP interprets WORD1 as a
226 PKT_INST_HDR. When set, WORD1[NTT]/PKT_INST_HDR[NTT]
227 prevents PIP from directly using
228 WORD1[TT]/PKT_INST_HDR[TT] for the TT value
229 in the work queue entry created by PIP.
230 PKT_INST_HDR[NTT] is new to 63xx - this
231 functionality did not exist in prior OCTEON's. */
232 uint64_t ntag : 1; /**< WORD1[NTAG] must not be set when WORD1[R]
233 is clear and PIP interprets WORD1 as a
234 PKT_INST_HDR. When set, WORD1[NTAG]/PKT_INST_HDR[NTAG]
235 prevents PIP from directly using
236 WORD1[TAG]/PKT_INST_HDR[TAG] for the TAG
237 value in the work queue entry created by PIP.
238 PKT_INST_HDR[NTAG] is new to 63xx - this
239 functionality did not exist in prior OCTEON's. */
240 uint64_t qos : 3; /**< Created by the hardware from an entry in a
241 256-entry table. The 8-bit value
242 WORD0[PRIO,TT,DIS,MBOX,LETTER] selects the
243 table entry. When WORD1[R] is set and WORD1[NQOS]
244 is clear, WORD1[QOS] becomes the QOS value
245 in the work queue entry created by PIP. The
246 QOS value in the work queue entry determines
247 the priority that SSO/POW will schedule the
248 work, and can also control how/if the sRIO
249 message gets dropped by PIP/IPD. The 256-entry
250 table is unique to each sRIO core, but
251 shared by the two controllers associated
252 with the sRIO core. */
253 uint64_t grp : 4; /**< Created by the hardware from an entry in a
254 256-entry table. The 8-bit value
255 WORD0[PRIO,TT,DIS,MBOX,LETTER] selects the
256 table entry. When WORD1[R] is set and WORD1[NGRP]
257 is clear, WORD1[GRP] becomes the GRP value
258 in the work queue entry created by PIP. The
259 GRP value in the work queue entry can direct
260 the work to particular cores or particular
261 groups of cores. The 256-entry table is
262 unique to each sRIO core, but shared by the
263 two controllers associated with the sRIO core. */
264 uint64_t rs : 1; /**< In some configurations, enables the sRIO
265 message to be buffered solely in the work
266 queue entry, and not otherwise in L2/DRAM. */
267 uint64_t tt : 2; /**< When WORD1[R] is set and WORD1[NTT] is
268 clear, WORD1[TT]/PKT_INST_HDR[TT] becomes
269 the TT value in the work queue entry created
270 by PIP. The TT and TAG values in the work
271 queue entry determine the scheduling/synchronization
272 constraints for the work (no constraints,
273 tag order, atomic tag order). */
274 uint64_t tag : 32; /**< Created by the hardware from a CSR
275 associated with the sRIO inbound message
276 controller. When WORD1[R] is set and WORD1[NTAG]
277 is clear, WORD1[TAG]/PKT_INST_HDR[TAG]
278 becomes the TAG value in the work queue
279 entry created by PIP. The TT and TAG values
280 in the work queue entry determine the
281 scheduling/synchronization constraints for
282 the work (no constraints, tag order, atomic
294 uint64_t reserved_47_46 : 2;
296 uint64_t reserved_55 : 1;
298 uint64_t reserved_62_58 : 5;
303 } cvmx_srio_rx_message_header_t;
306 * This structure represents the SRIO header required on the front
307 * of PKO packets destine for SRIO message queues.
314 #if __BYTE_ORDER == __BIG_ENDIAN
315 uint64_t prio : 2; /**< The sRIO prio (priority) field for all
316 segments in the message. */
317 uint64_t tt : 1; /**< When set, the sRIO message segments use a
318 16-bit source and destination ID for all the
319 segments in the message. When clear, the
320 message segments use an 8-bit ID. */
321 uint64_t sis : 1; /**< When set, the sRIO message segments use the
322 63xx's secondary ID as the source ID. When
323 clear, the sRIO message segments use the
324 primary ID as the source ID. */
325 uint64_t ssize : 4; /**< The RIO ssize (standard message segment
326 data size) field used for the message. */
327 uint64_t did : 16; /**< The destination ID in the sRIO message
328 segments of the message. When TT is clear,
329 the most-significant 8 bits must be zero. */
330 uint64_t xmbox : 4; /**< The RIO xmbox (recipient mailbox extension)
331 field in the sRIO message segment for a
332 single-segment message. Must be zero for
333 multi-segment messages. */
334 uint64_t mbox : 2; /**< The RIO mbox (recipient mailbox) field in
335 the sRIO message segments of the message. */
336 uint64_t letter : 2; /**< The RIO letter (slot within mailbox) field
337 in the sRIO message segments of the message
338 when LNS is clear. When LNS is set, this
339 LETTER field is not used and must be zero. */
340 uint64_t reserved_31_2 : 30;
341 uint64_t lns : 1; /**< When set, the outbound message controller
342 will dynamically selects an sRIO letter
343 field for the message (based on LETTER_SP or
344 LETTER_MP - see appendix A), and the LETTER
345 field in this sRIO outbound message
346 descriptor is unused. When clear, the LETTER
347 field in this sRIO outbound message
348 descriptor selects the sRIO letter used for
350 uint64_t intr : 1; /**< When set, the outbound message controller
351 will set an interrupt bit after all sRIO
352 segments of the message receive a message
353 DONE response. If the message transfer has
354 errors, the interrupt bit is not set (but
359 uint64_t reserved_31_2 : 30;
370 } cvmx_srio_tx_message_header_t;
373 * Initialize a SRIO port for use.
375 * @param srio_port SRIO port to initialize
376 * @param flags Optional flags
378 * @return Zero on success
380 int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags);
383 * Read 32bits from a Device's config space
385 * @param srio_port SRIO port the device is on
387 * Which SRIO source ID to use. 0 = Primary, 1 = Secondary
388 * @param destid RapidIO device ID, or -1 for the local Octeon.
389 * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero
390 * if transactions should use 8bit device IDs.
391 * @param hopcount Number of hops to the remote device. Use 0 for the local Octeon.
392 * @param offset Offset in config space. This must be a multiple of 32 bits.
393 * @param result Result of the read. This will be unmodified on failure.
395 * @return Zero on success, negative on failure.
397 int cvmx_srio_config_read32(int srio_port, int srcid_index, int destid,
398 int is16bit, uint8_t hopcount, uint32_t offset,
402 * Write 32bits to a Device's config space
404 * @param srio_port SRIO port the device is on
406 * Which SRIO source ID to use. 0 = Primary, 1 = Secondary
407 * @param destid RapidIO device ID, or -1 for the local Octeon.
408 * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero
409 * if transactions should use 8bit device IDs.
410 * @param hopcount Number of hops to the remote device. Use 0 for the local Octeon.
411 * @param offset Offset in config space. This must be a multiple of 32 bits.
412 * @param data Data to write.
414 * @return Zero on success, negative on failure.
416 int cvmx_srio_config_write32(int srio_port, int srcid_index, int destid,
417 int is16bit, uint8_t hopcount, uint32_t offset,
421 * Send a RapidIO doorbell to a remote device
423 * @param srio_port SRIO port the device is on
425 * Which SRIO source ID to use. 0 = Primary, 1 = Secondary
426 * @param destid RapidIO device ID.
427 * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero
428 * if transactions should use 8bit device IDs.
429 * @param priority Doorbell priority (0-3)
430 * @param data Data for doorbell.
432 * @return Zero on success, negative on failure.
434 int cvmx_srio_send_doorbell(int srio_port, int srcid_index, int destid,
435 int is16bit, int priority, uint16_t data);
438 * Get the status of the last doorbell sent. If the dooorbell
439 * hardware is done, then the status is cleared to get ready for
440 * the next doorbell (or retry).
442 * @param srio_port SRIO port to check doorbell on
444 * @return Doorbell status
446 cvmx_srio_doorbell_status_t cvmx_srio_send_doorbell_status(int srio_port);
449 * Read a received doorbell and report data about it.
451 * @param srio_port SRIO port to check for the received doorbell
452 * @param destid_index
453 * Which Octeon destination ID was the doorbell for
454 * @param sequence_num
455 * Sequence number of doorbell (32bits)
456 * @param srcid RapidIO source ID of the doorbell sender
457 * @param priority Priority of the doorbell (0-3)
458 * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero
459 * if transactions should use 8bit device IDs.
460 * @param data Data in the doorbell (16 bits)
462 * @return Doorbell status. Either DONE, NONE, or ERROR.
464 cvmx_srio_doorbell_status_t cvmx_srio_receive_doorbell(int srio_port,
465 int *destid_index, uint32_t *sequence_num, int *srcid, int *priority,
466 int *is16bit, uint16_t *data);
469 * Receive a packet from the Soft Packet FIFO (SPF).
471 * @param srio_port SRIO port to read the packet from.
472 * @param buffer Buffer to receive the packet.
473 * @param buffer_length
474 * Length of the buffer in bytes.
476 * @return Returns the length of the packet read. Negative on failure.
477 * Zero if no packets are available.
479 int cvmx_srio_receive_spf(int srio_port, void *buffer, int buffer_length);
482 * Map a remote device's memory region into Octeon's physical
483 * address area. The caller can then map this into a core using
486 * @param srio_port SRIO port to map the device on
487 * @param write_op Type of operation to perform on a write to the device.
488 * Normally should be CVMX_SRIO_WRITE_MODE_AUTO.
489 * @param write_priority
490 * SRIO priority of writes (0-3)
491 * @param read_op Type of operation to perform on reads to the device.
492 * Normally should be CVMX_SRIO_READ_MODE_NORMAL.
493 * @param read_priority
494 * SRIO priority of reads (0-3)
496 * Which SRIO source ID to use. 0 = Primary, 1 = Secondary
497 * @param destid RapidIO device ID.
498 * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero
499 * if transactions should use 8bit device IDs.
500 * @param base Device base address to start the mapping
501 * @param size Size of the mapping in bytes
503 * @return Octeon 64bit physical address that accesses the remote device,
504 * or zero on failure.
506 uint64_t cvmx_srio_physical_map(int srio_port, cvmx_srio_write_mode_t write_op,
507 int write_priority, cvmx_srio_read_mode_t read_op, int read_priority,
508 int srcid_index, int destid, int is16bit, uint64_t base, uint64_t size);
511 * Unmap a physical address window created by cvmx_srio_phys_map().
513 * @param physical_address
514 * Physical address returned by cvmx_srio_phys_map().
515 * @param size Size used on original call.
517 * @return Zero on success, negative on failure.
519 int cvmx_srio_physical_unmap(uint64_t physical_address, uint64_t size);