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49 * Support library for the hardware work queue timers.
51 * <hr>$Revision: 49448 $<hr>
53 #include "executive-config.h"
54 #include "cvmx-config.h"
56 #include "cvmx-sysinfo.h"
58 #include "cvmx-bootmem.h"
60 /* CSR typedefs have been moved to cvmx-tim-defs.h */
63 * Global structure holding the state of all timers.
65 CVMX_SHARED cvmx_tim_t cvmx_tim;
68 #ifdef CVMX_ENABLE_TIMER_FUNCTIONS
70 * Setup a timer for use. Must be called before the timer
73 * @param tick Time between each bucket in microseconds. This must not be
74 * smaller than 1024/(clock frequency in MHz).
75 * @param max_ticks The maximum number of ticks the timer must be able
76 * to schedule in the future. There are guaranteed to be enough
77 * timer buckets such that:
78 * number of buckets >= max_ticks.
79 * @return Zero on success. Negative on error. Failures are possible
80 * if the number of buckets needed is too large or memory
81 * allocation fails for creating the buckets.
83 int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
85 cvmx_tim_mem_ring0_t config_ring0;
86 cvmx_tim_mem_ring1_t config_ring1;
89 uint64_t tim_clock_hz = cvmx_clock_get_rate(CVMX_CLOCK_TIM);
91 uint64_t hw_tick_ns_allowed;
92 uint64_t tick_ns = 1000 * tick;
96 /* for the simulator */
97 if (tim_clock_hz == 0)
98 tim_clock_hz = 333000000;
100 hw_tick_ns = 1024 * 1000000000ull / tim_clock_hz;
102 * Double the minimal allowed tick to 2 * HW tick. tick between
103 * (hw_tick_ns, 2*hw_tick_ns) will set config_ring1.s.interval
104 * to zero, or 1024 cycles. This is not enough time for the timer unit
105 * to fetch the bucket data, Resulting in timer ring error interrupt
106 * be always generated. Avoid such setting in software.
108 hw_tick_ns_allowed = hw_tick_ns * 2;
110 /* Make sure the timers are stopped */
113 /* Reinitialize out timer state */
114 memset(&cvmx_tim, 0, sizeof(cvmx_tim));
117 if ((tick_ns < (hw_tick_ns_allowed)) || (tick_ns > 4194304 * hw_tick_ns))
119 cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is smaller than"
120 " the minimal ticks allowed by hardware %lu(ns)\n",
121 tick_ns, hw_tick_ns_allowed);
127 if (tick_ns < (hw_tick_ns << i))
131 cvmx_tim.max_ticks = (uint32_t)max_ticks;
132 cvmx_tim.bucket_shift = (uint32_t)(i - 1 + 10);
133 cvmx_tim.tick_cycles = tick * tim_clock_hz / 1000000;
135 temp = (max_ticks * cvmx_tim.tick_cycles) >> cvmx_tim.bucket_shift;
137 /* round up to nearest power of 2 */
139 temp = temp | (temp >> 1);
140 temp = temp | (temp >> 2);
141 temp = temp | (temp >> 4);
142 temp = temp | (temp >> 8);
143 temp = temp | (temp >> 16);
144 cvmx_tim.num_buckets = temp + 1;
146 /* ensure input params fall into permitted ranges */
147 if ((cvmx_tim.num_buckets < 3) || cvmx_tim.num_buckets > 1048576)
149 cvmx_dprintf("ERROR: cvmx_tim_setup: num_buckets out of range\n");
153 /* Allocate the timer buckets from hardware addressable memory */
154 cvmx_tim.bucket = cvmx_bootmem_alloc(CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets
155 * sizeof(cvmx_tim_bucket_entry_t), CVMX_CACHE_LINE_SIZE);
156 if (cvmx_tim.bucket == NULL)
158 cvmx_dprintf("ERROR: cvmx_tim_setup: allocation problem\n");
161 memset(cvmx_tim.bucket, 0, CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets * sizeof(cvmx_tim_bucket_entry_t));
163 cvmx_tim.start_time = 0;
165 /* Loop through all timers */
166 for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++)
168 cvmx_tim_bucket_entry_t *bucket = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets;
169 /* Tell the hardware where about the bucket array */
170 config_ring0.u64 = 0;
171 config_ring0.s.first_bucket = cvmx_ptr_to_phys(bucket) >> 5;
172 config_ring0.s.num_buckets = cvmx_tim.num_buckets - 1;
173 config_ring0.s.ring = timer_id;
174 cvmx_write_csr(CVMX_TIM_MEM_RING0, config_ring0.u64);
176 /* Tell the hardware the size of each chunk block in pointers */
177 config_ring1.u64 = 0;
178 config_ring1.s.enable = 1;
179 config_ring1.s.pool = CVMX_FPA_TIMER_POOL;
180 config_ring1.s.words_per_chunk = CVMX_FPA_TIMER_POOL_SIZE / 8;
181 config_ring1.s.interval = (1 << (cvmx_tim.bucket_shift - 10)) - 1;
182 config_ring1.s.ring = timer_id;
183 cvmx_write_csr(CVMX_TIM_MEM_RING1, config_ring1.u64);
191 * Start the hardware timer processing
193 void cvmx_tim_start(void)
195 cvmx_tim_control_t control;
198 control.s.enable_dwb = 1;
199 control.s.enable_timers = 1;
201 /* Remember when we started the timers */
202 cvmx_tim.start_time = cvmx_clock_get_count(CVMX_CLOCK_TIM);
203 cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
208 * Stop the hardware timer processing. Timers stay configured.
210 void cvmx_tim_stop(void)
212 cvmx_tim_control_t control;
214 control.s.enable_dwb = 0;
215 control.s.enable_timers = 0;
216 cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
221 * Stop the timer. After this the timer must be setup again
224 #ifdef CVMX_ENABLE_TIMER_FUNCTIONS
225 void cvmx_tim_shutdown(void)
229 uint64_t entries_per_chunk;
231 /* Make sure the timers are stopped */
234 entries_per_chunk = CVMX_FPA_TIMER_POOL_SIZE/8 - 1;
236 /* Now walk all buckets freeing the chunks */
237 for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++)
239 for (bucket=0; bucket<cvmx_tim.num_buckets; bucket++)
242 uint64_t next_chunk_addr;
243 cvmx_tim_bucket_entry_t *bucket_ptr = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets + bucket;
244 CVMX_PREFETCH128(CAST64(bucket_ptr)); /* prefetch the next cacheline for future buckets */
246 /* Each bucket contains a list of chunks */
247 chunk_addr = bucket_ptr->first_chunk_addr;
248 while (bucket_ptr->num_entries)
251 cvmx_dprintf("Freeing Timer Chunk 0x%llx\n", CAST64(chunk_addr));
253 /* Read next chunk pointer from end of the current chunk */
254 next_chunk_addr = cvmx_read_csr(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, chunk_addr + CVMX_FPA_TIMER_POOL_SIZE - 8));
256 cvmx_fpa_free(cvmx_phys_to_ptr(chunk_addr), CVMX_FPA_TIMER_POOL, 0);
257 chunk_addr = next_chunk_addr;
258 if (bucket_ptr->num_entries > entries_per_chunk)
259 bucket_ptr->num_entries -= entries_per_chunk;
261 bucket_ptr->num_entries = 0;