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50 * Interface to the Trace buffer hardware.
52 * WRITING THE TRACE BUFFER
54 * When the trace is enabled, commands are traced continuously (wrapping) or until the buffer is filled once
55 * (no wrapping). Additionally and independent of wrapping, tracing can be temporarily enabled and disabled
56 * by the tracing triggers. All XMC commands can be traced except for IDLE and IOBRSP. The subset of XMC
57 * commands that are traced is determined by the filter and the two triggers, each of which is comprised of
58 * masks for command, sid, did, and address). If triggers are disabled, then only those commands matching
59 * the filter are traced. If triggers are enabled, then only those commands matching the filter, the start
60 * trigger, or the stop trigger are traced during the time between a start trigger and a stop trigger.
62 * For a given command, its XMC data is written immediately to the buffer. If the command has XMD data,
63 * then that data comes in-order at some later time. The XMD data is accumulated across all valid
64 * XMD cycles and written to the buffer or to a shallow fifo. Data from the fifo is written to the buffer
65 * as soon as it gets access to write the buffer (i.e. the buffer is not currently being written with XMC
66 * data). If the fifo overflows, it simply overwrites itself and the previous XMD data is lost.
69 * READING THE TRACE BUFFER
71 * Each entry of the trace buffer is read by a CSR read command. The trace buffer services each read in order,
72 * as soon as it has access to the (single-ported) trace buffer.
74 * On Octeon2, each entry of the trace buffer is read by two CSR memory read operations. The first read accesses
75 * bits 63:0 of the buffer entry, and the second read accesses bits 68:64 of the buffer entry. The trace buffer
76 * services each read in order, as soon as it has access to the (single-ported) trace buffer. Buffer's read pointer
77 * increments after two CSR memory read operations.
80 * OVERFLOW, UNDERFLOW AND THRESHOLD EVENTS
82 * The trace buffer maintains a write pointer and a read pointer and detects both the overflow and underflow
83 * conditions. Each time a new trace is enabled, both pointers are reset to entry 0. Normally, each write
84 * (traced event) increments the write pointer and each read increments the read pointer. During the overflow
85 * condition, writing (tracing) is disabled. Tracing will continue as soon as the overflow condition is
86 * resolved. The first entry that is written immediately following the overflow condition may be marked to
87 * indicate that a tracing discontinuity has occurred before this entry. During the underflow condition,
88 * reading does not increment the read pointer and the read data is marked to indicate that no read data is
91 * The full threshold events are defined to signal an interrupt a certain levels of "fullness" (1/2, 3/4, 4/4).
92 * "fullness" is defined as the relative distance between the write and read pointers (i.e. not defined as the
93 * absolute distance between the write pointer and entry 0). When enabled, the full threshold event occurs
94 * every time the desired level of "fullness" is achieved.
97 * Trace buffer entry format
100 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
101 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
102 * |sta| address[35:3] | 0 | src id | 0 | DWB | diff timestamp|
103 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
104 * |sta| address[35:3] | 0 | src id | 0 | PL2 | diff timestamp|
105 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
106 * |sta| address[35:3] | 0 | src id | 0 | PSL1 | diff timestamp|
107 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
108 * |sta| address[35:3] | 0 | src id | 0 | LDD | diff timestamp|
109 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
110 * |sta| address[35:3] | 0 | src id | 0 | LDI | diff timestamp|
111 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
112 * |sta| address[35:3] | 0 | src id | 0 | LDT | diff timestamp|
113 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
114 * |sta| address[35:3] | * or 16B mask | src id | 0 | STC | diff timestamp|
115 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
116 * |sta| address[35:3] | * or 16B mask | src id | 0 | STF | diff timestamp|
117 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
118 * |sta| address[35:3] | * or 16B mask | src id | 0 | STP | diff timestamp|
119 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
120 * |sta| address[35:3] | * or 16B mask | src id | 0 | STT | diff timestamp|
121 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
122 * |sta| address[35:0] | 0 | src id| dest id |IOBLD8 | diff timestamp|
123 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
124 * |sta| address[35:1] | 0 | src id| dest id |IOBLD16| diff timestamp|
125 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
126 * |sta| address[35:2] | 0 | src id| dest id |IOBLD32| diff timestamp|
127 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
128 * |sta| address[35:3] | 0 | src id| dest id |IOBLD64| diff timestamp|
129 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
130 * |sta| address[35:3] | * or 16B mask | src id| dest id |IOBST | diff timestamp|
131 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
132 * |sta| * or address[35:3] | * or length | src id| dest id |IOBDMA | diff timestamp|
133 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
136 * Trace buffer entry format in Octeon2 is different
139 * 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
140 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
141 * |sta| address[37:0] | 0 | src id | Group 1 | diff timestamp|
142 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
143 * |sta| address[37:0] | 0 | xmd mask | src id | Group 2 | diff timestamp|
144 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
145 * |sta| address[37:0] | 0 |s-did| dest id | src id | Group 3 | diff timestamp|
146 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
147 * |sta| *address[37:3] | *Length | dest id | src id | Group 4 | diff timestamp|
148 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
151 * - diff timestamp is the difference in time from the previous trace event to this event - 1. the granularity of the timestamp is programmable
152 * - Fields marked as '*' are first filled with '0' at XMC time and may be filled with real data later at XMD time. Note that the
153 * XMD write may be dropped if the shallow FIFO overflows which leaves the '*' fields as '0'.
154 * - 2 bits (sta) are used not to trace, but to return global state information with each read, encoded as follows:
156 * 0x1=valid, no discontinuity
157 * 0x2=not valid, discontinuity
158 * 0x3=valid, discontinuity
159 * - commands are encoded as follows:
176 * - In Octeon2 the commands are grouped as follows:
178 * XMC_LDT, XMC_LDI, XMC_PL2, XMC_RPL2, XMC_DWB, XMC_WBL2,
179 * XMC_SET8, XMC_SET16, XMC_SET32, XMC_SET64,
180 * XMC_CLR8, XMC_CLR16, XMC_CLR32, XMC_CLR64,
181 * XMC_INCR8, XMC_INCR16, XMC_INCR32, XMC_INCR64,
182 * XMC_DECR8, XMC_DECR16, XMC_DECR32, XMC_DECR64
184 * XMC_STF, XMC_STT, XMC_STP, XMC_STC,
186 * XMC_SAA32, XMC_SAA64,
187 * XMC_FAA32, XMC_FAA64,
188 * XMC_FAS32, XMC_FAS64
190 * XMC_IOBLD8, XMC_IOBLD16, XMC_IOBLD32, XMC_IOBLD64,
191 * XMC_IOBST8, XMC_IOBST16, XMC_IOBST32, XMC_IOBST64
194 * - For non IOB* commands
195 * - source id is encoded as follows:
199 * 0x12=IOB(ReqLoad, ReqStore)
203 * - dest id is unused (can only be L2c)
204 * - For IOB* commands
205 * - source id is encoded as follows:
207 * - dest id is encoded as follows:
208 * 0 = CIU/GPIO (for CSRs)
210 * 3 = PCIe (access to RSL-type CSRs)
211 * 4 = KEY (read/write operations)
212 * 5 = FPA (free pool allocate/free operations)
214 * 7 = ZIP (doorbell operations)
215 * 8 = RNG (load/IOBDMA operations)
216 * 10 = PKO (doorbell operations)
218 * 12 = POW (get work, add work, status/memory/index loads, NULLrd load operations, CSR operations)
222 * <hr>$Revision: 70030 $<hr>
225 #ifndef __CVMX_TRA_H__
226 #define __CVMX_TRA_H__
229 #include "cvmx-l2c.h"
230 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
231 #include "cvmx-tra-defs.h"
239 /* CSR typedefs have been moved to cvmx-tra-defs.h */
241 /* The 'saa' filter command is renamed as 'saa64' */
242 #define CVMX_TRA_FILT_SAA CVMX_TRA_FILT_SAA64
243 /* The 'iobst' filter command is renamed as 'iobst64' */
244 #define CVMX_TRA_FILT_IOBST CVMX_TRA_FILT_IOBST64
247 * Enumeration of the bitmask of all the filter commands. The bit positions
248 * correspond to Octeon2 model.
252 CVMX_TRA_FILT_NOP = 1ull<<0, /**< none */
253 CVMX_TRA_FILT_LDT = 1ull<<1, /**< don't allocate L2 or L1 */
254 CVMX_TRA_FILT_LDI = 1ull<<2, /**< don't allocate L1 */
255 CVMX_TRA_FILT_PL2 = 1ull<<3, /**< pref L2 */
256 CVMX_TRA_FILT_RPL2 = 1ull<<4, /**< mark for replacement in L2 */
257 CVMX_TRA_FILT_DWB = 1ull<<5, /**< clear L2 dirty bit (no writeback) + RPL2 */
258 CVMX_TRA_FILT_LDD = 1ull<<8, /**< normal load */
259 CVMX_TRA_FILT_PSL1 = 1ull<<9, /**< pref L1, bypass L2 */
260 CVMX_TRA_FILT_IOBDMA = 1ull<<15, /**< store reflection by IOB for prior load */
261 CVMX_TRA_FILT_STF = 1ull<<16, /**< full block store to L2, fill 0's */
262 CVMX_TRA_FILT_STT = 1ull<<17, /**< full block store bypass-L2, fill 0's */
263 CVMX_TRA_FILT_STP = 1ull<<18, /**< partial store to L2 */
264 CVMX_TRA_FILT_STC = 1ull<<19, /**< partial store to L2, if duptag valid */
265 CVMX_TRA_FILT_STFIL1 = 1ull<<20, /**< full block store to L2, fill 0's, invalidate L1 */
266 CVMX_TRA_FILT_STTIL1 = 1ull<<21, /**< full block store bypass-L2, fill 0's, invalidate L1 */
267 CVMX_TRA_FILT_FAS32 = 1ull<<22, /**< to load from and write a word of memory atomically */
268 CVMX_TRA_FILT_FAS64 = 1ull<<23, /**< to load from and write a doubleword of memory atomically */
269 CVMX_TRA_FILT_WBIL2I = 1ull<<24, /**< writeback if dirty, invalidate, clear use bit, by index/way */
270 CVMX_TRA_FILT_LTGL2I = 1ull<<25, /**< read tag @ index/way into CSR */
271 CVMX_TRA_FILT_STGL2I = 1ull<<26, /**< write tag @ index/way from CSR */
272 CVMX_TRA_FILT_INVL2 = 1ull<<28, /**< invalidate, clear use bit, by address (dirty data is LOST) */
273 CVMX_TRA_FILT_WBIL2 = 1ull<<29, /**< writeback if dirty, invalidate, clear use bit, by address */
274 CVMX_TRA_FILT_WBL2 = 1ull<<30, /**< writeback if dirty, make clean, clear use bit, by address */
275 CVMX_TRA_FILT_LCKL2 = 1ull<<31, /**< allocate (if miss), set lock bit, set use bit, by address */
276 CVMX_TRA_FILT_IOBLD8 = 1ull<<32, /**< load reflection 8bit */
277 CVMX_TRA_FILT_IOBLD16 = 1ull<<33, /**< load reflection 16bit */
278 CVMX_TRA_FILT_IOBLD32 = 1ull<<34, /**< load reflection 32bit */
279 CVMX_TRA_FILT_IOBLD64 = 1ull<<35, /**< load reflection 64bit */
280 CVMX_TRA_FILT_IOBST8 = 1ull<<36, /**< store reflection 8bit */
281 CVMX_TRA_FILT_IOBST16 = 1ull<<37, /**< store reflection 16bit */
282 CVMX_TRA_FILT_IOBST32 = 1ull<<38, /**< store reflection 32bit */
283 CVMX_TRA_FILT_IOBST64 = 1ull<<39, /**< store reflection 64bit */
284 CVMX_TRA_FILT_SET8 = 1ull<<40, /**< to load from and write 1's to 8bit of memory atomically */
285 CVMX_TRA_FILT_SET16 = 1ull<<41, /**< to load from and write 1's to 16bit of memory atomically */
286 CVMX_TRA_FILT_SET32 = 1ull<<42, /**< to load from and write 1's to 32bit of memory atomically */
287 CVMX_TRA_FILT_SET64 = 1ull<<43, /**< to load from and write 1's to 64bit of memory atomically */
288 CVMX_TRA_FILT_CLR8 = 1ull<<44, /**< to load from and write 0's to 8bit of memory atomically */
289 CVMX_TRA_FILT_CLR16 = 1ull<<45, /**< to load from and write 0's to 16bit of memory atomically */
290 CVMX_TRA_FILT_CLR32 = 1ull<<46, /**< to load from and write 0's to 32bit of memory atomically */
291 CVMX_TRA_FILT_CLR64 = 1ull<<47, /**< to load from and write 0's to 64bit of memory atomically */
292 CVMX_TRA_FILT_INCR8 = 1ull<<48, /**< to load and increment 8bit of memory atomically */
293 CVMX_TRA_FILT_INCR16 = 1ull<<49, /**< to load and increment 16bit of memory atomically */
294 CVMX_TRA_FILT_INCR32 = 1ull<<50, /**< to load and increment 32bit of memory atomically */
295 CVMX_TRA_FILT_INCR64 = 1ull<<51, /**< to load and increment 64bit of memory atomically */
296 CVMX_TRA_FILT_DECR8 = 1ull<<52, /**< to load and decrement 8bit of memory atomically */
297 CVMX_TRA_FILT_DECR16 = 1ull<<53, /**< to load and decrement 16bit of memory atomically */
298 CVMX_TRA_FILT_DECR32 = 1ull<<54, /**< to load and decrement 32bit of memory atomically */
299 CVMX_TRA_FILT_DECR64 = 1ull<<55, /**< to load and decrement 64bit of memory atomically */
300 CVMX_TRA_FILT_FAA32 = 1ull<<58, /**< to load from and add to a word of memory atomically */
301 CVMX_TRA_FILT_FAA64 = 1ull<<59, /**< to load from and add to a doubleword of memory atomically */
302 CVMX_TRA_FILT_SAA32 = 1ull<<62, /**< to atomically add a word to a memory location */
303 CVMX_TRA_FILT_SAA64 = 1ull<<63, /**< to atomically add a doubleword to a memory location */
304 CVMX_TRA_FILT_ALL = -1ull /**< all the above filter commands */
308 * Enumeration of the bitmask of all source commands.
312 CVMX_TRA_SID_PP0 = 1ull<<0, /**< Enable tracing from PP0 with matching sourceID */
313 CVMX_TRA_SID_PP1 = 1ull<<1, /**< Enable tracing from PP1 with matching sourceID */
314 CVMX_TRA_SID_PP2 = 1ull<<2, /**< Enable tracing from PP2 with matching sourceID */
315 CVMX_TRA_SID_PP3 = 1ull<<3, /**< Enable tracing from PP3 with matching sourceID */
316 CVMX_TRA_SID_PP4 = 1ull<<4, /**< Enable tracing from PP4 with matching sourceID */
317 CVMX_TRA_SID_PP5 = 1ull<<5, /**< Enable tracing from PP5 with matching sourceID */
318 CVMX_TRA_SID_PP6 = 1ull<<6, /**< Enable tracing from PP6 with matching sourceID */
319 CVMX_TRA_SID_PP7 = 1ull<<7, /**< Enable tracing from PP7 with matching sourceID */
320 CVMX_TRA_SID_PP8 = 1ull<<8, /**< Enable tracing from PP8 with matching sourceID */
321 CVMX_TRA_SID_PP9 = 1ull<<9, /**< Enable tracing from PP9 with matching sourceID */
322 CVMX_TRA_SID_PP10 = 1ull<<10, /**< Enable tracing from PP10 with matching sourceID */
323 CVMX_TRA_SID_PP11 = 1ull<<11, /**< Enable tracing from PP11 with matching sourceID */
324 CVMX_TRA_SID_PP12 = 1ull<<12, /**< Enable tracing from PP12 with matching sourceID */
325 CVMX_TRA_SID_PP13 = 1ull<<13, /**< Enable tracing from PP13 with matching sourceID */
326 CVMX_TRA_SID_PP14 = 1ull<<14, /**< Enable tracing from PP14 with matching sourceID */
327 CVMX_TRA_SID_PP15 = 1ull<<15, /**< Enable tracing from PP15 with matching sourceID */
328 CVMX_TRA_SID_PKI = 1ull<<16, /**< Enable tracing of write requests from PIP/IPD */
329 CVMX_TRA_SID_PKO = 1ull<<17, /**< Enable tracing of write requests from PKO */
330 CVMX_TRA_SID_IOBREQ = 1ull<<18, /**< Enable tracing of write requests from FPA,TIM,DFA,PCI,ZIP,POW, and PKO (writes) */
331 CVMX_TRA_SID_DWB = 1ull<<19, /**< Enable tracing of write requests from IOB DWB engine */
332 CVMX_TRA_SID_ALL = -1ull /**< Enable tracing all the above source commands */
336 #define CVMX_TRA_DID_SLI CVMX_TRA_DID_PCI /**< Enable tracing of requests to SLI and RSL-type CSRs. */
338 * Enumeration of the bitmask of all destination commands.
342 CVMX_TRA_DID_MIO = 1ull<<0, /**< Enable tracing of CIU and GPIO CSR's */
343 CVMX_TRA_DID_PCI = 1ull<<3, /**< Enable tracing of requests to PCI and RSL type CSR's */
344 CVMX_TRA_DID_KEY = 1ull<<4, /**< Enable tracing of requests to KEY memory */
345 CVMX_TRA_DID_FPA = 1ull<<5, /**< Enable tracing of requests to FPA */
346 CVMX_TRA_DID_DFA = 1ull<<6, /**< Enable tracing of requests to DFA */
347 CVMX_TRA_DID_ZIP = 1ull<<7, /**< Enable tracing of requests to ZIP */
348 CVMX_TRA_DID_RNG = 1ull<<8, /**< Enable tracing of requests to RNG */
349 CVMX_TRA_DID_IPD = 1ull<<9, /**< Enable tracing of IPD CSR accesses */
350 CVMX_TRA_DID_PKO = 1ull<<10, /**< Enable tracing of PKO accesses (doorbells) */
351 CVMX_TRA_DID_POW = 1ull<<12, /**< Enable tracing of requests to RNG */
352 CVMX_TRA_DID_USB0 = 1ull<<13, /**< Enable tracing of USB0 accesses (UAHC0 EHCI and OHCI NCB CSRs) */
353 CVMX_TRA_DID_RAD = 1ull<<14, /**< Enable tracing of RAD accesses (doorbells) */
354 CVMX_TRA_DID_DPI = 1ull<<27, /**< Enable tracing of DPI accesses (DPI NCD CSRs) */
355 CVMX_TRA_DID_FAU = 1ull<<30, /**< Enable tracing FAU accesses */
356 CVMX_TRA_DID_ALL = -1ull /**< Enable tracing all the above destination commands */
360 * TRA data format definition. Use the type field to
361 * determine which union element to use.
363 * In Octeon 2, the trace buffer is 69 bits,
364 * the first read accesses bits 63:0 of the trace buffer entry, and
365 * the second read accesses bits 68:64 of the trace buffer entry.
371 #ifdef __BIG_ENDIAN_BITFIELD
382 #ifdef __BIG_ENDIAN_BITFIELD
383 uint64_t reserved3 : 64;
385 uint64_t discontinuity:1;
386 uint64_t address : 36;
387 uint64_t reserved : 5;
389 uint64_t reserved2 : 3;
391 uint64_t timestamp : 8;
393 uint64_t timestamp : 8;
395 uint64_t reserved2 : 3;
397 uint64_t reserved : 5;
398 uint64_t address : 36;
399 uint64_t discontinuity:1;
401 uint64_t reserved3 : 64;
403 } cmn; /**< for DWB, PL2, PSL1, LDD, LDI, LDT */
406 #ifdef __BIG_ENDIAN_BITFIELD
407 uint64_t reserved3 : 64;
409 uint64_t discontinuity:1;
410 uint64_t address : 33;
413 uint64_t reserved2 : 3;
415 uint64_t timestamp : 8;
417 uint64_t timestamp : 8;
419 uint64_t reserved2 : 3;
422 uint64_t address : 33;
423 uint64_t discontinuity:1;
425 uint64_t reserved3 : 64;
427 } store; /**< STC, STF, STP, STT */
430 #ifdef __BIG_ENDIAN_BITFIELD
431 uint64_t reserved3 : 64;
433 uint64_t discontinuity:1;
434 uint64_t address : 36;
435 uint64_t reserved : 2;
440 uint64_t timestamp : 8;
442 uint64_t timestamp : 8;
447 uint64_t reserved : 2;
448 uint64_t address : 36;
449 uint64_t discontinuity:1;
451 uint64_t reserved3 : 64;
453 } iobld; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST, SAA */
456 #ifdef __BIG_ENDIAN_BITFIELD
457 uint64_t reserved3 : 64;
459 uint64_t discontinuity:1;
460 uint64_t address : 33;
465 uint64_t timestamp : 8;
467 uint64_t timestamp : 8;
472 uint64_t address : 33;
473 uint64_t discontinuity:1;
475 uint64_t reserved3 : 64;
477 } iob; /**< for IOBDMA */
481 #ifdef __BIG_ENDIAN_BITFIELD
482 uint64_t reserved1 : 59;
483 uint64_t discontinuity:1;
485 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
486 uint64_t addresslo : 35; /* and lower 64-bits. */
487 uint64_t reserved : 10;
490 uint64_t timestamp : 8;
492 uint64_t timestamp : 8;
495 uint64_t reserved : 10;
496 uint64_t addresslo : 35;
497 uint64_t addresshi : 3;
499 uint64_t discontinuity:1;
500 uint64_t reserved1 : 59;
502 } cmn2; /**< for LDT, LDI, PL2, RPL2, DWB, WBL2, WBIL2i, LTGL2i, STGL2i, INVL2, WBIL2, LCKL2, SET*, CLR*, INCR*, DECR* */
505 #ifdef __BIG_ENDIAN_BITFIELD
506 uint64_t reserved1 : 59;
507 uint64_t discontinuity:1;
509 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
510 uint64_t addresslo : 35; /* and lower 64-bits */
511 uint64_t reserved : 2;
515 uint64_t timestamp : 8;
517 uint64_t timestamp : 8;
521 uint64_t reserved : 2;
522 uint64_t addresslo : 35;
523 uint64_t addresshi : 3;
525 uint64_t discontinuity:1;
526 uint64_t reserved1 : 59;
528 } store2; /**< for STC, STF, STP, STT, LDD, PSL1, SAA32, SAA64, FAA32, FAA64, FAS32, FAS64, STTIL1, STFIL1 */
531 #ifdef __BIG_ENDIAN_BITFIELD
532 uint64_t reserved1 : 59;
533 uint64_t discontinuity:1;
535 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
536 uint64_t addresslo : 35; /* and lower 64-bits */
537 uint64_t reserved : 2;
542 uint64_t timestamp : 8;
544 uint64_t timestamp : 8;
549 uint64_t reserved : 2;
550 uint64_t addresslo : 35;
551 uint64_t addresshi : 3;
553 uint64_t discontinuity:1;
554 uint64_t reserved1 : 59;
556 } iobld2; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST64, IOBST32, IOBST16, IOBST8 */
559 #ifdef __BIG_ENDIAN_BITFIELD
560 uint64_t reserved1 : 59;
561 uint64_t discontinuity:1;
563 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
564 uint64_t addresslo : 32; /* and lower 64-bits */
569 uint64_t timestamp : 8;
571 uint64_t timestamp : 8;
576 uint64_t addresslo : 32;
577 uint64_t addresshi : 3;
579 uint64_t discontinuity:1;
580 uint64_t reserved1 : 59;
582 } iob2; /**< for IOBDMA */
585 /* The trace buffer number to use. */
586 extern int _cvmx_tra_unit;
589 * Setup the TRA buffer for use
591 * @param control TRA control setup
592 * @param filter Which events to log
593 * @param source_filter
597 * @param address Address compare
598 * @param address_mask
601 extern void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
602 cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
603 uint64_t address, uint64_t address_mask);
606 * Setup each TRA buffer for use
608 * @param tra Which TRA buffer to use (0-3)
609 * @param control TRA control setup
610 * @param filter Which events to log
611 * @param source_filter
615 * @param address Address compare
616 * @param address_mask
619 extern void cvmx_tra_setup_v2(int tra, cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
620 cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
621 uint64_t address, uint64_t address_mask);
624 * Setup a TRA trigger. How the triggers are used should be
625 * setup using cvmx_tra_setup.
627 * @param trigger Trigger to setup (0 or 1)
628 * @param filter Which types of events to trigger on
629 * @param source_filter
630 * Source trigger match
632 * Destination trigger match
633 * @param address Trigger address compare
634 * @param address_mask
635 * Trigger address mask
637 extern void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_t filter,
638 cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
639 uint64_t address, uint64_t address_mask);
642 * Setup each TRA trigger. How the triggers are used should be
643 * setup using cvmx_tra_setup.
645 * @param tra Which TRA buffer to use (0-3)
646 * @param trigger Trigger to setup (0 or 1)
647 * @param filter Which types of events to trigger on
648 * @param source_filter
649 * Source trigger match
651 * Destination trigger match
652 * @param address Trigger address compare
653 * @param address_mask
654 * Trigger address mask
656 extern void cvmx_tra_trig_setup_v2(int tra, uint64_t trigger, cvmx_tra_filt_t filter,
657 cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
658 uint64_t address, uint64_t address_mask);
661 * Read an entry from the TRA buffer. The trace buffer format is
662 * different in Octeon2, need to read twice from TRA_READ_DAT.
664 * @return Value return. High bit will be zero if there wasn't any data
666 extern cvmx_tra_data_t cvmx_tra_read(void);
669 * Read an entry from the TRA buffer from a given TRA unit.
671 * @param tra_unit Trace buffer unit to read
673 * @return Value return. High bit will be zero if there wasn't any data
675 cvmx_tra_data_t cvmx_tra_read_v2(int tra_unit);
678 * Decode a TRA entry into human readable output
680 * @param tra_ctl Trace control setup
681 * @param data Data to decode
683 extern void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data);
686 * Display the entire trace buffer. It is advised that you
687 * disable the trace buffer before calling this routine
688 * otherwise it could infinitely loop displaying trace data
691 extern void cvmx_tra_display(void);
694 * Display the entire trace buffer. It is advised that you
695 * disable the trace buffer before calling this routine
696 * otherwise it could infinitely loop displaying trace data
699 * @param tra_unit Which TRA buffer to use.
701 extern void cvmx_tra_display_v2(int tra_unit);
704 * Enable or disable the TRA hardware, by default enables all TRAs.
706 * @param enable 1=enable, 0=disable
708 static inline void cvmx_tra_enable(int enable)
710 cvmx_tra_ctl_t control;
713 for (tad = 0; tad < CVMX_L2C_TADS; tad++)
715 control.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tad));
716 control.s.ena = enable;
717 cvmx_write_csr(CVMX_TRAX_CTL(tad), control.u64);
718 cvmx_read_csr(CVMX_TRAX_CTL(tad));
723 * Enable or disable a particular TRA hardware
725 * @param enable 1=enable, 0=disable
726 * @param tra which TRA to enable, CN68XX has 4.
728 static inline void cvmx_tra_enable_v2(int enable, int tra)
730 cvmx_tra_ctl_t control;
732 if ((tra + 1) > CVMX_L2C_TADS)
734 cvmx_dprintf("cvmx_tra_enable: Invalid TRA(%d), max allowed are %d\n", tra, CVMX_L2C_TADS - 1);
737 control.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tra));
738 control.s.ena = enable;
739 cvmx_write_csr(CVMX_TRAX_CTL(tra), control.u64);
740 cvmx_read_csr(CVMX_TRAX_CTL(tra));