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168 * Copyright (c) 2003-2007, Cavium Networks. All rights reserved.
172 * OCTEON SDK License Type 4:
174 * Author: Cavium Networks
176 * Contact: support@caviumnetworks.com
177 * This file is part of the OCTEON SDK
179 * Copyright (c) 2007 Cavium Networks
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199 ***********************license end**************************************/
202 #ifndef __CVMX_TWSI_RAW_H__
203 #define __CVMX_TWSI_RAW_H__
205 /* Addresses for twsi 8-bit registers. Gets written to EOP_IA field of MIO_TWS_SW_TWSI reg
206 * when OP = 6 and SLONLY =0 */
207 #define TWSI_SLAVE_ADD_REG 0
208 #define TWSI_DATA_REG 1
209 #define TWSI_CTL_REG 2
210 #define TWSI_STAT_REG 3 /* read only */
211 #define TWSI_CLKCTL_REG 3 /* write only */
212 #define TWSI_SLAVE_EXTADD_REG 4
213 #define TWSI_RST_REG 7
215 /* twsi core slave address reg */
219 uint8_t slave_addr7 : 7;
223 } octeon_twsi_slave_add_t;
225 /* twsi core 10-bit slave address reg */
229 uint8_t slave_addr8 : 8;
231 } octeon_twsi_slave_extadd_t;
233 /* twsi core control register */
237 uint8_t ce : 1; /* enable HLC*/
238 uint8_t enab : 1; /* bus enable */
239 uint8_t sta : 1; /* start request */
240 uint8_t stp : 1; /* stop request */
241 uint8_t iflg : 1; /* interrupt flag - request completed (1) start new (0) */
242 uint8_t aak : 1; /* assert ack (1) -neg ack at end of Rx sequence */
243 uint8_t rsv : 2; /* not used */
247 /* clock dividers register */
251 uint8_t m_divider : 4;
252 uint8_t n_divider : 3;
254 } octeon_twsi_clkctl_t;
256 /* address of the remote slave + r/w bit */
260 uint8_t slave_addr7 : 7;
261 uint8_t r : 1; /* read (1) write (0) bit */
263 } octeon_twsi_addr_t;
271 } octeon_twsi_stat_t;
279 } octeon_twsi_data_t;
281 /* twsi core states as reported in twsi core stat register */
282 #define TWSI_BUS_ERROR 0x00
283 #define TWSI_START_TXED 0x08
284 #define TWSI_ADDR_W_TX_ACK_RXED 0x18
285 #define TWSI_ADDR_W_TX_NACK_RXED 0x20
287 #define TWSI_DATA_TX_ACK_RXED 0x28
288 #define TWSI_DATA_TX_NACK_RXED 0x30
289 #define TWSI_ARB_LOST 0x38
290 #define TWSI_ADDR_R_TX_ACK_RXED 0x40
292 #define TWSI_ADDR_R_TX_NACK_RXED 0x48
293 #define TWSI_DATA_RX_ACK_TXED 0x50
294 #define TWSI_DATA_RX_NACK_TXED 0x58
295 #define TWSI_SLAVE_ADDR_RX_ACK_TXED 0x60
297 #define TWSI_ARB_LOST_SLAVE_ADDR_RX 0x68
298 #define TWSI_GEN_ADDR_RXED_ACK_TXED 0x70
299 #define TWSI_ARB_LOST_GEN_ADDR_RXED 0x78
300 #define TWSI_SLAVE_DATA_RX_ACK_TXED 0x80
302 #define TWSI_SLAVE_DATA_RX_NACK_TXED 0x88
303 #define TWSI_GEN_DATA_RX_ACK_TXED 0x90
304 #define TWSI_GEN_DATA_RX_NACK_TXED 0x98
305 #define TWSI_SLAVE_STOP_OR_START_RXED 0xa0
307 #define TWSI_SLAVE_ADDR_R_RX_ACK_TXED 0xa8
308 #define TWSI_ARB_LOST_SLAVE_ADDR_R_RX_ACK_TXED 0xb0
309 #define TWSI_SLAVE_DATA_TX_ACK_RXED 0xb8
310 #define TWSI_SLAVE_DATA_TX_NACK_RXED 0xc0
312 #define TWSI_SLAVE_LAST_DATA_TX_ACK_RXED 0xc8
313 #define TWSI_SECOND_ADDR_W_TX_ACK_RXED 0xd0
314 #define TWSI_SECOND_ADDR_W_TX_NACK_RXED 0xd8
315 #define TWSI_IDLE 0xf8
318 /* msg definition similar to Linux */
320 uint16_t addr; /* slave address */
322 uint16_t len; /* msg length */
323 uint8_t *buf; /* pointer to msg data */
325 #define I2C_M_TEN 0x10 /* we have a ten bit chip address */
326 #define I2C_M_RD 0x01
329 int octeon_i2c_xfer_msg_raw(int twsi_id, struct i2c_msg *msg);