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44 * This header file defines the work queue entry (wqe) data structure.
45 * Since this is a commonly used structure that depends on structures
46 * from several hardware blocks, those definitions have been placed
47 * in this file to create a single point of definition of the wqe
49 * Data structures are still named according to the block that they
52 * This file must not depend on any other header files, except for cvmx.h!!!
55 * <hr>$Revision: 49448 $<hr>
60 #ifndef __CVMX_WQE_H__
61 #define __CVMX_WQE_H__
67 #define OCT_TAG_TYPE_STRING(x) (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \
68 (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \
69 (((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \
74 * HW decode / err_code in work queue entry
80 /** Use this struct if the hardware determines that the packet is IP */
83 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
84 uint64_t ip_offset : 8; /**< HW sets to the number of L2 bytes prior to the IP */
85 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
86 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
87 uint64_t unassigned : 1;
88 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
89 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
90 uint64_t pr : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
91 uint64_t unassigned2 : 8;
92 uint64_t dec_ipcomp : 1; /**< the packet needs to be decompressed */
93 uint64_t tcp_or_udp : 1; /**< the packet is either TCP or UDP */
94 uint64_t dec_ipsec : 1; /**< the packet needs to be decrypted (ESP or AH) */
95 uint64_t is_v6 : 1; /**< the packet is IPv6 */
97 /* (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.) */
99 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
100 /* exceptional conditions below */
101 uint64_t L4_error : 1; /**< the receive interface hardware detected an L4 error (only applies if !is_frag)
102 (only applies if !rcv_error && !not_IP && !IP_exc && !is_frag)
103 failure indicated in err_code below, decode:
105 - 2 = L4 Checksum Error: the L4 checksum value is
106 - 3 = UDP Length Error: The UDP length field would make the UDP data longer than what
107 remains in the IP packet (as defined by the IP header length field).
108 - 4 = Bad L4 Port: either the source or destination TCP/UDP port is 0.
109 - 8 = TCP FIN Only: the packet is TCP and only the FIN flag set.
110 - 9 = TCP No Flags: the packet is TCP and no flags are set.
111 - 10 = TCP FIN RST: the packet is TCP and both FIN and RST are set.
112 - 11 = TCP SYN URG: the packet is TCP and both SYN and URG are set.
113 - 12 = TCP SYN RST: the packet is TCP and both SYN and RST are set.
114 - 13 = TCP SYN FIN: the packet is TCP and both SYN and FIN are set. */
118 uint64_t is_frag : 1; /**< set if the packet is a fragment */
119 uint64_t IP_exc : 1; /**< the receive interface hardware detected an IP error / exception
120 (only applies if !rcv_error && !not_IP) failure indicated in err_code below, decode:
121 - 1 = Not IP: the IP version field is neither 4 nor 6.
122 - 2 = IPv4 Header Checksum Error: the IPv4 header has a checksum violation.
123 - 3 = IP Malformed Header: the packet is not long enough to contain the IP header.
124 - 4 = IP Malformed: the packet is not long enough to contain the bytes indicated by the IP
125 header. Pad is allowed.
126 - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 Hop Count field are zero.
129 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
130 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
131 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be zero in this case) */
132 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error (must be zero in this case) */
133 /* lower err_code = first-level descriptor of the work */
134 /* zero for packet submitted by hardware that isn't on the slow path */
136 uint64_t err_code : 8; /**< type is cvmx_pip_err_t */
139 /**< use this to get at the 16 vlan bits */
142 uint64_t unused1 :16;
144 uint64_t unused2 :32;
147 /**< use this struct if the hardware could not determine that the packet is ip */
150 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
152 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
153 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
154 uint64_t unassigned : 1;
155 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
156 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
157 uint64_t pr : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
158 uint64_t unassigned2 :12;
159 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
160 uint64_t unassigned3 : 1;
161 uint64_t is_rarp : 1; /**< set if the hardware determined that the packet is rarp */
162 uint64_t is_arp : 1; /**< set if the hardware determined that the packet is arp */
163 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
164 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
165 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be one in this case) */
166 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error.
167 Failure indicated in err_code below, decode:
168 - 1 = partial error: a packet was partially received, but internal
169 buffering / bandwidth was not adequate to receive the entire packet.
170 - 2 = jabber error: the RGMII packet was too large and is truncated.
171 - 3 = overrun error: the RGMII packet is longer than allowed and had
173 - 4 = oversize error: the RGMII packet is longer than allowed.
174 - 5 = alignment error: the RGMII packet is not an integer number of bytes
175 and had an FCS error (100M and 10M only).
176 - 6 = fragment error: the RGMII packet is shorter than allowed and had an
178 - 7 = GMX FCS error: the RGMII packet had an FCS error.
179 - 8 = undersize error: the RGMII packet is shorter than allowed.
180 - 9 = extend error: the RGMII packet had an extend error.
181 - 10 = length mismatch error: the RGMII packet had a length that did not
182 match the length field in the L2 HDR.
183 - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII packet had one or more
184 data reception errors (RXERR) or the SPI4 packet had one or more DIP4
186 - 12 = RGMII skip error/SPI4 Abort Error: the RGMII packet was not large
187 enough to cover the skipped bytes or the SPI4 packet was terminated
189 - 13 = RGMII nibble error/SPI4 Port NXA Error: the RGMII packet had a
190 studder error (data not repeated - 10/100M only) or the SPI4 packet
192 - 16 = FCS error: a SPI4.2 packet had an FCS error.
193 - 17 = Skip error: a packet was not large enough to cover the skipped bytes.
194 - 18 = L2 header malformed: the packet is not long enough to contain the L2 */
197 /* lower err_code = first-level descriptor of the work */
198 /* zero for packet submitted by hardware that isn't on the slow path */
199 uint64_t err_code : 8; /* type is cvmx_pip_err_t (union, so can't use directly */
202 } cvmx_pip_wqe_word2;
205 * Work queue entry format
207 * must be 8-byte aligned
212 /*****************************************************************
214 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
218 * raw chksum result generated by the HW
222 * Field unused by hardware - available for software
226 * Next pointer used by hardware for list maintenance.
227 * May be written/read by HW before the work queue
228 * entry is scheduled to a PP
229 * (Only 36 bits used in Octeon 1)
231 uint64_t next_ptr : 40;
234 /*****************************************************************
236 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
240 * HW sets to the total number of bytes in the packet
244 * HW sets this to input physical port
249 * HW sets this to what it thought the priority of the input packet was
254 * the group that the work queue entry will be scheduled to
258 * the type of the tag (ORDERED, ATOMIC, NULL)
260 cvmx_pow_tag_type_t tag_type : 3;
262 * the synchronization/ordering tag
268 * HW WRITE: the following 64-bits are filled in by hardware when a packet arrives
269 * This indicates a variety of status and error conditions.
271 cvmx_pip_wqe_word2 word2;
274 * Pointer to the first segment of the packet.
276 cvmx_buf_ptr_t packet_ptr;
279 * HW WRITE: octeon will fill in a programmable amount from the
280 * packet, up to (at most, but perhaps less) the amount
281 * needed to fill the work queue entry to 128 bytes
282 * If the packet is recognized to be IP, the hardware starts (except that
283 * the IPv4 header is padded for appropriate alignment) writing here where
284 * the IP header starts.
285 * If the packet is not recognized to be IP, the hardware starts writing
286 * the beginning of the packet here.
288 uint8_t packet_data[96];
292 * If desired, SW can make the work Q entry any length. For the
293 * purposes of discussion here, Assume 128B always, as this is all that
294 * the hardware deals with.
298 } CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
304 #endif /* __CVMX_WQE_H__ */