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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_ZIP_TYPEDEFS_H__
53 #define __CVMX_ZIP_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_ZIP_CMD_BIST_RESULT CVMX_ZIP_CMD_BIST_RESULT_FUNC()
57 static inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
60 cvmx_warn("CVMX_ZIP_CMD_BIST_RESULT not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180038000080ull);
64 #define CVMX_ZIP_CMD_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180038000080ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_ZIP_CMD_BUF CVMX_ZIP_CMD_BUF_FUNC()
68 static inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void)
70 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
71 cvmx_warn("CVMX_ZIP_CMD_BUF not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001180038000008ull);
75 #define CVMX_ZIP_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180038000008ull))
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_ZIP_CMD_CTL CVMX_ZIP_CMD_CTL_FUNC()
79 static inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void)
81 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
82 cvmx_warn("CVMX_ZIP_CMD_CTL not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x0001180038000000ull);
86 #define CVMX_ZIP_CMD_CTL (CVMX_ADD_IO_SEG(0x0001180038000000ull))
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_ZIP_CONSTANTS CVMX_ZIP_CONSTANTS_FUNC()
90 static inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void)
92 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
93 cvmx_warn("CVMX_ZIP_CONSTANTS not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x00011800380000A0ull);
97 #define CVMX_ZIP_CONSTANTS (CVMX_ADD_IO_SEG(0x00011800380000A0ull))
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 #define CVMX_ZIP_DEBUG0 CVMX_ZIP_DEBUG0_FUNC()
101 static inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void)
103 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
104 cvmx_warn("CVMX_ZIP_DEBUG0 not supported on this chip\n");
105 return CVMX_ADD_IO_SEG(0x0001180038000098ull);
108 #define CVMX_ZIP_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180038000098ull))
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111 #define CVMX_ZIP_ERROR CVMX_ZIP_ERROR_FUNC()
112 static inline uint64_t CVMX_ZIP_ERROR_FUNC(void)
114 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
115 cvmx_warn("CVMX_ZIP_ERROR not supported on this chip\n");
116 return CVMX_ADD_IO_SEG(0x0001180038000088ull);
119 #define CVMX_ZIP_ERROR (CVMX_ADD_IO_SEG(0x0001180038000088ull))
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
122 #define CVMX_ZIP_INT_MASK CVMX_ZIP_INT_MASK_FUNC()
123 static inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void)
125 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
126 cvmx_warn("CVMX_ZIP_INT_MASK not supported on this chip\n");
127 return CVMX_ADD_IO_SEG(0x0001180038000090ull);
130 #define CVMX_ZIP_INT_MASK (CVMX_ADD_IO_SEG(0x0001180038000090ull))
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 #define CVMX_ZIP_THROTTLE CVMX_ZIP_THROTTLE_FUNC()
134 static inline uint64_t CVMX_ZIP_THROTTLE_FUNC(void)
136 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
137 cvmx_warn("CVMX_ZIP_THROTTLE not supported on this chip\n");
138 return CVMX_ADD_IO_SEG(0x0001180038000010ull);
141 #define CVMX_ZIP_THROTTLE (CVMX_ADD_IO_SEG(0x0001180038000010ull))
145 * cvmx_zip_cmd_bist_result
148 * Access to the internal BiST results
149 * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
151 union cvmx_zip_cmd_bist_result
154 struct cvmx_zip_cmd_bist_result_s
156 #if __BYTE_ORDER == __BIG_ENDIAN
157 uint64_t reserved_43_63 : 21;
158 uint64_t zip_core : 39; /**< BiST result of the ZIP_CORE memories */
159 uint64_t zip_ctl : 4; /**< BiST result of the ZIP_CTL memories */
161 uint64_t zip_ctl : 4;
162 uint64_t zip_core : 39;
163 uint64_t reserved_43_63 : 21;
166 struct cvmx_zip_cmd_bist_result_cn31xx
168 #if __BYTE_ORDER == __BIG_ENDIAN
169 uint64_t reserved_31_63 : 33;
170 uint64_t zip_core : 27; /**< BiST result of the ZIP_CORE memories */
171 uint64_t zip_ctl : 4; /**< BiST result of the ZIP_CTL memories */
173 uint64_t zip_ctl : 4;
174 uint64_t zip_core : 27;
175 uint64_t reserved_31_63 : 33;
178 struct cvmx_zip_cmd_bist_result_cn31xx cn38xx;
179 struct cvmx_zip_cmd_bist_result_cn31xx cn38xxp2;
180 struct cvmx_zip_cmd_bist_result_cn31xx cn56xx;
181 struct cvmx_zip_cmd_bist_result_cn31xx cn56xxp1;
182 struct cvmx_zip_cmd_bist_result_cn31xx cn58xx;
183 struct cvmx_zip_cmd_bist_result_cn31xx cn58xxp1;
184 struct cvmx_zip_cmd_bist_result_s cn63xx;
185 struct cvmx_zip_cmd_bist_result_s cn63xxp1;
187 typedef union cvmx_zip_cmd_bist_result cvmx_zip_cmd_bist_result_t;
193 * Sets the command buffer parameters
194 * The size of the command buffer segments is measured in uint64s. The pool specifies (1 of 8 free
195 * lists to be used when freeing command buffer segments. The PTR field is overwritten with the next
196 * pointer each time that the command buffer segment is exhausted.
197 * When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite
198 * this register to effectively reset the command buffer state machine. New commands will then be
199 * read from the newly specified command buffer pointer.
201 union cvmx_zip_cmd_buf
204 struct cvmx_zip_cmd_buf_s
206 #if __BYTE_ORDER == __BIG_ENDIAN
207 uint64_t reserved_58_63 : 6;
208 uint64_t dwb : 9; /**< Number of DontWriteBacks */
209 uint64_t pool : 3; /**< Free list used to free command buffer segments */
210 uint64_t size : 13; /**< Number of uint64s per command buffer segment */
211 uint64_t ptr : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */
217 uint64_t reserved_58_63 : 6;
220 struct cvmx_zip_cmd_buf_s cn31xx;
221 struct cvmx_zip_cmd_buf_s cn38xx;
222 struct cvmx_zip_cmd_buf_s cn38xxp2;
223 struct cvmx_zip_cmd_buf_s cn56xx;
224 struct cvmx_zip_cmd_buf_s cn56xxp1;
225 struct cvmx_zip_cmd_buf_s cn58xx;
226 struct cvmx_zip_cmd_buf_s cn58xxp1;
227 struct cvmx_zip_cmd_buf_s cn63xx;
228 struct cvmx_zip_cmd_buf_s cn63xxp1;
230 typedef union cvmx_zip_cmd_buf cvmx_zip_cmd_buf_t;
235 union cvmx_zip_cmd_ctl
238 struct cvmx_zip_cmd_ctl_s
240 #if __BYTE_ORDER == __BIG_ENDIAN
241 uint64_t reserved_2_63 : 62;
242 uint64_t forceclk : 1; /**< Force zip_ctl__clock_on_b == 1 when set */
243 uint64_t reset : 1; /**< Reset oneshot pulse for zip core */
246 uint64_t forceclk : 1;
247 uint64_t reserved_2_63 : 62;
250 struct cvmx_zip_cmd_ctl_s cn31xx;
251 struct cvmx_zip_cmd_ctl_s cn38xx;
252 struct cvmx_zip_cmd_ctl_s cn38xxp2;
253 struct cvmx_zip_cmd_ctl_s cn56xx;
254 struct cvmx_zip_cmd_ctl_s cn56xxp1;
255 struct cvmx_zip_cmd_ctl_s cn58xx;
256 struct cvmx_zip_cmd_ctl_s cn58xxp1;
257 struct cvmx_zip_cmd_ctl_s cn63xx;
258 struct cvmx_zip_cmd_ctl_s cn63xxp1;
260 typedef union cvmx_zip_cmd_ctl cvmx_zip_cmd_ctl_t;
266 * Note that this CSR is present only in chip revisions beginning with pass2.
269 union cvmx_zip_constants
272 struct cvmx_zip_constants_s
274 #if __BYTE_ORDER == __BIG_ENDIAN
275 uint64_t reserved_48_63 : 16;
276 uint64_t depth : 16; /**< Maximum search depth for compression */
277 uint64_t onfsize : 12; /**< Output near full threshhold in bytes */
278 uint64_t ctxsize : 12; /**< Context size in bytes */
279 uint64_t reserved_1_7 : 7;
280 uint64_t disabled : 1; /**< 1=zip unit isdisabled, 0=zip unit not disabled */
282 uint64_t disabled : 1;
283 uint64_t reserved_1_7 : 7;
284 uint64_t ctxsize : 12;
285 uint64_t onfsize : 12;
287 uint64_t reserved_48_63 : 16;
290 struct cvmx_zip_constants_s cn31xx;
291 struct cvmx_zip_constants_s cn38xx;
292 struct cvmx_zip_constants_s cn38xxp2;
293 struct cvmx_zip_constants_s cn56xx;
294 struct cvmx_zip_constants_s cn56xxp1;
295 struct cvmx_zip_constants_s cn58xx;
296 struct cvmx_zip_constants_s cn58xxp1;
297 struct cvmx_zip_constants_s cn63xx;
298 struct cvmx_zip_constants_s cn63xxp1;
300 typedef union cvmx_zip_constants cvmx_zip_constants_t;
306 * Note that this CSR is present only in chip revisions beginning with pass2.
309 union cvmx_zip_debug0
312 struct cvmx_zip_debug0_s
314 #if __BYTE_ORDER == __BIG_ENDIAN
315 uint64_t reserved_17_63 : 47;
316 uint64_t asserts : 17; /**< FIFO assertion checks */
318 uint64_t asserts : 17;
319 uint64_t reserved_17_63 : 47;
322 struct cvmx_zip_debug0_cn31xx
324 #if __BYTE_ORDER == __BIG_ENDIAN
325 uint64_t reserved_14_63 : 50;
326 uint64_t asserts : 14; /**< FIFO assertion checks */
328 uint64_t asserts : 14;
329 uint64_t reserved_14_63 : 50;
332 struct cvmx_zip_debug0_cn31xx cn38xx;
333 struct cvmx_zip_debug0_cn31xx cn38xxp2;
334 struct cvmx_zip_debug0_cn31xx cn56xx;
335 struct cvmx_zip_debug0_cn31xx cn56xxp1;
336 struct cvmx_zip_debug0_cn31xx cn58xx;
337 struct cvmx_zip_debug0_cn31xx cn58xxp1;
338 struct cvmx_zip_debug0_s cn63xx;
339 struct cvmx_zip_debug0_s cn63xxp1;
341 typedef union cvmx_zip_debug0 cvmx_zip_debug0_t;
347 * Note that this CSR is present only in chip revisions beginning with pass2.
353 struct cvmx_zip_error_s
355 #if __BYTE_ORDER == __BIG_ENDIAN
356 uint64_t reserved_1_63 : 63;
357 uint64_t doorbell : 1; /**< A doorbell count has overflowed */
359 uint64_t doorbell : 1;
360 uint64_t reserved_1_63 : 63;
363 struct cvmx_zip_error_s cn31xx;
364 struct cvmx_zip_error_s cn38xx;
365 struct cvmx_zip_error_s cn38xxp2;
366 struct cvmx_zip_error_s cn56xx;
367 struct cvmx_zip_error_s cn56xxp1;
368 struct cvmx_zip_error_s cn58xx;
369 struct cvmx_zip_error_s cn58xxp1;
370 struct cvmx_zip_error_s cn63xx;
371 struct cvmx_zip_error_s cn63xxp1;
373 typedef union cvmx_zip_error cvmx_zip_error_t;
379 * Note that this CSR is present only in chip revisions beginning with pass2.
380 * When a mask bit is set, the corresponding interrupt is enabled.
382 union cvmx_zip_int_mask
385 struct cvmx_zip_int_mask_s
387 #if __BYTE_ORDER == __BIG_ENDIAN
388 uint64_t reserved_1_63 : 63;
389 uint64_t doorbell : 1; /**< Bit mask corresponding to ZIP_ERROR[0] above */
391 uint64_t doorbell : 1;
392 uint64_t reserved_1_63 : 63;
395 struct cvmx_zip_int_mask_s cn31xx;
396 struct cvmx_zip_int_mask_s cn38xx;
397 struct cvmx_zip_int_mask_s cn38xxp2;
398 struct cvmx_zip_int_mask_s cn56xx;
399 struct cvmx_zip_int_mask_s cn56xxp1;
400 struct cvmx_zip_int_mask_s cn58xx;
401 struct cvmx_zip_int_mask_s cn58xxp1;
402 struct cvmx_zip_int_mask_s cn63xx;
403 struct cvmx_zip_int_mask_s cn63xxp1;
405 typedef union cvmx_zip_int_mask cvmx_zip_int_mask_t;
411 * The maximum number of inflight data fetch transactions. Values > 8 are illegal.
412 * Writing 0 to this register causes the ZIP module to temporarily suspend NCB
413 * accesses; it is not recommended for normal operation, but may be useful for
416 union cvmx_zip_throttle
419 struct cvmx_zip_throttle_s
421 #if __BYTE_ORDER == __BIG_ENDIAN
422 uint64_t reserved_4_63 : 60;
423 uint64_t max_infl : 4; /**< Maximum number of inflight data fetch transactions on NCB */
425 uint64_t max_infl : 4;
426 uint64_t reserved_4_63 : 60;
429 struct cvmx_zip_throttle_s cn63xx;
430 struct cvmx_zip_throttle_s cn63xxp1;
432 typedef union cvmx_zip_throttle cvmx_zip_throttle_t;