2 * Copyright (c) 2005 Poul-Henning Kamp
3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #if defined(__amd64__) || defined(__ia64__)
37 #include <sys/param.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
45 #include <sys/sysctl.h>
46 #include <sys/timeet.h>
47 #include <sys/timetc.h>
49 #include <contrib/dev/acpica/include/acpi.h>
50 #include <contrib/dev/acpica/include/accommon.h>
52 #include <dev/acpica/acpivar.h>
53 #include <dev/acpica/acpi_hpet.h>
59 #define HPET_VENDID_AMD 0x4353
60 #define HPET_VENDID_INTEL 0x8086
61 #define HPET_VENDID_NVIDIA 0x10de
63 ACPI_SERIAL_DECL(hpet, "ACPI HPET support");
65 static devclass_t hpet_devclass;
67 /* ACPI CA debugging */
68 #define _COMPONENT ACPI_TIMER
69 ACPI_MODULE_NAME("HPET")
79 uint32_t allowed_irqs;
80 struct resource *mem_res;
81 struct resource *intr_res;
86 struct timecounter tc;
89 struct hpet_softc *sc;
97 int pcpu_slaves[MAXCPU];
98 struct resource *intr_res;
109 static u_int hpet_get_timecount(struct timecounter *tc);
110 static void hpet_test(struct hpet_softc *sc);
112 static char *hpet_ids[] = { "PNP0103", NULL };
115 hpet_get_timecount(struct timecounter *tc)
117 struct hpet_softc *sc;
120 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));
124 hpet_enable(struct hpet_softc *sc)
128 val = bus_read_4(sc->mem_res, HPET_CONFIG);
129 if (sc->legacy_route)
130 val |= HPET_CNF_LEG_RT;
132 val &= ~HPET_CNF_LEG_RT;
133 val |= HPET_CNF_ENABLE;
134 bus_write_4(sc->mem_res, HPET_CONFIG, val);
138 hpet_disable(struct hpet_softc *sc)
142 val = bus_read_4(sc->mem_res, HPET_CONFIG);
143 val &= ~HPET_CNF_ENABLE;
144 bus_write_4(sc->mem_res, HPET_CONFIG, val);
148 hpet_start(struct eventtimer *et,
149 struct bintime *first, struct bintime *period)
151 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
152 struct hpet_timer *t;
153 struct hpet_softc *sc = mt->sc;
156 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
157 if (period != NULL) {
159 t->div = (sc->freq * (period->frac >> 32)) >> 32;
160 if (period->sec != 0)
161 t->div += sc->freq * period->sec;
167 fdiv = (sc->freq * (first->frac >> 32)) >> 32;
169 fdiv += sc->freq * first->sec;
173 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
174 t->caps |= HPET_TCNF_INT_ENB;
175 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
177 t->next = now + fdiv;
178 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
179 t->caps |= HPET_TCNF_TYPE;
180 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
181 t->caps | HPET_TCNF_VAL_SET);
182 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
184 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
187 t->caps &= ~HPET_TCNF_TYPE;
188 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
190 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
193 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
194 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) {
202 hpet_stop(struct eventtimer *et)
204 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
205 struct hpet_timer *t;
206 struct hpet_softc *sc = mt->sc;
208 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
210 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE);
211 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
216 hpet_intr_single(void *arg)
218 struct hpet_timer *t = (struct hpet_timer *)arg;
219 struct hpet_timer *mt;
220 struct hpet_softc *sc = t->sc;
224 return (FILTER_STRAY);
225 /* Check that per-CPU timer interrupt reached right CPU. */
226 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) {
227 if ((++t->pcpu_misrouted) % 32 == 0) {
228 printf("HPET interrupt routed to the wrong CPU"
229 " (timer %d CPU %d -> %d)!\n",
230 t->num, t->pcpu_cpu, curcpu);
234 * Reload timer, hoping that next time may be more lucky
235 * (system will manage proper interrupt binding).
237 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) ||
239 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +
241 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
244 return (FILTER_HANDLED);
247 (t->caps & HPET_TCAP_PER_INT) == 0) {
249 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
250 if ((int32_t)((now + t->div / 2) - t->next) > 0)
251 t->next = now + t->div / 2;
252 bus_write_4(sc->mem_res,
253 HPET_TIMER_COMPARATOR(t->num), t->next);
254 } else if (t->mode == 2)
256 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master];
257 if (mt->et.et_active)
258 mt->et.et_event_cb(&mt->et, mt->et.et_arg);
259 return (FILTER_HANDLED);
265 struct hpet_softc *sc = (struct hpet_softc *)arg;
269 val = bus_read_4(sc->mem_res, HPET_ISR);
271 bus_write_4(sc->mem_res, HPET_ISR, val);
273 for (i = 0; i < sc->num_timers; i++) {
274 if ((val & (1 << i)) == 0)
276 hpet_intr_single(&sc->t[i]);
278 return (FILTER_HANDLED);
280 return (FILTER_STRAY);
284 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context,
288 uint32_t id = (uint32_t)(uintptr_t)context;
291 for (ids = hpet_ids; *ids != NULL; ids++) {
292 if (acpi_MatchHid(handle, *ids))
297 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) ||
299 *((int *)status) = 1;
304 * Find an existing IRQ resource that matches the requested IRQ range
305 * and return its RID. If one is not found, use a new RID.
308 hpet_find_irq_rid(device_t dev, u_long start, u_long end)
313 for (rid = 0;; rid++) {
314 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL);
315 if (error != 0 || (start <= irq && irq <= end))
320 /* Discover the HPET via the ACPI table of the same name. */
322 hpet_identify(driver_t *driver, device_t parent)
324 ACPI_TABLE_HPET *hpet;
329 /* Only one HPET device can be added. */
330 if (devclass_get_device(hpet_devclass, 0))
333 /* Search for HPET table. */
334 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet);
335 if (ACPI_FAILURE(status))
337 /* Search for HPET device with same ID. */
339 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
340 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found);
341 /* If found - let it be probed in normal way. */
344 /* If not - create it from table info. */
345 child = BUS_ADD_CHILD(parent, ACPI_DEV_BASE_ORDER, "hpet", 0);
347 printf("%s: can't add child\n", __func__);
350 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address,
356 hpet_probe(device_t dev)
358 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
360 if (acpi_disabled("hpet"))
362 if (acpi_get_handle(dev) != NULL &&
363 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL)
366 device_set_desc(dev, "High Precision Event Timer");
371 hpet_attach(device_t dev)
373 struct hpet_softc *sc;
374 struct hpet_timer *t;
375 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu;
377 static int maxhpetet = 0;
378 uint32_t val, val2, cvectors, dvectors;
379 uint16_t vendor, rev;
381 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
383 sc = device_get_softc(dev);
385 sc->handle = acpi_get_handle(dev);
388 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
390 if (sc->mem_res == NULL)
393 /* Validate that we can access the whole region. */
394 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) {
395 device_printf(dev, "memory region width %ld too small\n",
396 rman_get_size(sc->mem_res));
397 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
401 /* Be sure timer is enabled. */
404 /* Read basic statistics about the timer. */
405 val = bus_read_4(sc->mem_res, HPET_PERIOD);
407 device_printf(dev, "invalid period\n");
409 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
413 sc->freq = (1000000000000000LL + val / 2) / val;
414 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);
415 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16;
416 rev = sc->caps & HPET_CAP_REV_ID;
417 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8);
419 * ATI/AMD violates IA-PC HPET (High Precision Event Timers)
420 * Specification and provides an off by one number
421 * of timers/comparators.
422 * Additionally, they use unregistered value in VENDOR_ID field.
424 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0)
426 sc->num_timers = num_timers;
429 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n",
430 vendor, rev, sc->freq,
431 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "",
433 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : "");
435 for (i = 0; i < num_timers; i++) {
443 t->pcpu_misrouted = 0;
445 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));
446 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);
449 " t%d: irqs 0x%08x (%d)%s%s%s\n", i,
450 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9,
451 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "",
452 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "",
453 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : "");
456 if (testenv("debug.acpi.hpet_test"))
459 * Don't attach if the timer never increments. Since the spec
460 * requires it to be at least 10 MHz, it has to change in 1 us.
462 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
464 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
466 device_printf(dev, "HPET never increments, disabling\n");
468 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
471 /* Announce first HPET as timecounter. */
472 if (device_get_unit(dev) == 0) {
473 sc->tc.tc_get_timecount = hpet_get_timecount,
474 sc->tc.tc_counter_mask = ~0u,
475 sc->tc.tc_name = "HPET",
476 sc->tc.tc_quality = 950,
477 sc->tc.tc_frequency = sc->freq;
481 /* If not disabled - setup and announce event timers. */
482 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
483 "clock", &i) == 0 && i == 0)
486 /* Check whether we can and want legacy routing. */
487 sc->legacy_route = 0;
488 resource_int_value(device_get_name(dev), device_get_unit(dev),
489 "legacy_route", &sc->legacy_route);
490 if ((sc->caps & HPET_CAP_LEG_RT) == 0)
491 sc->legacy_route = 0;
492 if (sc->legacy_route) {
493 sc->t[0].vectors = 0;
494 sc->t[1].vectors = 0;
497 /* Check what IRQs we want use. */
498 /* By default allow any PCI IRQs. */
499 sc->allowed_irqs = 0xffff0000;
501 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16
502 * Lower are also not always working for different reasons.
503 * SB800 fixed it, but seems do not implements level triggering
504 * properly, that makes it very unreliable - it freezes after any
505 * interrupt loss. Avoid legacy IRQs for AMD.
507 if (vendor == HPET_VENDID_AMD)
508 sc->allowed_irqs = 0x00000000;
510 * NVidia MCP5x chipsets have number of unexplained interrupt
511 * problems. For some reason, using HPET interrupts breaks HDA sound.
513 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01)
514 sc->allowed_irqs = 0x00000000;
516 * Neither QEMU nor VirtualBox report supported IRQs correctly.
517 * The only way to use HPET there is to specify IRQs manually
518 * and/or use legacy_route. Legacy_route mode works on both.
521 sc->allowed_irqs = 0x00000000;
522 /* Let user override. */
523 resource_int_value(device_get_name(dev), device_get_unit(dev),
524 "allowed_irqs", &sc->allowed_irqs);
526 /* Get how much per-CPU timers we should try to provide. */
528 resource_int_value(device_get_name(dev), device_get_unit(dev),
529 "per_cpu", &sc->per_cpu);
533 /* Find IRQ vectors for all timers. */
534 cvectors = sc->allowed_irqs & 0xffff0000;
535 dvectors = sc->allowed_irqs & 0x0000ffff;
536 if (sc->legacy_route)
537 dvectors &= 0x0000fefe;
538 for (i = 0; i < num_timers; i++) {
540 if (sc->legacy_route && i < 2)
541 t->irq = (i == 0) ? 0 : 8;
543 else if (t->caps & HPET_TCAP_FSB_INT_DEL) {
544 if ((j = PCIB_ALLOC_MSIX(
545 device_get_parent(device_get_parent(dev)), dev,
548 "Can't allocate interrupt for t%d.\n", j);
552 else if (dvectors & t->vectors) {
553 t->irq = ffs(dvectors & t->vectors) - 1;
554 dvectors &= ~(1 << t->irq);
557 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq);
558 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
559 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE);
560 if (t->intr_res == NULL) {
563 "Can't map interrupt for t%d.\n", i);
564 } else if (bus_setup_intr(dev, t->intr_res,
565 INTR_TYPE_CLK, hpet_intr_single, NULL, t,
566 &t->intr_handle) != 0) {
569 "Can't setup interrupt for t%d.\n", i);
571 bus_describe_intr(dev, t->intr_res,
572 t->intr_handle, "t%d", i);
576 if (t->irq < 0 && (cvectors & t->vectors) != 0) {
577 cvectors &= t->vectors;
578 sc->useirq |= (1 << i);
581 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0)
582 sc->legacy_route = 0;
583 if (sc->legacy_route)
585 /* Group timers for per-CPU operation. */
586 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu);
587 num_percpu_t = num_percpu_et * mp_ncpus;
589 cur_cpu = CPU_FIRST();
590 for (i = 0; i < num_timers; i++) {
592 if (t->irq >= 0 && num_percpu_t > 0) {
593 if (cur_cpu == CPU_FIRST())
595 t->pcpu_cpu = cur_cpu;
596 t->pcpu_master = pcpu_master;
598 pcpu_slaves[cur_cpu] = i;
599 bus_bind_intr(dev, t->intr_res, cur_cpu);
600 cur_cpu = CPU_NEXT(cur_cpu);
602 } else if (t->irq >= 0)
603 bus_bind_intr(dev, t->intr_res, CPU_FIRST());
605 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);
607 /* If at least one timer needs legacy IRQ - set it up. */
609 j = i = fls(cvectors) - 1;
610 while (j > 0 && (cvectors & (1 << (j - 1))) != 0)
612 sc->intr_rid = hpet_find_irq_rid(dev, j, i);
613 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
614 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE);
615 if (sc->intr_res == NULL)
616 device_printf(dev, "Can't map interrupt.\n");
617 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
618 hpet_intr, NULL, sc, &sc->intr_handle) != 0) {
619 device_printf(dev, "Can't setup interrupt.\n");
621 sc->irq = rman_get_start(sc->intr_res);
622 /* Bind IRQ to BSP to avoid live migration. */
623 bus_bind_intr(dev, sc->intr_res, CPU_FIRST());
626 /* Program and announce event timers. */
627 for (i = 0; i < num_timers; i++) {
629 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE);
630 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB);
631 t->caps &= ~(HPET_TCNF_INT_TYPE);
632 t->caps |= HPET_TCNF_32MODE;
633 if (t->irq >= 0 && sc->legacy_route && i < 2) {
634 /* Legacy route doesn't need more configuration. */
637 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) {
642 device_get_parent(device_get_parent(dev)), dev,
643 t->irq, &addr, &data) == 0) {
644 bus_write_4(sc->mem_res,
645 HPET_TIMER_FSB_ADDR(i), addr);
646 bus_write_4(sc->mem_res,
647 HPET_TIMER_FSB_VAL(i), data);
648 t->caps |= HPET_TCNF_FSB_EN;
654 t->caps |= (t->irq << 9);
655 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq)))
656 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE;
657 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);
658 /* Skip event timers without set up IRQ. */
660 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0))
662 /* Announce the reset. */
664 t->et.et_name = "HPET";
666 sprintf(t->name, "HPET%d", maxhpetet);
667 t->et.et_name = t->name;
669 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
670 t->et.et_quality = 450;
671 if (t->pcpu_master >= 0) {
672 t->et.et_flags |= ET_FLAGS_PERCPU;
673 t->et.et_quality += 100;
675 if ((t->caps & HPET_TCAP_PER_INT) == 0)
676 t->et.et_quality -= 10;
677 t->et.et_frequency = sc->freq;
678 t->et.et_min_period.sec = 0;
679 t->et.et_min_period.frac =
680 (((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq) << 32;
681 t->et.et_max_period.sec = 0xfffffffeLLU / sc->freq;
682 t->et.et_max_period.frac =
683 ((0xfffffffeLLU << 32) / sc->freq) << 32;
684 t->et.et_start = hpet_start;
685 t->et.et_stop = hpet_stop;
686 t->et.et_priv = &sc->t[i];
687 if (t->pcpu_master < 0 || t->pcpu_master == i) {
696 hpet_detach(device_t dev)
698 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
700 /* XXX Without a tc_remove() function, we can't detach. */
705 hpet_suspend(device_t dev)
707 // struct hpet_softc *sc;
710 * Disable the timer during suspend. The timer will not lose
711 * its state in S1 or S2, but we are required to disable
714 // sc = device_get_softc(dev);
721 hpet_resume(device_t dev)
723 struct hpet_softc *sc;
724 struct hpet_timer *t;
727 /* Re-enable the timer after a resume to keep the clock advancing. */
728 sc = device_get_softc(dev);
730 /* Restart event timers that were running on suspend. */
731 for (i = 0; i < sc->num_timers; i++) {
734 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) {
739 device_get_parent(device_get_parent(dev)), dev,
740 t->irq, &addr, &data) == 0) {
741 bus_write_4(sc->mem_res,
742 HPET_TIMER_FSB_ADDR(i), addr);
743 bus_write_4(sc->mem_res,
744 HPET_TIMER_FSB_VAL(i), data);
750 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
751 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
752 t->caps |= HPET_TCNF_TYPE;
754 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
755 t->caps | HPET_TCNF_VAL_SET);
756 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
758 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));
759 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
762 t->next += sc->freq / 1024;
763 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
766 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
767 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
772 /* Print some basic latency/rate information to assist in debugging. */
774 hpet_test(struct hpet_softc *sc)
778 struct bintime b0, b1, b2;
784 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
785 for (i = 1; i < 1000; i++)
786 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
788 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
790 bintime_sub(&b2, &b1);
791 bintime_sub(&b1, &b0);
792 bintime_sub(&b2, &b1);
793 bintime2timespec(&b2, &ts);
795 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n",
796 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1);
798 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000);
803 hpet_remap_intr(device_t dev, device_t child, u_int irq)
805 struct hpet_softc *sc = device_get_softc(dev);
806 struct hpet_timer *t;
811 for (i = 0; i < sc->num_timers; i++) {
815 error = PCIB_MAP_MSI(
816 device_get_parent(device_get_parent(dev)), dev,
820 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */
821 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);
822 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);
830 static device_method_t hpet_methods[] = {
831 /* Device interface */
832 DEVMETHOD(device_identify, hpet_identify),
833 DEVMETHOD(device_probe, hpet_probe),
834 DEVMETHOD(device_attach, hpet_attach),
835 DEVMETHOD(device_detach, hpet_detach),
836 DEVMETHOD(device_suspend, hpet_suspend),
837 DEVMETHOD(device_resume, hpet_resume),
840 DEVMETHOD(bus_remap_intr, hpet_remap_intr),
846 static driver_t hpet_driver = {
849 sizeof(struct hpet_softc),
852 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0);
853 MODULE_DEPEND(hpet, acpi, 1, 1, 1);