2 * Copyright (c) 2005 Poul-Henning Kamp
3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #if defined(__amd64__) || defined(__ia64__)
37 #include <sys/param.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
45 #include <sys/sysctl.h>
46 #include <sys/timeet.h>
47 #include <sys/timetc.h>
49 #include <contrib/dev/acpica/include/acpi.h>
50 #include <contrib/dev/acpica/include/accommon.h>
52 #include <dev/acpica/acpivar.h>
53 #include <dev/acpica/acpi_hpet.h>
59 #define HPET_VENDID_AMD 0x4353
60 #define HPET_VENDID_AMD2 0x1022
61 #define HPET_VENDID_INTEL 0x8086
62 #define HPET_VENDID_NVIDIA 0x10de
63 #define HPET_VENDID_SW 0x1166
65 ACPI_SERIAL_DECL(hpet, "ACPI HPET support");
67 static devclass_t hpet_devclass;
69 /* ACPI CA debugging */
70 #define _COMPONENT ACPI_TIMER
71 ACPI_MODULE_NAME("HPET")
81 uint32_t allowed_irqs;
82 struct resource *mem_res;
83 struct resource *intr_res;
88 struct timecounter tc;
91 struct hpet_softc *sc;
99 int pcpu_slaves[MAXCPU];
100 struct resource *intr_res;
111 static u_int hpet_get_timecount(struct timecounter *tc);
112 static void hpet_test(struct hpet_softc *sc);
114 static char *hpet_ids[] = { "PNP0103", NULL };
117 hpet_get_timecount(struct timecounter *tc)
119 struct hpet_softc *sc;
122 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));
126 hpet_enable(struct hpet_softc *sc)
130 val = bus_read_4(sc->mem_res, HPET_CONFIG);
131 if (sc->legacy_route)
132 val |= HPET_CNF_LEG_RT;
134 val &= ~HPET_CNF_LEG_RT;
135 val |= HPET_CNF_ENABLE;
136 bus_write_4(sc->mem_res, HPET_CONFIG, val);
140 hpet_disable(struct hpet_softc *sc)
144 val = bus_read_4(sc->mem_res, HPET_CONFIG);
145 val &= ~HPET_CNF_ENABLE;
146 bus_write_4(sc->mem_res, HPET_CONFIG, val);
150 hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
152 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
153 struct hpet_timer *t;
154 struct hpet_softc *sc = mt->sc;
157 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
160 t->div = (sc->freq * period) >> 32;
166 fdiv = (sc->freq * first) >> 32;
170 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
171 t->caps |= HPET_TCNF_INT_ENB;
172 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
174 t->next = now + fdiv;
175 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
176 t->caps |= HPET_TCNF_TYPE;
177 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
178 t->caps | HPET_TCNF_VAL_SET);
179 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
181 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
184 t->caps &= ~HPET_TCNF_TYPE;
185 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
187 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
190 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
191 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) {
199 hpet_stop(struct eventtimer *et)
201 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
202 struct hpet_timer *t;
203 struct hpet_softc *sc = mt->sc;
205 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
207 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE);
208 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
213 hpet_intr_single(void *arg)
215 struct hpet_timer *t = (struct hpet_timer *)arg;
216 struct hpet_timer *mt;
217 struct hpet_softc *sc = t->sc;
221 return (FILTER_STRAY);
222 /* Check that per-CPU timer interrupt reached right CPU. */
223 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) {
224 if ((++t->pcpu_misrouted) % 32 == 0) {
225 printf("HPET interrupt routed to the wrong CPU"
226 " (timer %d CPU %d -> %d)!\n",
227 t->num, t->pcpu_cpu, curcpu);
231 * Reload timer, hoping that next time may be more lucky
232 * (system will manage proper interrupt binding).
234 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) ||
236 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +
238 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
241 return (FILTER_HANDLED);
244 (t->caps & HPET_TCAP_PER_INT) == 0) {
246 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
247 if ((int32_t)((now + t->div / 2) - t->next) > 0)
248 t->next = now + t->div / 2;
249 bus_write_4(sc->mem_res,
250 HPET_TIMER_COMPARATOR(t->num), t->next);
251 } else if (t->mode == 2)
253 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master];
254 if (mt->et.et_active)
255 mt->et.et_event_cb(&mt->et, mt->et.et_arg);
256 return (FILTER_HANDLED);
262 struct hpet_softc *sc = (struct hpet_softc *)arg;
266 val = bus_read_4(sc->mem_res, HPET_ISR);
268 bus_write_4(sc->mem_res, HPET_ISR, val);
270 for (i = 0; i < sc->num_timers; i++) {
271 if ((val & (1 << i)) == 0)
273 hpet_intr_single(&sc->t[i]);
275 return (FILTER_HANDLED);
277 return (FILTER_STRAY);
281 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context,
285 uint32_t id = (uint32_t)(uintptr_t)context;
288 for (ids = hpet_ids; *ids != NULL; ids++) {
289 if (acpi_MatchHid(handle, *ids))
294 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) ||
296 *((int *)status) = 1;
301 * Find an existing IRQ resource that matches the requested IRQ range
302 * and return its RID. If one is not found, use a new RID.
305 hpet_find_irq_rid(device_t dev, u_long start, u_long end)
310 for (rid = 0;; rid++) {
311 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL);
312 if (error != 0 || (start <= irq && irq <= end))
317 /* Discover the HPET via the ACPI table of the same name. */
319 hpet_identify(driver_t *driver, device_t parent)
321 ACPI_TABLE_HPET *hpet;
326 /* Only one HPET device can be added. */
327 if (devclass_get_device(hpet_devclass, 0))
330 /* Search for HPET table. */
331 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet);
332 if (ACPI_FAILURE(status))
334 /* Search for HPET device with same ID. */
336 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
337 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found);
338 /* If found - let it be probed in normal way. */
341 /* If not - create it from table info. */
342 child = BUS_ADD_CHILD(parent, 2, "hpet", 0);
344 printf("%s: can't add child\n", __func__);
347 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address,
353 hpet_probe(device_t dev)
355 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
357 if (acpi_disabled("hpet"))
359 if (acpi_get_handle(dev) != NULL &&
360 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL)
363 device_set_desc(dev, "High Precision Event Timer");
368 hpet_attach(device_t dev)
370 struct hpet_softc *sc;
371 struct hpet_timer *t;
372 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu;
374 static int maxhpetet = 0;
375 uint32_t val, val2, cvectors, dvectors;
376 uint16_t vendor, rev;
378 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
380 sc = device_get_softc(dev);
382 sc->handle = acpi_get_handle(dev);
385 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
387 if (sc->mem_res == NULL)
390 /* Validate that we can access the whole region. */
391 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) {
392 device_printf(dev, "memory region width %ld too small\n",
393 rman_get_size(sc->mem_res));
394 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
398 /* Be sure timer is enabled. */
401 /* Read basic statistics about the timer. */
402 val = bus_read_4(sc->mem_res, HPET_PERIOD);
404 device_printf(dev, "invalid period\n");
406 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
410 sc->freq = (1000000000000000LL + val / 2) / val;
411 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);
412 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16;
413 rev = sc->caps & HPET_CAP_REV_ID;
414 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8);
416 * ATI/AMD violates IA-PC HPET (High Precision Event Timers)
417 * Specification and provides an off by one number
418 * of timers/comparators.
419 * Additionally, they use unregistered value in VENDOR_ID field.
421 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0)
423 sc->num_timers = num_timers;
426 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n",
427 vendor, rev, sc->freq,
428 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "",
430 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : "");
432 for (i = 0; i < num_timers; i++) {
440 t->pcpu_misrouted = 0;
442 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));
443 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);
446 " t%d: irqs 0x%08x (%d)%s%s%s\n", i,
447 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9,
448 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "",
449 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "",
450 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : "");
453 if (testenv("debug.acpi.hpet_test"))
456 * Don't attach if the timer never increments. Since the spec
457 * requires it to be at least 10 MHz, it has to change in 1 us.
459 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
461 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
463 device_printf(dev, "HPET never increments, disabling\n");
465 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
468 /* Announce first HPET as timecounter. */
469 if (device_get_unit(dev) == 0) {
470 sc->tc.tc_get_timecount = hpet_get_timecount,
471 sc->tc.tc_counter_mask = ~0u,
472 sc->tc.tc_name = "HPET",
473 sc->tc.tc_quality = 950,
474 sc->tc.tc_frequency = sc->freq;
478 /* If not disabled - setup and announce event timers. */
479 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
480 "clock", &i) == 0 && i == 0)
483 /* Check whether we can and want legacy routing. */
484 sc->legacy_route = 0;
485 resource_int_value(device_get_name(dev), device_get_unit(dev),
486 "legacy_route", &sc->legacy_route);
487 if ((sc->caps & HPET_CAP_LEG_RT) == 0)
488 sc->legacy_route = 0;
489 if (sc->legacy_route) {
490 sc->t[0].vectors = 0;
491 sc->t[1].vectors = 0;
494 /* Check what IRQs we want use. */
495 /* By default allow any PCI IRQs. */
496 sc->allowed_irqs = 0xffff0000;
498 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16
499 * Lower are also not always working for different reasons.
500 * SB800 fixed it, but seems do not implements level triggering
501 * properly, that makes it very unreliable - it freezes after any
502 * interrupt loss. Avoid legacy IRQs for AMD.
504 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2)
505 sc->allowed_irqs = 0x00000000;
507 * NVidia MCP5x chipsets have number of unexplained interrupt
508 * problems. For some reason, using HPET interrupts breaks HDA sound.
510 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01)
511 sc->allowed_irqs = 0x00000000;
513 * ServerWorks HT1000 reported to have problems with IRQs >= 16.
514 * Lower IRQs are working, but allowed mask is not set correctly.
515 * Legacy_route mode works fine.
517 if (vendor == HPET_VENDID_SW && rev <= 0x01)
518 sc->allowed_irqs = 0x00000000;
520 * Neither QEMU nor VirtualBox report supported IRQs correctly.
521 * The only way to use HPET there is to specify IRQs manually
522 * and/or use legacy_route. Legacy_route mode works on both.
525 sc->allowed_irqs = 0x00000000;
526 /* Let user override. */
527 resource_int_value(device_get_name(dev), device_get_unit(dev),
528 "allowed_irqs", &sc->allowed_irqs);
530 /* Get how much per-CPU timers we should try to provide. */
532 resource_int_value(device_get_name(dev), device_get_unit(dev),
533 "per_cpu", &sc->per_cpu);
537 /* Find IRQ vectors for all timers. */
538 cvectors = sc->allowed_irqs & 0xffff0000;
539 dvectors = sc->allowed_irqs & 0x0000ffff;
540 if (sc->legacy_route)
541 dvectors &= 0x0000fefe;
542 for (i = 0; i < num_timers; i++) {
544 if (sc->legacy_route && i < 2)
545 t->irq = (i == 0) ? 0 : 8;
547 else if (t->caps & HPET_TCAP_FSB_INT_DEL) {
548 if ((j = PCIB_ALLOC_MSIX(
549 device_get_parent(device_get_parent(dev)), dev,
552 "Can't allocate interrupt for t%d.\n", j);
556 else if (dvectors & t->vectors) {
557 t->irq = ffs(dvectors & t->vectors) - 1;
558 dvectors &= ~(1 << t->irq);
561 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq);
562 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
563 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE);
564 if (t->intr_res == NULL) {
567 "Can't map interrupt for t%d.\n", i);
568 } else if (bus_setup_intr(dev, t->intr_res,
569 INTR_TYPE_CLK, hpet_intr_single, NULL, t,
570 &t->intr_handle) != 0) {
573 "Can't setup interrupt for t%d.\n", i);
575 bus_describe_intr(dev, t->intr_res,
576 t->intr_handle, "t%d", i);
580 if (t->irq < 0 && (cvectors & t->vectors) != 0) {
581 cvectors &= t->vectors;
582 sc->useirq |= (1 << i);
585 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0)
586 sc->legacy_route = 0;
587 if (sc->legacy_route)
589 /* Group timers for per-CPU operation. */
590 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu);
591 num_percpu_t = num_percpu_et * mp_ncpus;
593 cur_cpu = CPU_FIRST();
594 for (i = 0; i < num_timers; i++) {
596 if (t->irq >= 0 && num_percpu_t > 0) {
597 if (cur_cpu == CPU_FIRST())
599 t->pcpu_cpu = cur_cpu;
600 t->pcpu_master = pcpu_master;
602 pcpu_slaves[cur_cpu] = i;
603 bus_bind_intr(dev, t->intr_res, cur_cpu);
604 cur_cpu = CPU_NEXT(cur_cpu);
606 } else if (t->irq >= 0)
607 bus_bind_intr(dev, t->intr_res, CPU_FIRST());
609 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);
611 /* If at least one timer needs legacy IRQ - set it up. */
613 j = i = fls(cvectors) - 1;
614 while (j > 0 && (cvectors & (1 << (j - 1))) != 0)
616 sc->intr_rid = hpet_find_irq_rid(dev, j, i);
617 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
618 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE);
619 if (sc->intr_res == NULL)
620 device_printf(dev, "Can't map interrupt.\n");
621 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
622 hpet_intr, NULL, sc, &sc->intr_handle) != 0) {
623 device_printf(dev, "Can't setup interrupt.\n");
625 sc->irq = rman_get_start(sc->intr_res);
626 /* Bind IRQ to BSP to avoid live migration. */
627 bus_bind_intr(dev, sc->intr_res, CPU_FIRST());
630 /* Program and announce event timers. */
631 for (i = 0; i < num_timers; i++) {
633 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE);
634 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB);
635 t->caps &= ~(HPET_TCNF_INT_TYPE);
636 t->caps |= HPET_TCNF_32MODE;
637 if (t->irq >= 0 && sc->legacy_route && i < 2) {
638 /* Legacy route doesn't need more configuration. */
641 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) {
646 device_get_parent(device_get_parent(dev)), dev,
647 t->irq, &addr, &data) == 0) {
648 bus_write_4(sc->mem_res,
649 HPET_TIMER_FSB_ADDR(i), addr);
650 bus_write_4(sc->mem_res,
651 HPET_TIMER_FSB_VAL(i), data);
652 t->caps |= HPET_TCNF_FSB_EN;
658 t->caps |= (t->irq << 9);
659 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq)))
660 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE;
661 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);
662 /* Skip event timers without set up IRQ. */
664 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0))
666 /* Announce the reset. */
668 t->et.et_name = "HPET";
670 sprintf(t->name, "HPET%d", maxhpetet);
671 t->et.et_name = t->name;
673 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
674 t->et.et_quality = 450;
675 if (t->pcpu_master >= 0) {
676 t->et.et_flags |= ET_FLAGS_PERCPU;
677 t->et.et_quality += 100;
678 } else if (mp_ncpus >= 8)
679 t->et.et_quality -= 100;
680 if ((t->caps & HPET_TCAP_PER_INT) == 0)
681 t->et.et_quality -= 10;
682 t->et.et_frequency = sc->freq;
683 t->et.et_min_period =
684 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq;
685 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq;
686 t->et.et_start = hpet_start;
687 t->et.et_stop = hpet_stop;
688 t->et.et_priv = &sc->t[i];
689 if (t->pcpu_master < 0 || t->pcpu_master == i) {
698 hpet_detach(device_t dev)
700 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
702 /* XXX Without a tc_remove() function, we can't detach. */
707 hpet_suspend(device_t dev)
709 // struct hpet_softc *sc;
712 * Disable the timer during suspend. The timer will not lose
713 * its state in S1 or S2, but we are required to disable
716 // sc = device_get_softc(dev);
723 hpet_resume(device_t dev)
725 struct hpet_softc *sc;
726 struct hpet_timer *t;
729 /* Re-enable the timer after a resume to keep the clock advancing. */
730 sc = device_get_softc(dev);
732 /* Restart event timers that were running on suspend. */
733 for (i = 0; i < sc->num_timers; i++) {
736 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) {
741 device_get_parent(device_get_parent(dev)), dev,
742 t->irq, &addr, &data) == 0) {
743 bus_write_4(sc->mem_res,
744 HPET_TIMER_FSB_ADDR(i), addr);
745 bus_write_4(sc->mem_res,
746 HPET_TIMER_FSB_VAL(i), data);
752 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
753 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
754 t->caps |= HPET_TCNF_TYPE;
756 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
757 t->caps | HPET_TCNF_VAL_SET);
758 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
760 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));
761 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
764 t->next += sc->freq / 1024;
765 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
768 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
769 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
774 /* Print some basic latency/rate information to assist in debugging. */
776 hpet_test(struct hpet_softc *sc)
780 struct bintime b0, b1, b2;
786 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
787 for (i = 1; i < 1000; i++)
788 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
790 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
792 bintime_sub(&b2, &b1);
793 bintime_sub(&b1, &b0);
794 bintime_sub(&b2, &b1);
795 bintime2timespec(&b2, &ts);
797 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n",
798 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1);
800 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000);
805 hpet_remap_intr(device_t dev, device_t child, u_int irq)
807 struct hpet_softc *sc = device_get_softc(dev);
808 struct hpet_timer *t;
813 for (i = 0; i < sc->num_timers; i++) {
817 error = PCIB_MAP_MSI(
818 device_get_parent(device_get_parent(dev)), dev,
822 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */
823 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);
824 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);
832 static device_method_t hpet_methods[] = {
833 /* Device interface */
834 DEVMETHOD(device_identify, hpet_identify),
835 DEVMETHOD(device_probe, hpet_probe),
836 DEVMETHOD(device_attach, hpet_attach),
837 DEVMETHOD(device_detach, hpet_detach),
838 DEVMETHOD(device_suspend, hpet_suspend),
839 DEVMETHOD(device_resume, hpet_resume),
842 DEVMETHOD(bus_remap_intr, hpet_remap_intr),
848 static driver_t hpet_driver = {
851 sizeof(struct hpet_softc),
854 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0);
855 MODULE_DEPEND(hpet, acpi, 1, 1, 1);