2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
39 #include <sys/mutex.h>
41 #include <sys/taskqueue.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
52 #include <cam/cam_ccb.h>
53 #include <cam/cam_sim.h>
54 #include <cam/cam_xpt_sim.h>
55 #include <cam/cam_debug.h>
57 /* local prototypes */
58 static int ahci_setup_interrupt(device_t dev);
59 static void ahci_intr(void *data);
60 static void ahci_intr_one(void *data);
61 static int ahci_suspend(device_t dev);
62 static int ahci_resume(device_t dev);
63 static int ahci_ch_suspend(device_t dev);
64 static int ahci_ch_resume(device_t dev);
65 static void ahci_ch_pm(void *arg);
66 static void ahci_ch_intr_locked(void *data);
67 static void ahci_ch_intr(void *data);
68 static int ahci_ctlr_reset(device_t dev);
69 static int ahci_ctlr_setup(device_t dev);
70 static void ahci_begin_transaction(device_t dev, union ccb *ccb);
71 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
72 static void ahci_execute_transaction(struct ahci_slot *slot);
73 static void ahci_timeout(struct ahci_slot *slot);
74 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
75 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
76 static void ahci_dmainit(device_t dev);
77 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
78 static void ahci_dmafini(device_t dev);
79 static void ahci_slotsalloc(device_t dev);
80 static void ahci_slotsfree(device_t dev);
81 static void ahci_reset(device_t dev);
82 static void ahci_start(device_t dev, int fbs);
83 static void ahci_stop(device_t dev);
84 static void ahci_clo(device_t dev);
85 static void ahci_start_fr(device_t dev);
86 static void ahci_stop_fr(device_t dev);
88 static int ahci_sata_connect(struct ahci_channel *ch);
89 static int ahci_sata_phy_reset(device_t dev);
90 static int ahci_wait_ready(device_t dev, int t);
92 static void ahci_issue_read_log(device_t dev);
93 static void ahci_process_read_log(device_t dev, union ccb *ccb);
95 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
96 static void ahcipoll(struct cam_sim *sim);
98 MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
105 #define AHCI_Q_NOFORCE 1
106 #define AHCI_Q_NOPMP 2
107 #define AHCI_Q_NONCQ 4
109 #define AHCI_Q_2CH 16
110 #define AHCI_Q_4CH 32
111 #define AHCI_Q_EDGEIS 64
112 #define AHCI_Q_SATA2 128
113 #define AHCI_Q_NOBSYRES 256
115 {0x43801002, 0x00, "ATI IXP600", 0},
116 {0x43901002, 0x00, "ATI IXP700", 0},
117 {0x43911002, 0x00, "ATI IXP700", 0},
118 {0x43921002, 0x00, "ATI IXP700", 0},
119 {0x43931002, 0x00, "ATI IXP700", 0},
120 {0x43941002, 0x00, "ATI IXP800", 0},
121 {0x43951002, 0x00, "ATI IXP800", 0},
122 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE},
123 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE},
124 {0x26818086, 0x00, "Intel ESB2", 0},
125 {0x26828086, 0x00, "Intel ESB2", 0},
126 {0x26838086, 0x00, "Intel ESB2", 0},
127 {0x27c18086, 0x00, "Intel ICH7", 0},
128 {0x27c38086, 0x00, "Intel ICH7", 0},
129 {0x27c58086, 0x00, "Intel ICH7M", 0},
130 {0x27c68086, 0x00, "Intel ICH7M", 0},
131 {0x28218086, 0x00, "Intel ICH8", 0},
132 {0x28228086, 0x00, "Intel ICH8", 0},
133 {0x28248086, 0x00, "Intel ICH8", 0},
134 {0x28298086, 0x00, "Intel ICH8M", 0},
135 {0x282a8086, 0x00, "Intel ICH8M", 0},
136 {0x29228086, 0x00, "Intel ICH9", 0},
137 {0x29238086, 0x00, "Intel ICH9", 0},
138 {0x29248086, 0x00, "Intel ICH9", 0},
139 {0x29258086, 0x00, "Intel ICH9", 0},
140 {0x29278086, 0x00, "Intel ICH9", 0},
141 {0x29298086, 0x00, "Intel ICH9M", 0},
142 {0x292a8086, 0x00, "Intel ICH9M", 0},
143 {0x292b8086, 0x00, "Intel ICH9M", 0},
144 {0x292c8086, 0x00, "Intel ICH9M", 0},
145 {0x292f8086, 0x00, "Intel ICH9M", 0},
146 {0x294d8086, 0x00, "Intel ICH9", 0},
147 {0x294e8086, 0x00, "Intel ICH9M", 0},
148 {0x3a058086, 0x00, "Intel ICH10", 0},
149 {0x3a228086, 0x00, "Intel ICH10", 0},
150 {0x3a258086, 0x00, "Intel ICH10", 0},
151 {0x3b228086, 0x00, "Intel PCH", 0},
152 {0x3b238086, 0x00, "Intel PCH", 0},
153 {0x3b248086, 0x00, "Intel PCH", 0},
154 {0x3b258086, 0x00, "Intel PCH", 0},
155 {0x3b298086, 0x00, "Intel PCH", 0},
156 {0x3b2b8086, 0x00, "Intel PCH", 0},
157 {0x3b2c8086, 0x00, "Intel PCH", 0},
158 {0x3b2f8086, 0x00, "Intel PCH", 0},
159 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE},
160 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE},
161 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE},
162 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE},
163 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE},
164 {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE|AHCI_Q_1CH|AHCI_Q_EDGEIS},
165 {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE|AHCI_Q_2CH|AHCI_Q_EDGEIS},
166 {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS},
167 {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS},
168 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES},
169 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES},
170 {0x044c10de, 0x00, "NVIDIA MCP65", 0},
171 {0x044d10de, 0x00, "NVIDIA MCP65", 0},
172 {0x044e10de, 0x00, "NVIDIA MCP65", 0},
173 {0x044f10de, 0x00, "NVIDIA MCP65", 0},
174 {0x045c10de, 0x00, "NVIDIA MCP65", 0},
175 {0x045d10de, 0x00, "NVIDIA MCP65", 0},
176 {0x045e10de, 0x00, "NVIDIA MCP65", 0},
177 {0x045f10de, 0x00, "NVIDIA MCP65", 0},
178 {0x055010de, 0x00, "NVIDIA MCP67", 0},
179 {0x055110de, 0x00, "NVIDIA MCP67", 0},
180 {0x055210de, 0x00, "NVIDIA MCP67", 0},
181 {0x055310de, 0x00, "NVIDIA MCP67", 0},
182 {0x055410de, 0x00, "NVIDIA MCP67", 0},
183 {0x055510de, 0x00, "NVIDIA MCP67", 0},
184 {0x055610de, 0x00, "NVIDIA MCP67", 0},
185 {0x055710de, 0x00, "NVIDIA MCP67", 0},
186 {0x055810de, 0x00, "NVIDIA MCP67", 0},
187 {0x055910de, 0x00, "NVIDIA MCP67", 0},
188 {0x055A10de, 0x00, "NVIDIA MCP67", 0},
189 {0x055B10de, 0x00, "NVIDIA MCP67", 0},
190 {0x058410de, 0x00, "NVIDIA MCP67", 0},
191 {0x07f010de, 0x00, "NVIDIA MCP73", 0},
192 {0x07f110de, 0x00, "NVIDIA MCP73", 0},
193 {0x07f210de, 0x00, "NVIDIA MCP73", 0},
194 {0x07f310de, 0x00, "NVIDIA MCP73", 0},
195 {0x07f410de, 0x00, "NVIDIA MCP73", 0},
196 {0x07f510de, 0x00, "NVIDIA MCP73", 0},
197 {0x07f610de, 0x00, "NVIDIA MCP73", 0},
198 {0x07f710de, 0x00, "NVIDIA MCP73", 0},
199 {0x07f810de, 0x00, "NVIDIA MCP73", 0},
200 {0x07f910de, 0x00, "NVIDIA MCP73", 0},
201 {0x07fa10de, 0x00, "NVIDIA MCP73", 0},
202 {0x07fb10de, 0x00, "NVIDIA MCP73", 0},
203 {0x0ad010de, 0x00, "NVIDIA MCP77", 0},
204 {0x0ad110de, 0x00, "NVIDIA MCP77", 0},
205 {0x0ad210de, 0x00, "NVIDIA MCP77", 0},
206 {0x0ad310de, 0x00, "NVIDIA MCP77", 0},
207 {0x0ad410de, 0x00, "NVIDIA MCP77", 0},
208 {0x0ad510de, 0x00, "NVIDIA MCP77", 0},
209 {0x0ad610de, 0x00, "NVIDIA MCP77", 0},
210 {0x0ad710de, 0x00, "NVIDIA MCP77", 0},
211 {0x0ad810de, 0x00, "NVIDIA MCP77", 0},
212 {0x0ad910de, 0x00, "NVIDIA MCP77", 0},
213 {0x0ada10de, 0x00, "NVIDIA MCP77", 0},
214 {0x0adb10de, 0x00, "NVIDIA MCP77", 0},
215 {0x0ab410de, 0x00, "NVIDIA MCP79", 0},
216 {0x0ab510de, 0x00, "NVIDIA MCP79", 0},
217 {0x0ab610de, 0x00, "NVIDIA MCP79", 0},
218 {0x0ab710de, 0x00, "NVIDIA MCP79", 0},
219 {0x0ab810de, 0x00, "NVIDIA MCP79", 0},
220 {0x0ab910de, 0x00, "NVIDIA MCP79", 0},
221 {0x0aba10de, 0x00, "NVIDIA MCP79", 0},
222 {0x0abb10de, 0x00, "NVIDIA MCP79", 0},
223 {0x0abc10de, 0x00, "NVIDIA MCP79", 0},
224 {0x0abd10de, 0x00, "NVIDIA MCP79", 0},
225 {0x0abe10de, 0x00, "NVIDIA MCP79", 0},
226 {0x0abf10de, 0x00, "NVIDIA MCP79", 0},
227 {0x0d8410de, 0x00, "NVIDIA MCP89", 0},
228 {0x0d8510de, 0x00, "NVIDIA MCP89", 0},
229 {0x0d8610de, 0x00, "NVIDIA MCP89", 0},
230 {0x0d8710de, 0x00, "NVIDIA MCP89", 0},
231 {0x0d8810de, 0x00, "NVIDIA MCP89", 0},
232 {0x0d8910de, 0x00, "NVIDIA MCP89", 0},
233 {0x0d8a10de, 0x00, "NVIDIA MCP89", 0},
234 {0x0d8b10de, 0x00, "NVIDIA MCP89", 0},
235 {0x0d8c10de, 0x00, "NVIDIA MCP89", 0},
236 {0x0d8d10de, 0x00, "NVIDIA MCP89", 0},
237 {0x0d8e10de, 0x00, "NVIDIA MCP89", 0},
238 {0x0d8f10de, 0x00, "NVIDIA MCP89", 0},
239 {0x33491106, 0x00, "VIA VT8251", 0},
240 {0x62871106, 0x00, "VIA VT8251", 0},
241 {0x11841039, 0x00, "SiS 966", 0},
242 {0x11851039, 0x00, "SiS 968", 0},
243 {0x01861039, 0x00, "SiS 968", 0},
244 {0x00000000, 0x00, NULL, 0}
248 ahci_probe(device_t dev)
252 uint32_t devid = pci_get_devid(dev);
253 uint8_t revid = pci_get_revid(dev);
255 /* Is this a possible AHCI candidate? */
256 if (pci_get_class(dev) == PCIC_STORAGE &&
257 pci_get_subclass(dev) == PCIS_STORAGE_SATA &&
258 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0)
260 /* Is this a known AHCI chip? */
261 for (i = 0; ahci_ids[i].id != 0; i++) {
262 if (ahci_ids[i].id == devid &&
263 ahci_ids[i].rev <= revid &&
264 (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) {
265 /* Do not attach JMicrons with single PCI function. */
266 if (pci_get_vendor(dev) == 0x197b &&
267 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
269 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
271 device_set_desc_copy(dev, buf);
272 return (BUS_PROBE_VENDOR);
277 device_set_desc_copy(dev, "AHCI SATA controller");
278 return (BUS_PROBE_VENDOR);
282 ahci_ata_probe(device_t dev)
286 uint32_t devid = pci_get_devid(dev);
287 uint8_t revid = pci_get_revid(dev);
289 if ((intptr_t)device_get_ivars(dev) >= 0)
291 /* Is this a known AHCI chip? */
292 for (i = 0; ahci_ids[i].id != 0; i++) {
293 if (ahci_ids[i].id == devid &&
294 ahci_ids[i].rev <= revid) {
295 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
297 device_set_desc_copy(dev, buf);
298 return (BUS_PROBE_VENDOR);
301 device_set_desc_copy(dev, "AHCI SATA controller");
302 return (BUS_PROBE_VENDOR);
306 ahci_attach(device_t dev)
308 struct ahci_controller *ctlr = device_get_softc(dev);
310 int error, unit, speed, i;
311 uint32_t devid = pci_get_devid(dev);
312 uint8_t revid = pci_get_revid(dev);
317 while (ahci_ids[i].id != 0 &&
318 (ahci_ids[i].id != devid ||
319 ahci_ids[i].rev > revid))
321 ctlr->quirks = ahci_ids[i].quirks;
322 resource_int_value(device_get_name(dev),
323 device_get_unit(dev), "ccc", &ctlr->ccc);
324 /* if we have a memory BAR(5) we are likely on an AHCI part */
325 ctlr->r_rid = PCIR_BAR(5);
326 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
327 &ctlr->r_rid, RF_ACTIVE)))
329 /* Setup our own memory management for channels. */
330 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
331 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
332 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
333 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
336 if ((error = rman_manage_region(&ctlr->sc_iomem,
337 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
338 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
339 rman_fini(&ctlr->sc_iomem);
342 /* Reset controller */
343 if ((error = ahci_ctlr_reset(dev)) != 0) {
344 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
345 rman_fini(&ctlr->sc_iomem);
348 /* Get the HW capabilities */
349 version = ATA_INL(ctlr->r_mem, AHCI_VS);
350 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
351 if (version >= 0x00010020)
352 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
353 if (ctlr->caps & AHCI_CAP_EMS)
354 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
355 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
356 if (ctlr->quirks & AHCI_Q_1CH) {
357 ctlr->caps &= ~AHCI_CAP_NPMASK;
358 ctlr->ichannels &= 0x01;
360 if (ctlr->quirks & AHCI_Q_2CH) {
361 ctlr->caps &= ~AHCI_CAP_NPMASK;
363 ctlr->ichannels &= 0x03;
365 if (ctlr->quirks & AHCI_Q_4CH) {
366 ctlr->caps &= ~AHCI_CAP_NPMASK;
368 ctlr->ichannels &= 0x0f;
370 ctlr->channels = MAX(flsl(ctlr->ichannels),
371 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
372 if (ctlr->quirks & AHCI_Q_NOPMP)
373 ctlr->caps &= ~AHCI_CAP_SPM;
374 if (ctlr->quirks & AHCI_Q_NONCQ)
375 ctlr->caps &= ~AHCI_CAP_SNCQ;
376 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
378 ahci_ctlr_setup(dev);
379 /* Setup interrupts. */
380 if (ahci_setup_interrupt(dev)) {
381 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
382 rman_fini(&ctlr->sc_iomem);
385 /* Announce HW capabilities. */
386 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
388 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
389 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
390 ((version >> 4) & 0xf0) + (version & 0x0f),
391 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
392 ((speed == 1) ? "1.5":((speed == 2) ? "3":
393 ((speed == 3) ? "6":"?"))),
394 (ctlr->caps & AHCI_CAP_SPM) ?
395 "supported" : "not supported",
396 (ctlr->caps & AHCI_CAP_FBSS) ?
399 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
400 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
401 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
402 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
403 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
404 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
405 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
406 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
407 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
408 ((speed == 1) ? "1.5":((speed == 2) ? "3":
409 ((speed == 3) ? "6":"?"))));
410 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
411 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
412 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
413 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
414 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
415 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
416 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
417 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
418 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
419 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
420 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
421 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
423 if (bootverbose && version >= 0x00010020) {
424 device_printf(dev, "Caps2:%s%s%s\n",
425 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
426 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
427 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
429 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) {
430 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n",
431 (ctlr->capsem & AHCI_EM_PM) ? " PM":"",
432 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"",
433 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"",
434 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"",
435 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"",
436 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"",
437 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"",
438 (ctlr->capsem & AHCI_EM_LED) ? " LED":"");
440 /* Attach all channels on this controller */
441 for (unit = 0; unit < ctlr->channels; unit++) {
442 if ((ctlr->ichannels & (1 << unit)) == 0)
444 child = device_add_child(dev, "ahcich", -1);
446 device_printf(dev, "failed to add channel device\n");
448 device_set_ivars(child, (void *)(intptr_t)unit);
450 bus_generic_attach(dev);
455 ahci_detach(device_t dev)
457 struct ahci_controller *ctlr = device_get_softc(dev);
461 /* Detach & delete all children */
462 if (!device_get_children(dev, &children, &nchildren)) {
463 for (i = 0; i < nchildren; i++)
464 device_delete_child(dev, children[i]);
465 free(children, M_TEMP);
467 /* Free interrupts. */
468 for (i = 0; i < ctlr->numirqs; i++) {
469 if (ctlr->irqs[i].r_irq) {
470 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
471 ctlr->irqs[i].handle);
472 bus_release_resource(dev, SYS_RES_IRQ,
473 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
476 pci_release_msi(dev);
478 rman_fini(&ctlr->sc_iomem);
480 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
485 ahci_ctlr_reset(device_t dev)
487 struct ahci_controller *ctlr = device_get_softc(dev);
490 if (pci_read_config(dev, 0x00, 4) == 0x28298086 &&
491 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
492 pci_write_config(dev, 0x92, 0x01, 1);
493 /* Enable AHCI mode */
494 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
495 /* Reset AHCI controller */
496 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
497 for (timeout = 1000; timeout > 0; timeout--) {
499 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
503 device_printf(dev, "AHCI controller reset failure\n");
506 /* Reenable AHCI mode */
507 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
512 ahci_ctlr_setup(device_t dev)
514 struct ahci_controller *ctlr = device_get_softc(dev);
515 /* Clear interrupts */
516 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
519 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
520 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
521 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
522 (4 << AHCI_CCCC_CC_SHIFT) |
524 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
525 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
528 "CCC with %dms/4cmd enabled on vector %d\n",
529 ctlr->ccc, ctlr->cccv);
532 /* Enable AHCI interrupts */
533 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
534 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
539 ahci_suspend(device_t dev)
541 struct ahci_controller *ctlr = device_get_softc(dev);
543 bus_generic_suspend(dev);
544 /* Disable interupts, so the state change(s) doesn't trigger */
545 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
546 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
551 ahci_resume(device_t dev)
555 if ((res = ahci_ctlr_reset(dev)) != 0)
557 ahci_ctlr_setup(dev);
558 return (bus_generic_resume(dev));
562 ahci_setup_interrupt(device_t dev)
564 struct ahci_controller *ctlr = device_get_softc(dev);
568 resource_int_value(device_get_name(dev),
569 device_get_unit(dev), "msi", &msi);
573 msi = min(1, pci_msi_count(dev));
575 msi = pci_msi_count(dev);
576 /* Allocate MSI if needed/present. */
577 if (msi && pci_alloc_msi(dev, &msi) == 0) {
583 /* Check for single MSI vector fallback. */
584 if (ctlr->numirqs > 1 &&
585 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
586 device_printf(dev, "Falling back to one MSI\n");
589 /* Allocate all IRQs. */
590 for (i = 0; i < ctlr->numirqs; i++) {
591 ctlr->irqs[i].ctlr = ctlr;
592 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0);
593 if (ctlr->numirqs == 1 || i >= ctlr->channels ||
594 (ctlr->ccc && i == ctlr->cccv))
595 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
596 else if (i == ctlr->numirqs - 1)
597 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
599 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
600 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
601 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
602 device_printf(dev, "unable to map interrupt\n");
605 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
606 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr,
607 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
608 /* SOS XXX release r_irq */
609 device_printf(dev, "unable to setup interrupt\n");
617 * Common case interrupt handler.
620 ahci_intr(void *data)
622 struct ahci_controller_irq *irq = data;
623 struct ahci_controller *ctlr = irq->ctlr;
624 u_int32_t is, ise = 0;
628 if (irq->mode == AHCI_IRQ_MODE_ALL) {
631 is = ctlr->ichannels;
633 is = ATA_INL(ctlr->r_mem, AHCI_IS);
634 } else { /* AHCI_IRQ_MODE_AFTER */
635 unit = irq->r_irq_rid - 1;
636 is = ATA_INL(ctlr->r_mem, AHCI_IS);
638 /* CCC interrupt is edge triggered. */
640 ise = 1 << ctlr->cccv;
641 /* Some controllers have edge triggered IS. */
642 if (ctlr->quirks & AHCI_Q_EDGEIS)
645 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
646 for (; unit < ctlr->channels; unit++) {
647 if ((is & (1 << unit)) != 0 &&
648 (arg = ctlr->interrupt[unit].argument)) {
649 ctlr->interrupt[unit].function(arg);
652 /* AHCI declares level triggered IS. */
653 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
654 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
658 * Simplified interrupt handler for multivector MSI mode.
661 ahci_intr_one(void *data)
663 struct ahci_controller_irq *irq = data;
664 struct ahci_controller *ctlr = irq->ctlr;
668 unit = irq->r_irq_rid - 1;
669 /* Some controllers have edge triggered IS. */
670 if (ctlr->quirks & AHCI_Q_EDGEIS)
671 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
672 if ((arg = ctlr->interrupt[unit].argument))
673 ctlr->interrupt[unit].function(arg);
674 /* AHCI declares level triggered IS. */
675 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
676 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
679 static struct resource *
680 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
681 u_long start, u_long end, u_long count, u_int flags)
683 struct ahci_controller *ctlr = device_get_softc(dev);
684 int unit = ((struct ahci_channel *)device_get_softc(child))->unit;
685 struct resource *res = NULL;
686 int offset = AHCI_OFFSET + (unit << 7);
691 st = rman_get_start(ctlr->r_mem);
692 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
693 st + offset + 127, 128, RF_ACTIVE, child);
695 bus_space_handle_t bsh;
697 bsh = rman_get_bushandle(ctlr->r_mem);
698 bst = rman_get_bustag(ctlr->r_mem);
699 bus_space_subregion(bst, bsh, offset, 128, &bsh);
700 rman_set_bushandle(res, bsh);
701 rman_set_bustag(res, bst);
705 if (*rid == ATA_IRQ_RID)
706 res = ctlr->irqs[0].r_irq;
713 ahci_release_resource(device_t dev, device_t child, int type, int rid,
719 rman_release_resource(r);
722 if (rid != ATA_IRQ_RID)
730 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
731 int flags, driver_filter_t *filter, driver_intr_t *function,
732 void *argument, void **cookiep)
734 struct ahci_controller *ctlr = device_get_softc(dev);
735 int unit = (intptr_t)device_get_ivars(child);
737 if (filter != NULL) {
738 printf("ahci.c: we cannot use a filter here\n");
741 ctlr->interrupt[unit].function = function;
742 ctlr->interrupt[unit].argument = argument;
747 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
750 struct ahci_controller *ctlr = device_get_softc(dev);
751 int unit = (intptr_t)device_get_ivars(child);
753 ctlr->interrupt[unit].function = NULL;
754 ctlr->interrupt[unit].argument = NULL;
759 ahci_print_child(device_t dev, device_t child)
763 retval = bus_print_child_header(dev, child);
764 retval += printf(" at channel %d",
765 (int)(intptr_t)device_get_ivars(child));
766 retval += bus_print_child_footer(dev, child);
771 devclass_t ahci_devclass;
772 static device_method_t ahci_methods[] = {
773 DEVMETHOD(device_probe, ahci_probe),
774 DEVMETHOD(device_attach, ahci_attach),
775 DEVMETHOD(device_detach, ahci_detach),
776 DEVMETHOD(device_suspend, ahci_suspend),
777 DEVMETHOD(device_resume, ahci_resume),
778 DEVMETHOD(bus_print_child, ahci_print_child),
779 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
780 DEVMETHOD(bus_release_resource, ahci_release_resource),
781 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
782 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
785 static driver_t ahci_driver = {
788 sizeof(struct ahci_controller)
790 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0);
791 static device_method_t ahci_ata_methods[] = {
792 DEVMETHOD(device_probe, ahci_ata_probe),
793 DEVMETHOD(device_attach, ahci_attach),
794 DEVMETHOD(device_detach, ahci_detach),
795 DEVMETHOD(device_suspend, ahci_suspend),
796 DEVMETHOD(device_resume, ahci_resume),
797 DEVMETHOD(bus_print_child, ahci_print_child),
798 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
799 DEVMETHOD(bus_release_resource, ahci_release_resource),
800 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
801 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
804 static driver_t ahci_ata_driver = {
807 sizeof(struct ahci_controller)
809 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0);
810 MODULE_VERSION(ahci, 1);
811 MODULE_DEPEND(ahci, cam, 1, 1, 1);
814 ahci_ch_probe(device_t dev)
817 device_set_desc_copy(dev, "AHCI channel");
822 ahci_ch_attach(device_t dev)
824 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
825 struct ahci_channel *ch = device_get_softc(dev);
826 struct cam_devq *devq;
827 int rid, error, i, sata_rev = 0;
831 ch->unit = (intptr_t)device_get_ivars(dev);
832 ch->caps = ctlr->caps;
833 ch->caps2 = ctlr->caps2;
834 ch->quirks = ctlr->quirks;
835 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
836 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
837 resource_int_value(device_get_name(dev),
838 device_get_unit(dev), "pm_level", &ch->pm_level);
839 if (ch->pm_level > 3)
840 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
841 /* Limit speed for my onboard JMicron external port.
842 * It is not eSATA really. */
843 if (pci_get_devid(ctlr->dev) == 0x2363197b &&
844 pci_get_subvendor(ctlr->dev) == 0x1043 &&
845 pci_get_subdevice(ctlr->dev) == 0x81e4 &&
848 if (ch->quirks & AHCI_Q_SATA2)
850 resource_int_value(device_get_name(dev),
851 device_get_unit(dev), "sata_rev", &sata_rev);
852 for (i = 0; i < 16; i++) {
853 ch->user[i].revision = sata_rev;
854 ch->user[i].mode = 0;
855 ch->user[i].bytecount = 8192;
856 ch->user[i].tags = ch->numslots;
857 ch->curr[i] = ch->user[i];
860 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
864 ahci_slotsalloc(dev);
868 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
869 &rid, RF_SHAREABLE | RF_ACTIVE))) {
870 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
871 device_printf(dev, "Unable to map interrupt\n");
874 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
875 ahci_ch_intr_locked, dev, &ch->ih))) {
876 device_printf(dev, "Unable to setup interrupt\n");
880 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
881 version = ATA_INL(ctlr->r_mem, AHCI_VS);
882 if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS))
883 ch->chcaps |= AHCI_P_CMD_FBSCP;
885 device_printf(dev, "Caps:%s%s%s%s%s\n",
886 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
887 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
888 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
889 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
890 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"");
892 /* Create the device queue for our SIM. */
893 devq = cam_simq_alloc(ch->numslots);
895 device_printf(dev, "Unable to allocate simq\n");
899 /* Construct SIM entry */
900 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
901 device_get_unit(dev), &ch->mtx,
902 min(2, ch->numslots),
903 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
905 if (ch->sim == NULL) {
906 device_printf(dev, "unable to allocate sim\n");
910 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
911 device_printf(dev, "unable to register xpt bus\n");
915 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
916 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
917 device_printf(dev, "unable to create path\n");
921 if (ch->pm_level > 3) {
922 callout_reset(&ch->pm_timer,
923 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
926 mtx_unlock(&ch->mtx);
930 xpt_bus_deregister(cam_sim_path(ch->sim));
932 cam_sim_free(ch->sim, /*free_devq*/TRUE);
934 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
935 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
936 mtx_unlock(&ch->mtx);
941 ahci_ch_detach(device_t dev)
943 struct ahci_channel *ch = device_get_softc(dev);
946 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
947 xpt_free_path(ch->path);
948 xpt_bus_deregister(cam_sim_path(ch->sim));
949 cam_sim_free(ch->sim, /*free_devq*/TRUE);
950 mtx_unlock(&ch->mtx);
952 if (ch->pm_level > 3)
953 callout_drain(&ch->pm_timer);
954 bus_teardown_intr(dev, ch->r_irq, ch->ih);
955 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
957 ahci_ch_suspend(dev);
961 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
962 mtx_destroy(&ch->mtx);
967 ahci_ch_suspend(device_t dev)
969 struct ahci_channel *ch = device_get_softc(dev);
971 /* Disable port interrupts. */
972 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
973 /* Reset command register. */
976 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
977 /* Allow everything, including partial and slumber modes. */
978 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
979 /* Request slumber mode transition and give some time to get there. */
980 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
983 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
988 ahci_ch_resume(device_t dev)
990 struct ahci_channel *ch = device_get_softc(dev);
993 /* Disable port interrupts */
994 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
995 /* Setup work areas */
996 work = ch->dma.work_bus + AHCI_CL_OFFSET;
997 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
998 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
999 work = ch->dma.rfis_bus;
1000 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
1001 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
1002 /* Activate the channel and power/spin up device */
1003 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
1004 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1005 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
1006 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
1012 devclass_t ahcich_devclass;
1013 static device_method_t ahcich_methods[] = {
1014 DEVMETHOD(device_probe, ahci_ch_probe),
1015 DEVMETHOD(device_attach, ahci_ch_attach),
1016 DEVMETHOD(device_detach, ahci_ch_detach),
1017 DEVMETHOD(device_suspend, ahci_ch_suspend),
1018 DEVMETHOD(device_resume, ahci_ch_resume),
1021 static driver_t ahcich_driver = {
1024 sizeof(struct ahci_channel)
1026 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0);
1028 struct ahci_dc_cb_args {
1034 ahci_dmainit(device_t dev)
1036 struct ahci_channel *ch = device_get_softc(dev);
1037 struct ahci_dc_cb_args dcba;
1040 if (ch->caps & AHCI_CAP_64BIT)
1041 ch->dma.max_address = BUS_SPACE_MAXADDR;
1043 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT;
1045 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
1046 ch->dma.max_address, BUS_SPACE_MAXADDR,
1047 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
1048 0, NULL, NULL, &ch->dma.work_tag))
1050 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0,
1053 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1054 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1055 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1058 ch->dma.work_bus = dcba.maddr;
1059 /* FIS receive area. */
1060 if (ch->chcaps & AHCI_P_CMD_FBSCP)
1064 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
1065 ch->dma.max_address, BUS_SPACE_MAXADDR,
1066 NULL, NULL, rfsize, 1, rfsize,
1067 0, NULL, NULL, &ch->dma.rfis_tag))
1069 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1072 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1073 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1074 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1077 ch->dma.rfis_bus = dcba.maddr;
1079 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
1080 ch->dma.max_address, BUS_SPACE_MAXADDR,
1082 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
1083 AHCI_SG_ENTRIES, AHCI_PRD_MAX,
1084 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
1090 device_printf(dev, "WARNING - DMA initialization failed\n");
1095 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1097 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
1099 if (!(dcba->error = error))
1100 dcba->maddr = segs[0].ds_addr;
1104 ahci_dmafini(device_t dev)
1106 struct ahci_channel *ch = device_get_softc(dev);
1108 if (ch->dma.data_tag) {
1109 bus_dma_tag_destroy(ch->dma.data_tag);
1110 ch->dma.data_tag = NULL;
1112 if (ch->dma.rfis_bus) {
1113 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1114 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1115 ch->dma.rfis_bus = 0;
1116 ch->dma.rfis_map = NULL;
1117 ch->dma.rfis = NULL;
1119 if (ch->dma.work_bus) {
1120 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1121 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1122 ch->dma.work_bus = 0;
1123 ch->dma.work_map = NULL;
1124 ch->dma.work = NULL;
1126 if (ch->dma.work_tag) {
1127 bus_dma_tag_destroy(ch->dma.work_tag);
1128 ch->dma.work_tag = NULL;
1133 ahci_slotsalloc(device_t dev)
1135 struct ahci_channel *ch = device_get_softc(dev);
1138 /* Alloc and setup command/dma slots */
1139 bzero(ch->slot, sizeof(ch->slot));
1140 for (i = 0; i < ch->numslots; i++) {
1141 struct ahci_slot *slot = &ch->slot[i];
1145 slot->state = AHCI_SLOT_EMPTY;
1147 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1149 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1150 device_printf(ch->dev, "FAILURE - create data_map\n");
1155 ahci_slotsfree(device_t dev)
1157 struct ahci_channel *ch = device_get_softc(dev);
1160 /* Free all dma slots */
1161 for (i = 0; i < ch->numslots; i++) {
1162 struct ahci_slot *slot = &ch->slot[i];
1164 callout_drain(&slot->timeout);
1165 if (slot->dma.data_map) {
1166 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1167 slot->dma.data_map = NULL;
1173 ahci_phy_check_events(device_t dev, u_int32_t serr)
1175 struct ahci_channel *ch = device_get_softc(dev);
1177 if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) {
1178 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1182 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
1183 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
1184 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) {
1185 device_printf(dev, "CONNECT requested\n");
1187 device_printf(dev, "DISCONNECT requested\n");
1190 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1192 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1193 cam_sim_path(ch->sim),
1194 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1203 ahci_notify_events(device_t dev, u_int32_t status)
1205 struct ahci_channel *ch = device_get_softc(dev);
1206 struct cam_path *dpath;
1209 if (ch->caps & AHCI_CAP_SSNTF)
1210 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1212 device_printf(dev, "SNTF 0x%04x\n", status);
1213 for (i = 0; i < 16; i++) {
1214 if ((status & (1 << i)) == 0)
1216 if (xpt_create_path(&dpath, NULL,
1217 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1218 xpt_async(AC_SCSI_AEN, dpath, NULL);
1219 xpt_free_path(dpath);
1225 ahci_ch_intr_locked(void *data)
1227 device_t dev = (device_t)data;
1228 struct ahci_channel *ch = device_get_softc(dev);
1232 mtx_unlock(&ch->mtx);
1236 ahci_ch_pm(void *arg)
1238 device_t dev = (device_t)arg;
1239 struct ahci_channel *ch = device_get_softc(dev);
1242 if (ch->numrslots != 0)
1244 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1245 if (ch->pm_level == 4)
1246 work |= AHCI_P_CMD_PARTIAL;
1248 work |= AHCI_P_CMD_SLUMBER;
1249 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1253 ahci_ch_intr(void *data)
1255 device_t dev = (device_t)data;
1256 struct ahci_channel *ch = device_get_softc(dev);
1257 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err;
1258 enum ahci_err_type et;
1261 /* Read and clear interrupt statuses. */
1262 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1265 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1266 /* Read command statuses. */
1267 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1268 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI);
1269 if (istatus & AHCI_P_IX_SDB) {
1270 if (ch->caps & AHCI_CAP_SSNTF)
1271 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1272 else if (ch->fbs_enabled) {
1273 u_int8_t *fis = ch->dma.rfis + 0x58;
1275 for (i = 0; i < 16; i++) {
1276 if (fis[1] & 0x80) {
1283 u_int8_t *fis = ch->dma.rfis + 0x58;
1286 sntf = (1 << (fis[1] & 0x0f));
1289 /* Process PHY events */
1290 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1291 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1292 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1294 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1295 ahci_phy_check_events(dev, serr);
1298 /* Process command errors */
1299 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1300 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1301 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1302 >> AHCI_P_CMD_CCS_SHIFT;
1303 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1304 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1305 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1307 if (ch->fbs_enabled) {
1308 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1309 if (fbs & AHCI_P_FBS_SDE) {
1310 port = (fbs & AHCI_P_FBS_DWE)
1311 >> AHCI_P_FBS_DWE_SHIFT;
1313 for (i = 0; i < 16; i++) {
1314 if (ch->numrslotspd[i] == 0)
1318 else if (port != i) {
1325 err = ch->rslots & (cstatus | sstatus);
1331 /* Complete all successfull commands. */
1332 ok = ch->rslots & ~(cstatus | sstatus);
1333 for (i = 0; i < ch->numslots; i++) {
1335 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1337 /* On error, complete the rest of commands with error statuses. */
1340 union ccb *fccb = ch->frozen;
1342 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1343 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1344 xpt_freeze_devq(fccb->ccb_h.path, 1);
1345 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1349 for (i = 0; i < ch->numslots; i++) {
1350 /* XXX: reqests in loading state. */
1351 if (((err >> i) & 1) == 0)
1354 ch->slot[i].ccb->ccb_h.target_id != port)
1356 if (istatus & AHCI_P_IX_TFE) {
1358 /* Task File Error */
1359 if (ch->numtslotspd[
1360 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1361 /* Untagged operation. */
1365 et = AHCI_ERR_INNOCENT;
1367 /* Tagged operation. */
1374 } else if (istatus & AHCI_P_IX_IF) {
1375 if (ch->numtslots == 0 && i != ccs && port != -2)
1376 et = AHCI_ERR_INNOCENT;
1380 et = AHCI_ERR_INVALID;
1381 ahci_end_transaction(&ch->slot[i], et);
1384 * We can't reinit port if there are some other
1385 * commands active, use resume to complete them.
1387 if (ch->rslots != 0)
1388 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1390 /* Process NOTIFY events */
1392 ahci_notify_events(dev, sntf);
1395 /* Must be called with channel locked. */
1397 ahci_check_collision(device_t dev, union ccb *ccb)
1399 struct ahci_channel *ch = device_get_softc(dev);
1400 int t = ccb->ccb_h.target_id;
1402 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1403 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1404 /* Tagged command while we have no supported tag free. */
1405 if (((~ch->oslots) & (0xffffffff >> (32 -
1406 ch->curr[t].tags))) == 0)
1408 /* If we have FBS */
1409 if (ch->fbs_enabled) {
1410 /* Tagged command while untagged are active. */
1411 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1414 /* Tagged command while untagged are active. */
1415 if (ch->numrslots != 0 && ch->numtslots == 0)
1417 /* Tagged command while tagged to other target is active. */
1418 if (ch->numtslots != 0 &&
1419 ch->taggedtarget != ccb->ccb_h.target_id)
1423 /* If we have FBS */
1424 if (ch->fbs_enabled) {
1425 /* Untagged command while tagged are active. */
1426 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1429 /* Untagged command while tagged are active. */
1430 if (ch->numrslots != 0 && ch->numtslots != 0)
1434 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1435 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1436 /* Atomic command while anything active. */
1437 if (ch->numrslots != 0)
1440 /* We have some atomic command running. */
1441 if (ch->aslots != 0)
1446 /* Must be called with channel locked. */
1448 ahci_begin_transaction(device_t dev, union ccb *ccb)
1450 struct ahci_channel *ch = device_get_softc(dev);
1451 struct ahci_slot *slot;
1454 /* Choose empty slot. */
1455 tags = ch->numslots;
1456 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1457 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1458 tags = ch->curr[ccb->ccb_h.target_id].tags;
1463 if (ch->slot[tag].state == AHCI_SLOT_EMPTY)
1468 /* Occupy chosen slot. */
1469 slot = &ch->slot[tag];
1471 /* Stop PM timer. */
1472 if (ch->numrslots == 0 && ch->pm_level > 3)
1473 callout_stop(&ch->pm_timer);
1474 /* Update channel stats. */
1475 ch->oslots |= (1 << slot->slot);
1477 ch->numrslotspd[ccb->ccb_h.target_id]++;
1478 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1479 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1481 ch->numtslotspd[ccb->ccb_h.target_id]++;
1482 ch->taggedtarget = ccb->ccb_h.target_id;
1484 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1485 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1486 ch->aslots |= (1 << slot->slot);
1487 slot->dma.nsegs = 0;
1488 /* If request moves data, setup and load SG list */
1489 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1493 slot->state = AHCI_SLOT_LOADING;
1494 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1495 buf = ccb->ataio.data_ptr;
1496 size = ccb->ataio.dxfer_len;
1498 buf = ccb->csio.data_ptr;
1499 size = ccb->csio.dxfer_len;
1501 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map,
1502 buf, size, ahci_dmasetprd, slot, 0);
1504 ahci_execute_transaction(slot);
1507 /* Locked by busdma engine. */
1509 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1511 struct ahci_slot *slot = arg;
1512 struct ahci_channel *ch = device_get_softc(slot->dev);
1513 struct ahci_cmd_tab *ctp;
1514 struct ahci_dma_prd *prd;
1518 device_printf(slot->dev, "DMA load error\n");
1519 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1522 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1523 /* Get a piece of the workspace for this request */
1524 ctp = (struct ahci_cmd_tab *)
1525 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1526 /* Fill S/G table */
1527 prd = &ctp->prd_tab[0];
1528 for (i = 0; i < nsegs; i++) {
1529 prd[i].dba = htole64(segs[i].ds_addr);
1530 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1532 slot->dma.nsegs = nsegs;
1533 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1534 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1535 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1536 ahci_execute_transaction(slot);
1539 /* Must be called with channel locked. */
1541 ahci_execute_transaction(struct ahci_slot *slot)
1543 device_t dev = slot->dev;
1544 struct ahci_channel *ch = device_get_softc(dev);
1545 struct ahci_cmd_tab *ctp;
1546 struct ahci_cmd_list *clp;
1547 union ccb *ccb = slot->ccb;
1548 int port = ccb->ccb_h.target_id & 0x0f;
1550 uint8_t *fis = ch->dma.rfis + 0x40;
1553 /* Get a piece of the workspace for this request */
1554 ctp = (struct ahci_cmd_tab *)
1555 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1556 /* Setup the FIS for this request */
1557 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) {
1558 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1559 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1562 /* Setup the command list entry */
1563 clp = (struct ahci_cmd_list *)
1564 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1565 clp->prd_length = slot->dma.nsegs;
1566 clp->cmd_flags = (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1567 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1568 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1569 (fis_size / sizeof(u_int32_t)) |
1571 /* Special handling for Soft Reset command. */
1572 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1573 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1574 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1575 /* Kick controller into sane state */
1579 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1581 /* Prepare FIS receive area for check. */
1582 for (i = 0; i < 20; i++)
1587 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1588 (AHCI_CT_SIZE * slot->slot));
1589 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1590 BUS_DMASYNC_PREWRITE);
1591 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1592 BUS_DMASYNC_PREREAD);
1593 /* Set ACTIVE bit for NCQ commands. */
1594 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1595 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1596 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1598 /* If FBS is enabled, set PMP port. */
1599 if (ch->fbs_enabled) {
1600 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1601 (port << AHCI_P_FBS_DEV_SHIFT));
1603 /* Issue command to the controller. */
1604 slot->state = AHCI_SLOT_RUNNING;
1605 ch->rslots |= (1 << slot->slot);
1606 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1607 /* Device reset commands doesn't interrupt. Poll them. */
1608 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1609 (ccb->ataio.cmd.command == ATA_DEVICE_RESET ||
1610 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) {
1611 int count, timeout = ccb->ccb_h.timeout;
1612 enum ahci_err_type et = AHCI_ERR_NONE;
1614 for (count = 0; count < timeout; count++) {
1616 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1618 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) {
1619 device_printf(ch->dev,
1620 "Poll error on slot %d, TFD: %04x\n",
1621 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1625 /* Workaround for ATI SB600/SB700 chipsets. */
1626 if (ccb->ccb_h.target_id == 15 &&
1627 pci_get_vendor(device_get_parent(dev)) == 0x1002 &&
1628 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1629 et = AHCI_ERR_TIMEOUT;
1633 if (timeout && (count >= timeout)) {
1634 device_printf(ch->dev,
1635 "Poll timeout on slot %d\n", slot->slot);
1636 device_printf(dev, "is %08x cs %08x ss %08x "
1637 "rs %08x tfd %02x serr %08x\n",
1638 ATA_INL(ch->r_mem, AHCI_P_IS),
1639 ATA_INL(ch->r_mem, AHCI_P_CI),
1640 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1641 ATA_INL(ch->r_mem, AHCI_P_TFD),
1642 ATA_INL(ch->r_mem, AHCI_P_SERR));
1643 et = AHCI_ERR_TIMEOUT;
1645 /* Marvell controllers do not wait for readyness. */
1646 if ((ch->quirks & AHCI_Q_NOBSYRES) &&
1647 (ccb->ccb_h.func_code == XPT_ATA_IO) &&
1648 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1649 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1650 while ((val = fis[2]) & (ATA_S_BUSY | ATA_S_DRQ)) {
1652 if (count++ >= timeout) {
1653 device_printf(dev, "device is not "
1654 "ready after soft-reset: "
1655 "tfd = %08x\n", val);
1656 et = AHCI_ERR_TIMEOUT;
1661 ahci_end_transaction(slot, et);
1662 /* Kick controller into sane state and enable FBS. */
1663 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1664 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1665 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1667 ahci_start(ch->dev, 1);
1671 /* Start command execution timeout */
1672 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000,
1673 (timeout_t*)ahci_timeout, slot);
1677 /* Must be called with channel locked. */
1679 ahci_process_timeout(device_t dev)
1681 struct ahci_channel *ch = device_get_softc(dev);
1684 mtx_assert(&ch->mtx, MA_OWNED);
1685 /* Handle the rest of commands. */
1686 for (i = 0; i < ch->numslots; i++) {
1687 /* Do we have a running request on slot? */
1688 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1690 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1694 /* Must be called with channel locked. */
1696 ahci_rearm_timeout(device_t dev)
1698 struct ahci_channel *ch = device_get_softc(dev);
1701 mtx_assert(&ch->mtx, MA_OWNED);
1702 for (i = 0; i < ch->numslots; i++) {
1703 struct ahci_slot *slot = &ch->slot[i];
1705 /* Do we have a running request on slot? */
1706 if (slot->state < AHCI_SLOT_RUNNING)
1708 if ((ch->toslots & (1 << i)) == 0)
1710 callout_reset(&slot->timeout,
1711 (int)slot->ccb->ccb_h.timeout * hz / 2000,
1712 (timeout_t*)ahci_timeout, slot);
1716 /* Locked by callout mechanism. */
1718 ahci_timeout(struct ahci_slot *slot)
1720 device_t dev = slot->dev;
1721 struct ahci_channel *ch = device_get_softc(dev);
1726 /* Check for stale timeout. */
1727 if (slot->state < AHCI_SLOT_RUNNING)
1730 /* Check if slot was not being executed last time we checked. */
1731 if (slot->state < AHCI_SLOT_EXECUTING) {
1732 /* Check if slot started executing. */
1733 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1734 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1735 >> AHCI_P_CMD_CCS_SHIFT;
1736 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1738 slot->state = AHCI_SLOT_EXECUTING;
1740 callout_reset(&slot->timeout,
1741 (int)slot->ccb->ccb_h.timeout * hz / 2000,
1742 (timeout_t*)ahci_timeout, slot);
1746 device_printf(dev, "Timeout on slot %d\n", slot->slot);
1747 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n",
1748 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1749 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1750 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR));
1752 /* Handle frozen command. */
1754 union ccb *fccb = ch->frozen;
1756 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1757 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1758 xpt_freeze_devq(fccb->ccb_h.path, 1);
1759 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1763 if (!ch->fbs_enabled) {
1764 /* Without FBS we know real timeout source. */
1766 /* Handle command with timeout. */
1767 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1768 /* Handle the rest of commands. */
1769 for (i = 0; i < ch->numslots; i++) {
1770 /* Do we have a running request on slot? */
1771 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1773 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1776 /* With FBS we wait for other commands timeout and pray. */
1777 if (ch->toslots == 0)
1778 xpt_freeze_simq(ch->sim, 1);
1779 ch->toslots |= (1 << slot->slot);
1780 if ((ch->rslots & ~ch->toslots) == 0)
1781 ahci_process_timeout(dev);
1783 device_printf(dev, " ... waiting for slots %08x\n",
1784 ch->rslots & ~ch->toslots);
1788 /* Must be called with channel locked. */
1790 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
1792 device_t dev = slot->dev;
1793 struct ahci_channel *ch = device_get_softc(dev);
1794 union ccb *ccb = slot->ccb;
1796 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1797 BUS_DMASYNC_POSTWRITE);
1798 /* Read result registers to the result struct
1799 * May be incorrect if several commands finished same time,
1800 * so read only when sure or have to.
1802 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1803 struct ata_res *res = &ccb->ataio.res;
1805 if ((et == AHCI_ERR_TFE) ||
1806 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1807 u_int8_t *fis = ch->dma.rfis + 0x40;
1809 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1810 BUS_DMASYNC_POSTREAD);
1811 if (ch->fbs_enabled) {
1812 fis += ccb->ccb_h.target_id * 256;
1813 res->status = fis[2];
1814 res->error = fis[3];
1816 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1819 res->error = tfd >> 8;
1821 res->lba_low = fis[4];
1822 res->lba_mid = fis[5];
1823 res->lba_high = fis[6];
1824 res->device = fis[7];
1825 res->lba_low_exp = fis[8];
1826 res->lba_mid_exp = fis[9];
1827 res->lba_high_exp = fis[10];
1828 res->sector_count = fis[12];
1829 res->sector_count_exp = fis[13];
1831 bzero(res, sizeof(*res));
1833 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1834 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1835 (ccb->ccb_h.flags & CAM_DIR_IN) ?
1836 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1837 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1839 if (et != AHCI_ERR_NONE)
1840 ch->eslots |= (1 << slot->slot);
1841 /* In case of error, freeze device for proper recovery. */
1842 if ((et != AHCI_ERR_NONE) && (!ch->readlog) &&
1843 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
1844 xpt_freeze_devq(ccb->ccb_h.path, 1);
1845 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1847 /* Set proper result status. */
1848 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1851 ccb->ccb_h.status |= CAM_REQ_CMP;
1852 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1853 ccb->csio.scsi_status = SCSI_STATUS_OK;
1855 case AHCI_ERR_INVALID:
1857 ccb->ccb_h.status |= CAM_REQ_INVALID;
1859 case AHCI_ERR_INNOCENT:
1860 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1864 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1865 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1866 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1868 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1874 xpt_freeze_simq(ch->sim, 1);
1875 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1876 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1878 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1880 case AHCI_ERR_TIMEOUT:
1882 xpt_freeze_simq(ch->sim, 1);
1883 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1884 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1886 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1890 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1893 ch->oslots &= ~(1 << slot->slot);
1894 ch->rslots &= ~(1 << slot->slot);
1895 ch->aslots &= ~(1 << slot->slot);
1896 if (et != AHCI_ERR_TIMEOUT) {
1897 if (ch->toslots == (1 << slot->slot))
1898 xpt_release_simq(ch->sim, TRUE);
1899 ch->toslots &= ~(1 << slot->slot);
1901 slot->state = AHCI_SLOT_EMPTY;
1903 /* Update channel stats. */
1905 ch->numrslotspd[ccb->ccb_h.target_id]--;
1906 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1907 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1909 ch->numtslotspd[ccb->ccb_h.target_id]--;
1911 /* If it was first request of reset sequence and there is no error,
1912 * proceed to second request. */
1913 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1914 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1915 (ccb->ataio.cmd.control & ATA_A_RESET) &&
1916 et == AHCI_ERR_NONE) {
1917 ccb->ataio.cmd.control &= ~ATA_A_RESET;
1918 ahci_begin_transaction(dev, ccb);
1921 /* If it was our READ LOG command - process it. */
1923 ahci_process_read_log(dev, ccb);
1924 /* If it was NCQ command error, put result on hold. */
1925 } else if (et == AHCI_ERR_NCQ) {
1926 ch->hold[slot->slot] = ccb;
1930 /* Unfreeze frozen command. */
1931 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) {
1932 union ccb *fccb = ch->frozen;
1934 ahci_begin_transaction(dev, fccb);
1935 xpt_release_simq(ch->sim, TRUE);
1937 /* If we have no other active commands, ... */
1938 if (ch->rslots == 0) {
1939 /* if there was fatal error - reset port. */
1940 if (ch->toslots != 0 || ch->fatalerr) {
1943 /* if we have slots in error, we can reinit port. */
1944 if (ch->eslots != 0) {
1948 /* if there commands on hold, we can do READ LOG. */
1949 if (!ch->readlog && ch->numhslots)
1950 ahci_issue_read_log(dev);
1952 /* If all the rest of commands are in timeout - give them chance. */
1953 } else if ((ch->rslots & ~ch->toslots) == 0 &&
1954 et != AHCI_ERR_TIMEOUT)
1955 ahci_rearm_timeout(dev);
1956 /* Start PM timer. */
1957 if (ch->numrslots == 0 && ch->pm_level > 3) {
1958 callout_schedule(&ch->pm_timer,
1959 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
1964 ahci_issue_read_log(device_t dev)
1966 struct ahci_channel *ch = device_get_softc(dev);
1968 struct ccb_ataio *ataio;
1972 /* Find some holden command. */
1973 for (i = 0; i < ch->numslots; i++) {
1977 ccb = xpt_alloc_ccb_nowait();
1979 device_printf(dev, "Unable allocate READ LOG command");
1982 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
1983 ccb->ccb_h.func_code = XPT_ATA_IO;
1984 ccb->ccb_h.flags = CAM_DIR_IN;
1985 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
1986 ataio = &ccb->ataio;
1987 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
1988 if (ataio->data_ptr == NULL) {
1989 device_printf(dev, "Unable allocate memory for READ LOG command");
1992 ataio->dxfer_len = 512;
1993 bzero(&ataio->cmd, sizeof(ataio->cmd));
1994 ataio->cmd.flags = CAM_ATAIO_48BIT;
1995 ataio->cmd.command = 0x2F; /* READ LOG EXT */
1996 ataio->cmd.sector_count = 1;
1997 ataio->cmd.sector_count_exp = 0;
1998 ataio->cmd.lba_low = 0x10;
1999 ataio->cmd.lba_mid = 0;
2000 ataio->cmd.lba_mid_exp = 0;
2001 /* Freeze SIM while doing READ LOG EXT. */
2002 xpt_freeze_simq(ch->sim, 1);
2003 ahci_begin_transaction(dev, ccb);
2007 ahci_process_read_log(device_t dev, union ccb *ccb)
2009 struct ahci_channel *ch = device_get_softc(dev);
2011 struct ata_res *res;
2016 data = ccb->ataio.data_ptr;
2017 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2018 (data[0] & 0x80) == 0) {
2019 for (i = 0; i < ch->numslots; i++) {
2022 if ((data[0] & 0x1F) == i) {
2023 res = &ch->hold[i]->ataio.res;
2024 res->status = data[2];
2025 res->error = data[3];
2026 res->lba_low = data[4];
2027 res->lba_mid = data[5];
2028 res->lba_high = data[6];
2029 res->device = data[7];
2030 res->lba_low_exp = data[8];
2031 res->lba_mid_exp = data[9];
2032 res->lba_high_exp = data[10];
2033 res->sector_count = data[12];
2034 res->sector_count_exp = data[13];
2036 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2037 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2039 xpt_done(ch->hold[i]);
2044 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2045 device_printf(dev, "Error while READ LOG EXT\n");
2046 else if ((data[0] & 0x80) == 0) {
2047 device_printf(dev, "Non-queued command error in READ LOG EXT\n");
2049 for (i = 0; i < ch->numslots; i++) {
2052 xpt_done(ch->hold[i]);
2057 free(ccb->ataio.data_ptr, M_AHCI);
2059 xpt_release_simq(ch->sim, TRUE);
2063 ahci_start(device_t dev, int fbs)
2065 struct ahci_channel *ch = device_get_softc(dev);
2068 /* Clear SATA error register */
2069 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2070 /* Clear any interrupts pending on this channel */
2071 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2072 /* Configure FIS-based switching if supported. */
2073 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2074 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2075 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2076 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2078 /* Start operations on this channel */
2079 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2080 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2081 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2085 ahci_stop(device_t dev)
2087 struct ahci_channel *ch = device_get_softc(dev);
2091 /* Kill all activity on this channel */
2092 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2093 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2094 /* Wait for activity stop. */
2098 if (timeout++ > 1000) {
2099 device_printf(dev, "stopping AHCI engine failed\n");
2102 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2107 ahci_clo(device_t dev)
2109 struct ahci_channel *ch = device_get_softc(dev);
2113 /* Issue Command List Override if supported */
2114 if (ch->caps & AHCI_CAP_SCLO) {
2115 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2116 cmd |= AHCI_P_CMD_CLO;
2117 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2121 if (timeout++ > 1000) {
2122 device_printf(dev, "executing CLO failed\n");
2125 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2130 ahci_stop_fr(device_t dev)
2132 struct ahci_channel *ch = device_get_softc(dev);
2136 /* Kill all FIS reception on this channel */
2137 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2138 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2139 /* Wait for FIS reception stop. */
2143 if (timeout++ > 1000) {
2144 device_printf(dev, "stopping AHCI FR engine failed\n");
2147 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2151 ahci_start_fr(device_t dev)
2153 struct ahci_channel *ch = device_get_softc(dev);
2156 /* Start FIS reception on this channel */
2157 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2158 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2162 ahci_wait_ready(device_t dev, int t)
2164 struct ahci_channel *ch = device_get_softc(dev);
2168 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2169 (ATA_S_BUSY | ATA_S_DRQ)) {
2171 if (timeout++ > t) {
2172 device_printf(dev, "device is not ready (timeout %dms) "
2173 "tfd = %08x\n", t, val);
2178 device_printf(dev, "ready wait time=%dms\n", timeout);
2183 ahci_reset(device_t dev)
2185 struct ahci_channel *ch = device_get_softc(dev);
2186 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
2189 xpt_freeze_simq(ch->sim, 1);
2191 device_printf(dev, "AHCI reset...\n");
2192 /* Requeue freezed command. */
2194 union ccb *fccb = ch->frozen;
2196 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2197 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2198 xpt_freeze_devq(fccb->ccb_h.path, 1);
2199 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2203 /* Kill the engine and requeue all running commands. */
2205 for (i = 0; i < ch->numslots; i++) {
2206 /* Do we have a running request on slot? */
2207 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2209 /* XXX; Commands in loading state. */
2210 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2212 for (i = 0; i < ch->numslots; i++) {
2215 xpt_done(ch->hold[i]);
2219 if (ch->toslots != 0)
2220 xpt_release_simq(ch->sim, TRUE);
2224 /* Tell the XPT about the event */
2225 xpt_async(AC_BUS_RESET, ch->path, NULL);
2226 /* Disable port interrupts */
2227 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2228 /* Reset and reconnect PHY, */
2229 if (!ahci_sata_phy_reset(dev)) {
2232 "AHCI reset done: phy reset found no device\n");
2234 /* Enable wanted port interrupts */
2235 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2236 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC));
2237 xpt_release_simq(ch->sim, TRUE);
2240 /* Wait for clearing busy status. */
2241 if (ahci_wait_ready(dev, 15000))
2245 /* Enable wanted port interrupts */
2246 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2247 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2248 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2249 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) |
2250 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2251 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2253 device_printf(dev, "AHCI reset done: device found\n");
2254 xpt_release_simq(ch->sim, TRUE);
2258 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2260 struct ahci_channel *ch = device_get_softc(dev);
2261 u_int8_t *fis = &ctp->cfis[0];
2263 bzero(ctp->cfis, 64);
2264 fis[0] = 0x27; /* host to device */
2265 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2266 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2268 fis[2] = ATA_PACKET_CMD;
2269 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2270 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2273 fis[5] = ccb->csio.dxfer_len;
2274 fis[6] = ccb->csio.dxfer_len >> 8;
2277 fis[15] = ATA_A_4BIT;
2278 bzero(ctp->acmd, 32);
2279 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2280 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2281 ctp->acmd, ccb->csio.cdb_len);
2282 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2284 fis[2] = ccb->ataio.cmd.command;
2285 fis[3] = ccb->ataio.cmd.features;
2286 fis[4] = ccb->ataio.cmd.lba_low;
2287 fis[5] = ccb->ataio.cmd.lba_mid;
2288 fis[6] = ccb->ataio.cmd.lba_high;
2289 fis[7] = ccb->ataio.cmd.device;
2290 fis[8] = ccb->ataio.cmd.lba_low_exp;
2291 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2292 fis[10] = ccb->ataio.cmd.lba_high_exp;
2293 fis[11] = ccb->ataio.cmd.features_exp;
2294 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2298 fis[12] = ccb->ataio.cmd.sector_count;
2299 fis[13] = ccb->ataio.cmd.sector_count_exp;
2301 fis[15] = ATA_A_4BIT;
2303 fis[15] = ccb->ataio.cmd.control;
2309 ahci_sata_connect(struct ahci_channel *ch)
2314 /* Wait up to 100ms for "connect well" */
2315 for (timeout = 0; timeout < 100 ; timeout++) {
2316 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2317 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2318 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2319 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2321 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2323 device_printf(ch->dev, "SATA offline status=%08x\n",
2330 if (timeout >= 100) {
2332 device_printf(ch->dev, "SATA connect timeout status=%08x\n",
2338 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n",
2341 /* Clear SATA error register */
2342 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2347 ahci_sata_phy_reset(device_t dev)
2349 struct ahci_channel *ch = device_get_softc(dev);
2353 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2355 val = ATA_SC_SPD_SPEED_GEN1;
2356 else if (sata_rev == 2)
2357 val = ATA_SC_SPD_SPEED_GEN2;
2358 else if (sata_rev == 3)
2359 val = ATA_SC_SPD_SPEED_GEN3;
2362 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2363 ATA_SC_DET_RESET | val |
2364 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2366 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2367 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2368 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2370 if (!ahci_sata_connect(ch)) {
2371 if (ch->pm_level > 0)
2372 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2379 ahciaction(struct cam_sim *sim, union ccb *ccb)
2382 struct ahci_channel *ch;
2384 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2385 ccb->ccb_h.func_code));
2387 ch = (struct ahci_channel *)cam_sim_softc(sim);
2389 switch (ccb->ccb_h.func_code) {
2390 /* Common cases first */
2391 case XPT_ATA_IO: /* Execute the requested I/O operation */
2393 if (ch->devices == 0) {
2394 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2398 /* Check for command collision. */
2399 if (ahci_check_collision(dev, ccb)) {
2400 /* Freeze command. */
2402 /* We have only one frozen slot, so freeze simq also. */
2403 xpt_freeze_simq(ch->sim, 1);
2406 ahci_begin_transaction(dev, ccb);
2408 case XPT_EN_LUN: /* Enable LUN as a target */
2409 case XPT_TARGET_IO: /* Execute target I/O request */
2410 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2411 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2412 case XPT_ABORT: /* Abort the specified CCB */
2414 ccb->ccb_h.status = CAM_REQ_INVALID;
2417 case XPT_SET_TRAN_SETTINGS:
2419 struct ccb_trans_settings *cts = &ccb->cts;
2420 struct ahci_device *d;
2422 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2423 d = &ch->curr[ccb->ccb_h.target_id];
2425 d = &ch->user[ccb->ccb_h.target_id];
2426 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2427 d->revision = cts->xport_specific.sata.revision;
2428 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2429 d->mode = cts->xport_specific.sata.mode;
2430 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2431 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2432 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2433 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2434 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2435 ch->pm_present = cts->xport_specific.sata.pm_present;
2436 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2437 d->atapi = cts->xport_specific.sata.atapi;
2438 ccb->ccb_h.status = CAM_REQ_CMP;
2442 case XPT_GET_TRAN_SETTINGS:
2443 /* Get default/user set transfer settings for the target */
2445 struct ccb_trans_settings *cts = &ccb->cts;
2446 struct ahci_device *d;
2449 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2450 d = &ch->curr[ccb->ccb_h.target_id];
2452 d = &ch->user[ccb->ccb_h.target_id];
2453 cts->protocol = PROTO_ATA;
2454 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2455 cts->transport = XPORT_SATA;
2456 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2457 cts->proto_specific.valid = 0;
2458 cts->xport_specific.sata.valid = 0;
2459 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2460 (ccb->ccb_h.target_id == 15 ||
2461 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2462 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2463 if (status & 0x0f0) {
2464 cts->xport_specific.sata.revision =
2465 (status & 0x0f0) >> 4;
2466 cts->xport_specific.sata.valid |=
2467 CTS_SATA_VALID_REVISION;
2470 cts->xport_specific.sata.revision = d->revision;
2471 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2473 cts->xport_specific.sata.mode = d->mode;
2474 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2475 cts->xport_specific.sata.bytecount = d->bytecount;
2476 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2477 cts->xport_specific.sata.pm_present = ch->pm_present;
2478 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2479 cts->xport_specific.sata.tags = d->tags;
2480 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2481 cts->xport_specific.sata.atapi = d->atapi;
2482 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2483 ccb->ccb_h.status = CAM_REQ_CMP;
2488 case XPT_CALC_GEOMETRY:
2490 struct ccb_calc_geometry *ccg;
2492 uint32_t secs_per_cylinder;
2495 size_mb = ccg->volume_size
2496 / ((1024L * 1024L) / ccg->block_size);
2497 if (size_mb >= 1024 && (aha->extended_trans != 0)) {
2498 if (size_mb >= 2048) {
2500 ccg->secs_per_track = 63;
2503 ccg->secs_per_track = 32;
2507 ccg->secs_per_track = 32;
2509 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
2510 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
2511 ccb->ccb_h.status = CAM_REQ_CMP;
2516 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2517 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2519 ccb->ccb_h.status = CAM_REQ_CMP;
2522 case XPT_TERM_IO: /* Terminate the I/O process */
2524 ccb->ccb_h.status = CAM_REQ_INVALID;
2527 case XPT_PATH_INQ: /* Path routing inquiry */
2529 struct ccb_pathinq *cpi = &ccb->cpi;
2531 cpi->version_num = 1; /* XXX??? */
2532 cpi->hba_inquiry = PI_SDTR_ABLE;
2533 if (ch->caps & AHCI_CAP_SNCQ)
2534 cpi->hba_inquiry |= PI_TAG_ABLE;
2535 if (ch->caps & AHCI_CAP_SPM)
2536 cpi->hba_inquiry |= PI_SATAPM;
2537 cpi->target_sprt = 0;
2538 cpi->hba_misc = PIM_SEQSCAN;
2539 cpi->hba_eng_cnt = 0;
2540 if (ch->caps & AHCI_CAP_SPM)
2541 cpi->max_target = 15;
2543 cpi->max_target = 0;
2545 cpi->initiator_id = 0;
2546 cpi->bus_id = cam_sim_bus(sim);
2547 cpi->base_transfer_speed = 150000;
2548 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2549 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2550 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2551 cpi->unit_number = cam_sim_unit(sim);
2552 cpi->transport = XPORT_SATA;
2553 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2554 cpi->protocol = PROTO_ATA;
2555 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2556 cpi->maxio = MAXPHYS;
2557 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2558 if (pci_get_devid(device_get_parent(dev)) == 0x43801002)
2559 cpi->maxio = min(cpi->maxio, 128 * 512);
2560 cpi->ccb_h.status = CAM_REQ_CMP;
2565 ccb->ccb_h.status = CAM_REQ_INVALID;
2572 ahcipoll(struct cam_sim *sim)
2574 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
2576 ahci_ch_intr(ch->dev);