2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/led/led.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
54 #include <cam/cam_ccb.h>
55 #include <cam/cam_sim.h>
56 #include <cam/cam_xpt_sim.h>
57 #include <cam/cam_debug.h>
59 /* local prototypes */
60 static int ahci_setup_interrupt(device_t dev);
61 static void ahci_intr(void *data);
62 static void ahci_intr_one(void *data);
63 static int ahci_suspend(device_t dev);
64 static int ahci_resume(device_t dev);
65 static int ahci_ch_init(device_t dev);
66 static int ahci_ch_deinit(device_t dev);
67 static int ahci_ch_suspend(device_t dev);
68 static int ahci_ch_resume(device_t dev);
69 static void ahci_ch_pm(void *arg);
70 static void ahci_ch_intr_locked(void *data);
71 static void ahci_ch_intr(void *data);
72 static void ahci_ch_led(void *priv, int onoff);
73 static int ahci_ctlr_reset(device_t dev);
74 static int ahci_ctlr_setup(device_t dev);
75 static void ahci_begin_transaction(device_t dev, union ccb *ccb);
76 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
77 static void ahci_execute_transaction(struct ahci_slot *slot);
78 static void ahci_timeout(struct ahci_slot *slot);
79 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
80 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
81 static void ahci_dmainit(device_t dev);
82 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
83 static void ahci_dmafini(device_t dev);
84 static void ahci_slotsalloc(device_t dev);
85 static void ahci_slotsfree(device_t dev);
86 static void ahci_reset(device_t dev);
87 static void ahci_start(device_t dev, int fbs);
88 static void ahci_stop(device_t dev);
89 static void ahci_clo(device_t dev);
90 static void ahci_start_fr(device_t dev);
91 static void ahci_stop_fr(device_t dev);
93 static int ahci_sata_connect(struct ahci_channel *ch);
94 static int ahci_sata_phy_reset(device_t dev);
95 static int ahci_wait_ready(device_t dev, int t, int t0);
97 static void ahci_issue_recovery(device_t dev);
98 static void ahci_process_read_log(device_t dev, union ccb *ccb);
99 static void ahci_process_request_sense(device_t dev, union ccb *ccb);
101 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
102 static void ahcipoll(struct cam_sim *sim);
104 MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
111 #define AHCI_Q_NOFORCE 1
112 #define AHCI_Q_NOPMP 2
113 #define AHCI_Q_NONCQ 4
115 #define AHCI_Q_2CH 16
116 #define AHCI_Q_4CH 32
117 #define AHCI_Q_EDGEIS 64
118 #define AHCI_Q_SATA2 128
119 #define AHCI_Q_NOBSYRES 256
120 #define AHCI_Q_NOAA 512
121 #define AHCI_Q_NOCOUNT 1024
122 #define AHCI_Q_ALTSIG 2048
124 {0x43801002, 0x00, "ATI IXP600", 0},
125 {0x43901002, 0x00, "ATI IXP700", 0},
126 {0x43911002, 0x00, "ATI IXP700", 0},
127 {0x43921002, 0x00, "ATI IXP700", 0},
128 {0x43931002, 0x00, "ATI IXP700", 0},
129 {0x43941002, 0x00, "ATI IXP800", 0},
130 {0x43951002, 0x00, "ATI IXP800", 0},
131 {0x06121b21, 0x00, "ASMedia ASM1061", 0},
132 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE},
133 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE},
134 {0x26818086, 0x00, "Intel ESB2", 0},
135 {0x26828086, 0x00, "Intel ESB2", 0},
136 {0x26838086, 0x00, "Intel ESB2", 0},
137 {0x27c18086, 0x00, "Intel ICH7", 0},
138 {0x27c38086, 0x00, "Intel ICH7", 0},
139 {0x27c58086, 0x00, "Intel ICH7M", 0},
140 {0x27c68086, 0x00, "Intel ICH7M", 0},
141 {0x28218086, 0x00, "Intel ICH8", 0},
142 {0x28228086, 0x00, "Intel ICH8", 0},
143 {0x28248086, 0x00, "Intel ICH8", 0},
144 {0x28298086, 0x00, "Intel ICH8M", 0},
145 {0x282a8086, 0x00, "Intel ICH8M", 0},
146 {0x29228086, 0x00, "Intel ICH9", 0},
147 {0x29238086, 0x00, "Intel ICH9", 0},
148 {0x29248086, 0x00, "Intel ICH9", 0},
149 {0x29258086, 0x00, "Intel ICH9", 0},
150 {0x29278086, 0x00, "Intel ICH9", 0},
151 {0x29298086, 0x00, "Intel ICH9M", 0},
152 {0x292a8086, 0x00, "Intel ICH9M", 0},
153 {0x292b8086, 0x00, "Intel ICH9M", 0},
154 {0x292c8086, 0x00, "Intel ICH9M", 0},
155 {0x292f8086, 0x00, "Intel ICH9M", 0},
156 {0x294d8086, 0x00, "Intel ICH9", 0},
157 {0x294e8086, 0x00, "Intel ICH9M", 0},
158 {0x3a058086, 0x00, "Intel ICH10", 0},
159 {0x3a228086, 0x00, "Intel ICH10", 0},
160 {0x3a258086, 0x00, "Intel ICH10", 0},
161 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0},
162 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0},
163 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0},
164 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0},
165 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0},
166 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0},
167 {0x1c028086, 0x00, "Intel Cougar Point", 0},
168 {0x1c038086, 0x00, "Intel Cougar Point", 0},
169 {0x1c048086, 0x00, "Intel Cougar Point", 0},
170 {0x1c058086, 0x00, "Intel Cougar Point", 0},
171 {0x1d028086, 0x00, "Intel Patsburg", 0},
172 {0x1d048086, 0x00, "Intel Patsburg", 0},
173 {0x1d068086, 0x00, "Intel Patsburg", 0},
174 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0},
175 {0x1e028086, 0x00, "Intel Panther Point", 0},
176 {0x1e038086, 0x00, "Intel Panther Point", 0},
177 {0x1e048086, 0x00, "Intel Panther Point", 0},
178 {0x1e058086, 0x00, "Intel Panther Point", 0},
179 {0x1e068086, 0x00, "Intel Panther Point", 0},
180 {0x1e078086, 0x00, "Intel Panther Point", 0},
181 {0x1e0e8086, 0x00, "Intel Panther Point", 0},
182 {0x1e0f8086, 0x00, "Intel Panther Point", 0},
183 {0x23238086, 0x00, "Intel DH89xxCC", 0},
184 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE},
185 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE},
186 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE},
187 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE},
188 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE},
189 {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE | AHCI_Q_1CH |
191 {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE | AHCI_Q_2CH |
192 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
193 {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE | AHCI_Q_4CH |
194 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
195 {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE | AHCI_Q_4CH |
196 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
197 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES},
198 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
199 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES},
200 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES},
201 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
202 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES},
203 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES},
204 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
205 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
206 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
207 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
208 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES},
209 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES},
210 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES},
211 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES},
212 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
213 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
214 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
215 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
216 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
217 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
218 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
219 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
220 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
221 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
222 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
223 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
224 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
225 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
226 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
227 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
228 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
229 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
230 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
231 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
232 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
233 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
234 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
235 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
236 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
237 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
238 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
239 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
240 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
241 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
242 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
243 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
244 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
245 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
246 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
247 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
248 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
249 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
250 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
251 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
252 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
253 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
254 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
255 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
256 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
257 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
258 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
259 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
260 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
261 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
262 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
263 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
264 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
265 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
266 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
267 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
268 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
269 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
270 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA},
271 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
272 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
273 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
274 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
275 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
276 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
277 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
278 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
279 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
280 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
281 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
282 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
283 {0x11841039, 0x00, "SiS 966", 0},
284 {0x11851039, 0x00, "SiS 968", 0},
285 {0x01861039, 0x00, "SiS 968", 0},
286 {0x00000000, 0x00, NULL, 0}
289 #define recovery_type spriv_field0
290 #define RECOVERY_NONE 0
291 #define RECOVERY_READ_LOG 1
292 #define RECOVERY_REQUEST_SENSE 2
293 #define recovery_slot spriv_field1
295 static int force_ahci = 1;
296 TUNABLE_INT("hw.ahci.force", &force_ahci);
299 ahci_probe(device_t dev)
303 uint32_t devid = pci_get_devid(dev);
304 uint8_t revid = pci_get_revid(dev);
306 /* Is this a possible AHCI candidate? */
307 if (pci_get_class(dev) == PCIC_STORAGE &&
308 pci_get_subclass(dev) == PCIS_STORAGE_SATA &&
309 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0)
311 /* Is this a known AHCI chip? */
312 for (i = 0; ahci_ids[i].id != 0; i++) {
313 if (ahci_ids[i].id == devid &&
314 ahci_ids[i].rev <= revid &&
315 (valid || (force_ahci == 1 &&
316 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) {
317 /* Do not attach JMicrons with single PCI function. */
318 if (pci_get_vendor(dev) == 0x197b &&
319 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
321 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
323 device_set_desc_copy(dev, buf);
324 return (BUS_PROBE_VENDOR);
329 device_set_desc_copy(dev, "AHCI SATA controller");
330 return (BUS_PROBE_VENDOR);
334 ahci_ata_probe(device_t dev)
338 uint32_t devid = pci_get_devid(dev);
339 uint8_t revid = pci_get_revid(dev);
341 if ((intptr_t)device_get_ivars(dev) >= 0)
343 /* Is this a known AHCI chip? */
344 for (i = 0; ahci_ids[i].id != 0; i++) {
345 if (ahci_ids[i].id == devid &&
346 ahci_ids[i].rev <= revid) {
347 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
349 device_set_desc_copy(dev, buf);
350 return (BUS_PROBE_VENDOR);
353 device_set_desc_copy(dev, "AHCI SATA controller");
354 return (BUS_PROBE_VENDOR);
358 ahci_attach(device_t dev)
360 struct ahci_controller *ctlr = device_get_softc(dev);
362 int error, unit, speed, i;
363 uint32_t devid = pci_get_devid(dev);
364 uint8_t revid = pci_get_revid(dev);
369 while (ahci_ids[i].id != 0 &&
370 (ahci_ids[i].id != devid ||
371 ahci_ids[i].rev > revid))
373 ctlr->quirks = ahci_ids[i].quirks;
374 resource_int_value(device_get_name(dev),
375 device_get_unit(dev), "ccc", &ctlr->ccc);
376 /* if we have a memory BAR(5) we are likely on an AHCI part */
377 ctlr->r_rid = PCIR_BAR(5);
378 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
379 &ctlr->r_rid, RF_ACTIVE)))
381 /* Setup our own memory management for channels. */
382 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
383 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
384 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
385 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
386 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
387 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
390 if ((error = rman_manage_region(&ctlr->sc_iomem,
391 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
392 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
393 rman_fini(&ctlr->sc_iomem);
396 pci_enable_busmaster(dev);
397 /* Reset controller */
398 if ((error = ahci_ctlr_reset(dev)) != 0) {
399 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
400 rman_fini(&ctlr->sc_iomem);
403 /* Get the HW capabilities */
404 version = ATA_INL(ctlr->r_mem, AHCI_VS);
405 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
406 if (version >= 0x00010020)
407 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
408 if (ctlr->caps & AHCI_CAP_EMS)
409 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
410 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
412 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */
413 if ((ctlr->quirks & AHCI_Q_NOBSYRES) &&
414 (ctlr->quirks & AHCI_Q_ALTSIG) &&
415 (ctlr->caps & AHCI_CAP_SPM) == 0)
416 ctlr->quirks &= ~AHCI_Q_NOBSYRES;
418 if (ctlr->quirks & AHCI_Q_1CH) {
419 ctlr->caps &= ~AHCI_CAP_NPMASK;
420 ctlr->ichannels &= 0x01;
422 if (ctlr->quirks & AHCI_Q_2CH) {
423 ctlr->caps &= ~AHCI_CAP_NPMASK;
425 ctlr->ichannels &= 0x03;
427 if (ctlr->quirks & AHCI_Q_4CH) {
428 ctlr->caps &= ~AHCI_CAP_NPMASK;
430 ctlr->ichannels &= 0x0f;
432 ctlr->channels = MAX(flsl(ctlr->ichannels),
433 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
434 if (ctlr->quirks & AHCI_Q_NOPMP)
435 ctlr->caps &= ~AHCI_CAP_SPM;
436 if (ctlr->quirks & AHCI_Q_NONCQ)
437 ctlr->caps &= ~AHCI_CAP_SNCQ;
438 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
440 mtx_init(&ctlr->em_mtx, "AHCI EM lock", NULL, MTX_DEF);
441 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
442 ahci_ctlr_setup(dev);
443 /* Setup interrupts. */
444 if (ahci_setup_interrupt(dev)) {
445 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
446 rman_fini(&ctlr->sc_iomem);
449 /* Announce HW capabilities. */
450 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
452 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
453 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
454 ((version >> 4) & 0xf0) + (version & 0x0f),
455 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
456 ((speed == 1) ? "1.5":((speed == 2) ? "3":
457 ((speed == 3) ? "6":"?"))),
458 (ctlr->caps & AHCI_CAP_SPM) ?
459 "supported" : "not supported",
460 (ctlr->caps & AHCI_CAP_FBSS) ?
463 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
464 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
465 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
466 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
467 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
468 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
469 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
470 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
471 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
472 ((speed == 1) ? "1.5":((speed == 2) ? "3":
473 ((speed == 3) ? "6":"?"))));
474 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
475 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
476 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
477 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
478 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
479 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
480 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
481 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
482 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
483 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
484 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
485 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
487 if (bootverbose && version >= 0x00010020) {
488 device_printf(dev, "Caps2:%s%s%s\n",
489 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
490 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
491 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
493 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) {
494 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n",
495 (ctlr->capsem & AHCI_EM_PM) ? " PM":"",
496 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"",
497 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"",
498 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"",
499 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"",
500 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"",
501 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"",
502 (ctlr->capsem & AHCI_EM_LED) ? " LED":"");
504 /* Attach all channels on this controller */
505 for (unit = 0; unit < ctlr->channels; unit++) {
506 child = device_add_child(dev, "ahcich", -1);
508 device_printf(dev, "failed to add channel device\n");
511 device_set_ivars(child, (void *)(intptr_t)unit);
512 if ((ctlr->ichannels & (1 << unit)) == 0)
513 device_disable(child);
515 bus_generic_attach(dev);
520 ahci_detach(device_t dev)
522 struct ahci_controller *ctlr = device_get_softc(dev);
525 /* Detach & delete all children */
526 device_delete_children(dev);
528 /* Free interrupts. */
529 for (i = 0; i < ctlr->numirqs; i++) {
530 if (ctlr->irqs[i].r_irq) {
531 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
532 ctlr->irqs[i].handle);
533 bus_release_resource(dev, SYS_RES_IRQ,
534 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
537 pci_release_msi(dev);
539 rman_fini(&ctlr->sc_iomem);
541 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
542 mtx_destroy(&ctlr->em_mtx);
547 ahci_ctlr_reset(device_t dev)
549 struct ahci_controller *ctlr = device_get_softc(dev);
552 if (pci_read_config(dev, 0x00, 4) == 0x28298086 &&
553 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
554 pci_write_config(dev, 0x92, 0x01, 1);
555 /* Enable AHCI mode */
556 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
557 /* Reset AHCI controller */
558 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
559 for (timeout = 1000; timeout > 0; timeout--) {
561 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
565 device_printf(dev, "AHCI controller reset failure\n");
568 /* Reenable AHCI mode */
569 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
574 ahci_ctlr_setup(device_t dev)
576 struct ahci_controller *ctlr = device_get_softc(dev);
577 /* Clear interrupts */
578 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
581 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
582 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
583 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
584 (4 << AHCI_CCCC_CC_SHIFT) |
586 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
587 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
590 "CCC with %dms/4cmd enabled on vector %d\n",
591 ctlr->ccc, ctlr->cccv);
594 /* Enable AHCI interrupts */
595 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
596 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
601 ahci_suspend(device_t dev)
603 struct ahci_controller *ctlr = device_get_softc(dev);
605 bus_generic_suspend(dev);
606 /* Disable interupts, so the state change(s) doesn't trigger */
607 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
608 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
613 ahci_resume(device_t dev)
617 if ((res = ahci_ctlr_reset(dev)) != 0)
619 ahci_ctlr_setup(dev);
620 return (bus_generic_resume(dev));
624 ahci_setup_interrupt(device_t dev)
626 struct ahci_controller *ctlr = device_get_softc(dev);
630 resource_int_value(device_get_name(dev),
631 device_get_unit(dev), "msi", &msi);
635 msi = min(1, pci_msi_count(dev));
637 msi = pci_msi_count(dev);
638 /* Allocate MSI if needed/present. */
639 if (msi && pci_alloc_msi(dev, &msi) == 0) {
645 /* Check for single MSI vector fallback. */
646 if (ctlr->numirqs > 1 &&
647 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
648 device_printf(dev, "Falling back to one MSI\n");
651 /* Allocate all IRQs. */
652 for (i = 0; i < ctlr->numirqs; i++) {
653 ctlr->irqs[i].ctlr = ctlr;
654 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0);
655 if (ctlr->numirqs == 1 || i >= ctlr->channels ||
656 (ctlr->ccc && i == ctlr->cccv))
657 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
658 else if (i == ctlr->numirqs - 1)
659 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
661 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
662 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
663 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
664 device_printf(dev, "unable to map interrupt\n");
667 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
668 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr,
669 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
670 /* SOS XXX release r_irq */
671 device_printf(dev, "unable to setup interrupt\n");
674 if (ctlr->numirqs > 1) {
675 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
676 ctlr->irqs[i].handle,
677 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
685 * Common case interrupt handler.
688 ahci_intr(void *data)
690 struct ahci_controller_irq *irq = data;
691 struct ahci_controller *ctlr = irq->ctlr;
692 u_int32_t is, ise = 0;
696 if (irq->mode == AHCI_IRQ_MODE_ALL) {
699 is = ctlr->ichannels;
701 is = ATA_INL(ctlr->r_mem, AHCI_IS);
702 } else { /* AHCI_IRQ_MODE_AFTER */
703 unit = irq->r_irq_rid - 1;
704 is = ATA_INL(ctlr->r_mem, AHCI_IS);
706 /* CCC interrupt is edge triggered. */
708 ise = 1 << ctlr->cccv;
709 /* Some controllers have edge triggered IS. */
710 if (ctlr->quirks & AHCI_Q_EDGEIS)
713 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
714 for (; unit < ctlr->channels; unit++) {
715 if ((is & (1 << unit)) != 0 &&
716 (arg = ctlr->interrupt[unit].argument)) {
717 ctlr->interrupt[unit].function(arg);
720 /* AHCI declares level triggered IS. */
721 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
722 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
726 * Simplified interrupt handler for multivector MSI mode.
729 ahci_intr_one(void *data)
731 struct ahci_controller_irq *irq = data;
732 struct ahci_controller *ctlr = irq->ctlr;
736 unit = irq->r_irq_rid - 1;
737 /* Some controllers have edge triggered IS. */
738 if (ctlr->quirks & AHCI_Q_EDGEIS)
739 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
740 if ((arg = ctlr->interrupt[unit].argument))
741 ctlr->interrupt[unit].function(arg);
742 /* AHCI declares level triggered IS. */
743 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
744 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
747 static struct resource *
748 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
749 u_long start, u_long end, u_long count, u_int flags)
751 struct ahci_controller *ctlr = device_get_softc(dev);
752 int unit = ((struct ahci_channel *)device_get_softc(child))->unit;
753 struct resource *res = NULL;
754 int offset = AHCI_OFFSET + (unit << 7);
759 st = rman_get_start(ctlr->r_mem);
760 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
761 st + offset + 127, 128, RF_ACTIVE, child);
763 bus_space_handle_t bsh;
765 bsh = rman_get_bushandle(ctlr->r_mem);
766 bst = rman_get_bustag(ctlr->r_mem);
767 bus_space_subregion(bst, bsh, offset, 128, &bsh);
768 rman_set_bushandle(res, bsh);
769 rman_set_bustag(res, bst);
773 if (*rid == ATA_IRQ_RID)
774 res = ctlr->irqs[0].r_irq;
781 ahci_release_resource(device_t dev, device_t child, int type, int rid,
787 rman_release_resource(r);
790 if (rid != ATA_IRQ_RID)
798 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
799 int flags, driver_filter_t *filter, driver_intr_t *function,
800 void *argument, void **cookiep)
802 struct ahci_controller *ctlr = device_get_softc(dev);
803 int unit = (intptr_t)device_get_ivars(child);
805 if (filter != NULL) {
806 printf("ahci.c: we cannot use a filter here\n");
809 ctlr->interrupt[unit].function = function;
810 ctlr->interrupt[unit].argument = argument;
815 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
818 struct ahci_controller *ctlr = device_get_softc(dev);
819 int unit = (intptr_t)device_get_ivars(child);
821 ctlr->interrupt[unit].function = NULL;
822 ctlr->interrupt[unit].argument = NULL;
827 ahci_print_child(device_t dev, device_t child)
831 retval = bus_print_child_header(dev, child);
832 retval += printf(" at channel %d",
833 (int)(intptr_t)device_get_ivars(child));
834 retval += bus_print_child_footer(dev, child);
840 ahci_child_location_str(device_t dev, device_t child, char *buf,
844 snprintf(buf, buflen, "channel=%d",
845 (int)(intptr_t)device_get_ivars(child));
849 devclass_t ahci_devclass;
850 static device_method_t ahci_methods[] = {
851 DEVMETHOD(device_probe, ahci_probe),
852 DEVMETHOD(device_attach, ahci_attach),
853 DEVMETHOD(device_detach, ahci_detach),
854 DEVMETHOD(device_suspend, ahci_suspend),
855 DEVMETHOD(device_resume, ahci_resume),
856 DEVMETHOD(bus_print_child, ahci_print_child),
857 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
858 DEVMETHOD(bus_release_resource, ahci_release_resource),
859 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
860 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
861 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
864 static driver_t ahci_driver = {
867 sizeof(struct ahci_controller)
869 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0);
870 static device_method_t ahci_ata_methods[] = {
871 DEVMETHOD(device_probe, ahci_ata_probe),
872 DEVMETHOD(device_attach, ahci_attach),
873 DEVMETHOD(device_detach, ahci_detach),
874 DEVMETHOD(device_suspend, ahci_suspend),
875 DEVMETHOD(device_resume, ahci_resume),
876 DEVMETHOD(bus_print_child, ahci_print_child),
877 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
878 DEVMETHOD(bus_release_resource, ahci_release_resource),
879 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
880 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
881 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
884 static driver_t ahci_ata_driver = {
887 sizeof(struct ahci_controller)
889 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0);
890 MODULE_VERSION(ahci, 1);
891 MODULE_DEPEND(ahci, cam, 1, 1, 1);
894 ahci_ch_probe(device_t dev)
897 device_set_desc_copy(dev, "AHCI channel");
902 ahci_ch_attach(device_t dev)
904 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
905 struct ahci_channel *ch = device_get_softc(dev);
906 struct cam_devq *devq;
907 int rid, error, i, sata_rev = 0;
912 ch->unit = (intptr_t)device_get_ivars(dev);
913 ch->caps = ctlr->caps;
914 ch->caps2 = ctlr->caps2;
915 ch->quirks = ctlr->quirks;
916 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
917 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
918 resource_int_value(device_get_name(dev),
919 device_get_unit(dev), "pm_level", &ch->pm_level);
920 if (ch->pm_level > 3)
921 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
922 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
923 /* Limit speed for my onboard JMicron external port.
924 * It is not eSATA really. */
925 if (pci_get_devid(ctlr->dev) == 0x2363197b &&
926 pci_get_subvendor(ctlr->dev) == 0x1043 &&
927 pci_get_subdevice(ctlr->dev) == 0x81e4 &&
930 if (ch->quirks & AHCI_Q_SATA2)
932 resource_int_value(device_get_name(dev),
933 device_get_unit(dev), "sata_rev", &sata_rev);
934 for (i = 0; i < 16; i++) {
935 ch->user[i].revision = sata_rev;
936 ch->user[i].mode = 0;
937 ch->user[i].bytecount = 8192;
938 ch->user[i].tags = ch->numslots;
939 ch->user[i].caps = 0;
940 ch->curr[i] = ch->user[i];
942 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
943 CTS_SATA_CAPS_H_APST |
944 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
946 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
950 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
954 ahci_slotsalloc(dev);
958 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
959 &rid, RF_SHAREABLE | RF_ACTIVE))) {
960 device_printf(dev, "Unable to map interrupt\n");
964 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
965 ahci_ch_intr_locked, dev, &ch->ih))) {
966 device_printf(dev, "Unable to setup interrupt\n");
970 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
971 version = ATA_INL(ctlr->r_mem, AHCI_VS);
972 if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS))
973 ch->chcaps |= AHCI_P_CMD_FBSCP;
975 device_printf(dev, "Caps:%s%s%s%s%s\n",
976 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
977 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
978 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
979 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
980 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"");
982 /* Create the device queue for our SIM. */
983 devq = cam_simq_alloc(ch->numslots);
985 device_printf(dev, "Unable to allocate simq\n");
989 /* Construct SIM entry */
990 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
991 device_get_unit(dev), &ch->mtx,
992 min(2, ch->numslots),
993 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
995 if (ch->sim == NULL) {
997 device_printf(dev, "unable to allocate sim\n");
1001 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
1002 device_printf(dev, "unable to register xpt bus\n");
1006 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
1007 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1008 device_printf(dev, "unable to create path\n");
1012 if (ch->pm_level > 3) {
1013 callout_reset(&ch->pm_timer,
1014 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
1017 mtx_unlock(&ch->mtx);
1018 if ((ch->caps & AHCI_CAP_EMS) &&
1019 (ctlr->capsem & AHCI_EM_LED)) {
1020 for (i = 0; i < AHCI_NUM_LEDS; i++) {
1021 ch->leds[i].dev = dev;
1022 ch->leds[i].num = i;
1024 if ((ctlr->capsem & AHCI_EM_ALHD) == 0) {
1025 snprintf(buf, sizeof(buf), "%s.act",
1026 device_get_nameunit(dev));
1027 ch->leds[0].led = led_create(ahci_ch_led,
1030 snprintf(buf, sizeof(buf), "%s.locate",
1031 device_get_nameunit(dev));
1032 ch->leds[1].led = led_create(ahci_ch_led, &ch->leds[1], buf);
1033 snprintf(buf, sizeof(buf), "%s.fault",
1034 device_get_nameunit(dev));
1035 ch->leds[2].led = led_create(ahci_ch_led, &ch->leds[2], buf);
1040 xpt_bus_deregister(cam_sim_path(ch->sim));
1042 cam_sim_free(ch->sim, /*free_devq*/TRUE);
1044 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
1046 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
1047 mtx_unlock(&ch->mtx);
1048 mtx_destroy(&ch->mtx);
1053 ahci_ch_detach(device_t dev)
1055 struct ahci_channel *ch = device_get_softc(dev);
1058 for (i = 0; i < AHCI_NUM_LEDS; i++) {
1059 if (ch->leds[i].led)
1060 led_destroy(ch->leds[i].led);
1063 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
1064 /* Forget about reset. */
1065 if (ch->resetting) {
1067 xpt_release_simq(ch->sim, TRUE);
1069 xpt_free_path(ch->path);
1070 xpt_bus_deregister(cam_sim_path(ch->sim));
1071 cam_sim_free(ch->sim, /*free_devq*/TRUE);
1072 mtx_unlock(&ch->mtx);
1074 if (ch->pm_level > 3)
1075 callout_drain(&ch->pm_timer);
1076 callout_drain(&ch->reset_timer);
1077 bus_teardown_intr(dev, ch->r_irq, ch->ih);
1078 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
1080 ahci_ch_deinit(dev);
1081 ahci_slotsfree(dev);
1084 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
1085 mtx_destroy(&ch->mtx);
1090 ahci_ch_init(device_t dev)
1092 struct ahci_channel *ch = device_get_softc(dev);
1095 /* Disable port interrupts */
1096 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1097 /* Setup work areas */
1098 work = ch->dma.work_bus + AHCI_CL_OFFSET;
1099 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
1100 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
1101 work = ch->dma.rfis_bus;
1102 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
1103 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
1104 /* Activate the channel and power/spin up device */
1105 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
1106 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1107 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
1108 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
1115 ahci_ch_deinit(device_t dev)
1117 struct ahci_channel *ch = device_get_softc(dev);
1119 /* Disable port interrupts. */
1120 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1121 /* Reset command register. */
1124 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
1125 /* Allow everything, including partial and slumber modes. */
1126 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
1127 /* Request slumber mode transition and give some time to get there. */
1128 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
1131 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
1136 ahci_ch_suspend(device_t dev)
1138 struct ahci_channel *ch = device_get_softc(dev);
1141 xpt_freeze_simq(ch->sim, 1);
1142 /* Forget about reset. */
1143 if (ch->resetting) {
1145 callout_stop(&ch->reset_timer);
1146 xpt_release_simq(ch->sim, TRUE);
1149 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
1150 ahci_ch_deinit(dev);
1151 mtx_unlock(&ch->mtx);
1156 ahci_ch_resume(device_t dev)
1158 struct ahci_channel *ch = device_get_softc(dev);
1163 xpt_release_simq(ch->sim, TRUE);
1164 mtx_unlock(&ch->mtx);
1168 devclass_t ahcich_devclass;
1169 static device_method_t ahcich_methods[] = {
1170 DEVMETHOD(device_probe, ahci_ch_probe),
1171 DEVMETHOD(device_attach, ahci_ch_attach),
1172 DEVMETHOD(device_detach, ahci_ch_detach),
1173 DEVMETHOD(device_suspend, ahci_ch_suspend),
1174 DEVMETHOD(device_resume, ahci_ch_resume),
1177 static driver_t ahcich_driver = {
1180 sizeof(struct ahci_channel)
1182 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0);
1185 ahci_ch_setleds(device_t dev)
1187 struct ahci_channel *ch;
1188 struct ahci_controller *ctlr;
1193 ctlr = device_get_softc(device_get_parent(dev));
1194 ch = device_get_softc(dev);
1197 for (i = 0; i < AHCI_NUM_LEDS; i++)
1198 val |= ch->leds[i].state << (i * 3);
1200 buf = (ctlr->emloc & 0xffff0000) >> 14;
1201 mtx_lock(&ctlr->em_mtx);
1203 while (ATA_INL(ctlr->r_mem, AHCI_EM_CTL) & (AHCI_EM_TM | AHCI_EM_RST) &&
1207 device_printf(dev, "EM timeout\n");
1208 ATA_OUTL(ctlr->r_mem, buf, (1 << 8) | (0 << 16) | (0 << 24));
1209 ATA_OUTL(ctlr->r_mem, buf + 4, ch->unit | (val << 16));
1210 ATA_OUTL(ctlr->r_mem, AHCI_EM_CTL, AHCI_EM_TM);
1211 mtx_unlock(&ctlr->em_mtx);
1215 ahci_ch_led(void *priv, int onoff)
1217 struct ahci_led *led;
1219 led = (struct ahci_led *)priv;
1222 ahci_ch_setleds(led->dev);
1225 struct ahci_dc_cb_args {
1231 ahci_dmainit(device_t dev)
1233 struct ahci_channel *ch = device_get_softc(dev);
1234 struct ahci_dc_cb_args dcba;
1237 if (ch->caps & AHCI_CAP_64BIT)
1238 ch->dma.max_address = BUS_SPACE_MAXADDR;
1240 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT;
1242 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
1243 ch->dma.max_address, BUS_SPACE_MAXADDR,
1244 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
1245 0, NULL, NULL, &ch->dma.work_tag))
1247 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0,
1250 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1251 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1252 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1255 ch->dma.work_bus = dcba.maddr;
1256 /* FIS receive area. */
1257 if (ch->chcaps & AHCI_P_CMD_FBSCP)
1261 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
1262 ch->dma.max_address, BUS_SPACE_MAXADDR,
1263 NULL, NULL, rfsize, 1, rfsize,
1264 0, NULL, NULL, &ch->dma.rfis_tag))
1266 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1269 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1270 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1271 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1274 ch->dma.rfis_bus = dcba.maddr;
1276 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
1277 ch->dma.max_address, BUS_SPACE_MAXADDR,
1279 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
1280 AHCI_SG_ENTRIES, AHCI_PRD_MAX,
1281 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
1287 device_printf(dev, "WARNING - DMA initialization failed\n");
1292 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1294 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
1296 if (!(dcba->error = error))
1297 dcba->maddr = segs[0].ds_addr;
1301 ahci_dmafini(device_t dev)
1303 struct ahci_channel *ch = device_get_softc(dev);
1305 if (ch->dma.data_tag) {
1306 bus_dma_tag_destroy(ch->dma.data_tag);
1307 ch->dma.data_tag = NULL;
1309 if (ch->dma.rfis_bus) {
1310 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1311 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1312 ch->dma.rfis_bus = 0;
1313 ch->dma.rfis_map = NULL;
1314 ch->dma.rfis = NULL;
1316 if (ch->dma.work_bus) {
1317 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1318 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1319 ch->dma.work_bus = 0;
1320 ch->dma.work_map = NULL;
1321 ch->dma.work = NULL;
1323 if (ch->dma.work_tag) {
1324 bus_dma_tag_destroy(ch->dma.work_tag);
1325 ch->dma.work_tag = NULL;
1330 ahci_slotsalloc(device_t dev)
1332 struct ahci_channel *ch = device_get_softc(dev);
1335 /* Alloc and setup command/dma slots */
1336 bzero(ch->slot, sizeof(ch->slot));
1337 for (i = 0; i < ch->numslots; i++) {
1338 struct ahci_slot *slot = &ch->slot[i];
1342 slot->state = AHCI_SLOT_EMPTY;
1344 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1346 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1347 device_printf(ch->dev, "FAILURE - create data_map\n");
1352 ahci_slotsfree(device_t dev)
1354 struct ahci_channel *ch = device_get_softc(dev);
1357 /* Free all dma slots */
1358 for (i = 0; i < ch->numslots; i++) {
1359 struct ahci_slot *slot = &ch->slot[i];
1361 callout_drain(&slot->timeout);
1362 if (slot->dma.data_map) {
1363 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1364 slot->dma.data_map = NULL;
1370 ahci_phy_check_events(device_t dev, u_int32_t serr)
1372 struct ahci_channel *ch = device_get_softc(dev);
1374 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1375 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1376 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1380 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1381 device_printf(dev, "CONNECT requested\n");
1383 device_printf(dev, "DISCONNECT requested\n");
1386 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1388 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1389 cam_sim_path(ch->sim),
1390 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1401 ahci_cpd_check_events(device_t dev)
1403 struct ahci_channel *ch = device_get_softc(dev);
1407 if (ch->pm_level == 0)
1410 status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1411 if ((status & AHCI_P_CMD_CPD) == 0)
1415 if (status & AHCI_P_CMD_CPS) {
1416 device_printf(dev, "COLD CONNECT requested\n");
1418 device_printf(dev, "COLD DISCONNECT requested\n");
1421 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1423 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1424 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1432 ahci_notify_events(device_t dev, u_int32_t status)
1434 struct ahci_channel *ch = device_get_softc(dev);
1435 struct cam_path *dpath;
1438 if (ch->caps & AHCI_CAP_SSNTF)
1439 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1441 device_printf(dev, "SNTF 0x%04x\n", status);
1442 for (i = 0; i < 16; i++) {
1443 if ((status & (1 << i)) == 0)
1445 if (xpt_create_path(&dpath, NULL,
1446 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1447 xpt_async(AC_SCSI_AEN, dpath, NULL);
1448 xpt_free_path(dpath);
1454 ahci_ch_intr_locked(void *data)
1456 device_t dev = (device_t)data;
1457 struct ahci_channel *ch = device_get_softc(dev);
1461 mtx_unlock(&ch->mtx);
1465 ahci_ch_pm(void *arg)
1467 device_t dev = (device_t)arg;
1468 struct ahci_channel *ch = device_get_softc(dev);
1471 if (ch->numrslots != 0)
1473 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1474 if (ch->pm_level == 4)
1475 work |= AHCI_P_CMD_PARTIAL;
1477 work |= AHCI_P_CMD_SLUMBER;
1478 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1482 ahci_ch_intr(void *data)
1484 device_t dev = (device_t)data;
1485 struct ahci_channel *ch = device_get_softc(dev);
1486 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err;
1487 enum ahci_err_type et;
1488 int i, ccs, port, reset = 0;
1490 /* Read and clear interrupt statuses. */
1491 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1494 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1495 /* Read command statuses. */
1496 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1497 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI);
1498 if (istatus & AHCI_P_IX_SDB) {
1499 if (ch->caps & AHCI_CAP_SSNTF)
1500 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1501 else if (ch->fbs_enabled) {
1502 u_int8_t *fis = ch->dma.rfis + 0x58;
1504 for (i = 0; i < 16; i++) {
1505 if (fis[1] & 0x80) {
1512 u_int8_t *fis = ch->dma.rfis + 0x58;
1515 sntf = (1 << (fis[1] & 0x0f));
1518 /* Process PHY events */
1519 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1520 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1521 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1523 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1524 reset = ahci_phy_check_events(dev, serr);
1527 /* Process cold presence detection events */
1528 if ((istatus & AHCI_P_IX_CPD) && !reset)
1529 ahci_cpd_check_events(dev);
1530 /* Process command errors */
1531 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1532 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1533 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1534 >> AHCI_P_CMD_CCS_SHIFT;
1535 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1536 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1537 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1539 if (ch->fbs_enabled) {
1540 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1541 if (fbs & AHCI_P_FBS_SDE) {
1542 port = (fbs & AHCI_P_FBS_DWE)
1543 >> AHCI_P_FBS_DWE_SHIFT;
1545 for (i = 0; i < 16; i++) {
1546 if (ch->numrslotspd[i] == 0)
1550 else if (port != i) {
1557 err = ch->rslots & (cstatus | sstatus);
1563 /* Complete all successfull commands. */
1564 ok = ch->rslots & ~(cstatus | sstatus);
1565 for (i = 0; i < ch->numslots; i++) {
1567 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1569 /* On error, complete the rest of commands with error statuses. */
1572 union ccb *fccb = ch->frozen;
1574 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1575 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1576 xpt_freeze_devq(fccb->ccb_h.path, 1);
1577 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1581 for (i = 0; i < ch->numslots; i++) {
1582 /* XXX: reqests in loading state. */
1583 if (((err >> i) & 1) == 0)
1586 ch->slot[i].ccb->ccb_h.target_id != port)
1588 if (istatus & AHCI_P_IX_TFE) {
1590 /* Task File Error */
1591 if (ch->numtslotspd[
1592 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1593 /* Untagged operation. */
1597 et = AHCI_ERR_INNOCENT;
1599 /* Tagged operation. */
1606 } else if (istatus & AHCI_P_IX_IF) {
1607 if (ch->numtslots == 0 && i != ccs && port != -2)
1608 et = AHCI_ERR_INNOCENT;
1612 et = AHCI_ERR_INVALID;
1613 ahci_end_transaction(&ch->slot[i], et);
1616 * We can't reinit port if there are some other
1617 * commands active, use resume to complete them.
1619 if (ch->rslots != 0 && !ch->recoverycmd)
1620 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1622 /* Process NOTIFY events */
1624 ahci_notify_events(dev, sntf);
1627 /* Must be called with channel locked. */
1629 ahci_check_collision(device_t dev, union ccb *ccb)
1631 struct ahci_channel *ch = device_get_softc(dev);
1632 int t = ccb->ccb_h.target_id;
1634 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1635 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1636 /* Tagged command while we have no supported tag free. */
1637 if (((~ch->oslots) & (0xffffffff >> (32 -
1638 ch->curr[t].tags))) == 0)
1640 /* If we have FBS */
1641 if (ch->fbs_enabled) {
1642 /* Tagged command while untagged are active. */
1643 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1646 /* Tagged command while untagged are active. */
1647 if (ch->numrslots != 0 && ch->numtslots == 0)
1649 /* Tagged command while tagged to other target is active. */
1650 if (ch->numtslots != 0 &&
1651 ch->taggedtarget != ccb->ccb_h.target_id)
1655 /* If we have FBS */
1656 if (ch->fbs_enabled) {
1657 /* Untagged command while tagged are active. */
1658 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1661 /* Untagged command while tagged are active. */
1662 if (ch->numrslots != 0 && ch->numtslots != 0)
1666 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1667 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1668 /* Atomic command while anything active. */
1669 if (ch->numrslots != 0)
1672 /* We have some atomic command running. */
1673 if (ch->aslots != 0)
1678 /* Must be called with channel locked. */
1680 ahci_begin_transaction(device_t dev, union ccb *ccb)
1682 struct ahci_channel *ch = device_get_softc(dev);
1683 struct ahci_slot *slot;
1686 /* Choose empty slot. */
1687 tags = ch->numslots;
1688 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1689 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1690 tags = ch->curr[ccb->ccb_h.target_id].tags;
1695 if (ch->slot[tag].state == AHCI_SLOT_EMPTY)
1700 /* Occupy chosen slot. */
1701 slot = &ch->slot[tag];
1703 /* Stop PM timer. */
1704 if (ch->numrslots == 0 && ch->pm_level > 3)
1705 callout_stop(&ch->pm_timer);
1706 /* Update channel stats. */
1707 ch->oslots |= (1 << slot->slot);
1709 ch->numrslotspd[ccb->ccb_h.target_id]++;
1710 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1711 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1713 ch->numtslotspd[ccb->ccb_h.target_id]++;
1714 ch->taggedtarget = ccb->ccb_h.target_id;
1716 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1717 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1718 ch->aslots |= (1 << slot->slot);
1719 slot->dma.nsegs = 0;
1720 /* If request moves data, setup and load SG list */
1721 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1725 slot->state = AHCI_SLOT_LOADING;
1726 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1727 buf = ccb->ataio.data_ptr;
1728 size = ccb->ataio.dxfer_len;
1730 buf = ccb->csio.data_ptr;
1731 size = ccb->csio.dxfer_len;
1733 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map,
1734 buf, size, ahci_dmasetprd, slot, 0);
1736 ahci_execute_transaction(slot);
1739 /* Locked by busdma engine. */
1741 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1743 struct ahci_slot *slot = arg;
1744 struct ahci_channel *ch = device_get_softc(slot->dev);
1745 struct ahci_cmd_tab *ctp;
1746 struct ahci_dma_prd *prd;
1750 device_printf(slot->dev, "DMA load error\n");
1751 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1754 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1755 /* Get a piece of the workspace for this request */
1756 ctp = (struct ahci_cmd_tab *)
1757 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1758 /* Fill S/G table */
1759 prd = &ctp->prd_tab[0];
1760 for (i = 0; i < nsegs; i++) {
1761 prd[i].dba = htole64(segs[i].ds_addr);
1762 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1764 slot->dma.nsegs = nsegs;
1765 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1766 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1767 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1768 ahci_execute_transaction(slot);
1771 /* Must be called with channel locked. */
1773 ahci_execute_transaction(struct ahci_slot *slot)
1775 device_t dev = slot->dev;
1776 struct ahci_channel *ch = device_get_softc(dev);
1777 struct ahci_cmd_tab *ctp;
1778 struct ahci_cmd_list *clp;
1779 union ccb *ccb = slot->ccb;
1780 int port = ccb->ccb_h.target_id & 0x0f;
1781 int fis_size, i, softreset;
1782 uint8_t *fis = ch->dma.rfis + 0x40;
1785 /* Get a piece of the workspace for this request */
1786 ctp = (struct ahci_cmd_tab *)
1787 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1788 /* Setup the FIS for this request */
1789 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) {
1790 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1791 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1794 /* Setup the command list entry */
1795 clp = (struct ahci_cmd_list *)
1796 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1797 clp->cmd_flags = htole16(
1798 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1799 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1800 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1801 (fis_size / sizeof(u_int32_t)) |
1803 clp->prd_length = htole16(slot->dma.nsegs);
1804 /* Special handling for Soft Reset command. */
1805 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1806 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1807 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1809 /* Kick controller into sane state */
1813 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1816 /* Prepare FIS receive area for check. */
1817 for (i = 0; i < 20; i++)
1823 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1824 (AHCI_CT_SIZE * slot->slot));
1825 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1826 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1827 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1828 BUS_DMASYNC_PREREAD);
1829 /* Set ACTIVE bit for NCQ commands. */
1830 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1831 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1832 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1834 /* If FBS is enabled, set PMP port. */
1835 if (ch->fbs_enabled) {
1836 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1837 (port << AHCI_P_FBS_DEV_SHIFT));
1839 /* Issue command to the controller. */
1840 slot->state = AHCI_SLOT_RUNNING;
1841 ch->rslots |= (1 << slot->slot);
1842 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1843 /* Device reset commands doesn't interrupt. Poll them. */
1844 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1845 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1846 int count, timeout = ccb->ccb_h.timeout * 100;
1847 enum ahci_err_type et = AHCI_ERR_NONE;
1849 for (count = 0; count < timeout; count++) {
1851 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1853 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1856 device_printf(ch->dev,
1857 "Poll error on slot %d, TFD: %04x\n",
1858 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1863 /* Workaround for ATI SB600/SB700 chipsets. */
1864 if (ccb->ccb_h.target_id == 15 &&
1865 pci_get_vendor(device_get_parent(dev)) == 0x1002 &&
1866 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1867 et = AHCI_ERR_TIMEOUT;
1872 /* Marvell controllers do not wait for readyness. */
1873 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 &&
1874 et == AHCI_ERR_NONE) {
1875 while ((val = fis[2]) & ATA_S_BUSY) {
1877 if (count++ >= timeout)
1882 if (timeout && (count >= timeout)) {
1883 device_printf(dev, "Poll timeout on slot %d port %d\n",
1885 device_printf(dev, "is %08x cs %08x ss %08x "
1886 "rs %08x tfd %02x serr %08x cmd %08x\n",
1887 ATA_INL(ch->r_mem, AHCI_P_IS),
1888 ATA_INL(ch->r_mem, AHCI_P_CI),
1889 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1890 ATA_INL(ch->r_mem, AHCI_P_TFD),
1891 ATA_INL(ch->r_mem, AHCI_P_SERR),
1892 ATA_INL(ch->r_mem, AHCI_P_CMD));
1893 et = AHCI_ERR_TIMEOUT;
1896 /* Kick controller into sane state and enable FBS. */
1898 ch->eslots |= (1 << slot->slot);
1899 ahci_end_transaction(slot, et);
1902 /* Start command execution timeout */
1903 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000,
1904 (timeout_t*)ahci_timeout, slot);
1908 /* Must be called with channel locked. */
1910 ahci_process_timeout(device_t dev)
1912 struct ahci_channel *ch = device_get_softc(dev);
1915 mtx_assert(&ch->mtx, MA_OWNED);
1916 /* Handle the rest of commands. */
1917 for (i = 0; i < ch->numslots; i++) {
1918 /* Do we have a running request on slot? */
1919 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1921 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1925 /* Must be called with channel locked. */
1927 ahci_rearm_timeout(device_t dev)
1929 struct ahci_channel *ch = device_get_softc(dev);
1932 mtx_assert(&ch->mtx, MA_OWNED);
1933 for (i = 0; i < ch->numslots; i++) {
1934 struct ahci_slot *slot = &ch->slot[i];
1936 /* Do we have a running request on slot? */
1937 if (slot->state < AHCI_SLOT_RUNNING)
1939 if ((ch->toslots & (1 << i)) == 0)
1941 callout_reset(&slot->timeout,
1942 (int)slot->ccb->ccb_h.timeout * hz / 2000,
1943 (timeout_t*)ahci_timeout, slot);
1947 /* Locked by callout mechanism. */
1949 ahci_timeout(struct ahci_slot *slot)
1951 device_t dev = slot->dev;
1952 struct ahci_channel *ch = device_get_softc(dev);
1957 /* Check for stale timeout. */
1958 if (slot->state < AHCI_SLOT_RUNNING)
1961 /* Check if slot was not being executed last time we checked. */
1962 if (slot->state < AHCI_SLOT_EXECUTING) {
1963 /* Check if slot started executing. */
1964 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1965 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1966 >> AHCI_P_CMD_CCS_SHIFT;
1967 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1968 ch->fbs_enabled || ch->wrongccs)
1969 slot->state = AHCI_SLOT_EXECUTING;
1970 else if ((ch->rslots & (1 << ccs)) == 0) {
1972 slot->state = AHCI_SLOT_EXECUTING;
1975 callout_reset(&slot->timeout,
1976 (int)slot->ccb->ccb_h.timeout * hz / 2000,
1977 (timeout_t*)ahci_timeout, slot);
1981 device_printf(dev, "Timeout on slot %d port %d\n",
1982 slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
1983 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
1984 "serr %08x cmd %08x\n",
1985 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1986 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1987 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
1988 ATA_INL(ch->r_mem, AHCI_P_CMD));
1990 /* Handle frozen command. */
1992 union ccb *fccb = ch->frozen;
1994 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1995 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1996 xpt_freeze_devq(fccb->ccb_h.path, 1);
1997 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2001 if (!ch->fbs_enabled && !ch->wrongccs) {
2002 /* Without FBS we know real timeout source. */
2004 /* Handle command with timeout. */
2005 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
2006 /* Handle the rest of commands. */
2007 for (i = 0; i < ch->numslots; i++) {
2008 /* Do we have a running request on slot? */
2009 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2011 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2014 /* With FBS we wait for other commands timeout and pray. */
2015 if (ch->toslots == 0)
2016 xpt_freeze_simq(ch->sim, 1);
2017 ch->toslots |= (1 << slot->slot);
2018 if ((ch->rslots & ~ch->toslots) == 0)
2019 ahci_process_timeout(dev);
2021 device_printf(dev, " ... waiting for slots %08x\n",
2022 ch->rslots & ~ch->toslots);
2026 /* Must be called with channel locked. */
2028 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
2030 device_t dev = slot->dev;
2031 struct ahci_channel *ch = device_get_softc(dev);
2032 union ccb *ccb = slot->ccb;
2033 struct ahci_cmd_list *clp;
2037 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
2038 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2039 clp = (struct ahci_cmd_list *)
2040 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
2041 /* Read result registers to the result struct
2042 * May be incorrect if several commands finished same time,
2043 * so read only when sure or have to.
2045 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2046 struct ata_res *res = &ccb->ataio.res;
2048 if ((et == AHCI_ERR_TFE) ||
2049 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
2050 u_int8_t *fis = ch->dma.rfis + 0x40;
2052 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
2053 BUS_DMASYNC_POSTREAD);
2054 if (ch->fbs_enabled) {
2055 fis += ccb->ccb_h.target_id * 256;
2056 res->status = fis[2];
2057 res->error = fis[3];
2059 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
2062 res->error = tfd >> 8;
2064 res->lba_low = fis[4];
2065 res->lba_mid = fis[5];
2066 res->lba_high = fis[6];
2067 res->device = fis[7];
2068 res->lba_low_exp = fis[8];
2069 res->lba_mid_exp = fis[9];
2070 res->lba_high_exp = fis[10];
2071 res->sector_count = fis[12];
2072 res->sector_count_exp = fis[13];
2075 * Some weird controllers do not return signature in
2076 * FIS receive area. Read it from PxSIG register.
2078 if ((ch->quirks & AHCI_Q_ALTSIG) &&
2079 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2080 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
2081 sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
2082 res->lba_high = sig >> 24;
2083 res->lba_mid = sig >> 16;
2084 res->lba_low = sig >> 8;
2085 res->sector_count = sig;
2088 bzero(res, sizeof(*res));
2089 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
2090 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2091 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2093 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
2096 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2097 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2099 ccb->csio.dxfer_len - le32toh(clp->bytecount);
2102 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2103 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
2104 (ccb->ccb_h.flags & CAM_DIR_IN) ?
2105 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2106 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
2108 if (et != AHCI_ERR_NONE)
2109 ch->eslots |= (1 << slot->slot);
2110 /* In case of error, freeze device for proper recovery. */
2111 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
2112 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2113 xpt_freeze_devq(ccb->ccb_h.path, 1);
2114 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2116 /* Set proper result status. */
2117 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2120 ccb->ccb_h.status |= CAM_REQ_CMP;
2121 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
2122 ccb->csio.scsi_status = SCSI_STATUS_OK;
2124 case AHCI_ERR_INVALID:
2126 ccb->ccb_h.status |= CAM_REQ_INVALID;
2128 case AHCI_ERR_INNOCENT:
2129 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
2133 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2134 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2135 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2137 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2142 if (!ch->recoverycmd) {
2143 xpt_freeze_simq(ch->sim, 1);
2144 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2145 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2147 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
2149 case AHCI_ERR_TIMEOUT:
2150 if (!ch->recoverycmd) {
2151 xpt_freeze_simq(ch->sim, 1);
2152 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2153 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2155 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2159 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
2162 ch->oslots &= ~(1 << slot->slot);
2163 ch->rslots &= ~(1 << slot->slot);
2164 ch->aslots &= ~(1 << slot->slot);
2165 slot->state = AHCI_SLOT_EMPTY;
2167 /* Update channel stats. */
2169 ch->numrslotspd[ccb->ccb_h.target_id]--;
2170 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2171 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
2173 ch->numtslotspd[ccb->ccb_h.target_id]--;
2175 /* Cancel timeout state if request completed normally. */
2176 if (et != AHCI_ERR_TIMEOUT) {
2177 lastto = (ch->toslots == (1 << slot->slot));
2178 ch->toslots &= ~(1 << slot->slot);
2180 xpt_release_simq(ch->sim, TRUE);
2182 /* If it was first request of reset sequence and there is no error,
2183 * proceed to second request. */
2184 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2185 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2186 (ccb->ataio.cmd.control & ATA_A_RESET) &&
2187 et == AHCI_ERR_NONE) {
2188 ccb->ataio.cmd.control &= ~ATA_A_RESET;
2189 ahci_begin_transaction(dev, ccb);
2192 /* If it was our READ LOG command - process it. */
2193 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
2194 ahci_process_read_log(dev, ccb);
2195 /* If it was our REQUEST SENSE command - process it. */
2196 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
2197 ahci_process_request_sense(dev, ccb);
2198 /* If it was NCQ or ATAPI command error, put result on hold. */
2199 } else if (et == AHCI_ERR_NCQ ||
2200 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
2201 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
2202 ch->hold[slot->slot] = ccb;
2206 /* If we have no other active commands, ... */
2207 if (ch->rslots == 0) {
2208 /* if there was fatal error - reset port. */
2209 if (ch->toslots != 0 || ch->fatalerr) {
2212 /* if we have slots in error, we can reinit port. */
2213 if (ch->eslots != 0) {
2218 /* if there commands on hold, we can do READ LOG. */
2219 if (!ch->recoverycmd && ch->numhslots)
2220 ahci_issue_recovery(dev);
2222 /* If all the rest of commands are in timeout - give them chance. */
2223 } else if ((ch->rslots & ~ch->toslots) == 0 &&
2224 et != AHCI_ERR_TIMEOUT)
2225 ahci_rearm_timeout(dev);
2226 /* Unfreeze frozen command. */
2227 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) {
2228 union ccb *fccb = ch->frozen;
2230 ahci_begin_transaction(dev, fccb);
2231 xpt_release_simq(ch->sim, TRUE);
2233 /* Start PM timer. */
2234 if (ch->numrslots == 0 && ch->pm_level > 3 &&
2235 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
2236 callout_schedule(&ch->pm_timer,
2237 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
2242 ahci_issue_recovery(device_t dev)
2244 struct ahci_channel *ch = device_get_softc(dev);
2246 struct ccb_ataio *ataio;
2247 struct ccb_scsiio *csio;
2250 /* Find some held command. */
2251 for (i = 0; i < ch->numslots; i++) {
2255 ccb = xpt_alloc_ccb_nowait();
2257 device_printf(dev, "Unable to allocate recovery command\n");
2259 /* We can't do anything -- complete held commands. */
2260 for (i = 0; i < ch->numslots; i++) {
2261 if (ch->hold[i] == NULL)
2263 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2264 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2265 xpt_done(ch->hold[i]);
2272 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
2273 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2275 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2276 ccb->ccb_h.func_code = XPT_ATA_IO;
2277 ccb->ccb_h.flags = CAM_DIR_IN;
2278 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2279 ataio = &ccb->ataio;
2280 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2281 if (ataio->data_ptr == NULL) {
2284 "Unable to allocate memory for READ LOG command\n");
2287 ataio->dxfer_len = 512;
2288 bzero(&ataio->cmd, sizeof(ataio->cmd));
2289 ataio->cmd.flags = CAM_ATAIO_48BIT;
2290 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2291 ataio->cmd.sector_count = 1;
2292 ataio->cmd.sector_count_exp = 0;
2293 ataio->cmd.lba_low = 0x10;
2294 ataio->cmd.lba_mid = 0;
2295 ataio->cmd.lba_mid_exp = 0;
2298 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2299 ccb->ccb_h.recovery_slot = i;
2300 ccb->ccb_h.func_code = XPT_SCSI_IO;
2301 ccb->ccb_h.flags = CAM_DIR_IN;
2302 ccb->ccb_h.status = 0;
2303 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2305 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2306 csio->dxfer_len = ch->hold[i]->csio.sense_len;
2308 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2309 csio->cdb_io.cdb_bytes[0] = 0x03;
2310 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2312 /* Freeze SIM while doing recovery. */
2313 ch->recoverycmd = 1;
2314 xpt_freeze_simq(ch->sim, 1);
2315 ahci_begin_transaction(dev, ccb);
2319 ahci_process_read_log(device_t dev, union ccb *ccb)
2321 struct ahci_channel *ch = device_get_softc(dev);
2323 struct ata_res *res;
2326 ch->recoverycmd = 0;
2328 data = ccb->ataio.data_ptr;
2329 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2330 (data[0] & 0x80) == 0) {
2331 for (i = 0; i < ch->numslots; i++) {
2334 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2336 if ((data[0] & 0x1F) == i) {
2337 res = &ch->hold[i]->ataio.res;
2338 res->status = data[2];
2339 res->error = data[3];
2340 res->lba_low = data[4];
2341 res->lba_mid = data[5];
2342 res->lba_high = data[6];
2343 res->device = data[7];
2344 res->lba_low_exp = data[8];
2345 res->lba_mid_exp = data[9];
2346 res->lba_high_exp = data[10];
2347 res->sector_count = data[12];
2348 res->sector_count_exp = data[13];
2350 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2351 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2353 xpt_done(ch->hold[i]);
2358 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2359 device_printf(dev, "Error while READ LOG EXT\n");
2360 else if ((data[0] & 0x80) == 0) {
2361 device_printf(dev, "Non-queued command error in READ LOG EXT\n");
2363 for (i = 0; i < ch->numslots; i++) {
2366 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2368 xpt_done(ch->hold[i]);
2373 free(ccb->ataio.data_ptr, M_AHCI);
2375 xpt_release_simq(ch->sim, TRUE);
2379 ahci_process_request_sense(device_t dev, union ccb *ccb)
2381 struct ahci_channel *ch = device_get_softc(dev);
2384 ch->recoverycmd = 0;
2386 i = ccb->ccb_h.recovery_slot;
2387 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2388 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2390 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2391 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2393 xpt_done(ch->hold[i]);
2397 xpt_release_simq(ch->sim, TRUE);
2401 ahci_start(device_t dev, int fbs)
2403 struct ahci_channel *ch = device_get_softc(dev);
2406 /* Clear SATA error register */
2407 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2408 /* Clear any interrupts pending on this channel */
2409 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2410 /* Configure FIS-based switching if supported. */
2411 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2412 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2413 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2414 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2416 /* Start operations on this channel */
2417 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2418 cmd &= ~AHCI_P_CMD_PMA;
2419 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2420 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2424 ahci_stop(device_t dev)
2426 struct ahci_channel *ch = device_get_softc(dev);
2430 /* Kill all activity on this channel */
2431 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2432 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2433 /* Wait for activity stop. */
2437 if (timeout++ > 50000) {
2438 device_printf(dev, "stopping AHCI engine failed\n");
2441 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2446 ahci_clo(device_t dev)
2448 struct ahci_channel *ch = device_get_softc(dev);
2452 /* Issue Command List Override if supported */
2453 if (ch->caps & AHCI_CAP_SCLO) {
2454 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2455 cmd |= AHCI_P_CMD_CLO;
2456 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2460 if (timeout++ > 50000) {
2461 device_printf(dev, "executing CLO failed\n");
2464 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2469 ahci_stop_fr(device_t dev)
2471 struct ahci_channel *ch = device_get_softc(dev);
2475 /* Kill all FIS reception on this channel */
2476 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2477 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2478 /* Wait for FIS reception stop. */
2482 if (timeout++ > 50000) {
2483 device_printf(dev, "stopping AHCI FR engine failed\n");
2486 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2490 ahci_start_fr(device_t dev)
2492 struct ahci_channel *ch = device_get_softc(dev);
2495 /* Start FIS reception on this channel */
2496 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2497 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2501 ahci_wait_ready(device_t dev, int t, int t0)
2503 struct ahci_channel *ch = device_get_softc(dev);
2507 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2508 (ATA_S_BUSY | ATA_S_DRQ)) {
2512 "AHCI reset: device not ready after %dms "
2514 MAX(t, 0) + t0, val);
2522 device_printf(dev, "AHCI reset: device ready after %dms\n",
2528 ahci_reset_to(void *arg)
2531 struct ahci_channel *ch = device_get_softc(dev);
2533 if (ch->resetting == 0)
2536 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0,
2537 (310 - ch->resetting) * 100) == 0) {
2540 xpt_release_simq(ch->sim, TRUE);
2543 if (ch->resetting == 0) {
2546 xpt_release_simq(ch->sim, TRUE);
2549 callout_schedule(&ch->reset_timer, hz / 10);
2553 ahci_reset(device_t dev)
2555 struct ahci_channel *ch = device_get_softc(dev);
2556 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
2559 xpt_freeze_simq(ch->sim, 1);
2561 device_printf(dev, "AHCI reset...\n");
2562 /* Forget about previous reset. */
2563 if (ch->resetting) {
2565 callout_stop(&ch->reset_timer);
2566 xpt_release_simq(ch->sim, TRUE);
2568 /* Requeue freezed command. */
2570 union ccb *fccb = ch->frozen;
2572 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2573 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2574 xpt_freeze_devq(fccb->ccb_h.path, 1);
2575 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2579 /* Kill the engine and requeue all running commands. */
2581 for (i = 0; i < ch->numslots; i++) {
2582 /* Do we have a running request on slot? */
2583 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2585 /* XXX; Commands in loading state. */
2586 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2588 for (i = 0; i < ch->numslots; i++) {
2591 xpt_done(ch->hold[i]);
2595 if (ch->toslots != 0)
2596 xpt_release_simq(ch->sim, TRUE);
2601 /* Tell the XPT about the event */
2602 xpt_async(AC_BUS_RESET, ch->path, NULL);
2603 /* Disable port interrupts */
2604 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2605 /* Reset and reconnect PHY, */
2606 if (!ahci_sata_phy_reset(dev)) {
2609 "AHCI reset: device not found\n");
2611 /* Enable wanted port interrupts */
2612 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2613 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2614 AHCI_P_IX_PRC | AHCI_P_IX_PC));
2615 xpt_release_simq(ch->sim, TRUE);
2619 device_printf(dev, "AHCI reset: device found\n");
2620 /* Wait for clearing busy status. */
2621 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) {
2625 ch->resetting = 310;
2628 /* Enable wanted port interrupts */
2629 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2630 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2631 AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2632 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2633 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2634 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2635 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2637 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev);
2640 xpt_release_simq(ch->sim, TRUE);
2645 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2647 struct ahci_channel *ch = device_get_softc(dev);
2648 u_int8_t *fis = &ctp->cfis[0];
2650 bzero(ctp->cfis, 64);
2651 fis[0] = 0x27; /* host to device */
2652 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2653 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2655 fis[2] = ATA_PACKET_CMD;
2656 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2657 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2660 fis[5] = ccb->csio.dxfer_len;
2661 fis[6] = ccb->csio.dxfer_len >> 8;
2664 fis[15] = ATA_A_4BIT;
2665 bzero(ctp->acmd, 32);
2666 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2667 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2668 ctp->acmd, ccb->csio.cdb_len);
2669 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2671 fis[2] = ccb->ataio.cmd.command;
2672 fis[3] = ccb->ataio.cmd.features;
2673 fis[4] = ccb->ataio.cmd.lba_low;
2674 fis[5] = ccb->ataio.cmd.lba_mid;
2675 fis[6] = ccb->ataio.cmd.lba_high;
2676 fis[7] = ccb->ataio.cmd.device;
2677 fis[8] = ccb->ataio.cmd.lba_low_exp;
2678 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2679 fis[10] = ccb->ataio.cmd.lba_high_exp;
2680 fis[11] = ccb->ataio.cmd.features_exp;
2681 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2685 fis[12] = ccb->ataio.cmd.sector_count;
2686 fis[13] = ccb->ataio.cmd.sector_count_exp;
2688 fis[15] = ATA_A_4BIT;
2690 fis[15] = ccb->ataio.cmd.control;
2696 ahci_sata_connect(struct ahci_channel *ch)
2699 int timeout, found = 0;
2701 /* Wait up to 100ms for "connect well" */
2702 for (timeout = 0; timeout < 1000 ; timeout++) {
2703 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2704 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2706 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2707 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2708 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2710 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2712 device_printf(ch->dev, "SATA offline status=%08x\n",
2717 if (found == 0 && timeout >= 100)
2721 if (timeout >= 1000 || !found) {
2723 device_printf(ch->dev,
2724 "SATA connect timeout time=%dus status=%08x\n",
2725 timeout * 100, status);
2730 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2731 timeout * 100, status);
2733 /* Clear SATA error register */
2734 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2739 ahci_sata_phy_reset(device_t dev)
2741 struct ahci_channel *ch = device_get_softc(dev);
2745 if (ch->listening) {
2746 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2747 val |= AHCI_P_CMD_SUD;
2748 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2751 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2753 val = ATA_SC_SPD_SPEED_GEN1;
2754 else if (sata_rev == 2)
2755 val = ATA_SC_SPD_SPEED_GEN2;
2756 else if (sata_rev == 3)
2757 val = ATA_SC_SPD_SPEED_GEN3;
2760 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2761 ATA_SC_DET_RESET | val |
2762 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2764 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2765 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2766 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2767 if (!ahci_sata_connect(ch)) {
2768 if (ch->caps & AHCI_CAP_SSS) {
2769 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2770 val &= ~AHCI_P_CMD_SUD;
2771 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2773 } else if (ch->pm_level > 0)
2774 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2781 ahci_check_ids(device_t dev, union ccb *ccb)
2783 struct ahci_channel *ch = device_get_softc(dev);
2785 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2786 ccb->ccb_h.status = CAM_TID_INVALID;
2790 if (ccb->ccb_h.target_lun != 0) {
2791 ccb->ccb_h.status = CAM_LUN_INVALID;
2799 ahciaction(struct cam_sim *sim, union ccb *ccb)
2801 device_t dev, parent;
2802 struct ahci_channel *ch;
2804 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2805 ccb->ccb_h.func_code));
2807 ch = (struct ahci_channel *)cam_sim_softc(sim);
2809 switch (ccb->ccb_h.func_code) {
2810 /* Common cases first */
2811 case XPT_ATA_IO: /* Execute the requested I/O operation */
2813 if (ahci_check_ids(dev, ccb))
2815 if (ch->devices == 0 ||
2816 (ch->pm_present == 0 &&
2817 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2818 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2821 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2822 /* Check for command collision. */
2823 if (ahci_check_collision(dev, ccb)) {
2824 /* Freeze command. */
2826 /* We have only one frozen slot, so freeze simq also. */
2827 xpt_freeze_simq(ch->sim, 1);
2830 ahci_begin_transaction(dev, ccb);
2832 case XPT_EN_LUN: /* Enable LUN as a target */
2833 case XPT_TARGET_IO: /* Execute target I/O request */
2834 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2835 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2836 case XPT_ABORT: /* Abort the specified CCB */
2838 ccb->ccb_h.status = CAM_REQ_INVALID;
2840 case XPT_SET_TRAN_SETTINGS:
2842 struct ccb_trans_settings *cts = &ccb->cts;
2843 struct ahci_device *d;
2845 if (ahci_check_ids(dev, ccb))
2847 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2848 d = &ch->curr[ccb->ccb_h.target_id];
2850 d = &ch->user[ccb->ccb_h.target_id];
2851 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2852 d->revision = cts->xport_specific.sata.revision;
2853 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2854 d->mode = cts->xport_specific.sata.mode;
2855 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2856 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2857 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2858 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2859 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2860 ch->pm_present = cts->xport_specific.sata.pm_present;
2861 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2862 d->atapi = cts->xport_specific.sata.atapi;
2863 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2864 d->caps = cts->xport_specific.sata.caps;
2865 ccb->ccb_h.status = CAM_REQ_CMP;
2868 case XPT_GET_TRAN_SETTINGS:
2869 /* Get default/user set transfer settings for the target */
2871 struct ccb_trans_settings *cts = &ccb->cts;
2872 struct ahci_device *d;
2875 if (ahci_check_ids(dev, ccb))
2877 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2878 d = &ch->curr[ccb->ccb_h.target_id];
2880 d = &ch->user[ccb->ccb_h.target_id];
2881 cts->protocol = PROTO_ATA;
2882 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2883 cts->transport = XPORT_SATA;
2884 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2885 cts->proto_specific.valid = 0;
2886 cts->xport_specific.sata.valid = 0;
2887 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2888 (ccb->ccb_h.target_id == 15 ||
2889 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2890 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2891 if (status & 0x0f0) {
2892 cts->xport_specific.sata.revision =
2893 (status & 0x0f0) >> 4;
2894 cts->xport_specific.sata.valid |=
2895 CTS_SATA_VALID_REVISION;
2897 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2899 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2900 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2901 if (ch->caps2 & AHCI_CAP2_APST)
2902 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2904 if ((ch->caps & AHCI_CAP_SNCQ) &&
2905 (ch->quirks & AHCI_Q_NOAA) == 0)
2906 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2907 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2908 cts->xport_specific.sata.caps &=
2909 ch->user[ccb->ccb_h.target_id].caps;
2910 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2912 cts->xport_specific.sata.revision = d->revision;
2913 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2914 cts->xport_specific.sata.caps = d->caps;
2915 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2917 cts->xport_specific.sata.mode = d->mode;
2918 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2919 cts->xport_specific.sata.bytecount = d->bytecount;
2920 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2921 cts->xport_specific.sata.pm_present = ch->pm_present;
2922 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2923 cts->xport_specific.sata.tags = d->tags;
2924 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2925 cts->xport_specific.sata.atapi = d->atapi;
2926 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2927 ccb->ccb_h.status = CAM_REQ_CMP;
2930 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2931 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2933 ccb->ccb_h.status = CAM_REQ_CMP;
2935 case XPT_TERM_IO: /* Terminate the I/O process */
2937 ccb->ccb_h.status = CAM_REQ_INVALID;
2939 case XPT_PATH_INQ: /* Path routing inquiry */
2941 struct ccb_pathinq *cpi = &ccb->cpi;
2943 parent = device_get_parent(dev);
2944 cpi->version_num = 1; /* XXX??? */
2945 cpi->hba_inquiry = PI_SDTR_ABLE;
2946 if (ch->caps & AHCI_CAP_SNCQ)
2947 cpi->hba_inquiry |= PI_TAG_ABLE;
2948 if (ch->caps & AHCI_CAP_SPM)
2949 cpi->hba_inquiry |= PI_SATAPM;
2950 cpi->target_sprt = 0;
2951 cpi->hba_misc = PIM_SEQSCAN;
2952 cpi->hba_eng_cnt = 0;
2953 if (ch->caps & AHCI_CAP_SPM)
2954 cpi->max_target = 15;
2956 cpi->max_target = 0;
2958 cpi->initiator_id = 0;
2959 cpi->bus_id = cam_sim_bus(sim);
2960 cpi->base_transfer_speed = 150000;
2961 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2962 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2963 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2964 cpi->unit_number = cam_sim_unit(sim);
2965 cpi->transport = XPORT_SATA;
2966 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2967 cpi->protocol = PROTO_ATA;
2968 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2969 cpi->maxio = MAXPHYS;
2970 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2971 if (pci_get_devid(parent) == 0x43801002)
2972 cpi->maxio = min(cpi->maxio, 128 * 512);
2973 cpi->hba_vendor = pci_get_vendor(parent);
2974 cpi->hba_device = pci_get_device(parent);
2975 cpi->hba_subvendor = pci_get_subvendor(parent);
2976 cpi->hba_subdevice = pci_get_subdevice(parent);
2977 cpi->ccb_h.status = CAM_REQ_CMP;
2981 ccb->ccb_h.status = CAM_REQ_INVALID;
2988 ahcipoll(struct cam_sim *sim)
2990 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
2992 ahci_ch_intr(ch->dev);
2993 if (ch->resetting != 0 &&
2994 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2995 ch->resetpolldiv = 1000;
2996 ahci_reset_to(ch->dev);