2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/led/led.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
54 #include <cam/cam_ccb.h>
55 #include <cam/cam_sim.h>
56 #include <cam/cam_xpt_sim.h>
57 #include <cam/cam_debug.h>
59 /* local prototypes */
60 static int ahci_setup_interrupt(device_t dev);
61 static void ahci_intr(void *data);
62 static void ahci_intr_one(void *data);
63 static int ahci_suspend(device_t dev);
64 static int ahci_resume(device_t dev);
65 static int ahci_ch_init(device_t dev);
66 static int ahci_ch_deinit(device_t dev);
67 static int ahci_ch_suspend(device_t dev);
68 static int ahci_ch_resume(device_t dev);
69 static void ahci_ch_pm(void *arg);
70 static void ahci_ch_intr_locked(void *data);
71 static void ahci_ch_intr(void *data);
72 static void ahci_ch_led(void *priv, int onoff);
73 static int ahci_ctlr_reset(device_t dev);
74 static int ahci_ctlr_setup(device_t dev);
75 static void ahci_begin_transaction(device_t dev, union ccb *ccb);
76 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
77 static void ahci_execute_transaction(struct ahci_slot *slot);
78 static void ahci_timeout(struct ahci_slot *slot);
79 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
80 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
81 static void ahci_dmainit(device_t dev);
82 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
83 static void ahci_dmafini(device_t dev);
84 static void ahci_slotsalloc(device_t dev);
85 static void ahci_slotsfree(device_t dev);
86 static void ahci_reset(device_t dev);
87 static void ahci_start(device_t dev, int fbs);
88 static void ahci_stop(device_t dev);
89 static void ahci_clo(device_t dev);
90 static void ahci_start_fr(device_t dev);
91 static void ahci_stop_fr(device_t dev);
93 static int ahci_sata_connect(struct ahci_channel *ch);
94 static int ahci_sata_phy_reset(device_t dev);
95 static int ahci_wait_ready(device_t dev, int t, int t0);
97 static void ahci_issue_recovery(device_t dev);
98 static void ahci_process_read_log(device_t dev, union ccb *ccb);
99 static void ahci_process_request_sense(device_t dev, union ccb *ccb);
101 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
102 static void ahcipoll(struct cam_sim *sim);
104 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
111 #define AHCI_Q_NOFORCE 1
112 #define AHCI_Q_NOPMP 2
113 #define AHCI_Q_NONCQ 4
115 #define AHCI_Q_2CH 16
116 #define AHCI_Q_4CH 32
117 #define AHCI_Q_EDGEIS 64
118 #define AHCI_Q_SATA2 128
119 #define AHCI_Q_NOBSYRES 256
120 #define AHCI_Q_NOAA 512
121 #define AHCI_Q_NOCOUNT 1024
122 #define AHCI_Q_ALTSIG 2048
123 #define AHCI_Q_NOMSI 4096
125 #define AHCI_Q_BIT_STRING \
141 {0x43801002, 0x00, "AMD SB600", AHCI_Q_NOMSI},
142 {0x43901002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
143 {0x43911002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
144 {0x43921002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
145 {0x43931002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
146 {0x43941002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
147 {0x43951002, 0x00, "AMD SB8x0/SB9x0", 0},
148 {0x78001022, 0x00, "AMD Hudson-2", 0},
149 {0x78011022, 0x00, "AMD Hudson-2", 0},
150 {0x78021022, 0x00, "AMD Hudson-2", 0},
151 {0x78031022, 0x00, "AMD Hudson-2", 0},
152 {0x78041022, 0x00, "AMD Hudson-2", 0},
153 {0x06111b21, 0x00, "ASMedia ASM2106", 0},
154 {0x06121b21, 0x00, "ASMedia ASM1061", 0},
155 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE},
156 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE},
157 {0x26818086, 0x00, "Intel ESB2", 0},
158 {0x26828086, 0x00, "Intel ESB2", 0},
159 {0x26838086, 0x00, "Intel ESB2", 0},
160 {0x27c18086, 0x00, "Intel ICH7", 0},
161 {0x27c38086, 0x00, "Intel ICH7", 0},
162 {0x27c58086, 0x00, "Intel ICH7M", 0},
163 {0x27c68086, 0x00, "Intel ICH7M", 0},
164 {0x28218086, 0x00, "Intel ICH8", 0},
165 {0x28228086, 0x00, "Intel ICH8", 0},
166 {0x28248086, 0x00, "Intel ICH8", 0},
167 {0x28298086, 0x00, "Intel ICH8M", 0},
168 {0x282a8086, 0x00, "Intel ICH8M", 0},
169 {0x29228086, 0x00, "Intel ICH9", 0},
170 {0x29238086, 0x00, "Intel ICH9", 0},
171 {0x29248086, 0x00, "Intel ICH9", 0},
172 {0x29258086, 0x00, "Intel ICH9", 0},
173 {0x29278086, 0x00, "Intel ICH9", 0},
174 {0x29298086, 0x00, "Intel ICH9M", 0},
175 {0x292a8086, 0x00, "Intel ICH9M", 0},
176 {0x292b8086, 0x00, "Intel ICH9M", 0},
177 {0x292c8086, 0x00, "Intel ICH9M", 0},
178 {0x292f8086, 0x00, "Intel ICH9M", 0},
179 {0x294d8086, 0x00, "Intel ICH9", 0},
180 {0x294e8086, 0x00, "Intel ICH9M", 0},
181 {0x3a058086, 0x00, "Intel ICH10", 0},
182 {0x3a228086, 0x00, "Intel ICH10", 0},
183 {0x3a258086, 0x00, "Intel ICH10", 0},
184 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0},
185 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0},
186 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0},
187 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0},
188 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0},
189 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0},
190 {0x1c028086, 0x00, "Intel Cougar Point", 0},
191 {0x1c038086, 0x00, "Intel Cougar Point", 0},
192 {0x1c048086, 0x00, "Intel Cougar Point", 0},
193 {0x1c058086, 0x00, "Intel Cougar Point", 0},
194 {0x1d028086, 0x00, "Intel Patsburg", 0},
195 {0x1d048086, 0x00, "Intel Patsburg", 0},
196 {0x1d068086, 0x00, "Intel Patsburg", 0},
197 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0},
198 {0x1e028086, 0x00, "Intel Panther Point", 0},
199 {0x1e038086, 0x00, "Intel Panther Point", 0},
200 {0x1e048086, 0x00, "Intel Panther Point", 0},
201 {0x1e058086, 0x00, "Intel Panther Point", 0},
202 {0x1e068086, 0x00, "Intel Panther Point", 0},
203 {0x1e078086, 0x00, "Intel Panther Point", 0},
204 {0x1e0e8086, 0x00, "Intel Panther Point", 0},
205 {0x1e0f8086, 0x00, "Intel Panther Point", 0},
206 {0x23a38086, 0x00, "Intel Coleto Creek", 0},
207 {0x8c028086, 0x00, "Intel Lynx Point", 0},
208 {0x8c038086, 0x00, "Intel Lynx Point", 0},
209 {0x8c048086, 0x00, "Intel Lynx Point", 0},
210 {0x8c058086, 0x00, "Intel Lynx Point", 0},
211 {0x8c068086, 0x00, "Intel Lynx Point", 0},
212 {0x8c078086, 0x00, "Intel Lynx Point", 0},
213 {0x8c0e8086, 0x00, "Intel Lynx Point", 0},
214 {0x8c0f8086, 0x00, "Intel Lynx Point", 0},
215 {0x23238086, 0x00, "Intel DH89xxCC", 0},
216 {0x2360197b, 0x00, "JMicron JMB360", 0},
217 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE},
218 {0x2362197b, 0x00, "JMicron JMB362", 0},
219 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE},
220 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE},
221 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE},
222 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE},
223 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH |
225 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH |
226 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
227 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH |
228 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
229 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH |
230 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
231 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES},
232 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
233 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES},
234 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES},
235 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
236 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
237 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES},
238 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES},
239 {0x91831b4b, 0x00, "Marvell 88SS9183", AHCI_Q_NOBSYRES},
240 {0x91a01b4b, 0x00, "Marvell 88SE91Ax", AHCI_Q_NOBSYRES},
241 {0x92151b4b, 0x00, "Marvell 88SE9215", AHCI_Q_NOBSYRES},
242 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
243 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG},
244 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES},
245 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
246 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
247 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
248 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
249 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES},
250 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES},
251 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES},
252 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES},
253 {0x06411103, 0x00, "HighPoint RocketRAID 640L", AHCI_Q_NOBSYRES},
254 {0x06421103, 0x00, "HighPoint RocketRAID 642L", AHCI_Q_NOBSYRES},
255 {0x06451103, 0x00, "HighPoint RocketRAID 644L", AHCI_Q_NOBSYRES},
256 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
257 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
258 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
259 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
260 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
261 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
262 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
263 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
264 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
265 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
266 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
267 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
268 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
269 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
270 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
271 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
272 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
273 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
274 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
275 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
276 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
277 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
278 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
279 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
280 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
281 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
282 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
283 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
284 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
285 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
286 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
287 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
288 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
289 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
290 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
291 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
292 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
293 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
294 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
295 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
296 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
297 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
298 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
299 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
300 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
301 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
302 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
303 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
304 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
305 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
306 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
307 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
308 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
309 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
310 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
311 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
312 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
313 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
314 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA},
315 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
316 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
317 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
318 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
319 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
320 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
321 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
322 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
323 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
324 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
325 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
326 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
327 {0x11841039, 0x00, "SiS 966", 0},
328 {0x11851039, 0x00, "SiS 968", 0},
329 {0x01861039, 0x00, "SiS 968", 0},
330 {0x00000000, 0x00, NULL, 0}
333 #define recovery_type spriv_field0
334 #define RECOVERY_NONE 0
335 #define RECOVERY_READ_LOG 1
336 #define RECOVERY_REQUEST_SENSE 2
337 #define recovery_slot spriv_field1
339 static int force_ahci = 1;
340 TUNABLE_INT("hw.ahci.force", &force_ahci);
343 ahci_probe(device_t dev)
347 uint32_t devid = pci_get_devid(dev);
348 uint8_t revid = pci_get_revid(dev);
350 /* Is this a possible AHCI candidate? */
351 if (pci_get_class(dev) == PCIC_STORAGE &&
352 pci_get_subclass(dev) == PCIS_STORAGE_SATA &&
353 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0)
355 /* Is this a known AHCI chip? */
356 for (i = 0; ahci_ids[i].id != 0; i++) {
357 if (ahci_ids[i].id == devid &&
358 ahci_ids[i].rev <= revid &&
359 (valid || (force_ahci == 1 &&
360 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) {
361 /* Do not attach JMicrons with single PCI function. */
362 if (pci_get_vendor(dev) == 0x197b &&
363 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
365 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
367 device_set_desc_copy(dev, buf);
368 return (BUS_PROBE_VENDOR);
373 device_set_desc_copy(dev, "AHCI SATA controller");
374 return (BUS_PROBE_VENDOR);
378 ahci_ata_probe(device_t dev)
382 uint32_t devid = pci_get_devid(dev);
383 uint8_t revid = pci_get_revid(dev);
385 if ((intptr_t)device_get_ivars(dev) >= 0)
387 /* Is this a known AHCI chip? */
388 for (i = 0; ahci_ids[i].id != 0; i++) {
389 if (ahci_ids[i].id == devid &&
390 ahci_ids[i].rev <= revid) {
391 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
393 device_set_desc_copy(dev, buf);
394 return (BUS_PROBE_VENDOR);
397 device_set_desc_copy(dev, "AHCI SATA controller");
398 return (BUS_PROBE_VENDOR);
402 ahci_attach(device_t dev)
404 struct ahci_controller *ctlr = device_get_softc(dev);
406 int error, unit, speed, i;
407 uint32_t devid = pci_get_devid(dev);
408 uint8_t revid = pci_get_revid(dev);
413 while (ahci_ids[i].id != 0 &&
414 (ahci_ids[i].id != devid ||
415 ahci_ids[i].rev > revid))
417 ctlr->quirks = ahci_ids[i].quirks;
418 resource_int_value(device_get_name(dev),
419 device_get_unit(dev), "ccc", &ctlr->ccc);
420 /* if we have a memory BAR(5) we are likely on an AHCI part */
421 ctlr->r_rid = PCIR_BAR(5);
422 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
423 &ctlr->r_rid, RF_ACTIVE)))
425 /* Setup our own memory management for channels. */
426 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
427 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
428 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
429 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
430 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
431 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
434 if ((error = rman_manage_region(&ctlr->sc_iomem,
435 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
436 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
437 rman_fini(&ctlr->sc_iomem);
440 pci_enable_busmaster(dev);
441 /* Reset controller */
442 if ((error = ahci_ctlr_reset(dev)) != 0) {
443 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
444 rman_fini(&ctlr->sc_iomem);
447 /* Get the HW capabilities */
448 version = ATA_INL(ctlr->r_mem, AHCI_VS);
449 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
450 if (version >= 0x00010200)
451 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
452 if (ctlr->caps & AHCI_CAP_EMS)
453 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
454 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
456 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */
457 if ((ctlr->quirks & AHCI_Q_NOBSYRES) &&
458 (ctlr->quirks & AHCI_Q_ALTSIG) &&
459 (ctlr->caps & AHCI_CAP_SPM) == 0)
460 ctlr->quirks &= ~AHCI_Q_NOBSYRES;
462 if (ctlr->quirks & AHCI_Q_1CH) {
463 ctlr->caps &= ~AHCI_CAP_NPMASK;
464 ctlr->ichannels &= 0x01;
466 if (ctlr->quirks & AHCI_Q_2CH) {
467 ctlr->caps &= ~AHCI_CAP_NPMASK;
469 ctlr->ichannels &= 0x03;
471 if (ctlr->quirks & AHCI_Q_4CH) {
472 ctlr->caps &= ~AHCI_CAP_NPMASK;
474 ctlr->ichannels &= 0x0f;
476 ctlr->channels = MAX(flsl(ctlr->ichannels),
477 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
478 if (ctlr->quirks & AHCI_Q_NOPMP)
479 ctlr->caps &= ~AHCI_CAP_SPM;
480 if (ctlr->quirks & AHCI_Q_NONCQ)
481 ctlr->caps &= ~AHCI_CAP_SNCQ;
482 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
484 mtx_init(&ctlr->em_mtx, "AHCI EM lock", NULL, MTX_DEF);
485 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
487 /* Create controller-wide DMA tag. */
488 if (bus_dma_tag_create(bus_get_dma_tag(dev), 0, 0,
489 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
490 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
491 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
492 0, NULL, NULL, &ctlr->dma_tag)) {
493 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
495 rman_fini(&ctlr->sc_iomem);
499 ahci_ctlr_setup(dev);
500 /* Setup interrupts. */
501 if (ahci_setup_interrupt(dev)) {
502 bus_dma_tag_destroy(ctlr->dma_tag);
503 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
504 rman_fini(&ctlr->sc_iomem);
507 /* Announce HW capabilities. */
508 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
510 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
511 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
512 ((version >> 4) & 0xf0) + (version & 0x0f),
513 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
514 ((speed == 1) ? "1.5":((speed == 2) ? "3":
515 ((speed == 3) ? "6":"?"))),
516 (ctlr->caps & AHCI_CAP_SPM) ?
517 "supported" : "not supported",
518 (ctlr->caps & AHCI_CAP_FBSS) ?
520 if (ctlr->quirks != 0) {
521 device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
525 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
526 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
527 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
528 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
529 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
530 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
531 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
532 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
533 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
534 ((speed == 1) ? "1.5":((speed == 2) ? "3":
535 ((speed == 3) ? "6":"?"))));
536 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
537 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
538 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
539 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
540 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
541 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
542 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
543 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
544 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
545 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
546 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
547 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
549 if (bootverbose && version >= 0x00010200) {
550 device_printf(dev, "Caps2:%s%s%s%s%s%s\n",
551 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
552 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
553 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
554 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
555 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
556 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
558 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) {
559 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n",
560 (ctlr->capsem & AHCI_EM_PM) ? " PM":"",
561 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"",
562 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"",
563 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"",
564 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"",
565 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"",
566 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"",
567 (ctlr->capsem & AHCI_EM_LED) ? " LED":"");
569 /* Attach all channels on this controller */
570 for (unit = 0; unit < ctlr->channels; unit++) {
571 child = device_add_child(dev, "ahcich", -1);
573 device_printf(dev, "failed to add channel device\n");
576 device_set_ivars(child, (void *)(intptr_t)unit);
577 if ((ctlr->ichannels & (1 << unit)) == 0)
578 device_disable(child);
580 bus_generic_attach(dev);
585 ahci_detach(device_t dev)
587 struct ahci_controller *ctlr = device_get_softc(dev);
590 /* Detach & delete all children */
591 device_delete_children(dev);
593 /* Free interrupts. */
594 for (i = 0; i < ctlr->numirqs; i++) {
595 if (ctlr->irqs[i].r_irq) {
596 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
597 ctlr->irqs[i].handle);
598 bus_release_resource(dev, SYS_RES_IRQ,
599 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
602 pci_release_msi(dev);
603 bus_dma_tag_destroy(ctlr->dma_tag);
605 rman_fini(&ctlr->sc_iomem);
607 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
608 mtx_destroy(&ctlr->em_mtx);
613 ahci_ctlr_reset(device_t dev)
615 struct ahci_controller *ctlr = device_get_softc(dev);
618 if (pci_read_config(dev, 0x00, 4) == 0x28298086 &&
619 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
620 pci_write_config(dev, 0x92, 0x01, 1);
621 /* Enable AHCI mode */
622 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
623 /* Reset AHCI controller */
624 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
625 for (timeout = 1000; timeout > 0; timeout--) {
627 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
631 device_printf(dev, "AHCI controller reset failure\n");
634 /* Reenable AHCI mode */
635 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
640 ahci_ctlr_setup(device_t dev)
642 struct ahci_controller *ctlr = device_get_softc(dev);
643 /* Clear interrupts */
644 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
647 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
648 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
649 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
650 (4 << AHCI_CCCC_CC_SHIFT) |
652 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
653 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
656 "CCC with %dms/4cmd enabled on vector %d\n",
657 ctlr->ccc, ctlr->cccv);
660 /* Enable AHCI interrupts */
661 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
662 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
667 ahci_suspend(device_t dev)
669 struct ahci_controller *ctlr = device_get_softc(dev);
671 bus_generic_suspend(dev);
672 /* Disable interupts, so the state change(s) doesn't trigger */
673 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
674 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
679 ahci_resume(device_t dev)
683 if ((res = ahci_ctlr_reset(dev)) != 0)
685 ahci_ctlr_setup(dev);
686 return (bus_generic_resume(dev));
690 ahci_setup_interrupt(device_t dev)
692 struct ahci_controller *ctlr = device_get_softc(dev);
696 if (ctlr->quirks & AHCI_Q_NOMSI)
698 resource_int_value(device_get_name(dev),
699 device_get_unit(dev), "msi", &msi);
703 msi = min(1, pci_msi_count(dev));
705 msi = pci_msi_count(dev);
706 /* Allocate MSI if needed/present. */
707 if (msi && pci_alloc_msi(dev, &msi) == 0) {
713 /* Check for single MSI vector fallback. */
714 if (ctlr->numirqs > 1 &&
715 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
716 device_printf(dev, "Falling back to one MSI\n");
719 /* Allocate all IRQs. */
720 for (i = 0; i < ctlr->numirqs; i++) {
721 ctlr->irqs[i].ctlr = ctlr;
722 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0);
723 if (ctlr->numirqs == 1 || i >= ctlr->channels ||
724 (ctlr->ccc && i == ctlr->cccv))
725 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
726 else if (i == ctlr->numirqs - 1)
727 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
729 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
730 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
731 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
732 device_printf(dev, "unable to map interrupt\n");
735 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
736 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr,
737 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
738 /* SOS XXX release r_irq */
739 device_printf(dev, "unable to setup interrupt\n");
742 if (ctlr->numirqs > 1) {
743 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
744 ctlr->irqs[i].handle,
745 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
753 * Common case interrupt handler.
756 ahci_intr(void *data)
758 struct ahci_controller_irq *irq = data;
759 struct ahci_controller *ctlr = irq->ctlr;
760 u_int32_t is, ise = 0;
764 if (irq->mode == AHCI_IRQ_MODE_ALL) {
767 is = ctlr->ichannels;
769 is = ATA_INL(ctlr->r_mem, AHCI_IS);
770 } else { /* AHCI_IRQ_MODE_AFTER */
771 unit = irq->r_irq_rid - 1;
772 is = ATA_INL(ctlr->r_mem, AHCI_IS);
774 /* CCC interrupt is edge triggered. */
776 ise = 1 << ctlr->cccv;
777 /* Some controllers have edge triggered IS. */
778 if (ctlr->quirks & AHCI_Q_EDGEIS)
781 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
782 for (; unit < ctlr->channels; unit++) {
783 if ((is & (1 << unit)) != 0 &&
784 (arg = ctlr->interrupt[unit].argument)) {
785 ctlr->interrupt[unit].function(arg);
788 /* AHCI declares level triggered IS. */
789 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
790 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
794 * Simplified interrupt handler for multivector MSI mode.
797 ahci_intr_one(void *data)
799 struct ahci_controller_irq *irq = data;
800 struct ahci_controller *ctlr = irq->ctlr;
804 unit = irq->r_irq_rid - 1;
805 /* Some controllers have edge triggered IS. */
806 if (ctlr->quirks & AHCI_Q_EDGEIS)
807 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
808 if ((arg = ctlr->interrupt[unit].argument))
809 ctlr->interrupt[unit].function(arg);
810 /* AHCI declares level triggered IS. */
811 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
812 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
815 static struct resource *
816 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
817 u_long start, u_long end, u_long count, u_int flags)
819 struct ahci_controller *ctlr = device_get_softc(dev);
820 int unit = ((struct ahci_channel *)device_get_softc(child))->unit;
821 struct resource *res = NULL;
822 int offset = AHCI_OFFSET + (unit << 7);
827 st = rman_get_start(ctlr->r_mem);
828 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
829 st + offset + 127, 128, RF_ACTIVE, child);
831 bus_space_handle_t bsh;
833 bsh = rman_get_bushandle(ctlr->r_mem);
834 bst = rman_get_bustag(ctlr->r_mem);
835 bus_space_subregion(bst, bsh, offset, 128, &bsh);
836 rman_set_bushandle(res, bsh);
837 rman_set_bustag(res, bst);
841 if (*rid == ATA_IRQ_RID)
842 res = ctlr->irqs[0].r_irq;
849 ahci_release_resource(device_t dev, device_t child, int type, int rid,
855 rman_release_resource(r);
858 if (rid != ATA_IRQ_RID)
866 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
867 int flags, driver_filter_t *filter, driver_intr_t *function,
868 void *argument, void **cookiep)
870 struct ahci_controller *ctlr = device_get_softc(dev);
871 int unit = (intptr_t)device_get_ivars(child);
873 if (filter != NULL) {
874 printf("ahci.c: we cannot use a filter here\n");
877 ctlr->interrupt[unit].function = function;
878 ctlr->interrupt[unit].argument = argument;
883 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
886 struct ahci_controller *ctlr = device_get_softc(dev);
887 int unit = (intptr_t)device_get_ivars(child);
889 ctlr->interrupt[unit].function = NULL;
890 ctlr->interrupt[unit].argument = NULL;
895 ahci_print_child(device_t dev, device_t child)
899 retval = bus_print_child_header(dev, child);
900 retval += printf(" at channel %d",
901 (int)(intptr_t)device_get_ivars(child));
902 retval += bus_print_child_footer(dev, child);
908 ahci_child_location_str(device_t dev, device_t child, char *buf,
912 snprintf(buf, buflen, "channel=%d",
913 (int)(intptr_t)device_get_ivars(child));
918 ahci_get_dma_tag(device_t dev, device_t child)
920 struct ahci_controller *ctlr = device_get_softc(dev);
922 return (ctlr->dma_tag);
925 devclass_t ahci_devclass;
926 static device_method_t ahci_methods[] = {
927 DEVMETHOD(device_probe, ahci_probe),
928 DEVMETHOD(device_attach, ahci_attach),
929 DEVMETHOD(device_detach, ahci_detach),
930 DEVMETHOD(device_suspend, ahci_suspend),
931 DEVMETHOD(device_resume, ahci_resume),
932 DEVMETHOD(bus_print_child, ahci_print_child),
933 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
934 DEVMETHOD(bus_release_resource, ahci_release_resource),
935 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
936 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
937 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
938 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag),
941 static driver_t ahci_driver = {
944 sizeof(struct ahci_controller)
946 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0);
947 static device_method_t ahci_ata_methods[] = {
948 DEVMETHOD(device_probe, ahci_ata_probe),
949 DEVMETHOD(device_attach, ahci_attach),
950 DEVMETHOD(device_detach, ahci_detach),
951 DEVMETHOD(device_suspend, ahci_suspend),
952 DEVMETHOD(device_resume, ahci_resume),
953 DEVMETHOD(bus_print_child, ahci_print_child),
954 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
955 DEVMETHOD(bus_release_resource, ahci_release_resource),
956 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
957 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
958 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
961 static driver_t ahci_ata_driver = {
964 sizeof(struct ahci_controller)
966 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0);
967 MODULE_VERSION(ahci, 1);
968 MODULE_DEPEND(ahci, cam, 1, 1, 1);
971 ahci_ch_probe(device_t dev)
974 device_set_desc_copy(dev, "AHCI channel");
979 ahci_ch_attach(device_t dev)
981 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
982 struct ahci_channel *ch = device_get_softc(dev);
983 struct cam_devq *devq;
984 int rid, error, i, sata_rev = 0;
989 ch->unit = (intptr_t)device_get_ivars(dev);
990 ch->caps = ctlr->caps;
991 ch->caps2 = ctlr->caps2;
992 ch->quirks = ctlr->quirks;
993 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
994 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
995 resource_int_value(device_get_name(dev),
996 device_get_unit(dev), "pm_level", &ch->pm_level);
997 if (ch->pm_level > 3)
998 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
999 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
1000 /* Limit speed for my onboard JMicron external port.
1001 * It is not eSATA really. */
1002 if (pci_get_devid(ctlr->dev) == 0x2363197b &&
1003 pci_get_subvendor(ctlr->dev) == 0x1043 &&
1004 pci_get_subdevice(ctlr->dev) == 0x81e4 &&
1007 if (ch->quirks & AHCI_Q_SATA2)
1009 resource_int_value(device_get_name(dev),
1010 device_get_unit(dev), "sata_rev", &sata_rev);
1011 for (i = 0; i < 16; i++) {
1012 ch->user[i].revision = sata_rev;
1013 ch->user[i].mode = 0;
1014 ch->user[i].bytecount = 8192;
1015 ch->user[i].tags = ch->numslots;
1016 ch->user[i].caps = 0;
1017 ch->curr[i] = ch->user[i];
1019 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
1020 CTS_SATA_CAPS_H_APST |
1021 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
1023 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
1027 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1031 ahci_slotsalloc(dev);
1035 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1036 &rid, RF_SHAREABLE | RF_ACTIVE))) {
1037 device_printf(dev, "Unable to map interrupt\n");
1041 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
1042 ahci_ch_intr_locked, dev, &ch->ih))) {
1043 device_printf(dev, "Unable to setup interrupt\n");
1047 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
1048 version = ATA_INL(ctlr->r_mem, AHCI_VS);
1049 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
1050 ch->chcaps |= AHCI_P_CMD_FBSCP;
1052 device_printf(dev, "Caps:%s%s%s%s%s\n",
1053 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
1054 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
1055 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
1056 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
1057 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"");
1059 /* Create the device queue for our SIM. */
1060 devq = cam_simq_alloc(ch->numslots);
1062 device_printf(dev, "Unable to allocate simq\n");
1066 /* Construct SIM entry */
1067 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
1068 device_get_unit(dev), &ch->mtx,
1069 min(2, ch->numslots),
1070 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
1072 if (ch->sim == NULL) {
1073 cam_simq_free(devq);
1074 device_printf(dev, "unable to allocate sim\n");
1078 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
1079 device_printf(dev, "unable to register xpt bus\n");
1083 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
1084 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1085 device_printf(dev, "unable to create path\n");
1089 if (ch->pm_level > 3) {
1090 callout_reset(&ch->pm_timer,
1091 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
1094 mtx_unlock(&ch->mtx);
1095 if ((ch->caps & AHCI_CAP_EMS) &&
1096 (ctlr->capsem & AHCI_EM_LED)) {
1097 for (i = 0; i < AHCI_NUM_LEDS; i++) {
1098 ch->leds[i].dev = dev;
1099 ch->leds[i].num = i;
1101 if ((ctlr->capsem & AHCI_EM_ALHD) == 0) {
1102 snprintf(buf, sizeof(buf), "%s.act",
1103 device_get_nameunit(dev));
1104 ch->leds[0].led = led_create(ahci_ch_led,
1107 snprintf(buf, sizeof(buf), "%s.locate",
1108 device_get_nameunit(dev));
1109 ch->leds[1].led = led_create(ahci_ch_led, &ch->leds[1], buf);
1110 snprintf(buf, sizeof(buf), "%s.fault",
1111 device_get_nameunit(dev));
1112 ch->leds[2].led = led_create(ahci_ch_led, &ch->leds[2], buf);
1117 xpt_bus_deregister(cam_sim_path(ch->sim));
1119 cam_sim_free(ch->sim, /*free_devq*/TRUE);
1121 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
1123 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
1124 mtx_unlock(&ch->mtx);
1125 mtx_destroy(&ch->mtx);
1130 ahci_ch_detach(device_t dev)
1132 struct ahci_channel *ch = device_get_softc(dev);
1135 for (i = 0; i < AHCI_NUM_LEDS; i++) {
1136 if (ch->leds[i].led)
1137 led_destroy(ch->leds[i].led);
1140 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
1141 /* Forget about reset. */
1142 if (ch->resetting) {
1144 xpt_release_simq(ch->sim, TRUE);
1146 xpt_free_path(ch->path);
1147 xpt_bus_deregister(cam_sim_path(ch->sim));
1148 cam_sim_free(ch->sim, /*free_devq*/TRUE);
1149 mtx_unlock(&ch->mtx);
1151 if (ch->pm_level > 3)
1152 callout_drain(&ch->pm_timer);
1153 callout_drain(&ch->reset_timer);
1154 bus_teardown_intr(dev, ch->r_irq, ch->ih);
1155 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
1157 ahci_ch_deinit(dev);
1158 ahci_slotsfree(dev);
1161 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
1162 mtx_destroy(&ch->mtx);
1167 ahci_ch_init(device_t dev)
1169 struct ahci_channel *ch = device_get_softc(dev);
1172 /* Disable port interrupts */
1173 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1174 /* Setup work areas */
1175 work = ch->dma.work_bus + AHCI_CL_OFFSET;
1176 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
1177 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
1178 work = ch->dma.rfis_bus;
1179 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
1180 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
1181 /* Activate the channel and power/spin up device */
1182 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
1183 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1184 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
1185 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
1192 ahci_ch_deinit(device_t dev)
1194 struct ahci_channel *ch = device_get_softc(dev);
1196 /* Disable port interrupts. */
1197 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1198 /* Reset command register. */
1201 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
1202 /* Allow everything, including partial and slumber modes. */
1203 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
1204 /* Request slumber mode transition and give some time to get there. */
1205 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
1208 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
1213 ahci_ch_suspend(device_t dev)
1215 struct ahci_channel *ch = device_get_softc(dev);
1218 xpt_freeze_simq(ch->sim, 1);
1219 /* Forget about reset. */
1220 if (ch->resetting) {
1222 callout_stop(&ch->reset_timer);
1223 xpt_release_simq(ch->sim, TRUE);
1226 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
1227 ahci_ch_deinit(dev);
1228 mtx_unlock(&ch->mtx);
1233 ahci_ch_resume(device_t dev)
1235 struct ahci_channel *ch = device_get_softc(dev);
1240 xpt_release_simq(ch->sim, TRUE);
1241 mtx_unlock(&ch->mtx);
1245 devclass_t ahcich_devclass;
1246 static device_method_t ahcich_methods[] = {
1247 DEVMETHOD(device_probe, ahci_ch_probe),
1248 DEVMETHOD(device_attach, ahci_ch_attach),
1249 DEVMETHOD(device_detach, ahci_ch_detach),
1250 DEVMETHOD(device_suspend, ahci_ch_suspend),
1251 DEVMETHOD(device_resume, ahci_ch_resume),
1254 static driver_t ahcich_driver = {
1257 sizeof(struct ahci_channel)
1259 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0);
1262 ahci_ch_setleds(device_t dev)
1264 struct ahci_channel *ch;
1265 struct ahci_controller *ctlr;
1270 ctlr = device_get_softc(device_get_parent(dev));
1271 ch = device_get_softc(dev);
1274 for (i = 0; i < AHCI_NUM_LEDS; i++)
1275 val |= ch->leds[i].state << (i * 3);
1277 buf = (ctlr->emloc & 0xffff0000) >> 14;
1278 mtx_lock(&ctlr->em_mtx);
1280 while (ATA_INL(ctlr->r_mem, AHCI_EM_CTL) & (AHCI_EM_TM | AHCI_EM_RST) &&
1284 device_printf(dev, "EM timeout\n");
1285 ATA_OUTL(ctlr->r_mem, buf, (1 << 8) | (0 << 16) | (0 << 24));
1286 ATA_OUTL(ctlr->r_mem, buf + 4, ch->unit | (val << 16));
1287 ATA_OUTL(ctlr->r_mem, AHCI_EM_CTL, AHCI_EM_TM);
1288 mtx_unlock(&ctlr->em_mtx);
1292 ahci_ch_led(void *priv, int onoff)
1294 struct ahci_led *led;
1296 led = (struct ahci_led *)priv;
1299 ahci_ch_setleds(led->dev);
1302 struct ahci_dc_cb_args {
1308 ahci_dmainit(device_t dev)
1310 struct ahci_channel *ch = device_get_softc(dev);
1311 struct ahci_dc_cb_args dcba;
1315 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
1316 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1317 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
1318 0, NULL, NULL, &ch->dma.work_tag))
1320 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
1321 BUS_DMA_ZERO, &ch->dma.work_map))
1323 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1324 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1325 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1328 ch->dma.work_bus = dcba.maddr;
1329 /* FIS receive area. */
1330 if (ch->chcaps & AHCI_P_CMD_FBSCP)
1334 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
1335 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1336 NULL, NULL, rfsize, 1, rfsize,
1337 0, NULL, NULL, &ch->dma.rfis_tag))
1339 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1342 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1343 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1344 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1347 ch->dma.rfis_bus = dcba.maddr;
1349 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
1350 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1352 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
1353 AHCI_SG_ENTRIES, AHCI_PRD_MAX,
1354 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
1360 device_printf(dev, "WARNING - DMA initialization failed\n");
1365 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1367 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
1369 if (!(dcba->error = error))
1370 dcba->maddr = segs[0].ds_addr;
1374 ahci_dmafini(device_t dev)
1376 struct ahci_channel *ch = device_get_softc(dev);
1378 if (ch->dma.data_tag) {
1379 bus_dma_tag_destroy(ch->dma.data_tag);
1380 ch->dma.data_tag = NULL;
1382 if (ch->dma.rfis_bus) {
1383 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1384 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1385 ch->dma.rfis_bus = 0;
1386 ch->dma.rfis_map = NULL;
1387 ch->dma.rfis = NULL;
1389 if (ch->dma.work_bus) {
1390 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1391 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1392 ch->dma.work_bus = 0;
1393 ch->dma.work_map = NULL;
1394 ch->dma.work = NULL;
1396 if (ch->dma.work_tag) {
1397 bus_dma_tag_destroy(ch->dma.work_tag);
1398 ch->dma.work_tag = NULL;
1403 ahci_slotsalloc(device_t dev)
1405 struct ahci_channel *ch = device_get_softc(dev);
1408 /* Alloc and setup command/dma slots */
1409 bzero(ch->slot, sizeof(ch->slot));
1410 for (i = 0; i < ch->numslots; i++) {
1411 struct ahci_slot *slot = &ch->slot[i];
1415 slot->state = AHCI_SLOT_EMPTY;
1417 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1419 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1420 device_printf(ch->dev, "FAILURE - create data_map\n");
1425 ahci_slotsfree(device_t dev)
1427 struct ahci_channel *ch = device_get_softc(dev);
1430 /* Free all dma slots */
1431 for (i = 0; i < ch->numslots; i++) {
1432 struct ahci_slot *slot = &ch->slot[i];
1434 callout_drain(&slot->timeout);
1435 if (slot->dma.data_map) {
1436 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1437 slot->dma.data_map = NULL;
1443 ahci_phy_check_events(device_t dev, u_int32_t serr)
1445 struct ahci_channel *ch = device_get_softc(dev);
1447 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1448 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1449 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1453 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1454 device_printf(dev, "CONNECT requested\n");
1456 device_printf(dev, "DISCONNECT requested\n");
1459 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1461 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1462 cam_sim_path(ch->sim),
1463 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1474 ahci_cpd_check_events(device_t dev)
1476 struct ahci_channel *ch = device_get_softc(dev);
1480 if (ch->pm_level == 0)
1483 status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1484 if ((status & AHCI_P_CMD_CPD) == 0)
1488 if (status & AHCI_P_CMD_CPS) {
1489 device_printf(dev, "COLD CONNECT requested\n");
1491 device_printf(dev, "COLD DISCONNECT requested\n");
1494 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1496 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1497 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1505 ahci_notify_events(device_t dev, u_int32_t status)
1507 struct ahci_channel *ch = device_get_softc(dev);
1508 struct cam_path *dpath;
1511 if (ch->caps & AHCI_CAP_SSNTF)
1512 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1514 device_printf(dev, "SNTF 0x%04x\n", status);
1515 for (i = 0; i < 16; i++) {
1516 if ((status & (1 << i)) == 0)
1518 if (xpt_create_path(&dpath, NULL,
1519 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1520 xpt_async(AC_SCSI_AEN, dpath, NULL);
1521 xpt_free_path(dpath);
1527 ahci_ch_intr_locked(void *data)
1529 device_t dev = (device_t)data;
1530 struct ahci_channel *ch = device_get_softc(dev);
1533 xpt_batch_start(ch->sim);
1535 xpt_batch_done(ch->sim);
1536 mtx_unlock(&ch->mtx);
1540 ahci_ch_pm(void *arg)
1542 device_t dev = (device_t)arg;
1543 struct ahci_channel *ch = device_get_softc(dev);
1546 if (ch->numrslots != 0)
1548 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1549 if (ch->pm_level == 4)
1550 work |= AHCI_P_CMD_PARTIAL;
1552 work |= AHCI_P_CMD_SLUMBER;
1553 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1557 ahci_ch_intr(void *data)
1559 device_t dev = (device_t)data;
1560 struct ahci_channel *ch = device_get_softc(dev);
1561 uint32_t istatus, cstatus, serr = 0, sntf = 0, ok, err;
1562 enum ahci_err_type et;
1563 int i, ccs, port, reset = 0;
1565 /* Read and clear interrupt statuses. */
1566 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1569 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1570 /* Read command statuses. */
1571 if (ch->numtslots != 0)
1572 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1575 if (ch->numrslots != ch->numtslots)
1576 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1577 /* Read SNTF in one of possible ways. */
1578 if ((istatus & AHCI_P_IX_SDB) &&
1579 (ch->pm_present || ch->curr[0].atapi != 0)) {
1580 if (ch->caps & AHCI_CAP_SSNTF)
1581 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1582 else if (ch->fbs_enabled) {
1583 u_int8_t *fis = ch->dma.rfis + 0x58;
1585 for (i = 0; i < 16; i++) {
1586 if (fis[1] & 0x80) {
1593 u_int8_t *fis = ch->dma.rfis + 0x58;
1596 sntf = (1 << (fis[1] & 0x0f));
1599 /* Process PHY events */
1600 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1601 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1602 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1604 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1605 reset = ahci_phy_check_events(dev, serr);
1608 /* Process cold presence detection events */
1609 if ((istatus & AHCI_P_IX_CPD) && !reset)
1610 ahci_cpd_check_events(dev);
1611 /* Process command errors */
1612 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1613 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1614 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1615 >> AHCI_P_CMD_CCS_SHIFT;
1616 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1617 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1618 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1620 if (ch->fbs_enabled) {
1621 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1622 if (fbs & AHCI_P_FBS_SDE) {
1623 port = (fbs & AHCI_P_FBS_DWE)
1624 >> AHCI_P_FBS_DWE_SHIFT;
1626 for (i = 0; i < 16; i++) {
1627 if (ch->numrslotspd[i] == 0)
1631 else if (port != i) {
1638 err = ch->rslots & cstatus;
1644 /* Complete all successfull commands. */
1645 ok = ch->rslots & ~cstatus;
1646 for (i = 0; i < ch->numslots; i++) {
1648 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1650 /* On error, complete the rest of commands with error statuses. */
1653 union ccb *fccb = ch->frozen;
1655 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1656 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1657 xpt_freeze_devq(fccb->ccb_h.path, 1);
1658 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1662 for (i = 0; i < ch->numslots; i++) {
1663 /* XXX: reqests in loading state. */
1664 if (((err >> i) & 1) == 0)
1667 ch->slot[i].ccb->ccb_h.target_id != port)
1669 if (istatus & AHCI_P_IX_TFE) {
1671 /* Task File Error */
1672 if (ch->numtslotspd[
1673 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1674 /* Untagged operation. */
1678 et = AHCI_ERR_INNOCENT;
1680 /* Tagged operation. */
1687 } else if (istatus & AHCI_P_IX_IF) {
1688 if (ch->numtslots == 0 && i != ccs && port != -2)
1689 et = AHCI_ERR_INNOCENT;
1693 et = AHCI_ERR_INVALID;
1694 ahci_end_transaction(&ch->slot[i], et);
1697 * We can't reinit port if there are some other
1698 * commands active, use resume to complete them.
1700 if (ch->rslots != 0 && !ch->recoverycmd)
1701 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1703 /* Process NOTIFY events */
1705 ahci_notify_events(dev, sntf);
1708 /* Must be called with channel locked. */
1710 ahci_check_collision(device_t dev, union ccb *ccb)
1712 struct ahci_channel *ch = device_get_softc(dev);
1713 int t = ccb->ccb_h.target_id;
1715 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1716 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1717 /* Tagged command while we have no supported tag free. */
1718 if (((~ch->oslots) & (0xffffffff >> (32 -
1719 ch->curr[t].tags))) == 0)
1721 /* If we have FBS */
1722 if (ch->fbs_enabled) {
1723 /* Tagged command while untagged are active. */
1724 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1727 /* Tagged command while untagged are active. */
1728 if (ch->numrslots != 0 && ch->numtslots == 0)
1730 /* Tagged command while tagged to other target is active. */
1731 if (ch->numtslots != 0 &&
1732 ch->taggedtarget != ccb->ccb_h.target_id)
1736 /* If we have FBS */
1737 if (ch->fbs_enabled) {
1738 /* Untagged command while tagged are active. */
1739 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1742 /* Untagged command while tagged are active. */
1743 if (ch->numrslots != 0 && ch->numtslots != 0)
1747 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1748 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1749 /* Atomic command while anything active. */
1750 if (ch->numrslots != 0)
1753 /* We have some atomic command running. */
1754 if (ch->aslots != 0)
1759 /* Must be called with channel locked. */
1761 ahci_begin_transaction(device_t dev, union ccb *ccb)
1763 struct ahci_channel *ch = device_get_softc(dev);
1764 struct ahci_slot *slot;
1767 /* Choose empty slot. */
1768 tags = ch->numslots;
1769 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1770 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1771 tags = ch->curr[ccb->ccb_h.target_id].tags;
1776 if (ch->slot[tag].state == AHCI_SLOT_EMPTY)
1781 /* Occupy chosen slot. */
1782 slot = &ch->slot[tag];
1784 /* Stop PM timer. */
1785 if (ch->numrslots == 0 && ch->pm_level > 3)
1786 callout_stop(&ch->pm_timer);
1787 /* Update channel stats. */
1788 ch->oslots |= (1 << slot->slot);
1790 ch->numrslotspd[ccb->ccb_h.target_id]++;
1791 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1792 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1794 ch->numtslotspd[ccb->ccb_h.target_id]++;
1795 ch->taggedtarget = ccb->ccb_h.target_id;
1797 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1798 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1799 ch->aslots |= (1 << slot->slot);
1800 slot->dma.nsegs = 0;
1801 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1802 slot->state = AHCI_SLOT_LOADING;
1803 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1804 ahci_dmasetprd, slot, 0);
1806 ahci_execute_transaction(slot);
1809 /* Locked by busdma engine. */
1811 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1813 struct ahci_slot *slot = arg;
1814 struct ahci_channel *ch = device_get_softc(slot->dev);
1815 struct ahci_cmd_tab *ctp;
1816 struct ahci_dma_prd *prd;
1820 device_printf(slot->dev, "DMA load error\n");
1821 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1824 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1825 /* Get a piece of the workspace for this request */
1826 ctp = (struct ahci_cmd_tab *)
1827 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1828 /* Fill S/G table */
1829 prd = &ctp->prd_tab[0];
1830 for (i = 0; i < nsegs; i++) {
1831 prd[i].dba = htole64(segs[i].ds_addr);
1832 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1834 slot->dma.nsegs = nsegs;
1835 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1836 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1837 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1838 ahci_execute_transaction(slot);
1841 /* Must be called with channel locked. */
1843 ahci_execute_transaction(struct ahci_slot *slot)
1845 device_t dev = slot->dev;
1846 struct ahci_channel *ch = device_get_softc(dev);
1847 struct ahci_cmd_tab *ctp;
1848 struct ahci_cmd_list *clp;
1849 union ccb *ccb = slot->ccb;
1850 int port = ccb->ccb_h.target_id & 0x0f;
1851 int fis_size, i, softreset;
1852 uint8_t *fis = ch->dma.rfis + 0x40;
1855 /* Get a piece of the workspace for this request */
1856 ctp = (struct ahci_cmd_tab *)
1857 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1858 /* Setup the FIS for this request */
1859 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) {
1860 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1861 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1864 /* Setup the command list entry */
1865 clp = (struct ahci_cmd_list *)
1866 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1867 clp->cmd_flags = htole16(
1868 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1869 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1870 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1871 (fis_size / sizeof(u_int32_t)) |
1873 clp->prd_length = htole16(slot->dma.nsegs);
1874 /* Special handling for Soft Reset command. */
1875 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1876 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1877 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1879 /* Kick controller into sane state */
1883 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1886 /* Prepare FIS receive area for check. */
1887 for (i = 0; i < 20; i++)
1893 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1894 (AHCI_CT_SIZE * slot->slot));
1895 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1896 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1897 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1898 BUS_DMASYNC_PREREAD);
1899 /* Set ACTIVE bit for NCQ commands. */
1900 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1901 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1902 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1904 /* If FBS is enabled, set PMP port. */
1905 if (ch->fbs_enabled) {
1906 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1907 (port << AHCI_P_FBS_DEV_SHIFT));
1909 /* Issue command to the controller. */
1910 slot->state = AHCI_SLOT_RUNNING;
1911 ch->rslots |= (1 << slot->slot);
1912 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1913 /* Device reset commands doesn't interrupt. Poll them. */
1914 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1915 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1916 int count, timeout = ccb->ccb_h.timeout * 100;
1917 enum ahci_err_type et = AHCI_ERR_NONE;
1919 for (count = 0; count < timeout; count++) {
1921 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1923 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1926 device_printf(ch->dev,
1927 "Poll error on slot %d, TFD: %04x\n",
1928 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1933 /* Workaround for ATI SB600/SB700 chipsets. */
1934 if (ccb->ccb_h.target_id == 15 &&
1935 pci_get_vendor(device_get_parent(dev)) == 0x1002 &&
1936 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1937 et = AHCI_ERR_TIMEOUT;
1942 /* Marvell controllers do not wait for readyness. */
1943 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 &&
1944 et == AHCI_ERR_NONE) {
1945 while ((val = fis[2]) & ATA_S_BUSY) {
1947 if (count++ >= timeout)
1952 if (timeout && (count >= timeout)) {
1953 device_printf(dev, "Poll timeout on slot %d port %d\n",
1955 device_printf(dev, "is %08x cs %08x ss %08x "
1956 "rs %08x tfd %02x serr %08x cmd %08x\n",
1957 ATA_INL(ch->r_mem, AHCI_P_IS),
1958 ATA_INL(ch->r_mem, AHCI_P_CI),
1959 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1960 ATA_INL(ch->r_mem, AHCI_P_TFD),
1961 ATA_INL(ch->r_mem, AHCI_P_SERR),
1962 ATA_INL(ch->r_mem, AHCI_P_CMD));
1963 et = AHCI_ERR_TIMEOUT;
1966 /* Kick controller into sane state and enable FBS. */
1968 ch->eslots |= (1 << slot->slot);
1969 ahci_end_transaction(slot, et);
1972 /* Start command execution timeout */
1973 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000,
1974 (timeout_t*)ahci_timeout, slot);
1978 /* Must be called with channel locked. */
1980 ahci_process_timeout(device_t dev)
1982 struct ahci_channel *ch = device_get_softc(dev);
1985 mtx_assert(&ch->mtx, MA_OWNED);
1986 /* Handle the rest of commands. */
1987 for (i = 0; i < ch->numslots; i++) {
1988 /* Do we have a running request on slot? */
1989 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1991 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1995 /* Must be called with channel locked. */
1997 ahci_rearm_timeout(device_t dev)
1999 struct ahci_channel *ch = device_get_softc(dev);
2002 mtx_assert(&ch->mtx, MA_OWNED);
2003 for (i = 0; i < ch->numslots; i++) {
2004 struct ahci_slot *slot = &ch->slot[i];
2006 /* Do we have a running request on slot? */
2007 if (slot->state < AHCI_SLOT_RUNNING)
2009 if ((ch->toslots & (1 << i)) == 0)
2011 callout_reset(&slot->timeout,
2012 (int)slot->ccb->ccb_h.timeout * hz / 2000,
2013 (timeout_t*)ahci_timeout, slot);
2017 /* Locked by callout mechanism. */
2019 ahci_timeout(struct ahci_slot *slot)
2021 device_t dev = slot->dev;
2022 struct ahci_channel *ch = device_get_softc(dev);
2027 /* Check for stale timeout. */
2028 if (slot->state < AHCI_SLOT_RUNNING)
2031 /* Check if slot was not being executed last time we checked. */
2032 if (slot->state < AHCI_SLOT_EXECUTING) {
2033 /* Check if slot started executing. */
2034 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
2035 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
2036 >> AHCI_P_CMD_CCS_SHIFT;
2037 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
2038 ch->fbs_enabled || ch->wrongccs)
2039 slot->state = AHCI_SLOT_EXECUTING;
2040 else if ((ch->rslots & (1 << ccs)) == 0) {
2042 slot->state = AHCI_SLOT_EXECUTING;
2045 callout_reset(&slot->timeout,
2046 (int)slot->ccb->ccb_h.timeout * hz / 2000,
2047 (timeout_t*)ahci_timeout, slot);
2051 device_printf(dev, "Timeout on slot %d port %d\n",
2052 slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
2053 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
2054 "serr %08x cmd %08x\n",
2055 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
2056 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
2057 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
2058 ATA_INL(ch->r_mem, AHCI_P_CMD));
2060 /* Handle frozen command. */
2062 union ccb *fccb = ch->frozen;
2064 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2065 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2066 xpt_freeze_devq(fccb->ccb_h.path, 1);
2067 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2071 if (!ch->fbs_enabled && !ch->wrongccs) {
2072 /* Without FBS we know real timeout source. */
2074 /* Handle command with timeout. */
2075 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
2076 /* Handle the rest of commands. */
2077 for (i = 0; i < ch->numslots; i++) {
2078 /* Do we have a running request on slot? */
2079 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2081 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2084 /* With FBS we wait for other commands timeout and pray. */
2085 if (ch->toslots == 0)
2086 xpt_freeze_simq(ch->sim, 1);
2087 ch->toslots |= (1 << slot->slot);
2088 if ((ch->rslots & ~ch->toslots) == 0)
2089 ahci_process_timeout(dev);
2091 device_printf(dev, " ... waiting for slots %08x\n",
2092 ch->rslots & ~ch->toslots);
2096 /* Must be called with channel locked. */
2098 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
2100 device_t dev = slot->dev;
2101 struct ahci_channel *ch = device_get_softc(dev);
2102 union ccb *ccb = slot->ccb;
2103 struct ahci_cmd_list *clp;
2107 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
2108 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2109 clp = (struct ahci_cmd_list *)
2110 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
2111 /* Read result registers to the result struct
2112 * May be incorrect if several commands finished same time,
2113 * so read only when sure or have to.
2115 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2116 struct ata_res *res = &ccb->ataio.res;
2118 if ((et == AHCI_ERR_TFE) ||
2119 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
2120 u_int8_t *fis = ch->dma.rfis + 0x40;
2122 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
2123 BUS_DMASYNC_POSTREAD);
2124 if (ch->fbs_enabled) {
2125 fis += ccb->ccb_h.target_id * 256;
2126 res->status = fis[2];
2127 res->error = fis[3];
2129 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
2132 res->error = tfd >> 8;
2134 res->lba_low = fis[4];
2135 res->lba_mid = fis[5];
2136 res->lba_high = fis[6];
2137 res->device = fis[7];
2138 res->lba_low_exp = fis[8];
2139 res->lba_mid_exp = fis[9];
2140 res->lba_high_exp = fis[10];
2141 res->sector_count = fis[12];
2142 res->sector_count_exp = fis[13];
2145 * Some weird controllers do not return signature in
2146 * FIS receive area. Read it from PxSIG register.
2148 if ((ch->quirks & AHCI_Q_ALTSIG) &&
2149 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2150 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
2151 sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
2152 res->lba_high = sig >> 24;
2153 res->lba_mid = sig >> 16;
2154 res->lba_low = sig >> 8;
2155 res->sector_count = sig;
2158 bzero(res, sizeof(*res));
2159 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
2160 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2161 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2163 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
2166 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2167 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2169 ccb->csio.dxfer_len - le32toh(clp->bytecount);
2172 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2173 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
2174 (ccb->ccb_h.flags & CAM_DIR_IN) ?
2175 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2176 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
2178 if (et != AHCI_ERR_NONE)
2179 ch->eslots |= (1 << slot->slot);
2180 /* In case of error, freeze device for proper recovery. */
2181 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
2182 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2183 xpt_freeze_devq(ccb->ccb_h.path, 1);
2184 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2186 /* Set proper result status. */
2187 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2190 ccb->ccb_h.status |= CAM_REQ_CMP;
2191 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
2192 ccb->csio.scsi_status = SCSI_STATUS_OK;
2194 case AHCI_ERR_INVALID:
2196 ccb->ccb_h.status |= CAM_REQ_INVALID;
2198 case AHCI_ERR_INNOCENT:
2199 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
2203 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2204 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2205 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2207 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2212 if (!ch->recoverycmd) {
2213 xpt_freeze_simq(ch->sim, 1);
2214 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2215 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2217 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
2219 case AHCI_ERR_TIMEOUT:
2220 if (!ch->recoverycmd) {
2221 xpt_freeze_simq(ch->sim, 1);
2222 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2223 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2225 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2229 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
2232 ch->oslots &= ~(1 << slot->slot);
2233 ch->rslots &= ~(1 << slot->slot);
2234 ch->aslots &= ~(1 << slot->slot);
2235 slot->state = AHCI_SLOT_EMPTY;
2237 /* Update channel stats. */
2239 ch->numrslotspd[ccb->ccb_h.target_id]--;
2240 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2241 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
2243 ch->numtslotspd[ccb->ccb_h.target_id]--;
2245 /* Cancel timeout state if request completed normally. */
2246 if (et != AHCI_ERR_TIMEOUT) {
2247 lastto = (ch->toslots == (1 << slot->slot));
2248 ch->toslots &= ~(1 << slot->slot);
2250 xpt_release_simq(ch->sim, TRUE);
2252 /* If it was first request of reset sequence and there is no error,
2253 * proceed to second request. */
2254 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2255 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2256 (ccb->ataio.cmd.control & ATA_A_RESET) &&
2257 et == AHCI_ERR_NONE) {
2258 ccb->ataio.cmd.control &= ~ATA_A_RESET;
2259 ahci_begin_transaction(dev, ccb);
2262 /* If it was our READ LOG command - process it. */
2263 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
2264 ahci_process_read_log(dev, ccb);
2265 /* If it was our REQUEST SENSE command - process it. */
2266 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
2267 ahci_process_request_sense(dev, ccb);
2268 /* If it was NCQ or ATAPI command error, put result on hold. */
2269 } else if (et == AHCI_ERR_NCQ ||
2270 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
2271 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
2272 ch->hold[slot->slot] = ccb;
2276 /* If we have no other active commands, ... */
2277 if (ch->rslots == 0) {
2278 /* if there was fatal error - reset port. */
2279 if (ch->toslots != 0 || ch->fatalerr) {
2282 /* if we have slots in error, we can reinit port. */
2283 if (ch->eslots != 0) {
2288 /* if there commands on hold, we can do READ LOG. */
2289 if (!ch->recoverycmd && ch->numhslots)
2290 ahci_issue_recovery(dev);
2292 /* If all the rest of commands are in timeout - give them chance. */
2293 } else if ((ch->rslots & ~ch->toslots) == 0 &&
2294 et != AHCI_ERR_TIMEOUT)
2295 ahci_rearm_timeout(dev);
2296 /* Unfreeze frozen command. */
2297 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) {
2298 union ccb *fccb = ch->frozen;
2300 ahci_begin_transaction(dev, fccb);
2301 xpt_release_simq(ch->sim, TRUE);
2303 /* Start PM timer. */
2304 if (ch->numrslots == 0 && ch->pm_level > 3 &&
2305 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
2306 callout_schedule(&ch->pm_timer,
2307 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
2312 ahci_issue_recovery(device_t dev)
2314 struct ahci_channel *ch = device_get_softc(dev);
2316 struct ccb_ataio *ataio;
2317 struct ccb_scsiio *csio;
2320 /* Find some held command. */
2321 for (i = 0; i < ch->numslots; i++) {
2325 ccb = xpt_alloc_ccb_nowait();
2327 device_printf(dev, "Unable to allocate recovery command\n");
2329 /* We can't do anything -- complete held commands. */
2330 for (i = 0; i < ch->numslots; i++) {
2331 if (ch->hold[i] == NULL)
2333 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2334 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2335 xpt_done(ch->hold[i]);
2342 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
2343 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2345 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2346 ccb->ccb_h.func_code = XPT_ATA_IO;
2347 ccb->ccb_h.flags = CAM_DIR_IN;
2348 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2349 ataio = &ccb->ataio;
2350 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2351 if (ataio->data_ptr == NULL) {
2354 "Unable to allocate memory for READ LOG command\n");
2357 ataio->dxfer_len = 512;
2358 bzero(&ataio->cmd, sizeof(ataio->cmd));
2359 ataio->cmd.flags = CAM_ATAIO_48BIT;
2360 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2361 ataio->cmd.sector_count = 1;
2362 ataio->cmd.sector_count_exp = 0;
2363 ataio->cmd.lba_low = 0x10;
2364 ataio->cmd.lba_mid = 0;
2365 ataio->cmd.lba_mid_exp = 0;
2368 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2369 ccb->ccb_h.recovery_slot = i;
2370 ccb->ccb_h.func_code = XPT_SCSI_IO;
2371 ccb->ccb_h.flags = CAM_DIR_IN;
2372 ccb->ccb_h.status = 0;
2373 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2375 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2376 csio->dxfer_len = ch->hold[i]->csio.sense_len;
2378 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2379 csio->cdb_io.cdb_bytes[0] = 0x03;
2380 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2382 /* Freeze SIM while doing recovery. */
2383 ch->recoverycmd = 1;
2384 xpt_freeze_simq(ch->sim, 1);
2385 ahci_begin_transaction(dev, ccb);
2389 ahci_process_read_log(device_t dev, union ccb *ccb)
2391 struct ahci_channel *ch = device_get_softc(dev);
2393 struct ata_res *res;
2396 ch->recoverycmd = 0;
2398 data = ccb->ataio.data_ptr;
2399 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2400 (data[0] & 0x80) == 0) {
2401 for (i = 0; i < ch->numslots; i++) {
2404 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2406 if ((data[0] & 0x1F) == i) {
2407 res = &ch->hold[i]->ataio.res;
2408 res->status = data[2];
2409 res->error = data[3];
2410 res->lba_low = data[4];
2411 res->lba_mid = data[5];
2412 res->lba_high = data[6];
2413 res->device = data[7];
2414 res->lba_low_exp = data[8];
2415 res->lba_mid_exp = data[9];
2416 res->lba_high_exp = data[10];
2417 res->sector_count = data[12];
2418 res->sector_count_exp = data[13];
2420 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2421 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2423 xpt_done(ch->hold[i]);
2428 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2429 device_printf(dev, "Error while READ LOG EXT\n");
2430 else if ((data[0] & 0x80) == 0) {
2431 device_printf(dev, "Non-queued command error in READ LOG EXT\n");
2433 for (i = 0; i < ch->numslots; i++) {
2436 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2438 xpt_done(ch->hold[i]);
2443 free(ccb->ataio.data_ptr, M_AHCI);
2445 xpt_release_simq(ch->sim, TRUE);
2449 ahci_process_request_sense(device_t dev, union ccb *ccb)
2451 struct ahci_channel *ch = device_get_softc(dev);
2454 ch->recoverycmd = 0;
2456 i = ccb->ccb_h.recovery_slot;
2457 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2458 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2460 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2461 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2463 xpt_done(ch->hold[i]);
2467 xpt_release_simq(ch->sim, TRUE);
2471 ahci_start(device_t dev, int fbs)
2473 struct ahci_channel *ch = device_get_softc(dev);
2476 /* Clear SATA error register */
2477 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2478 /* Clear any interrupts pending on this channel */
2479 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2480 /* Configure FIS-based switching if supported. */
2481 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2482 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2483 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2484 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2486 /* Start operations on this channel */
2487 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2488 cmd &= ~AHCI_P_CMD_PMA;
2489 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2490 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2494 ahci_stop(device_t dev)
2496 struct ahci_channel *ch = device_get_softc(dev);
2500 /* Kill all activity on this channel */
2501 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2502 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2503 /* Wait for activity stop. */
2507 if (timeout++ > 50000) {
2508 device_printf(dev, "stopping AHCI engine failed\n");
2511 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2516 ahci_clo(device_t dev)
2518 struct ahci_channel *ch = device_get_softc(dev);
2522 /* Issue Command List Override if supported */
2523 if (ch->caps & AHCI_CAP_SCLO) {
2524 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2525 cmd |= AHCI_P_CMD_CLO;
2526 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2530 if (timeout++ > 50000) {
2531 device_printf(dev, "executing CLO failed\n");
2534 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2539 ahci_stop_fr(device_t dev)
2541 struct ahci_channel *ch = device_get_softc(dev);
2545 /* Kill all FIS reception on this channel */
2546 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2547 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2548 /* Wait for FIS reception stop. */
2552 if (timeout++ > 50000) {
2553 device_printf(dev, "stopping AHCI FR engine failed\n");
2556 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2560 ahci_start_fr(device_t dev)
2562 struct ahci_channel *ch = device_get_softc(dev);
2565 /* Start FIS reception on this channel */
2566 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2567 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2571 ahci_wait_ready(device_t dev, int t, int t0)
2573 struct ahci_channel *ch = device_get_softc(dev);
2577 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2578 (ATA_S_BUSY | ATA_S_DRQ)) {
2582 "AHCI reset: device not ready after %dms "
2584 MAX(t, 0) + t0, val);
2592 device_printf(dev, "AHCI reset: device ready after %dms\n",
2598 ahci_reset_to(void *arg)
2601 struct ahci_channel *ch = device_get_softc(dev);
2603 if (ch->resetting == 0)
2606 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0,
2607 (310 - ch->resetting) * 100) == 0) {
2610 xpt_release_simq(ch->sim, TRUE);
2613 if (ch->resetting == 0) {
2616 xpt_release_simq(ch->sim, TRUE);
2619 callout_schedule(&ch->reset_timer, hz / 10);
2623 ahci_reset(device_t dev)
2625 struct ahci_channel *ch = device_get_softc(dev);
2626 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
2629 xpt_freeze_simq(ch->sim, 1);
2631 device_printf(dev, "AHCI reset...\n");
2632 /* Forget about previous reset. */
2633 if (ch->resetting) {
2635 callout_stop(&ch->reset_timer);
2636 xpt_release_simq(ch->sim, TRUE);
2638 /* Requeue freezed command. */
2640 union ccb *fccb = ch->frozen;
2642 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2643 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2644 xpt_freeze_devq(fccb->ccb_h.path, 1);
2645 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2649 /* Kill the engine and requeue all running commands. */
2651 for (i = 0; i < ch->numslots; i++) {
2652 /* Do we have a running request on slot? */
2653 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2655 /* XXX; Commands in loading state. */
2656 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2658 for (i = 0; i < ch->numslots; i++) {
2661 xpt_done(ch->hold[i]);
2665 if (ch->toslots != 0)
2666 xpt_release_simq(ch->sim, TRUE);
2671 /* Tell the XPT about the event */
2672 xpt_async(AC_BUS_RESET, ch->path, NULL);
2673 /* Disable port interrupts */
2674 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2675 /* Reset and reconnect PHY, */
2676 if (!ahci_sata_phy_reset(dev)) {
2679 "AHCI reset: device not found\n");
2681 /* Enable wanted port interrupts */
2682 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2683 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2684 AHCI_P_IX_PRC | AHCI_P_IX_PC));
2685 xpt_release_simq(ch->sim, TRUE);
2689 device_printf(dev, "AHCI reset: device found\n");
2690 /* Wait for clearing busy status. */
2691 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) {
2695 ch->resetting = 310;
2698 /* Enable wanted port interrupts */
2699 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2700 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2701 AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2702 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2703 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2704 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2705 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2707 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev);
2710 xpt_release_simq(ch->sim, TRUE);
2715 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2717 struct ahci_channel *ch = device_get_softc(dev);
2718 u_int8_t *fis = &ctp->cfis[0];
2720 bzero(ctp->cfis, 16);
2721 fis[0] = 0x27; /* host to device */
2722 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2723 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2725 fis[2] = ATA_PACKET_CMD;
2726 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2727 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2730 fis[5] = ccb->csio.dxfer_len;
2731 fis[6] = ccb->csio.dxfer_len >> 8;
2734 fis[15] = ATA_A_4BIT;
2735 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2736 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2737 ctp->acmd, ccb->csio.cdb_len);
2738 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2739 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2741 fis[2] = ccb->ataio.cmd.command;
2742 fis[3] = ccb->ataio.cmd.features;
2743 fis[4] = ccb->ataio.cmd.lba_low;
2744 fis[5] = ccb->ataio.cmd.lba_mid;
2745 fis[6] = ccb->ataio.cmd.lba_high;
2746 fis[7] = ccb->ataio.cmd.device;
2747 fis[8] = ccb->ataio.cmd.lba_low_exp;
2748 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2749 fis[10] = ccb->ataio.cmd.lba_high_exp;
2750 fis[11] = ccb->ataio.cmd.features_exp;
2751 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2755 fis[12] = ccb->ataio.cmd.sector_count;
2756 fis[13] = ccb->ataio.cmd.sector_count_exp;
2758 fis[15] = ATA_A_4BIT;
2760 fis[15] = ccb->ataio.cmd.control;
2766 ahci_sata_connect(struct ahci_channel *ch)
2769 int timeout, found = 0;
2771 /* Wait up to 100ms for "connect well" */
2772 for (timeout = 0; timeout < 1000 ; timeout++) {
2773 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2774 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2776 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2777 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2778 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2780 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2782 device_printf(ch->dev, "SATA offline status=%08x\n",
2787 if (found == 0 && timeout >= 100)
2791 if (timeout >= 1000 || !found) {
2793 device_printf(ch->dev,
2794 "SATA connect timeout time=%dus status=%08x\n",
2795 timeout * 100, status);
2800 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2801 timeout * 100, status);
2803 /* Clear SATA error register */
2804 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2809 ahci_sata_phy_reset(device_t dev)
2811 struct ahci_channel *ch = device_get_softc(dev);
2815 if (ch->listening) {
2816 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2817 val |= AHCI_P_CMD_SUD;
2818 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2821 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2823 val = ATA_SC_SPD_SPEED_GEN1;
2824 else if (sata_rev == 2)
2825 val = ATA_SC_SPD_SPEED_GEN2;
2826 else if (sata_rev == 3)
2827 val = ATA_SC_SPD_SPEED_GEN3;
2830 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2831 ATA_SC_DET_RESET | val |
2832 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2834 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2835 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2836 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2837 if (!ahci_sata_connect(ch)) {
2838 if (ch->caps & AHCI_CAP_SSS) {
2839 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2840 val &= ~AHCI_P_CMD_SUD;
2841 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2843 } else if (ch->pm_level > 0)
2844 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2851 ahci_check_ids(device_t dev, union ccb *ccb)
2853 struct ahci_channel *ch = device_get_softc(dev);
2855 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2856 ccb->ccb_h.status = CAM_TID_INVALID;
2860 if (ccb->ccb_h.target_lun != 0) {
2861 ccb->ccb_h.status = CAM_LUN_INVALID;
2869 ahciaction(struct cam_sim *sim, union ccb *ccb)
2871 device_t dev, parent;
2872 struct ahci_channel *ch;
2874 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2875 ccb->ccb_h.func_code));
2877 ch = (struct ahci_channel *)cam_sim_softc(sim);
2879 switch (ccb->ccb_h.func_code) {
2880 /* Common cases first */
2881 case XPT_ATA_IO: /* Execute the requested I/O operation */
2883 if (ahci_check_ids(dev, ccb))
2885 if (ch->devices == 0 ||
2886 (ch->pm_present == 0 &&
2887 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2888 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2891 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2892 /* Check for command collision. */
2893 if (ahci_check_collision(dev, ccb)) {
2894 /* Freeze command. */
2896 /* We have only one frozen slot, so freeze simq also. */
2897 xpt_freeze_simq(ch->sim, 1);
2900 ahci_begin_transaction(dev, ccb);
2902 case XPT_EN_LUN: /* Enable LUN as a target */
2903 case XPT_TARGET_IO: /* Execute target I/O request */
2904 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2905 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2906 case XPT_ABORT: /* Abort the specified CCB */
2908 ccb->ccb_h.status = CAM_REQ_INVALID;
2910 case XPT_SET_TRAN_SETTINGS:
2912 struct ccb_trans_settings *cts = &ccb->cts;
2913 struct ahci_device *d;
2915 if (ahci_check_ids(dev, ccb))
2917 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2918 d = &ch->curr[ccb->ccb_h.target_id];
2920 d = &ch->user[ccb->ccb_h.target_id];
2921 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2922 d->revision = cts->xport_specific.sata.revision;
2923 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2924 d->mode = cts->xport_specific.sata.mode;
2925 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2926 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2927 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2928 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2929 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2930 ch->pm_present = cts->xport_specific.sata.pm_present;
2931 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2932 d->atapi = cts->xport_specific.sata.atapi;
2933 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2934 d->caps = cts->xport_specific.sata.caps;
2935 ccb->ccb_h.status = CAM_REQ_CMP;
2938 case XPT_GET_TRAN_SETTINGS:
2939 /* Get default/user set transfer settings for the target */
2941 struct ccb_trans_settings *cts = &ccb->cts;
2942 struct ahci_device *d;
2945 if (ahci_check_ids(dev, ccb))
2947 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2948 d = &ch->curr[ccb->ccb_h.target_id];
2950 d = &ch->user[ccb->ccb_h.target_id];
2951 cts->protocol = PROTO_UNSPECIFIED;
2952 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2953 cts->transport = XPORT_SATA;
2954 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2955 cts->proto_specific.valid = 0;
2956 cts->xport_specific.sata.valid = 0;
2957 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2958 (ccb->ccb_h.target_id == 15 ||
2959 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2960 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2961 if (status & 0x0f0) {
2962 cts->xport_specific.sata.revision =
2963 (status & 0x0f0) >> 4;
2964 cts->xport_specific.sata.valid |=
2965 CTS_SATA_VALID_REVISION;
2967 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2969 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2970 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2971 if (ch->caps2 & AHCI_CAP2_APST)
2972 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2974 if ((ch->caps & AHCI_CAP_SNCQ) &&
2975 (ch->quirks & AHCI_Q_NOAA) == 0)
2976 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2977 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2978 cts->xport_specific.sata.caps &=
2979 ch->user[ccb->ccb_h.target_id].caps;
2980 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2982 cts->xport_specific.sata.revision = d->revision;
2983 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2984 cts->xport_specific.sata.caps = d->caps;
2985 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2987 cts->xport_specific.sata.mode = d->mode;
2988 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2989 cts->xport_specific.sata.bytecount = d->bytecount;
2990 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2991 cts->xport_specific.sata.pm_present = ch->pm_present;
2992 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2993 cts->xport_specific.sata.tags = d->tags;
2994 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2995 cts->xport_specific.sata.atapi = d->atapi;
2996 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2997 ccb->ccb_h.status = CAM_REQ_CMP;
3000 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
3001 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
3003 ccb->ccb_h.status = CAM_REQ_CMP;
3005 case XPT_TERM_IO: /* Terminate the I/O process */
3007 ccb->ccb_h.status = CAM_REQ_INVALID;
3009 case XPT_PATH_INQ: /* Path routing inquiry */
3011 struct ccb_pathinq *cpi = &ccb->cpi;
3013 parent = device_get_parent(dev);
3014 cpi->version_num = 1; /* XXX??? */
3015 cpi->hba_inquiry = PI_SDTR_ABLE;
3016 if (ch->caps & AHCI_CAP_SNCQ)
3017 cpi->hba_inquiry |= PI_TAG_ABLE;
3018 if (ch->caps & AHCI_CAP_SPM)
3019 cpi->hba_inquiry |= PI_SATAPM;
3020 cpi->target_sprt = 0;
3021 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
3022 cpi->hba_eng_cnt = 0;
3023 if (ch->caps & AHCI_CAP_SPM)
3024 cpi->max_target = 15;
3026 cpi->max_target = 0;
3028 cpi->initiator_id = 0;
3029 cpi->bus_id = cam_sim_bus(sim);
3030 cpi->base_transfer_speed = 150000;
3031 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
3032 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
3033 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
3034 cpi->unit_number = cam_sim_unit(sim);
3035 cpi->transport = XPORT_SATA;
3036 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
3037 cpi->protocol = PROTO_ATA;
3038 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
3039 cpi->maxio = MAXPHYS;
3040 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
3041 if (pci_get_devid(parent) == 0x43801002)
3042 cpi->maxio = min(cpi->maxio, 128 * 512);
3043 cpi->hba_vendor = pci_get_vendor(parent);
3044 cpi->hba_device = pci_get_device(parent);
3045 cpi->hba_subvendor = pci_get_subvendor(parent);
3046 cpi->hba_subdevice = pci_get_subdevice(parent);
3047 cpi->ccb_h.status = CAM_REQ_CMP;
3051 ccb->ccb_h.status = CAM_REQ_INVALID;
3058 ahcipoll(struct cam_sim *sim)
3060 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
3062 ahci_ch_intr(ch->dev);
3063 if (ch->resetting != 0 &&
3064 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
3065 ch->resetpolldiv = 1000;
3066 ahci_reset_to(ch->dev);