2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
39 #include <sys/mutex.h>
40 #include <machine/stdarg.h>
41 #include <machine/resource.h>
42 #include <machine/bus.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
49 #include <cam/cam_ccb.h>
50 #include <cam/cam_sim.h>
51 #include <cam/cam_xpt_sim.h>
52 #include <cam/cam_debug.h>
54 /* local prototypes */
55 static int ahci_setup_interrupt(device_t dev);
56 static void ahci_intr(void *data);
57 static void ahci_intr_one(void *data);
58 static void ahci_intr_one_edge(void *data);
59 static int ahci_suspend(device_t dev);
60 static int ahci_resume(device_t dev);
61 static int ahci_ch_init(device_t dev);
62 static int ahci_ch_deinit(device_t dev);
63 static int ahci_ch_suspend(device_t dev);
64 static int ahci_ch_resume(device_t dev);
65 static void ahci_ch_pm(void *arg);
66 static void ahci_ch_intr(void *arg);
67 static void ahci_ch_intr_direct(void *arg);
68 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus);
69 static int ahci_ctlr_reset(device_t dev);
70 static int ahci_ctlr_setup(device_t dev);
71 static void ahci_begin_transaction(device_t dev, union ccb *ccb);
72 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
73 static void ahci_execute_transaction(struct ahci_slot *slot);
74 static void ahci_timeout(struct ahci_slot *slot);
75 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
76 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
77 static void ahci_dmainit(device_t dev);
78 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
79 static void ahci_dmafini(device_t dev);
80 static void ahci_slotsalloc(device_t dev);
81 static void ahci_slotsfree(device_t dev);
82 static void ahci_reset(device_t dev);
83 static void ahci_start(device_t dev, int fbs);
84 static void ahci_stop(device_t dev);
85 static void ahci_clo(device_t dev);
86 static void ahci_start_fr(device_t dev);
87 static void ahci_stop_fr(device_t dev);
89 static int ahci_sata_connect(struct ahci_channel *ch);
90 static int ahci_sata_phy_reset(device_t dev);
91 static int ahci_wait_ready(device_t dev, int t, int t0);
93 static void ahci_issue_recovery(device_t dev);
94 static void ahci_process_read_log(device_t dev, union ccb *ccb);
95 static void ahci_process_request_sense(device_t dev, union ccb *ccb);
97 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
98 static void ahcipoll(struct cam_sim *sim);
100 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
102 static const struct {
107 #define AHCI_Q_NOFORCE 1
108 #define AHCI_Q_NOPMP 2
109 #define AHCI_Q_NONCQ 4
111 #define AHCI_Q_2CH 16
112 #define AHCI_Q_4CH 32
113 #define AHCI_Q_EDGEIS 64
114 #define AHCI_Q_SATA2 128
115 #define AHCI_Q_NOBSYRES 256
116 #define AHCI_Q_NOAA 512
117 #define AHCI_Q_NOCOUNT 1024
118 #define AHCI_Q_ALTSIG 2048
119 #define AHCI_Q_NOMSI 4096
121 #define AHCI_Q_BIT_STRING \
137 {0x43801002, 0x00, "AMD SB600", AHCI_Q_NOMSI},
138 {0x43901002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
139 {0x43911002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
140 {0x43921002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
141 {0x43931002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
142 {0x43941002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
143 {0x43951002, 0x00, "AMD SB8x0/SB9x0", 0},
144 {0x78001022, 0x00, "AMD Hudson-2", 0},
145 {0x78011022, 0x00, "AMD Hudson-2", 0},
146 {0x78021022, 0x00, "AMD Hudson-2", 0},
147 {0x78031022, 0x00, "AMD Hudson-2", 0},
148 {0x78041022, 0x00, "AMD Hudson-2", 0},
149 {0x06111b21, 0x00, "ASMedia ASM2106", 0},
150 {0x06121b21, 0x00, "ASMedia ASM1061", 0},
151 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE},
152 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE},
153 {0x26818086, 0x00, "Intel ESB2", 0},
154 {0x26828086, 0x00, "Intel ESB2", 0},
155 {0x26838086, 0x00, "Intel ESB2", 0},
156 {0x27c18086, 0x00, "Intel ICH7", 0},
157 {0x27c38086, 0x00, "Intel ICH7", 0},
158 {0x27c58086, 0x00, "Intel ICH7M", 0},
159 {0x27c68086, 0x00, "Intel ICH7M", 0},
160 {0x28218086, 0x00, "Intel ICH8", 0},
161 {0x28228086, 0x00, "Intel ICH8", 0},
162 {0x28248086, 0x00, "Intel ICH8", 0},
163 {0x28298086, 0x00, "Intel ICH8M", 0},
164 {0x282a8086, 0x00, "Intel ICH8M", 0},
165 {0x29228086, 0x00, "Intel ICH9", 0},
166 {0x29238086, 0x00, "Intel ICH9", 0},
167 {0x29248086, 0x00, "Intel ICH9", 0},
168 {0x29258086, 0x00, "Intel ICH9", 0},
169 {0x29278086, 0x00, "Intel ICH9", 0},
170 {0x29298086, 0x00, "Intel ICH9M", 0},
171 {0x292a8086, 0x00, "Intel ICH9M", 0},
172 {0x292b8086, 0x00, "Intel ICH9M", 0},
173 {0x292c8086, 0x00, "Intel ICH9M", 0},
174 {0x292f8086, 0x00, "Intel ICH9M", 0},
175 {0x294d8086, 0x00, "Intel ICH9", 0},
176 {0x294e8086, 0x00, "Intel ICH9M", 0},
177 {0x3a058086, 0x00, "Intel ICH10", 0},
178 {0x3a228086, 0x00, "Intel ICH10", 0},
179 {0x3a258086, 0x00, "Intel ICH10", 0},
180 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0},
181 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0},
182 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0},
183 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0},
184 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0},
185 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0},
186 {0x1c028086, 0x00, "Intel Cougar Point", 0},
187 {0x1c038086, 0x00, "Intel Cougar Point", 0},
188 {0x1c048086, 0x00, "Intel Cougar Point", 0},
189 {0x1c058086, 0x00, "Intel Cougar Point", 0},
190 {0x1d028086, 0x00, "Intel Patsburg", 0},
191 {0x1d048086, 0x00, "Intel Patsburg", 0},
192 {0x1d068086, 0x00, "Intel Patsburg", 0},
193 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0},
194 {0x1e028086, 0x00, "Intel Panther Point", 0},
195 {0x1e038086, 0x00, "Intel Panther Point", 0},
196 {0x1e048086, 0x00, "Intel Panther Point (RAID)", 0},
197 {0x1e058086, 0x00, "Intel Panther Point (RAID)", 0},
198 {0x1e068086, 0x00, "Intel Panther Point (RAID)", 0},
199 {0x1e078086, 0x00, "Intel Panther Point (RAID)", 0},
200 {0x1e0e8086, 0x00, "Intel Panther Point (RAID)", 0},
201 {0x1e0f8086, 0x00, "Intel Panther Point (RAID)", 0},
202 {0x1f228086, 0x00, "Intel Avoton", 0},
203 {0x1f238086, 0x00, "Intel Avoton", 0},
204 {0x1f248086, 0x00, "Intel Avoton (RAID)", 0},
205 {0x1f258086, 0x00, "Intel Avoton (RAID)", 0},
206 {0x1f268086, 0x00, "Intel Avoton (RAID)", 0},
207 {0x1f278086, 0x00, "Intel Avoton (RAID)", 0},
208 {0x1f2e8086, 0x00, "Intel Avoton (RAID)", 0},
209 {0x1f2f8086, 0x00, "Intel Avoton (RAID)", 0},
210 {0x1f328086, 0x00, "Intel Avoton", 0},
211 {0x1f338086, 0x00, "Intel Avoton", 0},
212 {0x1f348086, 0x00, "Intel Avoton (RAID)", 0},
213 {0x1f358086, 0x00, "Intel Avoton (RAID)", 0},
214 {0x1f368086, 0x00, "Intel Avoton (RAID)", 0},
215 {0x1f378086, 0x00, "Intel Avoton (RAID)", 0},
216 {0x1f3e8086, 0x00, "Intel Avoton (RAID)", 0},
217 {0x1f3f8086, 0x00, "Intel Avoton (RAID)", 0},
218 {0x23a38086, 0x00, "Intel Coleto Creek", 0},
219 {0x28238086, 0x00, "Intel Wellsburg (RAID)", 0},
220 {0x28278086, 0x00, "Intel Wellsburg (RAID)", 0},
221 {0x8c028086, 0x00, "Intel Lynx Point", 0},
222 {0x8c038086, 0x00, "Intel Lynx Point", 0},
223 {0x8c048086, 0x00, "Intel Lynx Point (RAID)", 0},
224 {0x8c058086, 0x00, "Intel Lynx Point (RAID)", 0},
225 {0x8c068086, 0x00, "Intel Lynx Point (RAID)", 0},
226 {0x8c078086, 0x00, "Intel Lynx Point (RAID)", 0},
227 {0x8c0e8086, 0x00, "Intel Lynx Point (RAID)", 0},
228 {0x8c0f8086, 0x00, "Intel Lynx Point (RAID)", 0},
229 {0x8c828086, 0x00, "Intel Wildcat Point", 0},
230 {0x8c838086, 0x00, "Intel Wildcat Point", 0},
231 {0x8c848086, 0x00, "Intel Wildcat Point (RAID)", 0},
232 {0x8c858086, 0x00, "Intel Wildcat Point (RAID)", 0},
233 {0x8c868086, 0x00, "Intel Wildcat Point (RAID)", 0},
234 {0x8c878086, 0x00, "Intel Wildcat Point (RAID)", 0},
235 {0x8c8e8086, 0x00, "Intel Wildcat Point (RAID)", 0},
236 {0x8c8f8086, 0x00, "Intel Wildcat Point (RAID)", 0},
237 {0x8d028086, 0x00, "Intel Wellsburg", 0},
238 {0x8d048086, 0x00, "Intel Wellsburg (RAID)", 0},
239 {0x8d068086, 0x00, "Intel Wellsburg (RAID)", 0},
240 {0x8d628086, 0x00, "Intel Wellsburg", 0},
241 {0x8d648086, 0x00, "Intel Wellsburg (RAID)", 0},
242 {0x8d668086, 0x00, "Intel Wellsburg (RAID)", 0},
243 {0x8d6e8086, 0x00, "Intel Wellsburg (RAID)", 0},
244 {0x9c028086, 0x00, "Intel Lynx Point-LP", 0},
245 {0x9c038086, 0x00, "Intel Lynx Point-LP", 0},
246 {0x9c048086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
247 {0x9c058086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
248 {0x9c068086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
249 {0x9c078086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
250 {0x9c0e8086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
251 {0x9c0f8086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
252 {0x23238086, 0x00, "Intel DH89xxCC", 0},
253 {0x2360197b, 0x00, "JMicron JMB360", 0},
254 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE},
255 {0x2362197b, 0x00, "JMicron JMB362", 0},
256 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE},
257 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE},
258 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE},
259 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE},
260 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH |
262 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH |
263 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
264 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH |
265 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
266 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH |
267 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
268 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS},
269 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_ALTSIG},
270 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2},
271 {0x91251b4b, 0x00, "Marvell 88SE9125", 0},
272 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_ALTSIG},
273 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_ALTSIG},
274 {0x91721b4b, 0x00, "Marvell 88SE9172", 0},
275 {0x91821b4b, 0x00, "Marvell 88SE9182", 0},
276 {0x91831b4b, 0x00, "Marvell 88SS9183", 0},
277 {0x91a01b4b, 0x00, "Marvell 88SE91Ax", 0},
278 {0x92151b4b, 0x00, "Marvell 88SE9215", 0},
279 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_ALTSIG},
280 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_ALTSIG},
281 {0x92351b4b, 0x00, "Marvell 88SE9235", 0},
282 {0x06201103, 0x00, "HighPoint RocketRAID 620", 0},
283 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", 0},
284 {0x06221103, 0x00, "HighPoint RocketRAID 622", 0},
285 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", 0},
286 {0x06401103, 0x00, "HighPoint RocketRAID 640", 0},
287 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", 0},
288 {0x06441103, 0x00, "HighPoint RocketRAID 644", 0},
289 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", 0},
290 {0x06411103, 0x00, "HighPoint RocketRAID 640L", 0},
291 {0x06421103, 0x00, "HighPoint RocketRAID 642L", 0},
292 {0x06451103, 0x00, "HighPoint RocketRAID 644L", 0},
293 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
294 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
295 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
296 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
297 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
298 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
299 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
300 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
301 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
302 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
303 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
304 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
305 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
306 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
307 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
308 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
309 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
310 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
311 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
312 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
313 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
314 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
315 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
316 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
317 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
318 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
319 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
320 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
321 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
322 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
323 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
324 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
325 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
326 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
327 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
328 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
329 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
330 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
331 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
332 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
333 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
334 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
335 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
336 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
337 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
338 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
339 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
340 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
341 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
342 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
343 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
344 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
345 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
346 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
347 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
348 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
349 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
350 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
351 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA},
352 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
353 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
354 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
355 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
356 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
357 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
358 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
359 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
360 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
361 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
362 {0x3781105a, 0x00, "Promise TX8660", 0},
363 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
364 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
365 {0x11841039, 0x00, "SiS 966", 0},
366 {0x11851039, 0x00, "SiS 968", 0},
367 {0x01861039, 0x00, "SiS 968", 0},
368 {0x00000000, 0x00, NULL, 0}
371 #define recovery_type spriv_field0
372 #define RECOVERY_NONE 0
373 #define RECOVERY_READ_LOG 1
374 #define RECOVERY_REQUEST_SENSE 2
375 #define recovery_slot spriv_field1
377 static int force_ahci = 1;
378 TUNABLE_INT("hw.ahci.force", &force_ahci);
381 ahci_probe(device_t dev)
385 uint32_t devid = pci_get_devid(dev);
386 uint8_t revid = pci_get_revid(dev);
389 * Ensure it is not a PCI bridge (some vendors use
390 * the same PID and VID in PCI bridge and AHCI cards).
392 if (pci_get_class(dev) == PCIC_BRIDGE)
395 /* Is this a possible AHCI candidate? */
396 if (pci_get_class(dev) == PCIC_STORAGE &&
397 pci_get_subclass(dev) == PCIS_STORAGE_SATA &&
398 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0)
400 /* Is this a known AHCI chip? */
401 for (i = 0; ahci_ids[i].id != 0; i++) {
402 if (ahci_ids[i].id == devid &&
403 ahci_ids[i].rev <= revid &&
404 (valid || (force_ahci == 1 &&
405 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) {
406 /* Do not attach JMicrons with single PCI function. */
407 if (pci_get_vendor(dev) == 0x197b &&
408 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
410 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
412 device_set_desc_copy(dev, buf);
413 return (BUS_PROBE_VENDOR);
418 device_set_desc_copy(dev, "AHCI SATA controller");
419 return (BUS_PROBE_VENDOR);
423 ahci_ata_probe(device_t dev)
427 uint32_t devid = pci_get_devid(dev);
428 uint8_t revid = pci_get_revid(dev);
430 if ((intptr_t)device_get_ivars(dev) >= 0)
432 /* Is this a known AHCI chip? */
433 for (i = 0; ahci_ids[i].id != 0; i++) {
434 if (ahci_ids[i].id == devid &&
435 ahci_ids[i].rev <= revid) {
436 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
438 device_set_desc_copy(dev, buf);
439 return (BUS_PROBE_VENDOR);
442 device_set_desc_copy(dev, "AHCI SATA controller");
443 return (BUS_PROBE_VENDOR);
447 ahci_attach(device_t dev)
449 struct ahci_controller *ctlr = device_get_softc(dev);
451 int error, unit, speed, i;
453 uint32_t devid = pci_get_devid(dev);
454 uint8_t revid = pci_get_revid(dev);
459 while (ahci_ids[i].id != 0 &&
460 (ahci_ids[i].id != devid ||
461 ahci_ids[i].rev > revid))
463 ctlr->quirks = ahci_ids[i].quirks;
464 resource_int_value(device_get_name(dev),
465 device_get_unit(dev), "ccc", &ctlr->ccc);
466 /* if we have a memory BAR(5) we are likely on an AHCI part */
467 ctlr->r_rid = PCIR_BAR(5);
468 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
469 &ctlr->r_rid, RF_ACTIVE)))
471 /* Setup our own memory management for channels. */
472 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
473 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
474 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
475 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
476 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
477 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
480 if ((error = rman_manage_region(&ctlr->sc_iomem,
481 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
482 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
483 rman_fini(&ctlr->sc_iomem);
486 pci_enable_busmaster(dev);
487 /* Reset controller */
488 if ((error = ahci_ctlr_reset(dev)) != 0) {
489 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
490 rman_fini(&ctlr->sc_iomem);
493 /* Get the HW capabilities */
494 version = ATA_INL(ctlr->r_mem, AHCI_VS);
495 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
496 if (version >= 0x00010200)
497 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
498 if (ctlr->caps & AHCI_CAP_EMS)
499 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
500 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
502 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */
503 if ((ctlr->quirks & AHCI_Q_ALTSIG) &&
504 (ctlr->caps & AHCI_CAP_SPM) == 0)
505 ctlr->quirks |= AHCI_Q_NOBSYRES;
507 if (ctlr->quirks & AHCI_Q_1CH) {
508 ctlr->caps &= ~AHCI_CAP_NPMASK;
509 ctlr->ichannels &= 0x01;
511 if (ctlr->quirks & AHCI_Q_2CH) {
512 ctlr->caps &= ~AHCI_CAP_NPMASK;
514 ctlr->ichannels &= 0x03;
516 if (ctlr->quirks & AHCI_Q_4CH) {
517 ctlr->caps &= ~AHCI_CAP_NPMASK;
519 ctlr->ichannels &= 0x0f;
521 ctlr->channels = MAX(flsl(ctlr->ichannels),
522 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
523 if (ctlr->quirks & AHCI_Q_NOPMP)
524 ctlr->caps &= ~AHCI_CAP_SPM;
525 if (ctlr->quirks & AHCI_Q_NONCQ)
526 ctlr->caps &= ~AHCI_CAP_SNCQ;
527 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
529 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
531 /* Create controller-wide DMA tag. */
532 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
533 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
534 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
535 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
536 0, NULL, NULL, &ctlr->dma_tag)) {
537 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
539 rman_fini(&ctlr->sc_iomem);
543 ahci_ctlr_setup(dev);
544 /* Setup interrupts. */
545 if ((error = ahci_setup_interrupt(dev)) != 0) {
546 bus_dma_tag_destroy(ctlr->dma_tag);
547 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
548 rman_fini(&ctlr->sc_iomem);
552 for (u = ctlr->ichannels; u != 0; u >>= 1)
554 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
555 resource_int_value(device_get_name(dev), device_get_unit(dev),
556 "direct", &ctlr->direct);
557 /* Announce HW capabilities. */
558 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
560 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
561 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
562 ((version >> 4) & 0xf0) + (version & 0x0f),
563 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
564 ((speed == 1) ? "1.5":((speed == 2) ? "3":
565 ((speed == 3) ? "6":"?"))),
566 (ctlr->caps & AHCI_CAP_SPM) ?
567 "supported" : "not supported",
568 (ctlr->caps & AHCI_CAP_FBSS) ?
570 if (ctlr->quirks != 0) {
571 device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
575 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
576 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
577 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
578 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
579 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
580 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
581 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
582 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
583 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
584 ((speed == 1) ? "1.5":((speed == 2) ? "3":
585 ((speed == 3) ? "6":"?"))));
586 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
587 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
588 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
589 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
590 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
591 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
592 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
593 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
594 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
595 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
596 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
597 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
599 if (bootverbose && version >= 0x00010200) {
600 device_printf(dev, "Caps2:%s%s%s%s%s%s\n",
601 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
602 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
603 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
604 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
605 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
606 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
608 /* Attach all channels on this controller */
609 for (unit = 0; unit < ctlr->channels; unit++) {
610 child = device_add_child(dev, "ahcich", -1);
612 device_printf(dev, "failed to add channel device\n");
615 device_set_ivars(child, (void *)(intptr_t)unit);
616 if ((ctlr->ichannels & (1 << unit)) == 0)
617 device_disable(child);
619 if (ctlr->caps & AHCI_CAP_EMS) {
620 child = device_add_child(dev, "ahciem", -1);
622 device_printf(dev, "failed to add enclosure device\n");
624 device_set_ivars(child, (void *)(intptr_t)-1);
626 bus_generic_attach(dev);
631 ahci_detach(device_t dev)
633 struct ahci_controller *ctlr = device_get_softc(dev);
636 /* Detach & delete all children */
637 device_delete_children(dev);
639 /* Free interrupts. */
640 for (i = 0; i < ctlr->numirqs; i++) {
641 if (ctlr->irqs[i].r_irq) {
642 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
643 ctlr->irqs[i].handle);
644 bus_release_resource(dev, SYS_RES_IRQ,
645 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
648 pci_release_msi(dev);
649 bus_dma_tag_destroy(ctlr->dma_tag);
651 rman_fini(&ctlr->sc_iomem);
653 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
658 ahci_ctlr_reset(device_t dev)
660 struct ahci_controller *ctlr = device_get_softc(dev);
663 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 &&
664 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
665 pci_write_config(dev, 0x92, 0x01, 1);
666 /* Enable AHCI mode */
667 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
668 /* Reset AHCI controller */
669 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
670 for (timeout = 1000; timeout > 0; timeout--) {
672 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
676 device_printf(dev, "AHCI controller reset failure\n");
679 /* Reenable AHCI mode */
680 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
685 ahci_ctlr_setup(device_t dev)
687 struct ahci_controller *ctlr = device_get_softc(dev);
688 /* Clear interrupts */
689 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
692 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
693 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
694 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
695 (4 << AHCI_CCCC_CC_SHIFT) |
697 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
698 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
701 "CCC with %dms/4cmd enabled on vector %d\n",
702 ctlr->ccc, ctlr->cccv);
705 /* Enable AHCI interrupts */
706 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
707 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
712 ahci_suspend(device_t dev)
714 struct ahci_controller *ctlr = device_get_softc(dev);
716 bus_generic_suspend(dev);
717 /* Disable interupts, so the state change(s) doesn't trigger */
718 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
719 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
724 ahci_resume(device_t dev)
728 if ((res = ahci_ctlr_reset(dev)) != 0)
730 ahci_ctlr_setup(dev);
731 return (bus_generic_resume(dev));
735 ahci_setup_interrupt(device_t dev)
737 struct ahci_controller *ctlr = device_get_softc(dev);
742 if (ctlr->quirks & AHCI_Q_NOMSI)
744 resource_int_value(device_get_name(dev),
745 device_get_unit(dev), "msi", &ctlr->msi);
749 else if (ctlr->msi == 1)
750 ctlr->msi = min(1, pci_msi_count(dev));
751 else if (ctlr->msi > 1) {
753 ctlr->numirqs = pci_msi_count(dev);
755 /* Allocate MSI if needed/present. */
756 if (ctlr->msi && pci_alloc_msi(dev, &ctlr->numirqs) != 0) {
760 /* Check for single MSI vector fallback. */
761 if (ctlr->numirqs > 1 &&
762 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
763 device_printf(dev, "Falling back to one MSI\n");
767 /* Ensure we don't overrun irqs. */
768 if (ctlr->numirqs > AHCI_MAX_IRQS) {
769 device_printf(dev, "Too many irqs %d > %d (clamping)\n",
770 ctlr->numirqs, AHCI_MAX_IRQS);
771 ctlr->numirqs = AHCI_MAX_IRQS;
774 /* Allocate all IRQs. */
775 for (i = 0; i < ctlr->numirqs; i++) {
776 ctlr->irqs[i].ctlr = ctlr;
777 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
778 if (ctlr->numirqs == 1 || i >= ctlr->channels ||
779 (ctlr->ccc && i == ctlr->cccv))
780 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
781 else if (i == ctlr->numirqs - 1)
782 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
784 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
785 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
786 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
787 device_printf(dev, "unable to map interrupt\n");
790 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
791 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
792 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
794 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
795 /* SOS XXX release r_irq */
796 device_printf(dev, "unable to setup interrupt\n");
799 if (ctlr->numirqs > 1) {
800 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
801 ctlr->irqs[i].handle,
802 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
810 * Common case interrupt handler.
813 ahci_intr(void *data)
815 struct ahci_controller_irq *irq = data;
816 struct ahci_controller *ctlr = irq->ctlr;
817 u_int32_t is, ise = 0;
821 if (irq->mode == AHCI_IRQ_MODE_ALL) {
824 is = ctlr->ichannels;
826 is = ATA_INL(ctlr->r_mem, AHCI_IS);
827 } else { /* AHCI_IRQ_MODE_AFTER */
828 unit = irq->r_irq_rid - 1;
829 is = ATA_INL(ctlr->r_mem, AHCI_IS);
831 /* CCC interrupt is edge triggered. */
833 ise = 1 << ctlr->cccv;
834 /* Some controllers have edge triggered IS. */
835 if (ctlr->quirks & AHCI_Q_EDGEIS)
838 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
839 for (; unit < ctlr->channels; unit++) {
840 if ((is & (1 << unit)) != 0 &&
841 (arg = ctlr->interrupt[unit].argument)) {
842 ctlr->interrupt[unit].function(arg);
845 /* AHCI declares level triggered IS. */
846 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
847 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
851 * Simplified interrupt handler for multivector MSI mode.
854 ahci_intr_one(void *data)
856 struct ahci_controller_irq *irq = data;
857 struct ahci_controller *ctlr = irq->ctlr;
861 unit = irq->r_irq_rid - 1;
862 if ((arg = ctlr->interrupt[unit].argument))
863 ctlr->interrupt[unit].function(arg);
864 /* AHCI declares level triggered IS. */
865 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
869 ahci_intr_one_edge(void *data)
871 struct ahci_controller_irq *irq = data;
872 struct ahci_controller *ctlr = irq->ctlr;
876 unit = irq->r_irq_rid - 1;
877 /* Some controllers have edge triggered IS. */
878 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
879 if ((arg = ctlr->interrupt[unit].argument))
880 ctlr->interrupt[unit].function(arg);
883 static struct resource *
884 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
885 u_long start, u_long end, u_long count, u_int flags)
887 struct ahci_controller *ctlr = device_get_softc(dev);
888 struct resource *res;
890 int offset, size, unit;
892 unit = (intptr_t)device_get_ivars(child);
897 offset = AHCI_OFFSET + (unit << 7);
899 } else if (*rid == 0) {
900 offset = AHCI_EM_CTL;
903 offset = (ctlr->emloc & 0xffff0000) >> 14;
904 size = (ctlr->emloc & 0x0000ffff) << 2;
906 if (*rid == 2 && (ctlr->capsem &
907 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0)
913 st = rman_get_start(ctlr->r_mem);
914 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
915 st + offset + size - 1, size, RF_ACTIVE, child);
917 bus_space_handle_t bsh;
919 bsh = rman_get_bushandle(ctlr->r_mem);
920 bst = rman_get_bustag(ctlr->r_mem);
921 bus_space_subregion(bst, bsh, offset, 128, &bsh);
922 rman_set_bushandle(res, bsh);
923 rman_set_bustag(res, bst);
927 if (*rid == ATA_IRQ_RID)
928 res = ctlr->irqs[0].r_irq;
935 ahci_release_resource(device_t dev, device_t child, int type, int rid,
941 rman_release_resource(r);
944 if (rid != ATA_IRQ_RID)
952 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
953 int flags, driver_filter_t *filter, driver_intr_t *function,
954 void *argument, void **cookiep)
956 struct ahci_controller *ctlr = device_get_softc(dev);
957 int unit = (intptr_t)device_get_ivars(child);
959 if (filter != NULL) {
960 printf("ahci.c: we cannot use a filter here\n");
963 ctlr->interrupt[unit].function = function;
964 ctlr->interrupt[unit].argument = argument;
969 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
972 struct ahci_controller *ctlr = device_get_softc(dev);
973 int unit = (intptr_t)device_get_ivars(child);
975 ctlr->interrupt[unit].function = NULL;
976 ctlr->interrupt[unit].argument = NULL;
981 ahci_print_child(device_t dev, device_t child)
985 retval = bus_print_child_header(dev, child);
986 channel = (int)(intptr_t)device_get_ivars(child);
988 retval += printf(" at channel %d", channel);
989 retval += bus_print_child_footer(dev, child);
994 ahci_child_location_str(device_t dev, device_t child, char *buf,
999 channel = (int)(intptr_t)device_get_ivars(child);
1001 snprintf(buf, buflen, "channel=%d", channel);
1005 static bus_dma_tag_t
1006 ahci_get_dma_tag(device_t dev, device_t child)
1008 struct ahci_controller *ctlr = device_get_softc(dev);
1010 return (ctlr->dma_tag);
1013 devclass_t ahci_devclass;
1014 static device_method_t ahci_methods[] = {
1015 DEVMETHOD(device_probe, ahci_probe),
1016 DEVMETHOD(device_attach, ahci_attach),
1017 DEVMETHOD(device_detach, ahci_detach),
1018 DEVMETHOD(device_suspend, ahci_suspend),
1019 DEVMETHOD(device_resume, ahci_resume),
1020 DEVMETHOD(bus_print_child, ahci_print_child),
1021 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
1022 DEVMETHOD(bus_release_resource, ahci_release_resource),
1023 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
1024 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
1025 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
1026 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag),
1029 static driver_t ahci_driver = {
1032 sizeof(struct ahci_controller)
1034 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, NULL, NULL);
1035 static device_method_t ahci_ata_methods[] = {
1036 DEVMETHOD(device_probe, ahci_ata_probe),
1037 DEVMETHOD(device_attach, ahci_attach),
1038 DEVMETHOD(device_detach, ahci_detach),
1039 DEVMETHOD(device_suspend, ahci_suspend),
1040 DEVMETHOD(device_resume, ahci_resume),
1041 DEVMETHOD(bus_print_child, ahci_print_child),
1042 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
1043 DEVMETHOD(bus_release_resource, ahci_release_resource),
1044 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
1045 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
1046 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
1049 static driver_t ahci_ata_driver = {
1052 sizeof(struct ahci_controller)
1054 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, NULL, NULL);
1055 MODULE_VERSION(ahci, 1);
1056 MODULE_DEPEND(ahci, cam, 1, 1, 1);
1059 ahci_ch_probe(device_t dev)
1062 device_set_desc_copy(dev, "AHCI channel");
1067 ahci_ch_attach(device_t dev)
1069 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
1070 struct ahci_channel *ch = device_get_softc(dev);
1071 struct cam_devq *devq;
1072 int rid, error, i, sata_rev = 0;
1076 ch->unit = (intptr_t)device_get_ivars(dev);
1077 ch->caps = ctlr->caps;
1078 ch->caps2 = ctlr->caps2;
1079 ch->quirks = ctlr->quirks;
1080 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
1081 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
1082 resource_int_value(device_get_name(dev),
1083 device_get_unit(dev), "pm_level", &ch->pm_level);
1084 STAILQ_INIT(&ch->doneq);
1085 if (ch->pm_level > 3)
1086 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
1087 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
1088 /* Limit speed for my onboard JMicron external port.
1089 * It is not eSATA really. */
1090 if (pci_get_devid(ctlr->dev) == 0x2363197b &&
1091 pci_get_subvendor(ctlr->dev) == 0x1043 &&
1092 pci_get_subdevice(ctlr->dev) == 0x81e4 &&
1095 if (ch->quirks & AHCI_Q_SATA2)
1097 resource_int_value(device_get_name(dev),
1098 device_get_unit(dev), "sata_rev", &sata_rev);
1099 for (i = 0; i < 16; i++) {
1100 ch->user[i].revision = sata_rev;
1101 ch->user[i].mode = 0;
1102 ch->user[i].bytecount = 8192;
1103 ch->user[i].tags = ch->numslots;
1104 ch->user[i].caps = 0;
1105 ch->curr[i] = ch->user[i];
1107 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
1108 CTS_SATA_CAPS_H_APST |
1109 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
1111 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
1115 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1119 ahci_slotsalloc(dev);
1123 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1124 &rid, RF_SHAREABLE | RF_ACTIVE))) {
1125 device_printf(dev, "Unable to map interrupt\n");
1129 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
1130 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
1132 device_printf(dev, "Unable to setup interrupt\n");
1136 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
1137 version = ATA_INL(ctlr->r_mem, AHCI_VS);
1138 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
1139 ch->chcaps |= AHCI_P_CMD_FBSCP;
1140 if (ch->caps2 & AHCI_CAP2_SDS)
1141 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
1143 device_printf(dev, "Caps:%s%s%s%s%s%s\n",
1144 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
1145 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
1146 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
1147 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
1148 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"",
1149 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":"");
1151 /* Create the device queue for our SIM. */
1152 devq = cam_simq_alloc(ch->numslots);
1154 device_printf(dev, "Unable to allocate simq\n");
1158 /* Construct SIM entry */
1159 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
1160 device_get_unit(dev), &ch->mtx,
1161 min(2, ch->numslots),
1162 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
1164 if (ch->sim == NULL) {
1165 cam_simq_free(devq);
1166 device_printf(dev, "unable to allocate sim\n");
1170 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
1171 device_printf(dev, "unable to register xpt bus\n");
1175 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
1176 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1177 device_printf(dev, "unable to create path\n");
1181 if (ch->pm_level > 3) {
1182 callout_reset(&ch->pm_timer,
1183 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
1186 mtx_unlock(&ch->mtx);
1190 xpt_bus_deregister(cam_sim_path(ch->sim));
1192 cam_sim_free(ch->sim, /*free_devq*/TRUE);
1194 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
1196 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
1197 mtx_unlock(&ch->mtx);
1198 mtx_destroy(&ch->mtx);
1203 ahci_ch_detach(device_t dev)
1205 struct ahci_channel *ch = device_get_softc(dev);
1208 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
1209 /* Forget about reset. */
1210 if (ch->resetting) {
1212 xpt_release_simq(ch->sim, TRUE);
1214 xpt_free_path(ch->path);
1215 xpt_bus_deregister(cam_sim_path(ch->sim));
1216 cam_sim_free(ch->sim, /*free_devq*/TRUE);
1217 mtx_unlock(&ch->mtx);
1219 if (ch->pm_level > 3)
1220 callout_drain(&ch->pm_timer);
1221 callout_drain(&ch->reset_timer);
1222 bus_teardown_intr(dev, ch->r_irq, ch->ih);
1223 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
1225 ahci_ch_deinit(dev);
1226 ahci_slotsfree(dev);
1229 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
1230 mtx_destroy(&ch->mtx);
1235 ahci_ch_init(device_t dev)
1237 struct ahci_channel *ch = device_get_softc(dev);
1240 /* Disable port interrupts */
1241 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1242 /* Setup work areas */
1243 work = ch->dma.work_bus + AHCI_CL_OFFSET;
1244 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
1245 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
1246 work = ch->dma.rfis_bus;
1247 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
1248 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
1249 /* Activate the channel and power/spin up device */
1250 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
1251 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1252 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
1253 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
1260 ahci_ch_deinit(device_t dev)
1262 struct ahci_channel *ch = device_get_softc(dev);
1264 /* Disable port interrupts. */
1265 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1266 /* Reset command register. */
1269 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
1270 /* Allow everything, including partial and slumber modes. */
1271 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
1272 /* Request slumber mode transition and give some time to get there. */
1273 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
1276 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
1281 ahci_ch_suspend(device_t dev)
1283 struct ahci_channel *ch = device_get_softc(dev);
1286 xpt_freeze_simq(ch->sim, 1);
1287 /* Forget about reset. */
1288 if (ch->resetting) {
1290 callout_stop(&ch->reset_timer);
1291 xpt_release_simq(ch->sim, TRUE);
1294 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
1295 ahci_ch_deinit(dev);
1296 mtx_unlock(&ch->mtx);
1301 ahci_ch_resume(device_t dev)
1303 struct ahci_channel *ch = device_get_softc(dev);
1308 xpt_release_simq(ch->sim, TRUE);
1309 mtx_unlock(&ch->mtx);
1313 devclass_t ahcich_devclass;
1314 static device_method_t ahcich_methods[] = {
1315 DEVMETHOD(device_probe, ahci_ch_probe),
1316 DEVMETHOD(device_attach, ahci_ch_attach),
1317 DEVMETHOD(device_detach, ahci_ch_detach),
1318 DEVMETHOD(device_suspend, ahci_ch_suspend),
1319 DEVMETHOD(device_resume, ahci_ch_resume),
1322 static driver_t ahcich_driver = {
1325 sizeof(struct ahci_channel)
1327 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL);
1329 struct ahci_dc_cb_args {
1335 ahci_dmainit(device_t dev)
1337 struct ahci_channel *ch = device_get_softc(dev);
1338 struct ahci_dc_cb_args dcba;
1342 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
1343 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1344 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
1345 0, NULL, NULL, &ch->dma.work_tag))
1347 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
1348 BUS_DMA_ZERO, &ch->dma.work_map))
1350 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1351 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1352 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1355 ch->dma.work_bus = dcba.maddr;
1356 /* FIS receive area. */
1357 if (ch->chcaps & AHCI_P_CMD_FBSCP)
1361 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
1362 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1363 NULL, NULL, rfsize, 1, rfsize,
1364 0, NULL, NULL, &ch->dma.rfis_tag))
1366 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1369 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1370 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1371 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1374 ch->dma.rfis_bus = dcba.maddr;
1376 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
1377 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1379 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
1380 AHCI_SG_ENTRIES, AHCI_PRD_MAX,
1381 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
1387 device_printf(dev, "WARNING - DMA initialization failed\n");
1392 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1394 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
1396 if (!(dcba->error = error))
1397 dcba->maddr = segs[0].ds_addr;
1401 ahci_dmafini(device_t dev)
1403 struct ahci_channel *ch = device_get_softc(dev);
1405 if (ch->dma.data_tag) {
1406 bus_dma_tag_destroy(ch->dma.data_tag);
1407 ch->dma.data_tag = NULL;
1409 if (ch->dma.rfis_bus) {
1410 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1411 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1412 ch->dma.rfis_bus = 0;
1413 ch->dma.rfis_map = NULL;
1414 ch->dma.rfis = NULL;
1416 if (ch->dma.work_bus) {
1417 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1418 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1419 ch->dma.work_bus = 0;
1420 ch->dma.work_map = NULL;
1421 ch->dma.work = NULL;
1423 if (ch->dma.work_tag) {
1424 bus_dma_tag_destroy(ch->dma.work_tag);
1425 ch->dma.work_tag = NULL;
1430 ahci_slotsalloc(device_t dev)
1432 struct ahci_channel *ch = device_get_softc(dev);
1435 /* Alloc and setup command/dma slots */
1436 bzero(ch->slot, sizeof(ch->slot));
1437 for (i = 0; i < ch->numslots; i++) {
1438 struct ahci_slot *slot = &ch->slot[i];
1442 slot->state = AHCI_SLOT_EMPTY;
1444 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1446 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1447 device_printf(ch->dev, "FAILURE - create data_map\n");
1452 ahci_slotsfree(device_t dev)
1454 struct ahci_channel *ch = device_get_softc(dev);
1457 /* Free all dma slots */
1458 for (i = 0; i < ch->numslots; i++) {
1459 struct ahci_slot *slot = &ch->slot[i];
1461 callout_drain(&slot->timeout);
1462 if (slot->dma.data_map) {
1463 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1464 slot->dma.data_map = NULL;
1470 ahci_phy_check_events(device_t dev, u_int32_t serr)
1472 struct ahci_channel *ch = device_get_softc(dev);
1474 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1475 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1476 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1480 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1481 device_printf(dev, "CONNECT requested\n");
1483 device_printf(dev, "DISCONNECT requested\n");
1486 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1488 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1489 cam_sim_path(ch->sim),
1490 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1501 ahci_cpd_check_events(device_t dev)
1503 struct ahci_channel *ch = device_get_softc(dev);
1507 if (ch->pm_level == 0)
1510 status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1511 if ((status & AHCI_P_CMD_CPD) == 0)
1515 if (status & AHCI_P_CMD_CPS) {
1516 device_printf(dev, "COLD CONNECT requested\n");
1518 device_printf(dev, "COLD DISCONNECT requested\n");
1521 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1523 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1524 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1532 ahci_notify_events(device_t dev, u_int32_t status)
1534 struct ahci_channel *ch = device_get_softc(dev);
1535 struct cam_path *dpath;
1538 if (ch->caps & AHCI_CAP_SSNTF)
1539 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1541 device_printf(dev, "SNTF 0x%04x\n", status);
1542 for (i = 0; i < 16; i++) {
1543 if ((status & (1 << i)) == 0)
1545 if (xpt_create_path(&dpath, NULL,
1546 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1547 xpt_async(AC_SCSI_AEN, dpath, NULL);
1548 xpt_free_path(dpath);
1554 ahci_done(struct ahci_channel *ch, union ccb *ccb)
1557 mtx_assert(&ch->mtx, MA_OWNED);
1558 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 ||
1564 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe);
1568 ahci_ch_intr(void *arg)
1570 device_t dev = (device_t)arg;
1571 struct ahci_channel *ch = device_get_softc(dev);
1574 /* Read interrupt statuses. */
1575 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1580 ahci_ch_intr_main(ch, istatus);
1581 mtx_unlock(&ch->mtx);
1585 ahci_ch_intr_direct(void *arg)
1587 device_t dev = (device_t)arg;
1588 struct ahci_channel *ch = device_get_softc(dev);
1589 struct ccb_hdr *ccb_h;
1591 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq);
1593 /* Read interrupt statuses. */
1594 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1600 ahci_ch_intr_main(ch, istatus);
1603 * Prevent the possibility of issues caused by processing the queue
1604 * while unlocked below by moving the contents to a local queue.
1606 STAILQ_CONCAT(&tmp_doneq, &ch->doneq);
1607 mtx_unlock(&ch->mtx);
1608 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) {
1609 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe);
1610 xpt_done_direct((union ccb *)ccb_h);
1615 ahci_ch_pm(void *arg)
1617 device_t dev = (device_t)arg;
1618 struct ahci_channel *ch = device_get_softc(dev);
1621 if (ch->numrslots != 0)
1623 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1624 if (ch->pm_level == 4)
1625 work |= AHCI_P_CMD_PARTIAL;
1627 work |= AHCI_P_CMD_SLUMBER;
1628 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1632 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus)
1634 device_t dev = ch->dev;
1635 uint32_t cstatus, serr = 0, sntf = 0, ok, err;
1636 enum ahci_err_type et;
1637 int i, ccs, port, reset = 0;
1639 /* Clear interrupt statuses. */
1640 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1641 /* Read command statuses. */
1642 if (ch->numtslots != 0)
1643 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1646 if (ch->numrslots != ch->numtslots)
1647 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1648 /* Read SNTF in one of possible ways. */
1649 if ((istatus & AHCI_P_IX_SDB) &&
1650 (ch->pm_present || ch->curr[0].atapi != 0)) {
1651 if (ch->caps & AHCI_CAP_SSNTF)
1652 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1653 else if (ch->fbs_enabled) {
1654 u_int8_t *fis = ch->dma.rfis + 0x58;
1656 for (i = 0; i < 16; i++) {
1657 if (fis[1] & 0x80) {
1664 u_int8_t *fis = ch->dma.rfis + 0x58;
1667 sntf = (1 << (fis[1] & 0x0f));
1670 /* Process PHY events */
1671 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1672 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1673 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1675 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1676 reset = ahci_phy_check_events(dev, serr);
1679 /* Process cold presence detection events */
1680 if ((istatus & AHCI_P_IX_CPD) && !reset)
1681 ahci_cpd_check_events(dev);
1682 /* Process command errors */
1683 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1684 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1685 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1686 >> AHCI_P_CMD_CCS_SHIFT;
1687 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1688 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1689 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1691 if (ch->fbs_enabled) {
1692 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1693 if (fbs & AHCI_P_FBS_SDE) {
1694 port = (fbs & AHCI_P_FBS_DWE)
1695 >> AHCI_P_FBS_DWE_SHIFT;
1697 for (i = 0; i < 16; i++) {
1698 if (ch->numrslotspd[i] == 0)
1702 else if (port != i) {
1709 err = ch->rslots & cstatus;
1715 /* Complete all successfull commands. */
1716 ok = ch->rslots & ~cstatus;
1717 for (i = 0; i < ch->numslots; i++) {
1719 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1721 /* On error, complete the rest of commands with error statuses. */
1724 union ccb *fccb = ch->frozen;
1726 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1727 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1728 xpt_freeze_devq(fccb->ccb_h.path, 1);
1729 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1731 ahci_done(ch, fccb);
1733 for (i = 0; i < ch->numslots; i++) {
1734 /* XXX: reqests in loading state. */
1735 if (((err >> i) & 1) == 0)
1738 ch->slot[i].ccb->ccb_h.target_id != port)
1740 if (istatus & AHCI_P_IX_TFE) {
1742 /* Task File Error */
1743 if (ch->numtslotspd[
1744 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1745 /* Untagged operation. */
1749 et = AHCI_ERR_INNOCENT;
1751 /* Tagged operation. */
1758 } else if (istatus & AHCI_P_IX_IF) {
1759 if (ch->numtslots == 0 && i != ccs && port != -2)
1760 et = AHCI_ERR_INNOCENT;
1764 et = AHCI_ERR_INVALID;
1765 ahci_end_transaction(&ch->slot[i], et);
1768 * We can't reinit port if there are some other
1769 * commands active, use resume to complete them.
1771 if (ch->rslots != 0 && !ch->recoverycmd)
1772 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1774 /* Process NOTIFY events */
1776 ahci_notify_events(dev, sntf);
1779 /* Must be called with channel locked. */
1781 ahci_check_collision(device_t dev, union ccb *ccb)
1783 struct ahci_channel *ch = device_get_softc(dev);
1784 int t = ccb->ccb_h.target_id;
1786 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1787 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1788 /* Tagged command while we have no supported tag free. */
1789 if (((~ch->oslots) & (0xffffffff >> (32 -
1790 ch->curr[t].tags))) == 0)
1792 /* If we have FBS */
1793 if (ch->fbs_enabled) {
1794 /* Tagged command while untagged are active. */
1795 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1798 /* Tagged command while untagged are active. */
1799 if (ch->numrslots != 0 && ch->numtslots == 0)
1801 /* Tagged command while tagged to other target is active. */
1802 if (ch->numtslots != 0 &&
1803 ch->taggedtarget != ccb->ccb_h.target_id)
1807 /* If we have FBS */
1808 if (ch->fbs_enabled) {
1809 /* Untagged command while tagged are active. */
1810 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1813 /* Untagged command while tagged are active. */
1814 if (ch->numrslots != 0 && ch->numtslots != 0)
1818 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1819 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1820 /* Atomic command while anything active. */
1821 if (ch->numrslots != 0)
1824 /* We have some atomic command running. */
1825 if (ch->aslots != 0)
1830 /* Must be called with channel locked. */
1832 ahci_begin_transaction(device_t dev, union ccb *ccb)
1834 struct ahci_channel *ch = device_get_softc(dev);
1835 struct ahci_slot *slot;
1838 /* Choose empty slot. */
1839 tags = ch->numslots;
1840 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1841 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1842 tags = ch->curr[ccb->ccb_h.target_id].tags;
1847 if (ch->slot[tag].state == AHCI_SLOT_EMPTY)
1852 /* Occupy chosen slot. */
1853 slot = &ch->slot[tag];
1855 /* Stop PM timer. */
1856 if (ch->numrslots == 0 && ch->pm_level > 3)
1857 callout_stop(&ch->pm_timer);
1858 /* Update channel stats. */
1859 ch->oslots |= (1 << slot->slot);
1861 ch->numrslotspd[ccb->ccb_h.target_id]++;
1862 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1863 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1865 ch->numtslotspd[ccb->ccb_h.target_id]++;
1866 ch->taggedtarget = ccb->ccb_h.target_id;
1868 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1869 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1870 ch->aslots |= (1 << slot->slot);
1871 slot->dma.nsegs = 0;
1872 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1873 slot->state = AHCI_SLOT_LOADING;
1874 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1875 ahci_dmasetprd, slot, 0);
1877 ahci_execute_transaction(slot);
1880 /* Locked by busdma engine. */
1882 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1884 struct ahci_slot *slot = arg;
1885 struct ahci_channel *ch = device_get_softc(slot->dev);
1886 struct ahci_cmd_tab *ctp;
1887 struct ahci_dma_prd *prd;
1891 device_printf(slot->dev, "DMA load error\n");
1892 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1895 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1896 /* Get a piece of the workspace for this request */
1897 ctp = (struct ahci_cmd_tab *)
1898 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1899 /* Fill S/G table */
1900 prd = &ctp->prd_tab[0];
1901 for (i = 0; i < nsegs; i++) {
1902 prd[i].dba = htole64(segs[i].ds_addr);
1903 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1905 slot->dma.nsegs = nsegs;
1906 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1907 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1908 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1909 ahci_execute_transaction(slot);
1912 /* Must be called with channel locked. */
1914 ahci_execute_transaction(struct ahci_slot *slot)
1916 device_t dev = slot->dev;
1917 struct ahci_channel *ch = device_get_softc(dev);
1918 struct ahci_cmd_tab *ctp;
1919 struct ahci_cmd_list *clp;
1920 union ccb *ccb = slot->ccb;
1921 int port = ccb->ccb_h.target_id & 0x0f;
1922 int fis_size, i, softreset;
1923 uint8_t *fis = ch->dma.rfis + 0x40;
1926 /* Get a piece of the workspace for this request */
1927 ctp = (struct ahci_cmd_tab *)
1928 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1929 /* Setup the FIS for this request */
1930 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) {
1931 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1932 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1935 /* Setup the command list entry */
1936 clp = (struct ahci_cmd_list *)
1937 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1938 clp->cmd_flags = htole16(
1939 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1940 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1941 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1942 (fis_size / sizeof(u_int32_t)) |
1944 clp->prd_length = htole16(slot->dma.nsegs);
1945 /* Special handling for Soft Reset command. */
1946 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1947 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1948 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1950 /* Kick controller into sane state */
1954 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1957 /* Prepare FIS receive area for check. */
1958 for (i = 0; i < 20; i++)
1964 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1965 (AHCI_CT_SIZE * slot->slot));
1966 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1967 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1968 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1969 BUS_DMASYNC_PREREAD);
1970 /* Set ACTIVE bit for NCQ commands. */
1971 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1972 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1973 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1975 /* If FBS is enabled, set PMP port. */
1976 if (ch->fbs_enabled) {
1977 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1978 (port << AHCI_P_FBS_DEV_SHIFT));
1980 /* Issue command to the controller. */
1981 slot->state = AHCI_SLOT_RUNNING;
1982 ch->rslots |= (1 << slot->slot);
1983 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1984 /* Device reset commands doesn't interrupt. Poll them. */
1985 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1986 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1987 int count, timeout = ccb->ccb_h.timeout * 100;
1988 enum ahci_err_type et = AHCI_ERR_NONE;
1990 for (count = 0; count < timeout; count++) {
1992 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1994 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1997 device_printf(ch->dev,
1998 "Poll error on slot %d, TFD: %04x\n",
1999 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
2004 /* Workaround for ATI SB600/SB700 chipsets. */
2005 if (ccb->ccb_h.target_id == 15 &&
2006 pci_get_vendor(device_get_parent(dev)) == 0x1002 &&
2007 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
2008 et = AHCI_ERR_TIMEOUT;
2014 * Marvell HBAs with non-RAID firmware do not wait for
2015 * readiness after soft reset, so we have to wait here.
2016 * Marvell RAIDs do not have this problem, but instead
2017 * sometimes forget to update FIS receive area, breaking
2020 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 &&
2021 softreset == 2 && et == AHCI_ERR_NONE) {
2022 while ((val = fis[2]) & ATA_S_BUSY) {
2024 if (count++ >= timeout)
2029 if (timeout && (count >= timeout)) {
2030 device_printf(dev, "Poll timeout on slot %d port %d\n",
2032 device_printf(dev, "is %08x cs %08x ss %08x "
2033 "rs %08x tfd %02x serr %08x cmd %08x\n",
2034 ATA_INL(ch->r_mem, AHCI_P_IS),
2035 ATA_INL(ch->r_mem, AHCI_P_CI),
2036 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
2037 ATA_INL(ch->r_mem, AHCI_P_TFD),
2038 ATA_INL(ch->r_mem, AHCI_P_SERR),
2039 ATA_INL(ch->r_mem, AHCI_P_CMD));
2040 et = AHCI_ERR_TIMEOUT;
2043 /* Kick controller into sane state and enable FBS. */
2045 ch->eslots |= (1 << slot->slot);
2046 ahci_end_transaction(slot, et);
2049 /* Start command execution timeout */
2050 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2,
2051 0, (timeout_t*)ahci_timeout, slot, 0);
2055 /* Must be called with channel locked. */
2057 ahci_process_timeout(device_t dev)
2059 struct ahci_channel *ch = device_get_softc(dev);
2062 mtx_assert(&ch->mtx, MA_OWNED);
2063 /* Handle the rest of commands. */
2064 for (i = 0; i < ch->numslots; i++) {
2065 /* Do we have a running request on slot? */
2066 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2068 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
2072 /* Must be called with channel locked. */
2074 ahci_rearm_timeout(device_t dev)
2076 struct ahci_channel *ch = device_get_softc(dev);
2079 mtx_assert(&ch->mtx, MA_OWNED);
2080 for (i = 0; i < ch->numslots; i++) {
2081 struct ahci_slot *slot = &ch->slot[i];
2083 /* Do we have a running request on slot? */
2084 if (slot->state < AHCI_SLOT_RUNNING)
2086 if ((ch->toslots & (1 << i)) == 0)
2088 callout_reset_sbt(&slot->timeout,
2089 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
2090 (timeout_t*)ahci_timeout, slot, 0);
2094 /* Locked by callout mechanism. */
2096 ahci_timeout(struct ahci_slot *slot)
2098 device_t dev = slot->dev;
2099 struct ahci_channel *ch = device_get_softc(dev);
2104 /* Check for stale timeout. */
2105 if (slot->state < AHCI_SLOT_RUNNING)
2108 /* Check if slot was not being executed last time we checked. */
2109 if (slot->state < AHCI_SLOT_EXECUTING) {
2110 /* Check if slot started executing. */
2111 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
2112 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
2113 >> AHCI_P_CMD_CCS_SHIFT;
2114 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
2115 ch->fbs_enabled || ch->wrongccs)
2116 slot->state = AHCI_SLOT_EXECUTING;
2117 else if ((ch->rslots & (1 << ccs)) == 0) {
2119 slot->state = AHCI_SLOT_EXECUTING;
2122 callout_reset_sbt(&slot->timeout,
2123 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
2124 (timeout_t*)ahci_timeout, slot, 0);
2128 device_printf(dev, "Timeout on slot %d port %d\n",
2129 slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
2130 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
2131 "serr %08x cmd %08x\n",
2132 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
2133 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
2134 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
2135 ATA_INL(ch->r_mem, AHCI_P_CMD));
2137 /* Handle frozen command. */
2139 union ccb *fccb = ch->frozen;
2141 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2142 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2143 xpt_freeze_devq(fccb->ccb_h.path, 1);
2144 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2146 ahci_done(ch, fccb);
2148 if (!ch->fbs_enabled && !ch->wrongccs) {
2149 /* Without FBS we know real timeout source. */
2151 /* Handle command with timeout. */
2152 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
2153 /* Handle the rest of commands. */
2154 for (i = 0; i < ch->numslots; i++) {
2155 /* Do we have a running request on slot? */
2156 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2158 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2161 /* With FBS we wait for other commands timeout and pray. */
2162 if (ch->toslots == 0)
2163 xpt_freeze_simq(ch->sim, 1);
2164 ch->toslots |= (1 << slot->slot);
2165 if ((ch->rslots & ~ch->toslots) == 0)
2166 ahci_process_timeout(dev);
2168 device_printf(dev, " ... waiting for slots %08x\n",
2169 ch->rslots & ~ch->toslots);
2173 /* Must be called with channel locked. */
2175 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
2177 device_t dev = slot->dev;
2178 struct ahci_channel *ch = device_get_softc(dev);
2179 union ccb *ccb = slot->ccb;
2180 struct ahci_cmd_list *clp;
2184 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
2185 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2186 clp = (struct ahci_cmd_list *)
2187 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
2188 /* Read result registers to the result struct
2189 * May be incorrect if several commands finished same time,
2190 * so read only when sure or have to.
2192 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2193 struct ata_res *res = &ccb->ataio.res;
2195 if ((et == AHCI_ERR_TFE) ||
2196 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
2197 u_int8_t *fis = ch->dma.rfis + 0x40;
2199 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
2200 BUS_DMASYNC_POSTREAD);
2201 if (ch->fbs_enabled) {
2202 fis += ccb->ccb_h.target_id * 256;
2203 res->status = fis[2];
2204 res->error = fis[3];
2206 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
2209 res->error = tfd >> 8;
2211 res->lba_low = fis[4];
2212 res->lba_mid = fis[5];
2213 res->lba_high = fis[6];
2214 res->device = fis[7];
2215 res->lba_low_exp = fis[8];
2216 res->lba_mid_exp = fis[9];
2217 res->lba_high_exp = fis[10];
2218 res->sector_count = fis[12];
2219 res->sector_count_exp = fis[13];
2222 * Some weird controllers do not return signature in
2223 * FIS receive area. Read it from PxSIG register.
2225 if ((ch->quirks & AHCI_Q_ALTSIG) &&
2226 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2227 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
2228 sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
2229 res->lba_high = sig >> 24;
2230 res->lba_mid = sig >> 16;
2231 res->lba_low = sig >> 8;
2232 res->sector_count = sig;
2235 bzero(res, sizeof(*res));
2236 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
2237 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2238 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2240 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
2243 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2244 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2246 ccb->csio.dxfer_len - le32toh(clp->bytecount);
2249 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2250 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
2251 (ccb->ccb_h.flags & CAM_DIR_IN) ?
2252 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2253 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
2255 if (et != AHCI_ERR_NONE)
2256 ch->eslots |= (1 << slot->slot);
2257 /* In case of error, freeze device for proper recovery. */
2258 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
2259 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2260 xpt_freeze_devq(ccb->ccb_h.path, 1);
2261 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2263 /* Set proper result status. */
2264 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2267 ccb->ccb_h.status |= CAM_REQ_CMP;
2268 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
2269 ccb->csio.scsi_status = SCSI_STATUS_OK;
2271 case AHCI_ERR_INVALID:
2273 ccb->ccb_h.status |= CAM_REQ_INVALID;
2275 case AHCI_ERR_INNOCENT:
2276 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
2280 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2281 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2282 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2284 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2289 if (!ch->recoverycmd) {
2290 xpt_freeze_simq(ch->sim, 1);
2291 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2292 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2294 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
2296 case AHCI_ERR_TIMEOUT:
2297 if (!ch->recoverycmd) {
2298 xpt_freeze_simq(ch->sim, 1);
2299 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2300 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2302 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2306 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
2309 ch->oslots &= ~(1 << slot->slot);
2310 ch->rslots &= ~(1 << slot->slot);
2311 ch->aslots &= ~(1 << slot->slot);
2312 slot->state = AHCI_SLOT_EMPTY;
2314 /* Update channel stats. */
2316 ch->numrslotspd[ccb->ccb_h.target_id]--;
2317 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2318 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
2320 ch->numtslotspd[ccb->ccb_h.target_id]--;
2322 /* Cancel timeout state if request completed normally. */
2323 if (et != AHCI_ERR_TIMEOUT) {
2324 lastto = (ch->toslots == (1 << slot->slot));
2325 ch->toslots &= ~(1 << slot->slot);
2327 xpt_release_simq(ch->sim, TRUE);
2329 /* If it was first request of reset sequence and there is no error,
2330 * proceed to second request. */
2331 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2332 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2333 (ccb->ataio.cmd.control & ATA_A_RESET) &&
2334 et == AHCI_ERR_NONE) {
2335 ccb->ataio.cmd.control &= ~ATA_A_RESET;
2336 ahci_begin_transaction(dev, ccb);
2339 /* If it was our READ LOG command - process it. */
2340 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
2341 ahci_process_read_log(dev, ccb);
2342 /* If it was our REQUEST SENSE command - process it. */
2343 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
2344 ahci_process_request_sense(dev, ccb);
2345 /* If it was NCQ or ATAPI command error, put result on hold. */
2346 } else if (et == AHCI_ERR_NCQ ||
2347 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
2348 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
2349 ch->hold[slot->slot] = ccb;
2353 /* If we have no other active commands, ... */
2354 if (ch->rslots == 0) {
2355 /* if there was fatal error - reset port. */
2356 if (ch->toslots != 0 || ch->fatalerr) {
2359 /* if we have slots in error, we can reinit port. */
2360 if (ch->eslots != 0) {
2365 /* if there commands on hold, we can do READ LOG. */
2366 if (!ch->recoverycmd && ch->numhslots)
2367 ahci_issue_recovery(dev);
2369 /* If all the rest of commands are in timeout - give them chance. */
2370 } else if ((ch->rslots & ~ch->toslots) == 0 &&
2371 et != AHCI_ERR_TIMEOUT)
2372 ahci_rearm_timeout(dev);
2373 /* Unfreeze frozen command. */
2374 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) {
2375 union ccb *fccb = ch->frozen;
2377 ahci_begin_transaction(dev, fccb);
2378 xpt_release_simq(ch->sim, TRUE);
2380 /* Start PM timer. */
2381 if (ch->numrslots == 0 && ch->pm_level > 3 &&
2382 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
2383 callout_schedule(&ch->pm_timer,
2384 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
2389 ahci_issue_recovery(device_t dev)
2391 struct ahci_channel *ch = device_get_softc(dev);
2393 struct ccb_ataio *ataio;
2394 struct ccb_scsiio *csio;
2397 /* Find some held command. */
2398 for (i = 0; i < ch->numslots; i++) {
2402 ccb = xpt_alloc_ccb_nowait();
2404 device_printf(dev, "Unable to allocate recovery command\n");
2406 /* We can't do anything -- complete held commands. */
2407 for (i = 0; i < ch->numslots; i++) {
2408 if (ch->hold[i] == NULL)
2410 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2411 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2412 ahci_done(ch, ch->hold[i]);
2419 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
2420 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2422 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2423 ccb->ccb_h.func_code = XPT_ATA_IO;
2424 ccb->ccb_h.flags = CAM_DIR_IN;
2425 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2426 ataio = &ccb->ataio;
2427 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2428 if (ataio->data_ptr == NULL) {
2431 "Unable to allocate memory for READ LOG command\n");
2434 ataio->dxfer_len = 512;
2435 bzero(&ataio->cmd, sizeof(ataio->cmd));
2436 ataio->cmd.flags = CAM_ATAIO_48BIT;
2437 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2438 ataio->cmd.sector_count = 1;
2439 ataio->cmd.sector_count_exp = 0;
2440 ataio->cmd.lba_low = 0x10;
2441 ataio->cmd.lba_mid = 0;
2442 ataio->cmd.lba_mid_exp = 0;
2445 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2446 ccb->ccb_h.recovery_slot = i;
2447 ccb->ccb_h.func_code = XPT_SCSI_IO;
2448 ccb->ccb_h.flags = CAM_DIR_IN;
2449 ccb->ccb_h.status = 0;
2450 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2452 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2453 csio->dxfer_len = ch->hold[i]->csio.sense_len;
2455 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2456 csio->cdb_io.cdb_bytes[0] = 0x03;
2457 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2459 /* Freeze SIM while doing recovery. */
2460 ch->recoverycmd = 1;
2461 xpt_freeze_simq(ch->sim, 1);
2462 ahci_begin_transaction(dev, ccb);
2466 ahci_process_read_log(device_t dev, union ccb *ccb)
2468 struct ahci_channel *ch = device_get_softc(dev);
2470 struct ata_res *res;
2473 ch->recoverycmd = 0;
2475 data = ccb->ataio.data_ptr;
2476 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2477 (data[0] & 0x80) == 0) {
2478 for (i = 0; i < ch->numslots; i++) {
2481 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2483 if ((data[0] & 0x1F) == i) {
2484 res = &ch->hold[i]->ataio.res;
2485 res->status = data[2];
2486 res->error = data[3];
2487 res->lba_low = data[4];
2488 res->lba_mid = data[5];
2489 res->lba_high = data[6];
2490 res->device = data[7];
2491 res->lba_low_exp = data[8];
2492 res->lba_mid_exp = data[9];
2493 res->lba_high_exp = data[10];
2494 res->sector_count = data[12];
2495 res->sector_count_exp = data[13];
2497 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2498 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2500 ahci_done(ch, ch->hold[i]);
2505 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2506 device_printf(dev, "Error while READ LOG EXT\n");
2507 else if ((data[0] & 0x80) == 0) {
2508 device_printf(dev, "Non-queued command error in READ LOG EXT\n");
2510 for (i = 0; i < ch->numslots; i++) {
2513 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2515 ahci_done(ch, ch->hold[i]);
2520 free(ccb->ataio.data_ptr, M_AHCI);
2522 xpt_release_simq(ch->sim, TRUE);
2526 ahci_process_request_sense(device_t dev, union ccb *ccb)
2528 struct ahci_channel *ch = device_get_softc(dev);
2531 ch->recoverycmd = 0;
2533 i = ccb->ccb_h.recovery_slot;
2534 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2535 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2537 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2538 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2540 ahci_done(ch, ch->hold[i]);
2544 xpt_release_simq(ch->sim, TRUE);
2548 ahci_start(device_t dev, int fbs)
2550 struct ahci_channel *ch = device_get_softc(dev);
2553 /* Clear SATA error register */
2554 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2555 /* Clear any interrupts pending on this channel */
2556 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2557 /* Configure FIS-based switching if supported. */
2558 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2559 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2560 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2561 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2563 /* Start operations on this channel */
2564 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2565 cmd &= ~AHCI_P_CMD_PMA;
2566 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2567 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2571 ahci_stop(device_t dev)
2573 struct ahci_channel *ch = device_get_softc(dev);
2577 /* Kill all activity on this channel */
2578 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2579 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2580 /* Wait for activity stop. */
2584 if (timeout++ > 50000) {
2585 device_printf(dev, "stopping AHCI engine failed\n");
2588 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2593 ahci_clo(device_t dev)
2595 struct ahci_channel *ch = device_get_softc(dev);
2599 /* Issue Command List Override if supported */
2600 if (ch->caps & AHCI_CAP_SCLO) {
2601 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2602 cmd |= AHCI_P_CMD_CLO;
2603 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2607 if (timeout++ > 50000) {
2608 device_printf(dev, "executing CLO failed\n");
2611 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2616 ahci_stop_fr(device_t dev)
2618 struct ahci_channel *ch = device_get_softc(dev);
2622 /* Kill all FIS reception on this channel */
2623 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2624 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2625 /* Wait for FIS reception stop. */
2629 if (timeout++ > 50000) {
2630 device_printf(dev, "stopping AHCI FR engine failed\n");
2633 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2637 ahci_start_fr(device_t dev)
2639 struct ahci_channel *ch = device_get_softc(dev);
2642 /* Start FIS reception on this channel */
2643 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2644 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2648 ahci_wait_ready(device_t dev, int t, int t0)
2650 struct ahci_channel *ch = device_get_softc(dev);
2654 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2655 (ATA_S_BUSY | ATA_S_DRQ)) {
2659 "AHCI reset: device not ready after %dms "
2661 MAX(t, 0) + t0, val);
2669 device_printf(dev, "AHCI reset: device ready after %dms\n",
2675 ahci_reset_to(void *arg)
2678 struct ahci_channel *ch = device_get_softc(dev);
2680 if (ch->resetting == 0)
2683 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0,
2684 (310 - ch->resetting) * 100) == 0) {
2687 xpt_release_simq(ch->sim, TRUE);
2690 if (ch->resetting == 0) {
2693 xpt_release_simq(ch->sim, TRUE);
2696 callout_schedule(&ch->reset_timer, hz / 10);
2700 ahci_reset(device_t dev)
2702 struct ahci_channel *ch = device_get_softc(dev);
2703 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
2706 xpt_freeze_simq(ch->sim, 1);
2708 device_printf(dev, "AHCI reset...\n");
2709 /* Forget about previous reset. */
2710 if (ch->resetting) {
2712 callout_stop(&ch->reset_timer);
2713 xpt_release_simq(ch->sim, TRUE);
2715 /* Requeue freezed command. */
2717 union ccb *fccb = ch->frozen;
2719 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2720 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2721 xpt_freeze_devq(fccb->ccb_h.path, 1);
2722 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2724 ahci_done(ch, fccb);
2726 /* Kill the engine and requeue all running commands. */
2728 for (i = 0; i < ch->numslots; i++) {
2729 /* Do we have a running request on slot? */
2730 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2732 /* XXX; Commands in loading state. */
2733 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2735 for (i = 0; i < ch->numslots; i++) {
2738 ahci_done(ch, ch->hold[i]);
2742 if (ch->toslots != 0)
2743 xpt_release_simq(ch->sim, TRUE);
2748 /* Tell the XPT about the event */
2749 xpt_async(AC_BUS_RESET, ch->path, NULL);
2750 /* Disable port interrupts */
2751 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2752 /* Reset and reconnect PHY, */
2753 if (!ahci_sata_phy_reset(dev)) {
2756 "AHCI reset: device not found\n");
2758 /* Enable wanted port interrupts */
2759 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2760 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2761 AHCI_P_IX_PRC | AHCI_P_IX_PC));
2762 xpt_release_simq(ch->sim, TRUE);
2766 device_printf(dev, "AHCI reset: device found\n");
2767 /* Wait for clearing busy status. */
2768 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) {
2772 ch->resetting = 310;
2775 /* Enable wanted port interrupts */
2776 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2777 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2778 AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2779 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2780 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2781 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2782 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2784 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev);
2787 xpt_release_simq(ch->sim, TRUE);
2792 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2794 struct ahci_channel *ch = device_get_softc(dev);
2795 u_int8_t *fis = &ctp->cfis[0];
2797 bzero(ctp->cfis, 16);
2798 fis[0] = 0x27; /* host to device */
2799 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2800 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2802 fis[2] = ATA_PACKET_CMD;
2803 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2804 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2807 fis[5] = ccb->csio.dxfer_len;
2808 fis[6] = ccb->csio.dxfer_len >> 8;
2811 fis[15] = ATA_A_4BIT;
2812 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2813 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2814 ctp->acmd, ccb->csio.cdb_len);
2815 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2816 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2818 fis[2] = ccb->ataio.cmd.command;
2819 fis[3] = ccb->ataio.cmd.features;
2820 fis[4] = ccb->ataio.cmd.lba_low;
2821 fis[5] = ccb->ataio.cmd.lba_mid;
2822 fis[6] = ccb->ataio.cmd.lba_high;
2823 fis[7] = ccb->ataio.cmd.device;
2824 fis[8] = ccb->ataio.cmd.lba_low_exp;
2825 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2826 fis[10] = ccb->ataio.cmd.lba_high_exp;
2827 fis[11] = ccb->ataio.cmd.features_exp;
2828 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2832 fis[12] = ccb->ataio.cmd.sector_count;
2833 fis[13] = ccb->ataio.cmd.sector_count_exp;
2835 fis[15] = ATA_A_4BIT;
2837 fis[15] = ccb->ataio.cmd.control;
2843 ahci_sata_connect(struct ahci_channel *ch)
2846 int timeout, found = 0;
2848 /* Wait up to 100ms for "connect well" */
2849 for (timeout = 0; timeout < 1000 ; timeout++) {
2850 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2851 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2853 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2854 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2855 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2857 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2859 device_printf(ch->dev, "SATA offline status=%08x\n",
2864 if (found == 0 && timeout >= 100)
2868 if (timeout >= 1000 || !found) {
2870 device_printf(ch->dev,
2871 "SATA connect timeout time=%dus status=%08x\n",
2872 timeout * 100, status);
2877 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2878 timeout * 100, status);
2880 /* Clear SATA error register */
2881 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2886 ahci_sata_phy_reset(device_t dev)
2888 struct ahci_channel *ch = device_get_softc(dev);
2892 if (ch->listening) {
2893 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2894 val |= AHCI_P_CMD_SUD;
2895 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2898 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2900 val = ATA_SC_SPD_SPEED_GEN1;
2901 else if (sata_rev == 2)
2902 val = ATA_SC_SPD_SPEED_GEN2;
2903 else if (sata_rev == 3)
2904 val = ATA_SC_SPD_SPEED_GEN3;
2907 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2908 ATA_SC_DET_RESET | val |
2909 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2911 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2912 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2913 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2914 if (!ahci_sata_connect(ch)) {
2915 if (ch->caps & AHCI_CAP_SSS) {
2916 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2917 val &= ~AHCI_P_CMD_SUD;
2918 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2920 } else if (ch->pm_level > 0)
2921 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2928 ahci_check_ids(device_t dev, union ccb *ccb)
2930 struct ahci_channel *ch = device_get_softc(dev);
2932 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2933 ccb->ccb_h.status = CAM_TID_INVALID;
2937 if (ccb->ccb_h.target_lun != 0) {
2938 ccb->ccb_h.status = CAM_LUN_INVALID;
2946 ahciaction(struct cam_sim *sim, union ccb *ccb)
2948 device_t dev, parent;
2949 struct ahci_channel *ch;
2951 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2952 ccb->ccb_h.func_code));
2954 ch = (struct ahci_channel *)cam_sim_softc(sim);
2956 switch (ccb->ccb_h.func_code) {
2957 /* Common cases first */
2958 case XPT_ATA_IO: /* Execute the requested I/O operation */
2960 if (ahci_check_ids(dev, ccb))
2962 if (ch->devices == 0 ||
2963 (ch->pm_present == 0 &&
2964 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2965 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2968 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2969 /* Check for command collision. */
2970 if (ahci_check_collision(dev, ccb)) {
2971 /* Freeze command. */
2973 /* We have only one frozen slot, so freeze simq also. */
2974 xpt_freeze_simq(ch->sim, 1);
2977 ahci_begin_transaction(dev, ccb);
2979 case XPT_EN_LUN: /* Enable LUN as a target */
2980 case XPT_TARGET_IO: /* Execute target I/O request */
2981 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2982 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2983 case XPT_ABORT: /* Abort the specified CCB */
2985 ccb->ccb_h.status = CAM_REQ_INVALID;
2987 case XPT_SET_TRAN_SETTINGS:
2989 struct ccb_trans_settings *cts = &ccb->cts;
2990 struct ahci_device *d;
2992 if (ahci_check_ids(dev, ccb))
2994 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2995 d = &ch->curr[ccb->ccb_h.target_id];
2997 d = &ch->user[ccb->ccb_h.target_id];
2998 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2999 d->revision = cts->xport_specific.sata.revision;
3000 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
3001 d->mode = cts->xport_specific.sata.mode;
3002 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
3003 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
3004 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
3005 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
3006 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
3007 ch->pm_present = cts->xport_specific.sata.pm_present;
3008 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
3009 d->atapi = cts->xport_specific.sata.atapi;
3010 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
3011 d->caps = cts->xport_specific.sata.caps;
3012 ccb->ccb_h.status = CAM_REQ_CMP;
3015 case XPT_GET_TRAN_SETTINGS:
3016 /* Get default/user set transfer settings for the target */
3018 struct ccb_trans_settings *cts = &ccb->cts;
3019 struct ahci_device *d;
3022 if (ahci_check_ids(dev, ccb))
3024 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
3025 d = &ch->curr[ccb->ccb_h.target_id];
3027 d = &ch->user[ccb->ccb_h.target_id];
3028 cts->protocol = PROTO_UNSPECIFIED;
3029 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
3030 cts->transport = XPORT_SATA;
3031 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
3032 cts->proto_specific.valid = 0;
3033 cts->xport_specific.sata.valid = 0;
3034 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
3035 (ccb->ccb_h.target_id == 15 ||
3036 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
3037 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
3038 if (status & 0x0f0) {
3039 cts->xport_specific.sata.revision =
3040 (status & 0x0f0) >> 4;
3041 cts->xport_specific.sata.valid |=
3042 CTS_SATA_VALID_REVISION;
3044 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
3046 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
3047 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
3048 if (ch->caps2 & AHCI_CAP2_APST)
3049 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
3051 if ((ch->caps & AHCI_CAP_SNCQ) &&
3052 (ch->quirks & AHCI_Q_NOAA) == 0)
3053 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
3054 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
3055 cts->xport_specific.sata.caps &=
3056 ch->user[ccb->ccb_h.target_id].caps;
3057 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
3059 cts->xport_specific.sata.revision = d->revision;
3060 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
3061 cts->xport_specific.sata.caps = d->caps;
3062 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
3064 cts->xport_specific.sata.mode = d->mode;
3065 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
3066 cts->xport_specific.sata.bytecount = d->bytecount;
3067 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
3068 cts->xport_specific.sata.pm_present = ch->pm_present;
3069 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
3070 cts->xport_specific.sata.tags = d->tags;
3071 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
3072 cts->xport_specific.sata.atapi = d->atapi;
3073 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
3074 ccb->ccb_h.status = CAM_REQ_CMP;
3077 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
3078 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
3080 ccb->ccb_h.status = CAM_REQ_CMP;
3082 case XPT_TERM_IO: /* Terminate the I/O process */
3084 ccb->ccb_h.status = CAM_REQ_INVALID;
3086 case XPT_PATH_INQ: /* Path routing inquiry */
3088 struct ccb_pathinq *cpi = &ccb->cpi;
3090 parent = device_get_parent(dev);
3091 cpi->version_num = 1; /* XXX??? */
3092 cpi->hba_inquiry = PI_SDTR_ABLE;
3093 if (ch->caps & AHCI_CAP_SNCQ)
3094 cpi->hba_inquiry |= PI_TAG_ABLE;
3095 if (ch->caps & AHCI_CAP_SPM)
3096 cpi->hba_inquiry |= PI_SATAPM;
3097 cpi->target_sprt = 0;
3098 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
3099 cpi->hba_eng_cnt = 0;
3100 if (ch->caps & AHCI_CAP_SPM)
3101 cpi->max_target = 15;
3103 cpi->max_target = 0;
3105 cpi->initiator_id = 0;
3106 cpi->bus_id = cam_sim_bus(sim);
3107 cpi->base_transfer_speed = 150000;
3108 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
3109 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
3110 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
3111 cpi->unit_number = cam_sim_unit(sim);
3112 cpi->transport = XPORT_SATA;
3113 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
3114 cpi->protocol = PROTO_ATA;
3115 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
3116 cpi->maxio = MAXPHYS;
3117 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
3118 if (pci_get_devid(parent) == 0x43801002)
3119 cpi->maxio = min(cpi->maxio, 128 * 512);
3120 cpi->hba_vendor = pci_get_vendor(parent);
3121 cpi->hba_device = pci_get_device(parent);
3122 cpi->hba_subvendor = pci_get_subvendor(parent);
3123 cpi->hba_subdevice = pci_get_subdevice(parent);
3124 cpi->ccb_h.status = CAM_REQ_CMP;
3128 ccb->ccb_h.status = CAM_REQ_INVALID;
3135 ahcipoll(struct cam_sim *sim)
3137 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
3140 /* Read interrupt statuses and process if any. */
3141 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
3143 ahci_ch_intr_main(ch, istatus);
3144 if (ch->resetting != 0 &&
3145 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
3146 ch->resetpolldiv = 1000;
3147 ahci_reset_to(ch->dev);