2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
44 #include "aic7xxx_osm.h"
45 #include "aic7xxx_inline.h"
46 #include "aicasm/aicasm_insformat.h"
48 #include <sys/cdefs.h>
49 __FBSDID("$FreeBSD$");
50 #include <dev/aic7xxx/aic7xxx_osm.h>
51 #include <dev/aic7xxx/aic7xxx_inline.h>
52 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
55 /****************************** Softc Data ************************************/
56 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
58 /***************************** Lookup Tables **********************************/
59 char *ahc_chip_names[] =
76 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
79 * Hardware error codes.
81 struct ahc_hard_error_entry {
86 static struct ahc_hard_error_entry ahc_hard_errors[] = {
87 { ILLHADDR, "Illegal Host Access" },
88 { ILLSADDR, "Illegal Sequencer Address referrenced" },
89 { ILLOPCODE, "Illegal Opcode in sequencer program" },
90 { SQPARERR, "Sequencer Parity Error" },
91 { DPARERR, "Data-path Parity Error" },
92 { MPARERR, "Scratch or SCB Memory Parity Error" },
93 { PCIERRSTAT, "PCI Error detected" },
94 { CIOPARERR, "CIOBUS Parity Error" },
96 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
98 static struct ahc_phase_table_entry ahc_phase_table[] =
100 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
101 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
102 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
103 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
104 { P_COMMAND, MSG_NOOP, "in Command phase" },
105 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
106 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
107 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
108 { P_BUSFREE, MSG_NOOP, "while idle" },
109 { 0, MSG_NOOP, "in unknown phase" }
113 * In most cases we only wish to itterate over real phases, so
114 * exclude the last element from the count.
116 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
119 * Valid SCSIRATE values. (p. 3-17)
120 * Provides a mapping of tranfer periods in ns to the proper value to
121 * stick in the scsixfer reg.
123 static struct ahc_syncrate ahc_syncrates[] =
125 /* ultra2 fast/ultra period rate */
126 { 0x42, 0x000, 9, "80.0" },
127 { 0x03, 0x000, 10, "40.0" },
128 { 0x04, 0x000, 11, "33.0" },
129 { 0x05, 0x100, 12, "20.0" },
130 { 0x06, 0x110, 15, "16.0" },
131 { 0x07, 0x120, 18, "13.4" },
132 { 0x08, 0x000, 25, "10.0" },
133 { 0x19, 0x010, 31, "8.0" },
134 { 0x1a, 0x020, 37, "6.67" },
135 { 0x1b, 0x030, 43, "5.7" },
136 { 0x1c, 0x040, 50, "5.0" },
137 { 0x00, 0x050, 56, "4.4" },
138 { 0x00, 0x060, 62, "4.0" },
139 { 0x00, 0x070, 68, "3.6" },
140 { 0x00, 0x000, 0, NULL }
143 /* Our Sequencer Program */
144 #include "aic7xxx_seq.h"
146 /**************************** Function Declarations ***************************/
147 static void ahc_force_renegotiation(struct ahc_softc *ahc,
148 struct ahc_devinfo *devinfo);
149 static struct ahc_tmode_tstate*
150 ahc_alloc_tstate(struct ahc_softc *ahc,
151 u_int scsi_id, char channel);
152 #ifdef AHC_TARGET_MODE
153 static void ahc_free_tstate(struct ahc_softc *ahc,
154 u_int scsi_id, char channel, int force);
156 static struct ahc_syncrate*
157 ahc_devlimited_syncrate(struct ahc_softc *ahc,
158 struct ahc_initiator_tinfo *,
162 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
163 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
164 struct ahc_devinfo *devinfo);
165 static void ahc_scb_devinfo(struct ahc_softc *ahc,
166 struct ahc_devinfo *devinfo,
168 static void ahc_assert_atn(struct ahc_softc *ahc);
169 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
170 struct ahc_devinfo *devinfo,
172 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
173 struct ahc_devinfo *devinfo);
174 static void ahc_construct_sdtr(struct ahc_softc *ahc,
175 struct ahc_devinfo *devinfo,
176 u_int period, u_int offset);
177 static void ahc_construct_wdtr(struct ahc_softc *ahc,
178 struct ahc_devinfo *devinfo,
180 static void ahc_construct_ppr(struct ahc_softc *ahc,
181 struct ahc_devinfo *devinfo,
182 u_int period, u_int offset,
183 u_int bus_width, u_int ppr_options);
184 static void ahc_clear_msg_state(struct ahc_softc *ahc);
185 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
186 static void ahc_handle_message_phase(struct ahc_softc *ahc);
192 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
193 u_int msgval, int full);
194 static int ahc_parse_msg(struct ahc_softc *ahc,
195 struct ahc_devinfo *devinfo);
196 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
197 struct ahc_devinfo *devinfo);
198 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
199 struct ahc_devinfo *devinfo);
200 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
201 static void ahc_handle_devreset(struct ahc_softc *ahc,
202 struct ahc_devinfo *devinfo,
203 cam_status status, char *message,
205 #ifdef AHC_TARGET_MODE
206 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
207 struct ahc_devinfo *devinfo,
211 static bus_dmamap_callback_t ahc_dmamap_cb;
212 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
213 static int ahc_init_scbdata(struct ahc_softc *ahc);
214 static void ahc_fini_scbdata(struct ahc_softc *ahc);
215 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
216 struct scb *prev_scb,
218 static int ahc_qinfifo_count(struct ahc_softc *ahc);
219 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
220 u_int prev, u_int scbptr);
221 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
222 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
223 u_int scbpos, u_int prev);
224 static void ahc_reset_current_bus(struct ahc_softc *ahc);
226 static void ahc_dumpseq(struct ahc_softc *ahc);
228 static int ahc_loadseq(struct ahc_softc *ahc);
229 static int ahc_check_patch(struct ahc_softc *ahc,
230 struct patch **start_patch,
231 u_int start_instr, u_int *skip_addr);
232 static void ahc_download_instr(struct ahc_softc *ahc,
233 u_int instrptr, uint8_t *dconsts);
234 static int ahc_other_scb_timeout(struct ahc_softc *ahc,
236 struct scb *other_scb);
237 #ifdef AHC_TARGET_MODE
238 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
239 struct ahc_tmode_lstate *lstate,
243 static void ahc_update_scsiid(struct ahc_softc *ahc,
245 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
246 struct target_cmd *cmd);
248 /************************* Sequencer Execution Control ************************/
250 * Restart the sequencer program from address zero
253 ahc_restart(struct ahc_softc *ahc)
258 /* No more pending messages. */
259 ahc_clear_msg_state(ahc);
261 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
262 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
263 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
264 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
265 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
266 ahc_outb(ahc, SAVED_LUN, 0xFF);
269 * Ensure that the sequencer's idea of TQINPOS
270 * matches our own. The sequencer increments TQINPOS
271 * only after it sees a DMA complete and a reset could
272 * occur before the increment leaving the kernel to believe
273 * the command arrived but the sequencer to not.
275 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
277 /* Always allow reselection */
278 ahc_outb(ahc, SCSISEQ,
279 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
280 if ((ahc->features & AHC_CMD_CHAN) != 0) {
281 /* Ensure that no DMA operations are in progress */
282 ahc_outb(ahc, CCSCBCNT, 0);
283 ahc_outb(ahc, CCSGCTL, 0);
284 ahc_outb(ahc, CCSCBCTL, 0);
287 * If we were in the process of DMA'ing SCB data into
288 * an SCB, replace that SCB on the free list. This prevents
291 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
292 ahc_add_curscb_to_free_list(ahc);
293 ahc_outb(ahc, SEQ_FLAGS2,
294 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
298 * Clear any pending sequencer interrupt. It is no
299 * longer relevant since we're resetting the Program
302 ahc_outb(ahc, CLRINT, CLRSEQINT);
304 ahc_outb(ahc, MWI_RESIDUAL, 0);
305 ahc_outb(ahc, SEQCTL, ahc->seqctl);
306 ahc_outb(ahc, SEQADDR0, 0);
307 ahc_outb(ahc, SEQADDR1, 0);
312 /************************* Input/Output Queues ********************************/
314 ahc_run_qoutfifo(struct ahc_softc *ahc)
319 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
320 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
322 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
323 if ((ahc->qoutfifonext & 0x03) == 0x03) {
327 * Clear 32bits of QOUTFIFO at a time
328 * so that we don't clobber an incoming
329 * byte DMA to the array on architectures
330 * that only support 32bit load and store
333 modnext = ahc->qoutfifonext & ~0x3;
334 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
335 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
336 ahc->shared_data_dmamap,
337 /*offset*/modnext, /*len*/4,
338 BUS_DMASYNC_PREREAD);
342 scb = ahc_lookup_scb(ahc, scb_index);
344 printf("%s: WARNING no command for scb %d "
345 "(cmdcmplt)\nQOUTPOS = %d\n",
346 ahc_name(ahc), scb_index,
347 (ahc->qoutfifonext - 1) & 0xFF);
352 * Save off the residual
355 ahc_update_residual(ahc, scb);
361 ahc_run_untagged_queues(struct ahc_softc *ahc)
365 for (i = 0; i < 16; i++)
366 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
370 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
374 if (ahc->untagged_queue_lock != 0)
377 if ((scb = TAILQ_FIRST(queue)) != NULL
378 && (scb->flags & SCB_ACTIVE) == 0) {
379 scb->flags |= SCB_ACTIVE;
381 * Timers are disabled while recovery is in progress.
383 aic_scb_timer_start(scb);
384 ahc_queue_scb(ahc, scb);
388 /************************* Interrupt Handling *********************************/
390 ahc_handle_brkadrint(struct ahc_softc *ahc)
393 * We upset the sequencer :-(
394 * Lookup the error message
399 error = ahc_inb(ahc, ERROR);
400 for (i = 0; error != 1 && i < num_errors; i++)
402 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
403 ahc_name(ahc), ahc_hard_errors[i].errmesg,
404 ahc_inb(ahc, SEQADDR0) |
405 (ahc_inb(ahc, SEQADDR1) << 8));
407 ahc_dump_card_state(ahc);
409 /* Tell everyone that this HBA is no longer available */
410 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
411 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
414 /* Disable all interrupt sources by resetting the controller */
419 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
422 struct ahc_devinfo devinfo;
424 ahc_fetch_devinfo(ahc, &devinfo);
427 * Clear the upper byte that holds SEQINT status
428 * codes and clear the SEQINT bit. We will unpause
429 * the sequencer, if appropriate, after servicing
432 ahc_outb(ahc, CLRINT, CLRSEQINT);
433 switch (intstat & SEQINT_MASK) {
437 struct hardware_scb *hscb;
440 * Set the default return value to 0 (don't
441 * send sense). The sense code will change
444 ahc_outb(ahc, RETURN_1, 0);
447 * The sequencer will notify us when a command
448 * has an error that would be of interest to
449 * the kernel. This allows us to leave the sequencer
450 * running in the common case of command completes
451 * without error. The sequencer will already have
452 * dma'd the SCB back up to us, so we can reference
453 * the in kernel copy directly.
455 scb_index = ahc_inb(ahc, SCB_TAG);
456 scb = ahc_lookup_scb(ahc, scb_index);
458 ahc_print_devinfo(ahc, &devinfo);
459 printf("ahc_intr - referenced scb "
460 "not valid during seqint 0x%x scb(%d)\n",
462 ahc_dump_card_state(ahc);
469 /* Don't want to clobber the original sense code */
470 if ((scb->flags & SCB_SENSE) != 0) {
472 * Clear the SCB_SENSE Flag and have
473 * the sequencer do a normal command
476 scb->flags &= ~SCB_SENSE;
477 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
480 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
481 /* Freeze the queue until the client sees the error. */
482 ahc_freeze_devq(ahc, scb);
484 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
485 switch (hscb->shared_data.status.scsi_status) {
487 printf("%s: Interrupted for staus of 0???\n",
490 case SCSI_STATUS_CMD_TERMINATED:
491 case SCSI_STATUS_CHECK_COND:
493 struct ahc_dma_seg *sg;
494 struct scsi_sense *sc;
495 struct ahc_initiator_tinfo *targ_info;
496 struct ahc_tmode_tstate *tstate;
497 struct ahc_transinfo *tinfo;
499 if (ahc_debug & AHC_SHOW_SENSE) {
500 ahc_print_path(ahc, scb);
501 printf("SCB %d: requests Check Status\n",
506 if (aic_perform_autosense(scb) == 0)
509 targ_info = ahc_fetch_transinfo(ahc,
514 tinfo = &targ_info->curr;
516 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
518 * Save off the residual if there is one.
520 ahc_update_residual(ahc, scb);
522 if (ahc_debug & AHC_SHOW_SENSE) {
523 ahc_print_path(ahc, scb);
524 printf("Sending Sense\n");
527 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
528 sg->len = aic_get_sense_bufsize(ahc, scb);
529 sg->len |= AHC_DMA_LAST_SEG;
531 /* Fixup byte order */
532 sg->addr = aic_htole32(sg->addr);
533 sg->len = aic_htole32(sg->len);
535 sc->opcode = REQUEST_SENSE;
537 if (tinfo->protocol_version <= SCSI_REV_2
538 && SCB_GET_LUN(scb) < 8)
539 sc->byte2 = SCB_GET_LUN(scb) << 5;
542 sc->length = sg->len;
546 * We can't allow the target to disconnect.
547 * This will be an untagged transaction and
548 * having the target disconnect will make this
549 * transaction indestinguishable from outstanding
550 * tagged transactions.
555 * This request sense could be because the
556 * the device lost power or in some other
557 * way has lost our transfer negotiations.
558 * Renegotiate if appropriate. Unit attention
559 * errors will be reported before any data
562 if (aic_get_residual(scb)
563 == aic_get_transfer_length(scb)) {
564 ahc_update_neg_request(ahc, &devinfo,
566 AHC_NEG_IF_NON_ASYNC);
568 if (tstate->auto_negotiate & devinfo.target_mask) {
569 hscb->control |= MK_MESSAGE;
570 scb->flags &= ~SCB_NEGOTIATE;
571 scb->flags |= SCB_AUTO_NEGOTIATE;
573 hscb->cdb_len = sizeof(*sc);
574 hscb->dataptr = sg->addr;
575 hscb->datacnt = sg->len;
576 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
577 hscb->sgptr = aic_htole32(hscb->sgptr);
579 scb->flags |= SCB_SENSE;
580 ahc_qinfifo_requeue_tail(ahc, scb);
581 ahc_outb(ahc, RETURN_1, SEND_SENSE);
583 * Ensure we have enough time to actually
584 * retrieve the sense, but only schedule
585 * the timer if we are not in recovery or
586 * this is a recovery SCB that is allowed
587 * to have an active timer.
589 if (ahc->scb_data->recovery_scbs == 0
590 || (scb->flags & SCB_RECOVERY_SCB) != 0)
591 aic_scb_timer_reset(scb, 5 * 1000);
601 /* Ensure we don't leave the selection hardware on */
602 ahc_outb(ahc, SCSISEQ,
603 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
605 printf("%s:%c:%d: no active SCB for reconnecting "
606 "target - issuing BUS DEVICE RESET\n",
607 ahc_name(ahc), devinfo.channel, devinfo.target);
608 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
609 "ARG_1 == 0x%x ACCUM = 0x%x\n",
610 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
611 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
612 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
614 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
615 ahc_index_busy_tcl(ahc,
616 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
617 ahc_inb(ahc, SAVED_LUN))),
618 ahc_inb(ahc, SINDEX));
619 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
620 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
621 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
622 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
623 ahc_inb(ahc, SCB_CONTROL));
624 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
625 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
626 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
627 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
628 ahc_dump_card_state(ahc);
629 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
631 ahc->msgout_index = 0;
632 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
633 ahc_outb(ahc, MSG_OUT, HOST_MSG);
639 u_int rejbyte = ahc_inb(ahc, ACCUM);
640 printf("%s:%c:%d: Warning - unknown message received from "
641 "target (0x%x). Rejecting\n",
642 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
645 case PROTO_VIOLATION:
647 ahc_handle_proto_violation(ahc);
651 ahc_handle_ign_wide_residue(ahc, &devinfo);
654 ahc_reinitialize_dataptrs(ahc);
660 lastphase = ahc_inb(ahc, LASTPHASE);
661 printf("%s:%c:%d: unknown scsi bus phase %x, "
662 "lastphase = 0x%x. Attempting to continue\n",
663 ahc_name(ahc), devinfo.channel, devinfo.target,
664 lastphase, ahc_inb(ahc, SCSISIGI));
671 lastphase = ahc_inb(ahc, LASTPHASE);
672 printf("%s:%c:%d: Missed busfree. "
673 "Lastphase = 0x%x, Curphase = 0x%x\n",
674 ahc_name(ahc), devinfo.channel, devinfo.target,
675 lastphase, ahc_inb(ahc, SCSISIGI));
682 * The sequencer has encountered a message phase
683 * that requires host assistance for completion.
684 * While handling the message phase(s), we will be
685 * notified by the sequencer after each byte is
686 * transfered so we can track bus phase changes.
688 * If this is the first time we've seen a HOST_MSG_LOOP
689 * interrupt, initialize the state of the host message
692 if (ahc->msg_type == MSG_TYPE_NONE) {
697 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
698 if (bus_phase != P_MESGIN
699 && bus_phase != P_MESGOUT) {
700 printf("ahc_intr: HOST_MSG_LOOP bad "
704 * Probably transitioned to bus free before
705 * we got here. Just punt the message.
707 ahc_clear_intstat(ahc);
712 scb_index = ahc_inb(ahc, SCB_TAG);
713 scb = ahc_lookup_scb(ahc, scb_index);
714 if (devinfo.role == ROLE_INITIATOR) {
716 panic("HOST_MSG_LOOP with "
717 "invalid SCB %x\n", scb_index);
719 if (bus_phase == P_MESGOUT)
720 ahc_setup_initiator_msgout(ahc,
725 MSG_TYPE_INITIATOR_MSGIN;
726 ahc->msgin_index = 0;
729 #ifdef AHC_TARGET_MODE
731 if (bus_phase == P_MESGOUT) {
733 MSG_TYPE_TARGET_MSGOUT;
734 ahc->msgin_index = 0;
737 ahc_setup_target_msgin(ahc,
744 ahc_handle_message_phase(ahc);
750 * If we've cleared the parity error interrupt
751 * but the sequencer still believes that SCSIPERR
752 * is true, it must be that the parity error is
753 * for the currently presented byte on the bus,
754 * and we are not in a phase (data-in) where we will
755 * eventually ack this byte. Ack the byte and
756 * throw it away in the hope that the target will
757 * take us to message out to deliver the appropriate
760 if ((intstat & SCSIINT) == 0
761 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
763 if ((ahc->features & AHC_DT) == 0) {
767 * The hardware will only let you ack bytes
768 * if the expected phase in SCSISIGO matches
769 * the current phase. Make sure this is
770 * currently the case.
772 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
773 ahc_outb(ahc, LASTPHASE, curphase);
774 ahc_outb(ahc, SCSISIGO, curphase);
776 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
780 * In a data phase. Faster to bitbucket
781 * the data than to individually ack each
782 * byte. This is also the only strategy
783 * that will work with AUTOACK enabled.
785 ahc_outb(ahc, SXFRCTL1,
786 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
788 while (--wait != 0) {
789 if ((ahc_inb(ahc, SCSISIGI)
794 ahc_outb(ahc, SXFRCTL1,
795 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
800 ahc_print_devinfo(ahc, &devinfo);
801 printf("Unable to clear parity error. "
803 scb_index = ahc_inb(ahc, SCB_TAG);
804 scb = ahc_lookup_scb(ahc, scb_index);
806 aic_set_transaction_status(scb,
808 ahc_reset_channel(ahc, devinfo.channel,
812 ahc_inb(ahc, SCSIDATL);
820 * When the sequencer detects an overrun, it
821 * places the controller in "BITBUCKET" mode
822 * and allows the target to complete its transfer.
823 * Unfortunately, none of the counters get updated
824 * when the controller is in this mode, so we have
825 * no way of knowing how large the overrun was.
827 u_int scbindex = ahc_inb(ahc, SCB_TAG);
828 u_int lastphase = ahc_inb(ahc, LASTPHASE);
831 scb = ahc_lookup_scb(ahc, scbindex);
832 for (i = 0; i < num_phases; i++) {
833 if (lastphase == ahc_phase_table[i].phase)
836 ahc_print_path(ahc, scb);
837 printf("data overrun detected %s."
839 ahc_phase_table[i].phasemsg,
841 ahc_print_path(ahc, scb);
842 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
843 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
844 aic_get_transfer_length(scb), scb->sg_count);
845 if (scb->sg_count > 0) {
846 for (i = 0; i < scb->sg_count; i++) {
848 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
850 (aic_le32toh(scb->sg_list[i].len) >> 24
851 & SG_HIGH_ADDR_BITS),
852 aic_le32toh(scb->sg_list[i].addr),
853 aic_le32toh(scb->sg_list[i].len)
858 * Set this and it will take effect when the
859 * target does a command complete.
861 ahc_freeze_devq(ahc, scb);
862 if ((scb->flags & SCB_SENSE) == 0) {
863 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
865 scb->flags &= ~SCB_SENSE;
866 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
870 if ((ahc->features & AHC_ULTRA2) != 0) {
872 * Clear the channel in case we return
873 * to data phase later.
875 ahc_outb(ahc, SXFRCTL0,
876 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
877 ahc_outb(ahc, SXFRCTL0,
878 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
880 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
883 /* Ensure HHADDR is 0 for future DMA operations. */
884 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
885 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
886 ahc_outb(ahc, HADDR, 0);
887 ahc_outb(ahc, DSCOMMAND1, dscommand1);
895 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
896 ahc_name(ahc), devinfo.channel, devinfo.target,
898 scbindex = ahc_inb(ahc, SCB_TAG);
899 scb = ahc_lookup_scb(ahc, scbindex);
901 && (scb->flags & SCB_RECOVERY_SCB) != 0)
903 * Ensure that we didn't put a second instance of this
904 * SCB into the QINFIFO.
906 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
907 SCB_GET_CHANNEL(ahc, scb),
908 SCB_GET_LUN(scb), scb->hscb->tag,
909 ROLE_INITIATOR, /*status*/0,
915 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
916 ahc_dump_card_state(ahc);
924 scbptr = ahc_inb(ahc, SCBPTR);
925 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
926 scbptr, ahc_inb(ahc, ARG_1),
927 ahc->scb_data->hscbs[scbptr].tag);
928 ahc_dump_card_state(ahc);
934 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
935 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
936 "ARG_1 == 0x%x ACCUM = 0x%x\n",
937 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
938 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
939 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
940 "SINDEX == 0x%x\n, A == 0x%x\n",
941 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
942 ahc_index_busy_tcl(ahc,
943 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
944 ahc_inb(ahc, SAVED_LUN))),
945 ahc_inb(ahc, SINDEX),
946 ahc_inb(ahc, ACCUM));
947 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
948 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
949 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
950 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
951 ahc_inb(ahc, SCB_CONTROL));
952 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
953 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
954 ahc_dump_card_state(ahc);
959 printf("ahc_intr: seqint, "
960 "intstat == 0x%x, scsisigi = 0x%x\n",
961 intstat, ahc_inb(ahc, SCSISIGI));
966 * The sequencer is paused immediately on
967 * a SEQINT, so we should restart it when
974 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
983 if ((ahc->features & AHC_TWIN) != 0
984 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
988 intr_channel = cur_channel;
990 if ((ahc->features & AHC_ULTRA2) != 0)
991 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
994 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
995 if (status == 0 && status0 == 0) {
996 if ((ahc->features & AHC_TWIN) != 0) {
997 /* Try the other channel */
998 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
999 status = ahc_inb(ahc, SSTAT1)
1000 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1001 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
1004 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1005 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1011 /* Make sure the sequencer is in a safe location. */
1012 ahc_clear_critical_section(ahc);
1014 scb_index = ahc_inb(ahc, SCB_TAG);
1015 scb = ahc_lookup_scb(ahc, scb_index);
1017 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1020 if ((ahc->features & AHC_ULTRA2) != 0
1021 && (status0 & IOERR) != 0) {
1024 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1025 printf("%s: Transceiver State Has Changed to %s mode\n",
1026 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1027 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1029 * When transitioning to SE mode, the reset line
1030 * glitches, triggering an arbitration bug in some
1031 * Ultra2 controllers. This bug is cleared when we
1032 * assert the reset line. Since a reset glitch has
1033 * already occurred with this transition and a
1034 * transceiver state change is handled just like
1035 * a bus reset anyway, asserting the reset line
1036 * ourselves is safe.
1038 ahc_reset_channel(ahc, intr_channel,
1039 /*Initiate Reset*/now_lvd == 0);
1040 } else if ((status & SCSIRSTI) != 0) {
1041 printf("%s: Someone reset channel %c\n",
1042 ahc_name(ahc), intr_channel);
1043 if (intr_channel != cur_channel)
1044 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1045 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1046 } else if ((status & SCSIPERR) != 0) {
1048 * Determine the bus phase and queue an appropriate message.
1049 * SCSIPERR is latched true as soon as a parity error
1050 * occurs. If the sequencer acked the transfer that
1051 * caused the parity error and the currently presented
1052 * transfer on the bus has correct parity, SCSIPERR will
1053 * be cleared by CLRSCSIPERR. Use this to determine if
1054 * we should look at the last phase the sequencer recorded,
1055 * or the current phase presented on the bus.
1057 struct ahc_devinfo devinfo;
1067 lastphase = ahc_inb(ahc, LASTPHASE);
1068 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1069 sstat2 = ahc_inb(ahc, SSTAT2);
1070 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1072 * For all phases save DATA, the sequencer won't
1073 * automatically ack a byte that has a parity error
1074 * in it. So the only way that the current phase
1075 * could be 'data-in' is if the parity error is for
1076 * an already acked byte in the data phase. During
1077 * synchronous data-in transfers, we may actually
1078 * ack bytes before latching the current phase in
1079 * LASTPHASE, leading to the discrepancy between
1080 * curphase and lastphase.
1082 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1083 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1084 errorphase = curphase;
1086 errorphase = lastphase;
1088 for (i = 0; i < num_phases; i++) {
1089 if (errorphase == ahc_phase_table[i].phase)
1092 mesg_out = ahc_phase_table[i].mesg_out;
1095 if (SCB_IS_SILENT(scb))
1098 ahc_print_path(ahc, scb);
1099 scb->flags |= SCB_TRANSMISSION_ERROR;
1101 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1102 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1103 scsirate = ahc_inb(ahc, SCSIRATE);
1104 if (silent == FALSE) {
1105 printf("parity error detected %s. "
1106 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1107 ahc_phase_table[i].phasemsg,
1108 ahc_inw(ahc, SEQADDR0),
1110 if ((ahc->features & AHC_DT) != 0) {
1111 if ((sstat2 & CRCVALERR) != 0)
1112 printf("\tCRC Value Mismatch\n");
1113 if ((sstat2 & CRCENDERR) != 0)
1114 printf("\tNo terminal CRC packet "
1116 if ((sstat2 & CRCREQERR) != 0)
1117 printf("\tIllegal CRC packet "
1119 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1120 printf("\tUnexpected %sDT Data Phase\n",
1121 (scsirate & SINGLE_EDGE)
1126 if ((ahc->features & AHC_DT) != 0
1127 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1129 * This error applies regardless of
1130 * data direction, so ignore the value
1131 * in the phase table.
1133 mesg_out = MSG_INITIATOR_DET_ERR;
1137 * We've set the hardware to assert ATN if we
1138 * get a parity error on "in" phases, so all we
1139 * need to do is stuff the message buffer with
1140 * the appropriate message. "In" phases have set
1141 * mesg_out to something other than MSG_NOP.
1143 if (mesg_out != MSG_NOOP) {
1144 if (ahc->msg_type != MSG_TYPE_NONE)
1145 ahc->send_msg_perror = TRUE;
1147 ahc_outb(ahc, MSG_OUT, mesg_out);
1150 * Force a renegotiation with this target just in
1151 * case we are out of sync for some external reason
1152 * unknown (or unreported) by the target.
1154 ahc_fetch_devinfo(ahc, &devinfo);
1155 ahc_force_renegotiation(ahc, &devinfo);
1157 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1159 } else if ((status & SELTO) != 0) {
1162 /* Stop the selection */
1163 ahc_outb(ahc, SCSISEQ, 0);
1165 /* No more pending messages */
1166 ahc_clear_msg_state(ahc);
1168 /* Clear interrupt state */
1169 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1170 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1173 * Although the driver does not care about the
1174 * 'Selection in Progress' status bit, the busy
1175 * LED does. SELINGO is only cleared by a sucessfull
1176 * selection, so we must manually clear it to insure
1177 * the LED turns off just incase no future successful
1178 * selections occur (e.g. no devices on the bus).
1180 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1182 scbptr = ahc_inb(ahc, WAITING_SCBH);
1183 ahc_outb(ahc, SCBPTR, scbptr);
1184 scb_index = ahc_inb(ahc, SCB_TAG);
1186 scb = ahc_lookup_scb(ahc, scb_index);
1188 printf("%s: ahc_intr - referenced scb not "
1189 "valid during SELTO scb(%d, %d)\n",
1190 ahc_name(ahc), scbptr, scb_index);
1191 ahc_dump_card_state(ahc);
1193 struct ahc_devinfo devinfo;
1195 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1196 ahc_print_path(ahc, scb);
1197 printf("Saw Selection Timeout for SCB 0x%x\n",
1201 ahc_scb_devinfo(ahc, &devinfo, scb);
1202 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1203 ahc_freeze_devq(ahc, scb);
1206 * Cancel any pending transactions on the device
1207 * now that it seems to be missing. This will
1208 * also revert us to async/narrow transfers until
1209 * we can renegotiate with the device.
1211 ahc_handle_devreset(ahc, &devinfo,
1213 "Selection Timeout",
1214 /*verbose_level*/1);
1216 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1218 } else if ((status & BUSFREE) != 0
1219 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1220 struct ahc_devinfo devinfo;
1225 u_int initiator_role_id;
1230 * Clear our selection hardware as soon as possible.
1231 * We may have an entry in the waiting Q for this target,
1232 * that is affected by this busfree and we don't want to
1233 * go about selecting the target while we handle the event.
1235 ahc_outb(ahc, SCSISEQ,
1236 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1239 * Disable busfree interrupts and clear the busfree
1240 * interrupt status. We do this here so that several
1241 * bus transactions occur prior to clearing the SCSIINT
1242 * latch. It can take a bit for the clearing to take effect.
1244 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1245 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1248 * Look at what phase we were last in.
1249 * If its message out, chances are pretty good
1250 * that the busfree was in response to one of
1251 * our abort requests.
1253 lastphase = ahc_inb(ahc, LASTPHASE);
1254 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1255 saved_lun = ahc_inb(ahc, SAVED_LUN);
1256 target = SCSIID_TARGET(ahc, saved_scsiid);
1257 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1258 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1259 ahc_compile_devinfo(&devinfo, initiator_role_id,
1260 target, saved_lun, channel, ROLE_INITIATOR);
1263 if (lastphase == P_MESGOUT) {
1266 tag = SCB_LIST_NULL;
1267 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1268 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1269 if (ahc->msgout_buf[ahc->msgout_index - 1]
1271 tag = scb->hscb->tag;
1272 ahc_print_path(ahc, scb);
1273 printf("SCB %d - Abort%s Completed.\n",
1274 scb->hscb->tag, tag == SCB_LIST_NULL ?
1276 ahc_abort_scbs(ahc, target, channel,
1281 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1282 MSG_BUS_DEV_RESET, TRUE)) {
1285 * Don't mark the user's request for this BDR
1286 * as completing with CAM_BDR_SENT. CAM3
1287 * specifies CAM_REQ_CMP.
1290 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1291 && ahc_match_scb(ahc, scb, target, channel,
1295 aic_set_transaction_status(scb, CAM_REQ_CMP);
1298 ahc_compile_devinfo(&devinfo,
1304 ahc_handle_devreset(ahc, &devinfo,
1307 /*verbose_level*/0);
1309 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1310 MSG_EXT_PPR, FALSE)) {
1311 struct ahc_initiator_tinfo *tinfo;
1312 struct ahc_tmode_tstate *tstate;
1315 * PPR Rejected. Try non-ppr negotiation
1316 * and retry command.
1318 tinfo = ahc_fetch_transinfo(ahc,
1323 tinfo->curr.transport_version = 2;
1324 tinfo->goal.transport_version = 2;
1325 tinfo->goal.ppr_options = 0;
1326 ahc_qinfifo_requeue_tail(ahc, scb);
1328 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1329 MSG_EXT_WDTR, FALSE)) {
1331 * Negotiation Rejected. Go-narrow and
1334 ahc_set_width(ahc, &devinfo,
1335 MSG_EXT_WDTR_BUS_8_BIT,
1336 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1338 ahc_qinfifo_requeue_tail(ahc, scb);
1340 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1341 MSG_EXT_SDTR, FALSE)) {
1343 * Negotiation Rejected. Go-async and
1346 ahc_set_syncrate(ahc, &devinfo,
1348 /*period*/0, /*offset*/0,
1350 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1352 ahc_qinfifo_requeue_tail(ahc, scb);
1356 if (printerror != 0) {
1362 if ((scb->hscb->control & TAG_ENB) != 0)
1363 tag = scb->hscb->tag;
1365 tag = SCB_LIST_NULL;
1366 ahc_print_path(ahc, scb);
1367 ahc_abort_scbs(ahc, target, channel,
1368 SCB_GET_LUN(scb), tag,
1373 * We had not fully identified this connection,
1374 * so we cannot abort anything.
1376 printf("%s: ", ahc_name(ahc));
1378 for (i = 0; i < num_phases; i++) {
1379 if (lastphase == ahc_phase_table[i].phase)
1382 if (lastphase != P_BUSFREE) {
1384 * Renegotiate with this device at the
1385 * next oportunity just in case this busfree
1386 * is due to a negotiation mismatch with the
1389 ahc_force_renegotiation(ahc, &devinfo);
1391 printf("Unexpected busfree %s\n"
1392 "SEQADDR == 0x%x\n",
1393 ahc_phase_table[i].phasemsg,
1394 ahc_inb(ahc, SEQADDR0)
1395 | (ahc_inb(ahc, SEQADDR1) << 8));
1397 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1400 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1401 ahc_name(ahc), status);
1402 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1407 * Force renegotiation to occur the next time we initiate
1408 * a command to the current device.
1411 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1413 struct ahc_initiator_tinfo *targ_info;
1414 struct ahc_tmode_tstate *tstate;
1416 targ_info = ahc_fetch_transinfo(ahc,
1418 devinfo->our_scsiid,
1421 ahc_update_neg_request(ahc, devinfo, tstate,
1422 targ_info, AHC_NEG_IF_NON_ASYNC);
1425 #define AHC_MAX_STEPS 2000
1427 ahc_clear_critical_section(struct ahc_softc *ahc)
1434 if (ahc->num_critical_sections == 0)
1446 seqaddr = ahc_inb(ahc, SEQADDR0)
1447 | (ahc_inb(ahc, SEQADDR1) << 8);
1450 * Seqaddr represents the next instruction to execute,
1451 * so we are really executing the instruction just
1454 cs = ahc->critical_sections;
1455 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1457 if (cs->begin < seqaddr && cs->end >= seqaddr)
1461 if (i == ahc->num_critical_sections)
1464 if (steps > AHC_MAX_STEPS) {
1465 printf("%s: Infinite loop in critical section\n",
1467 ahc_dump_card_state(ahc);
1468 panic("critical section loop");
1472 if (stepping == FALSE) {
1475 * Disable all interrupt sources so that the
1476 * sequencer will not be stuck by a pausing
1477 * interrupt condition while we attempt to
1478 * leave a critical section.
1480 simode0 = ahc_inb(ahc, SIMODE0);
1481 ahc_outb(ahc, SIMODE0, 0);
1482 simode1 = ahc_inb(ahc, SIMODE1);
1483 if ((ahc->features & AHC_DT) != 0)
1485 * On DT class controllers, we
1486 * use the enhanced busfree logic.
1487 * Unfortunately we cannot re-enable
1488 * busfree detection within the
1489 * current connection, so we must
1490 * leave it on while single stepping.
1492 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1494 ahc_outb(ahc, SIMODE1, 0);
1495 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1496 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1499 if ((ahc->features & AHC_DT) != 0) {
1500 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1501 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1503 ahc_outb(ahc, HCNTRL, ahc->unpause);
1504 while (!ahc_is_paused(ahc))
1508 ahc_outb(ahc, SIMODE0, simode0);
1509 ahc_outb(ahc, SIMODE1, simode1);
1510 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1515 * Clear any pending interrupt status.
1518 ahc_clear_intstat(struct ahc_softc *ahc)
1520 /* Clear any interrupt conditions this may have caused */
1521 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1522 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1524 ahc_flush_device_writes(ahc);
1525 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1526 ahc_flush_device_writes(ahc);
1527 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1528 ahc_flush_device_writes(ahc);
1531 /**************************** Debugging Routines ******************************/
1533 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1537 ahc_print_scb(struct scb *scb)
1541 struct hardware_scb *hscb = scb->hscb;
1543 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1549 printf("Shared Data: ");
1550 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1551 printf("%#02x", hscb->shared_data.cdb[i]);
1552 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1553 aic_le32toh(hscb->dataptr),
1554 aic_le32toh(hscb->datacnt),
1555 aic_le32toh(hscb->sgptr),
1557 if (scb->sg_count > 0) {
1558 for (i = 0; i < scb->sg_count; i++) {
1559 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1561 (aic_le32toh(scb->sg_list[i].len) >> 24
1562 & SG_HIGH_ADDR_BITS),
1563 aic_le32toh(scb->sg_list[i].addr),
1564 aic_le32toh(scb->sg_list[i].len));
1569 /************************* Transfer Negotiation *******************************/
1571 * Allocate per target mode instance (ID we respond to as a target)
1572 * transfer negotiation data structures.
1574 static struct ahc_tmode_tstate *
1575 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1577 struct ahc_tmode_tstate *master_tstate;
1578 struct ahc_tmode_tstate *tstate;
1581 master_tstate = ahc->enabled_targets[ahc->our_id];
1582 if (channel == 'B') {
1584 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1586 if (ahc->enabled_targets[scsi_id] != NULL
1587 && ahc->enabled_targets[scsi_id] != master_tstate)
1588 panic("%s: ahc_alloc_tstate - Target already allocated",
1590 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1591 M_DEVBUF, M_NOWAIT);
1596 * If we have allocated a master tstate, copy user settings from
1597 * the master tstate (taken from SRAM or the EEPROM) for this
1598 * channel, but reset our current and goal settings to async/narrow
1599 * until an initiator talks to us.
1601 if (master_tstate != NULL) {
1602 memcpy(tstate, master_tstate, sizeof(*tstate));
1603 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1604 tstate->ultraenb = 0;
1605 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1606 memset(&tstate->transinfo[i].curr, 0,
1607 sizeof(tstate->transinfo[i].curr));
1608 memset(&tstate->transinfo[i].goal, 0,
1609 sizeof(tstate->transinfo[i].goal));
1612 memset(tstate, 0, sizeof(*tstate));
1613 ahc->enabled_targets[scsi_id] = tstate;
1617 #ifdef AHC_TARGET_MODE
1619 * Free per target mode instance (ID we respond to as a target)
1620 * transfer negotiation data structures.
1623 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1625 struct ahc_tmode_tstate *tstate;
1628 * Don't clean up our "master" tstate.
1629 * It has our default user settings.
1631 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1632 || (channel == 'A' && scsi_id == ahc->our_id))
1638 tstate = ahc->enabled_targets[scsi_id];
1640 free(tstate, M_DEVBUF);
1641 ahc->enabled_targets[scsi_id] = NULL;
1646 * Called when we have an active connection to a target on the bus,
1647 * this function finds the nearest syncrate to the input period limited
1648 * by the capabilities of the bus connectivity of and sync settings for
1651 struct ahc_syncrate *
1652 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1653 struct ahc_initiator_tinfo *tinfo,
1654 u_int *period, u_int *ppr_options, role_t role)
1656 struct ahc_transinfo *transinfo;
1659 if ((ahc->features & AHC_ULTRA2) != 0) {
1660 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1661 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1662 maxsync = AHC_SYNCRATE_DT;
1664 maxsync = AHC_SYNCRATE_ULTRA;
1665 /* Can't do DT on an SE bus */
1666 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1668 } else if ((ahc->features & AHC_ULTRA) != 0) {
1669 maxsync = AHC_SYNCRATE_ULTRA;
1671 maxsync = AHC_SYNCRATE_FAST;
1674 * Never allow a value higher than our current goal
1675 * period otherwise we may allow a target initiated
1676 * negotiation to go above the limit as set by the
1677 * user. In the case of an initiator initiated
1678 * sync negotiation, we limit based on the user
1679 * setting. This allows the system to still accept
1680 * incoming negotiations even if target initiated
1681 * negotiation is not performed.
1683 if (role == ROLE_TARGET)
1684 transinfo = &tinfo->user;
1686 transinfo = &tinfo->goal;
1687 *ppr_options &= transinfo->ppr_options;
1688 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1689 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1690 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1692 if (transinfo->period == 0) {
1697 *period = MAX(*period, transinfo->period);
1698 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1702 * Look up the valid period to SCSIRATE conversion in our table.
1703 * Return the period and offset that should be sent to the target
1704 * if this was the beginning of an SDTR.
1706 struct ahc_syncrate *
1707 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1708 u_int *ppr_options, u_int maxsync)
1710 struct ahc_syncrate *syncrate;
1712 if ((ahc->features & AHC_DT) == 0)
1713 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1715 /* Skip all DT only entries if DT is not available */
1716 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1717 && maxsync < AHC_SYNCRATE_ULTRA2)
1718 maxsync = AHC_SYNCRATE_ULTRA2;
1720 for (syncrate = &ahc_syncrates[maxsync];
1721 syncrate->rate != NULL;
1725 * The Ultra2 table doesn't go as low
1726 * as for the Fast/Ultra cards.
1728 if ((ahc->features & AHC_ULTRA2) != 0
1729 && (syncrate->sxfr_u2 == 0))
1732 if (*period <= syncrate->period) {
1734 * When responding to a target that requests
1735 * sync, the requested rate may fall between
1736 * two rates that we can output, but still be
1737 * a rate that we can receive. Because of this,
1738 * we want to respond to the target with
1739 * the same rate that it sent to us even
1740 * if the period we use to send data to it
1741 * is lower. Only lower the response period
1744 if (syncrate == &ahc_syncrates[maxsync])
1745 *period = syncrate->period;
1748 * At some speeds, we only support
1751 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1752 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1758 || (syncrate->rate == NULL)
1759 || ((ahc->features & AHC_ULTRA2) != 0
1760 && (syncrate->sxfr_u2 == 0))) {
1761 /* Use asynchronous transfers. */
1764 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1770 * Convert from an entry in our syncrate table to the SCSI equivalent
1771 * sync "period" factor.
1774 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1776 struct ahc_syncrate *syncrate;
1778 if ((ahc->features & AHC_ULTRA2) != 0)
1779 scsirate &= SXFR_ULTRA2;
1783 syncrate = &ahc_syncrates[maxsync];
1784 while (syncrate->rate != NULL) {
1786 if ((ahc->features & AHC_ULTRA2) != 0) {
1787 if (syncrate->sxfr_u2 == 0)
1789 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1790 return (syncrate->period);
1791 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1792 return (syncrate->period);
1796 return (0); /* async */
1800 * Truncate the given synchronous offset to a value the
1801 * current adapter type and syncrate are capable of.
1804 ahc_validate_offset(struct ahc_softc *ahc,
1805 struct ahc_initiator_tinfo *tinfo,
1806 struct ahc_syncrate *syncrate,
1807 u_int *offset, int wide, role_t role)
1811 /* Limit offset to what we can do */
1812 if (syncrate == NULL) {
1814 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1815 maxoffset = MAX_OFFSET_ULTRA2;
1818 maxoffset = MAX_OFFSET_16BIT;
1820 maxoffset = MAX_OFFSET_8BIT;
1822 *offset = MIN(*offset, maxoffset);
1823 if (tinfo != NULL) {
1824 if (role == ROLE_TARGET)
1825 *offset = MIN(*offset, tinfo->user.offset);
1827 *offset = MIN(*offset, tinfo->goal.offset);
1832 * Truncate the given transfer width parameter to a value the
1833 * current adapter type is capable of.
1836 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1837 u_int *bus_width, role_t role)
1839 switch (*bus_width) {
1841 if (ahc->features & AHC_WIDE) {
1843 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1847 case MSG_EXT_WDTR_BUS_8_BIT:
1848 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1851 if (tinfo != NULL) {
1852 if (role == ROLE_TARGET)
1853 *bus_width = MIN(tinfo->user.width, *bus_width);
1855 *bus_width = MIN(tinfo->goal.width, *bus_width);
1860 * Update the bitmask of targets for which the controller should
1861 * negotiate with at the next convenient oportunity. This currently
1862 * means the next time we send the initial identify messages for
1863 * a new transaction.
1866 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1867 struct ahc_tmode_tstate *tstate,
1868 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1870 u_int auto_negotiate_orig;
1872 auto_negotiate_orig = tstate->auto_negotiate;
1873 if (neg_type == AHC_NEG_ALWAYS) {
1875 * Force our "current" settings to be
1876 * unknown so that unless a bus reset
1877 * occurs the need to renegotiate is
1878 * recorded persistently.
1880 if ((ahc->features & AHC_WIDE) != 0)
1881 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1882 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1883 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1885 if (tinfo->curr.period != tinfo->goal.period
1886 || tinfo->curr.width != tinfo->goal.width
1887 || tinfo->curr.offset != tinfo->goal.offset
1888 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1889 || (neg_type == AHC_NEG_IF_NON_ASYNC
1890 && (tinfo->goal.offset != 0
1891 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1892 || tinfo->goal.ppr_options != 0)))
1893 tstate->auto_negotiate |= devinfo->target_mask;
1895 tstate->auto_negotiate &= ~devinfo->target_mask;
1897 return (auto_negotiate_orig != tstate->auto_negotiate);
1901 * Update the user/goal/curr tables of synchronous negotiation
1902 * parameters as well as, in the case of a current or active update,
1903 * any data structures on the host controller. In the case of an
1904 * active update, the specified target is currently talking to us on
1905 * the bus, so the transfer parameter update must take effect
1909 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1910 struct ahc_syncrate *syncrate, u_int period,
1911 u_int offset, u_int ppr_options, u_int type, int paused)
1913 struct ahc_initiator_tinfo *tinfo;
1914 struct ahc_tmode_tstate *tstate;
1921 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1924 if (syncrate == NULL) {
1929 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1930 devinfo->target, &tstate);
1932 if ((type & AHC_TRANS_USER) != 0) {
1933 tinfo->user.period = period;
1934 tinfo->user.offset = offset;
1935 tinfo->user.ppr_options = ppr_options;
1938 if ((type & AHC_TRANS_GOAL) != 0) {
1939 tinfo->goal.period = period;
1940 tinfo->goal.offset = offset;
1941 tinfo->goal.ppr_options = ppr_options;
1944 old_period = tinfo->curr.period;
1945 old_offset = tinfo->curr.offset;
1946 old_ppr = tinfo->curr.ppr_options;
1948 if ((type & AHC_TRANS_CUR) != 0
1949 && (old_period != period
1950 || old_offset != offset
1951 || old_ppr != ppr_options)) {
1955 scsirate = tinfo->scsirate;
1956 if ((ahc->features & AHC_ULTRA2) != 0) {
1958 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1959 if (syncrate != NULL) {
1960 scsirate |= syncrate->sxfr_u2;
1961 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1962 scsirate |= ENABLE_CRC;
1964 scsirate |= SINGLE_EDGE;
1968 scsirate &= ~(SXFR|SOFS);
1970 * Ensure Ultra mode is set properly for
1973 tstate->ultraenb &= ~devinfo->target_mask;
1974 if (syncrate != NULL) {
1975 if (syncrate->sxfr & ULTRA_SXFR) {
1977 devinfo->target_mask;
1979 scsirate |= syncrate->sxfr & SXFR;
1980 scsirate |= offset & SOFS;
1985 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1986 sxfrctl0 &= ~FAST20;
1987 if (tstate->ultraenb & devinfo->target_mask)
1989 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1993 ahc_outb(ahc, SCSIRATE, scsirate);
1994 if ((ahc->features & AHC_ULTRA2) != 0)
1995 ahc_outb(ahc, SCSIOFFSET, offset);
1998 tinfo->scsirate = scsirate;
1999 tinfo->curr.period = period;
2000 tinfo->curr.offset = offset;
2001 tinfo->curr.ppr_options = ppr_options;
2003 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2004 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2007 printf("%s: target %d synchronous at %sMHz%s, "
2008 "offset = 0x%x\n", ahc_name(ahc),
2009 devinfo->target, syncrate->rate,
2010 (ppr_options & MSG_EXT_PPR_DT_REQ)
2011 ? " DT" : "", offset);
2013 printf("%s: target %d using "
2014 "asynchronous transfers\n",
2015 ahc_name(ahc), devinfo->target);
2020 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2021 tinfo, AHC_NEG_TO_GOAL);
2024 ahc_update_pending_scbs(ahc);
2028 * Update the user/goal/curr tables of wide negotiation
2029 * parameters as well as, in the case of a current or active update,
2030 * any data structures on the host controller. In the case of an
2031 * active update, the specified target is currently talking to us on
2032 * the bus, so the transfer parameter update must take effect
2036 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2037 u_int width, u_int type, int paused)
2039 struct ahc_initiator_tinfo *tinfo;
2040 struct ahc_tmode_tstate *tstate;
2045 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2047 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2048 devinfo->target, &tstate);
2050 if ((type & AHC_TRANS_USER) != 0)
2051 tinfo->user.width = width;
2053 if ((type & AHC_TRANS_GOAL) != 0)
2054 tinfo->goal.width = width;
2056 oldwidth = tinfo->curr.width;
2057 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2061 scsirate = tinfo->scsirate;
2062 scsirate &= ~WIDEXFER;
2063 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2064 scsirate |= WIDEXFER;
2066 tinfo->scsirate = scsirate;
2069 ahc_outb(ahc, SCSIRATE, scsirate);
2071 tinfo->curr.width = width;
2073 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2074 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2076 printf("%s: target %d using %dbit transfers\n",
2077 ahc_name(ahc), devinfo->target,
2078 8 * (0x01 << width));
2082 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2083 tinfo, AHC_NEG_TO_GOAL);
2085 ahc_update_pending_scbs(ahc);
2089 * Update the current state of tagged queuing for a given target.
2092 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2095 ahc_platform_set_tags(ahc, devinfo, alg);
2096 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2097 devinfo->lun, AC_TRANSFER_NEG, &alg);
2101 * When the transfer settings for a connection change, update any
2102 * in-transit SCBs to contain the new data so the hardware will
2103 * be set correctly during future (re)selections.
2106 ahc_update_pending_scbs(struct ahc_softc *ahc)
2108 struct scb *pending_scb;
2109 int pending_scb_count;
2115 * Traverse the pending SCB list and ensure that all of the
2116 * SCBs there have the proper settings.
2118 pending_scb_count = 0;
2119 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2120 struct ahc_devinfo devinfo;
2121 struct hardware_scb *pending_hscb;
2122 struct ahc_initiator_tinfo *tinfo;
2123 struct ahc_tmode_tstate *tstate;
2125 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2126 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2128 devinfo.target, &tstate);
2129 pending_hscb = pending_scb->hscb;
2130 pending_hscb->control &= ~ULTRAENB;
2131 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2132 pending_hscb->control |= ULTRAENB;
2133 pending_hscb->scsirate = tinfo->scsirate;
2134 pending_hscb->scsioffset = tinfo->curr.offset;
2135 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2136 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2137 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2138 pending_hscb->control &= ~MK_MESSAGE;
2140 ahc_sync_scb(ahc, pending_scb,
2141 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2142 pending_scb_count++;
2145 if (pending_scb_count == 0)
2148 if (ahc_is_paused(ahc)) {
2155 saved_scbptr = ahc_inb(ahc, SCBPTR);
2156 /* Ensure that the hscbs down on the card match the new information */
2157 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2158 struct hardware_scb *pending_hscb;
2162 ahc_outb(ahc, SCBPTR, i);
2163 scb_tag = ahc_inb(ahc, SCB_TAG);
2164 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2165 if (pending_scb == NULL)
2168 pending_hscb = pending_scb->hscb;
2169 control = ahc_inb(ahc, SCB_CONTROL);
2170 control &= ~(ULTRAENB|MK_MESSAGE);
2171 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2172 ahc_outb(ahc, SCB_CONTROL, control);
2173 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2174 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2176 ahc_outb(ahc, SCBPTR, saved_scbptr);
2182 /**************************** Pathing Information *****************************/
2184 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2190 if (ahc_inb(ahc, SSTAT0) & TARGET)
2193 role = ROLE_INITIATOR;
2195 if (role == ROLE_TARGET
2196 && (ahc->features & AHC_MULTI_TID) != 0
2197 && (ahc_inb(ahc, SEQ_FLAGS)
2198 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2199 /* We were selected, so pull our id from TARGIDIN */
2200 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2201 } else if ((ahc->features & AHC_ULTRA2) != 0)
2202 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2204 our_id = ahc_inb(ahc, SCSIID) & OID;
2206 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2207 ahc_compile_devinfo(devinfo,
2209 SCSIID_TARGET(ahc, saved_scsiid),
2210 ahc_inb(ahc, SAVED_LUN),
2211 SCSIID_CHANNEL(ahc, saved_scsiid),
2215 struct ahc_phase_table_entry*
2216 ahc_lookup_phase_entry(int phase)
2218 struct ahc_phase_table_entry *entry;
2219 struct ahc_phase_table_entry *last_entry;
2222 * num_phases doesn't include the default entry which
2223 * will be returned if the phase doesn't match.
2225 last_entry = &ahc_phase_table[num_phases];
2226 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2227 if (phase == entry->phase)
2234 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2235 u_int lun, char channel, role_t role)
2237 devinfo->our_scsiid = our_id;
2238 devinfo->target = target;
2240 devinfo->target_offset = target;
2241 devinfo->channel = channel;
2242 devinfo->role = role;
2244 devinfo->target_offset += 8;
2245 devinfo->target_mask = (0x01 << devinfo->target_offset);
2249 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2251 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2252 devinfo->target, devinfo->lun);
2256 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2262 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2263 role = ROLE_INITIATOR;
2264 if ((scb->flags & SCB_TARGET_SCB) != 0)
2266 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2267 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2271 /************************ Message Phase Processing ****************************/
2273 ahc_assert_atn(struct ahc_softc *ahc)
2278 if ((ahc->features & AHC_DT) == 0)
2279 scsisigo |= ahc_inb(ahc, SCSISIGI);
2280 ahc_outb(ahc, SCSISIGO, scsisigo);
2284 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2285 * or enters the initial message out phase, we are interrupted. Fill our
2286 * outgoing message buffer with the appropriate message and beging handing
2287 * the message phase(s) manually.
2290 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2294 * To facilitate adding multiple messages together,
2295 * each routine should increment the index and len
2296 * variables instead of setting them explicitly.
2298 ahc->msgout_index = 0;
2299 ahc->msgout_len = 0;
2301 if ((scb->flags & SCB_DEVICE_RESET) == 0
2302 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2305 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2306 if ((scb->hscb->control & DISCENB) != 0)
2307 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2308 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2311 if ((scb->hscb->control & TAG_ENB) != 0) {
2312 ahc->msgout_buf[ahc->msgout_index++] =
2313 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2314 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2315 ahc->msgout_len += 2;
2319 if (scb->flags & SCB_DEVICE_RESET) {
2320 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2322 ahc_print_path(ahc, scb);
2323 printf("Bus Device Reset Message Sent\n");
2325 * Clear our selection hardware in advance of
2326 * the busfree. We may have an entry in the waiting
2327 * Q for this target, and we don't want to go about
2328 * selecting while we handle the busfree and blow it
2331 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2332 } else if ((scb->flags & SCB_ABORT) != 0) {
2333 if ((scb->hscb->control & TAG_ENB) != 0)
2334 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2336 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2338 ahc_print_path(ahc, scb);
2339 printf("Abort%s Message Sent\n",
2340 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2342 * Clear our selection hardware in advance of
2343 * the busfree. We may have an entry in the waiting
2344 * Q for this target, and we don't want to go about
2345 * selecting while we handle the busfree and blow it
2348 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2349 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2350 ahc_build_transfer_msg(ahc, devinfo);
2352 printf("ahc_intr: AWAITING_MSG for an SCB that "
2353 "does not have a waiting message\n");
2354 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2355 devinfo->target_mask);
2356 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2357 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2358 ahc_inb(ahc, MSG_OUT), scb->flags);
2362 * Clear the MK_MESSAGE flag from the SCB so we aren't
2363 * asked to send this message again.
2365 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2366 scb->hscb->control &= ~MK_MESSAGE;
2367 ahc->msgout_index = 0;
2368 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2372 * Build an appropriate transfer negotiation message for the
2373 * currently active target.
2376 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2379 * We need to initiate transfer negotiations.
2380 * If our current and goal settings are identical,
2381 * we want to renegotiate due to a check condition.
2383 struct ahc_initiator_tinfo *tinfo;
2384 struct ahc_tmode_tstate *tstate;
2385 struct ahc_syncrate *rate;
2393 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2394 devinfo->target, &tstate);
2396 * Filter our period based on the current connection.
2397 * If we can't perform DT transfers on this segment (not in LVD
2398 * mode for instance), then our decision to issue a PPR message
2401 period = tinfo->goal.period;
2402 offset = tinfo->goal.offset;
2403 ppr_options = tinfo->goal.ppr_options;
2404 /* Target initiated PPR is not allowed in the SCSI spec */
2405 if (devinfo->role == ROLE_TARGET)
2407 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2408 &ppr_options, devinfo->role);
2409 dowide = tinfo->curr.width != tinfo->goal.width;
2410 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2412 * Only use PPR if we have options that need it, even if the device
2413 * claims to support it. There might be an expander in the way
2416 doppr = ppr_options != 0;
2418 if (!dowide && !dosync && !doppr) {
2419 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2420 dosync = tinfo->goal.offset != 0;
2423 if (!dowide && !dosync && !doppr) {
2425 * Force async with a WDTR message if we have a wide bus,
2426 * or just issue an SDTR with a 0 offset.
2428 if ((ahc->features & AHC_WIDE) != 0)
2434 ahc_print_devinfo(ahc, devinfo);
2435 printf("Ensuring async\n");
2439 /* Target initiated PPR is not allowed in the SCSI spec */
2440 if (devinfo->role == ROLE_TARGET)
2444 * Both the PPR message and SDTR message require the
2445 * goal syncrate to be limited to what the target device
2446 * is capable of handling (based on whether an LVD->SE
2447 * expander is on the bus), so combine these two cases.
2448 * Regardless, guarantee that if we are using WDTR and SDTR
2449 * messages that WDTR comes first.
2451 if (doppr || (dosync && !dowide)) {
2453 offset = tinfo->goal.offset;
2454 ahc_validate_offset(ahc, tinfo, rate, &offset,
2455 doppr ? tinfo->goal.width
2456 : tinfo->curr.width,
2459 ahc_construct_ppr(ahc, devinfo, period, offset,
2460 tinfo->goal.width, ppr_options);
2462 ahc_construct_sdtr(ahc, devinfo, period, offset);
2465 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2470 * Build a synchronous negotiation message in our message
2471 * buffer based on the input parameters.
2474 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2475 u_int period, u_int offset)
2478 period = AHC_ASYNC_XFER_PERIOD;
2479 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2481 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2482 ahc->msgout_buf[ahc->msgout_index++] = period;
2483 ahc->msgout_buf[ahc->msgout_index++] = offset;
2484 ahc->msgout_len += 5;
2486 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2487 ahc_name(ahc), devinfo->channel, devinfo->target,
2488 devinfo->lun, period, offset);
2493 * Build a wide negotiation message in our message
2494 * buffer based on the input parameters.
2497 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2500 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2501 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2502 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2503 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2504 ahc->msgout_len += 4;
2506 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2507 ahc_name(ahc), devinfo->channel, devinfo->target,
2508 devinfo->lun, bus_width);
2513 * Build a parallel protocol request message in our message
2514 * buffer based on the input parameters.
2517 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2518 u_int period, u_int offset, u_int bus_width,
2522 period = AHC_ASYNC_XFER_PERIOD;
2523 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2524 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2525 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2526 ahc->msgout_buf[ahc->msgout_index++] = period;
2527 ahc->msgout_buf[ahc->msgout_index++] = 0;
2528 ahc->msgout_buf[ahc->msgout_index++] = offset;
2529 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2530 ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2531 ahc->msgout_len += 8;
2533 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2534 "offset %x, ppr_options %x\n", ahc_name(ahc),
2535 devinfo->channel, devinfo->target, devinfo->lun,
2536 bus_width, period, offset, ppr_options);
2541 * Clear any active message state.
2544 ahc_clear_msg_state(struct ahc_softc *ahc)
2546 ahc->msgout_len = 0;
2547 ahc->msgin_index = 0;
2548 ahc->msg_type = MSG_TYPE_NONE;
2549 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2551 * The target didn't care to respond to our
2552 * message request, so clear ATN.
2554 ahc_outb(ahc, CLRSINT1, CLRATNO);
2556 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2557 ahc_outb(ahc, SEQ_FLAGS2,
2558 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2562 ahc_handle_proto_violation(struct ahc_softc *ahc)
2564 struct ahc_devinfo devinfo;
2572 ahc_fetch_devinfo(ahc, &devinfo);
2573 scbid = ahc_inb(ahc, SCB_TAG);
2574 scb = ahc_lookup_scb(ahc, scbid);
2575 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2576 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2577 lastphase = ahc_inb(ahc, LASTPHASE);
2578 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2581 * The reconnecting target either did not send an
2582 * identify message, or did, but we didn't find an SCB
2585 ahc_print_devinfo(ahc, &devinfo);
2586 printf("Target did not send an IDENTIFY message. "
2587 "LASTPHASE = 0x%x.\n", lastphase);
2589 } else if (scb == NULL) {
2591 * We don't seem to have an SCB active for this
2592 * transaction. Print an error and reset the bus.
2594 ahc_print_devinfo(ahc, &devinfo);
2595 printf("No SCB found during protocol violation\n");
2596 goto proto_violation_reset;
2598 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2599 if ((seq_flags & NO_CDB_SENT) != 0) {
2600 ahc_print_path(ahc, scb);
2601 printf("No or incomplete CDB sent to device.\n");
2602 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2604 * The target never bothered to provide status to
2605 * us prior to completing the command. Since we don't
2606 * know the disposition of this command, we must attempt
2607 * to abort it. Assert ATN and prepare to send an abort
2610 ahc_print_path(ahc, scb);
2611 printf("Completed command without status.\n");
2613 ahc_print_path(ahc, scb);
2614 printf("Unknown protocol violation.\n");
2615 ahc_dump_card_state(ahc);
2618 if ((lastphase & ~P_DATAIN_DT) == 0
2619 || lastphase == P_COMMAND) {
2620 proto_violation_reset:
2622 * Target either went directly to data/command
2623 * phase or didn't respond to our ATN.
2624 * The only safe thing to do is to blow
2625 * it away with a bus reset.
2627 found = ahc_reset_channel(ahc, 'A', TRUE);
2628 printf("%s: Issued Channel %c Bus Reset. "
2629 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2632 * Leave the selection hardware off in case
2633 * this abort attempt will affect yet to
2636 ahc_outb(ahc, SCSISEQ,
2637 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2638 ahc_assert_atn(ahc);
2639 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2641 ahc_print_devinfo(ahc, &devinfo);
2642 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2643 ahc->msgout_len = 1;
2644 ahc->msgout_index = 0;
2645 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2647 ahc_print_path(ahc, scb);
2648 scb->flags |= SCB_ABORT;
2650 printf("Protocol violation %s. Attempting to abort.\n",
2651 ahc_lookup_phase_entry(curphase)->phasemsg);
2656 * Manual message loop handler.
2659 ahc_handle_message_phase(struct ahc_softc *ahc)
2661 struct ahc_devinfo devinfo;
2665 ahc_fetch_devinfo(ahc, &devinfo);
2666 end_session = FALSE;
2667 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2670 switch (ahc->msg_type) {
2671 case MSG_TYPE_INITIATOR_MSGOUT:
2677 if (ahc->msgout_len == 0)
2678 panic("HOST_MSG_LOOP interrupt with no active message");
2681 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2682 ahc_print_devinfo(ahc, &devinfo);
2683 printf("INITIATOR_MSG_OUT");
2686 phasemis = bus_phase != P_MESGOUT;
2689 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2690 printf(" PHASEMIS %s\n",
2691 ahc_lookup_phase_entry(bus_phase)
2695 if (bus_phase == P_MESGIN) {
2697 * Change gears and see if
2698 * this messages is of interest to
2699 * us or should be passed back to
2702 ahc_outb(ahc, CLRSINT1, CLRATNO);
2703 ahc->send_msg_perror = FALSE;
2704 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2705 ahc->msgin_index = 0;
2712 if (ahc->send_msg_perror) {
2713 ahc_outb(ahc, CLRSINT1, CLRATNO);
2714 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2716 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2717 printf(" byte 0x%x\n", ahc->send_msg_perror);
2719 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2723 msgdone = ahc->msgout_index == ahc->msgout_len;
2726 * The target has requested a retry.
2727 * Re-assert ATN, reset our message index to
2730 ahc->msgout_index = 0;
2731 ahc_assert_atn(ahc);
2734 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2736 /* Last byte is signified by dropping ATN */
2737 ahc_outb(ahc, CLRSINT1, CLRATNO);
2741 * Clear our interrupt status and present
2742 * the next byte on the bus.
2744 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2746 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2747 printf(" byte 0x%x\n",
2748 ahc->msgout_buf[ahc->msgout_index]);
2750 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2753 case MSG_TYPE_INITIATOR_MSGIN:
2759 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2760 ahc_print_devinfo(ahc, &devinfo);
2761 printf("INITIATOR_MSG_IN");
2764 phasemis = bus_phase != P_MESGIN;
2767 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2768 printf(" PHASEMIS %s\n",
2769 ahc_lookup_phase_entry(bus_phase)
2773 ahc->msgin_index = 0;
2774 if (bus_phase == P_MESGOUT
2775 && (ahc->send_msg_perror == TRUE
2776 || (ahc->msgout_len != 0
2777 && ahc->msgout_index == 0))) {
2778 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2785 /* Pull the byte in without acking it */
2786 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2788 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2789 printf(" byte 0x%x\n",
2790 ahc->msgin_buf[ahc->msgin_index]);
2793 message_done = ahc_parse_msg(ahc, &devinfo);
2797 * Clear our incoming message buffer in case there
2798 * is another message following this one.
2800 ahc->msgin_index = 0;
2803 * If this message illicited a response,
2804 * assert ATN so the target takes us to the
2805 * message out phase.
2807 if (ahc->msgout_len != 0) {
2809 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2810 ahc_print_devinfo(ahc, &devinfo);
2811 printf("Asserting ATN for response\n");
2814 ahc_assert_atn(ahc);
2819 if (message_done == MSGLOOP_TERMINATED) {
2823 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2824 ahc_inb(ahc, SCSIDATL);
2828 case MSG_TYPE_TARGET_MSGIN:
2832 if (ahc->msgout_len == 0)
2833 panic("Target MSGIN with no active message");
2836 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2837 ahc_print_devinfo(ahc, &devinfo);
2838 printf("TARGET_MSG_IN");
2843 * If we interrupted a mesgout session, the initiator
2844 * will not know this until our first REQ. So, we
2845 * only honor mesgout requests after we've sent our
2848 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2849 && ahc->msgout_index > 0) {
2852 * Change gears and see if this messages is
2853 * of interest to us or should be passed back
2857 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2858 printf(" Honoring ATN Request.\n");
2860 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2863 * Disable SCSI Programmed I/O during the
2864 * phase change so as to avoid phantom REQs.
2866 ahc_outb(ahc, SXFRCTL0,
2867 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2870 * Since SPIORDY asserts when ACK is asserted
2871 * for P_MSGOUT, and SPIORDY's assertion triggered
2872 * our entry into this routine, wait for ACK to
2873 * *de-assert* before changing phases.
2875 while ((ahc_inb(ahc, SCSISIGI) & ACKI) != 0)
2878 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2881 * All phase line changes require a bus
2882 * settle delay before REQ is asserted.
2883 * [SCSI SPI4 10.7.1]
2885 ahc_flush_device_writes(ahc);
2886 aic_delay(AHC_BUSSETTLE_DELAY);
2888 ahc->msgin_index = 0;
2889 /* Enable SCSI Programmed I/O to REQ for first byte */
2890 ahc_outb(ahc, SXFRCTL0,
2891 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2895 msgdone = ahc->msgout_index == ahc->msgout_len;
2897 ahc_outb(ahc, SXFRCTL0,
2898 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2904 * Present the next byte on the bus.
2907 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2908 printf(" byte 0x%x\n",
2909 ahc->msgout_buf[ahc->msgout_index]);
2911 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2912 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2915 case MSG_TYPE_TARGET_MSGOUT:
2921 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2922 ahc_print_devinfo(ahc, &devinfo);
2923 printf("TARGET_MSG_OUT");
2927 * The initiator signals that this is
2928 * the last byte by dropping ATN.
2930 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2933 * Read the latched byte, but turn off SPIOEN first
2934 * so that we don't inadvertently cause a REQ for the
2937 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2938 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2941 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2942 printf(" byte 0x%x\n",
2943 ahc->msgin_buf[ahc->msgin_index]);
2946 msgdone = ahc_parse_msg(ahc, &devinfo);
2947 if (msgdone == MSGLOOP_TERMINATED) {
2949 * The message is *really* done in that it caused
2950 * us to go to bus free. The sequencer has already
2951 * been reset at this point, so pull the ejection
2960 * XXX Read spec about initiator dropping ATN too soon
2961 * and use msgdone to detect it.
2963 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2964 ahc->msgin_index = 0;
2967 * If this message illicited a response, transition
2968 * to the Message in phase and send it.
2970 if (ahc->msgout_len != 0) {
2972 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2973 ahc_print_devinfo(ahc, &devinfo);
2974 printf(" preparing response.\n");
2977 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2980 * All phase line changes require a bus
2981 * settle delay before REQ is asserted.
2982 * [SCSI SPI4 10.7.1] When transitioning
2983 * from an OUT to an IN phase, we must
2984 * also wait a data release delay to allow
2985 * the initiator time to release the data
2986 * lines. [SCSI SPI4 10.12]
2988 ahc_flush_device_writes(ahc);
2989 aic_delay(AHC_BUSSETTLE_DELAY
2990 + AHC_DATARELEASE_DELAY);
2993 * Enable SCSI Programmed I/O. This will
2994 * immediately cause SPIORDY to assert,
2995 * and the sequencer will call our message
2998 ahc_outb(ahc, SXFRCTL0,
2999 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3000 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3001 ahc->msgin_index = 0;
3009 /* Ask for the next byte. */
3010 ahc_outb(ahc, SXFRCTL0,
3011 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3017 panic("Unknown REQINIT message type");
3021 ahc_clear_msg_state(ahc);
3022 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3024 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3028 * See if we sent a particular extended message to the target.
3029 * If "full" is true, return true only if the target saw the full
3030 * message. If "full" is false, return true if the target saw at
3031 * least the first byte of the message.
3034 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3042 while (index < ahc->msgout_len) {
3043 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3046 end_index = index + 1 + ahc->msgout_buf[index + 1];
3047 if (ahc->msgout_buf[index+2] == msgval
3048 && type == AHCMSG_EXT) {
3051 if (ahc->msgout_index > end_index)
3053 } else if (ahc->msgout_index > index)
3057 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3058 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3060 /* Skip tag type and tag id or residue param*/
3063 /* Single byte message */
3064 if (type == AHCMSG_1B
3065 && ahc->msgout_buf[index] == msgval
3066 && ahc->msgout_index > index)
3078 * Wait for a complete incoming message, parse it, and respond accordingly.
3081 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3083 struct ahc_initiator_tinfo *tinfo;
3084 struct ahc_tmode_tstate *tstate;
3088 u_int targ_scsirate;
3090 done = MSGLOOP_IN_PROG;
3093 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3094 devinfo->target, &tstate);
3095 targ_scsirate = tinfo->scsirate;
3098 * Parse as much of the message as is available,
3099 * rejecting it if we don't support it. When
3100 * the entire message is available and has been
3101 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3102 * that we have parsed an entire message.
3104 * In the case of extended messages, we accept the length
3105 * byte outright and perform more checking once we know the
3106 * extended message type.
3108 switch (ahc->msgin_buf[0]) {
3109 case MSG_DISCONNECT:
3110 case MSG_SAVEDATAPOINTER:
3111 case MSG_CMDCOMPLETE:
3112 case MSG_RESTOREPOINTERS:
3113 case MSG_IGN_WIDE_RESIDUE:
3115 * End our message loop as these are messages
3116 * the sequencer handles on its own.
3118 done = MSGLOOP_TERMINATED;
3120 case MSG_MESSAGE_REJECT:
3121 response = ahc_handle_msg_reject(ahc, devinfo);
3124 done = MSGLOOP_MSGCOMPLETE;
3128 /* Wait for enough of the message to begin validation */
3129 if (ahc->msgin_index < 2)
3131 switch (ahc->msgin_buf[2]) {
3134 struct ahc_syncrate *syncrate;
3140 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3146 * Wait until we have both args before validating
3147 * and acting on this message.
3149 * Add one to MSG_EXT_SDTR_LEN to account for
3150 * the extended message preamble.
3152 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3155 period = ahc->msgin_buf[3];
3157 saved_offset = offset = ahc->msgin_buf[4];
3158 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3161 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3162 targ_scsirate & WIDEXFER,
3165 printf("(%s:%c:%d:%d): Received "
3166 "SDTR period %x, offset %x\n\t"
3167 "Filtered to period %x, offset %x\n",
3168 ahc_name(ahc), devinfo->channel,
3169 devinfo->target, devinfo->lun,
3170 ahc->msgin_buf[3], saved_offset,
3173 ahc_set_syncrate(ahc, devinfo,
3175 offset, ppr_options,
3176 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3180 * See if we initiated Sync Negotiation
3181 * and didn't have to fall down to async
3184 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3186 if (saved_offset != offset) {
3187 /* Went too low - force async */
3192 * Send our own SDTR in reply
3195 && devinfo->role == ROLE_INITIATOR) {
3196 printf("(%s:%c:%d:%d): Target "
3198 ahc_name(ahc), devinfo->channel,
3199 devinfo->target, devinfo->lun);
3201 ahc->msgout_index = 0;
3202 ahc->msgout_len = 0;
3203 ahc_construct_sdtr(ahc, devinfo,
3205 ahc->msgout_index = 0;
3208 done = MSGLOOP_MSGCOMPLETE;
3215 u_int sending_reply;
3217 sending_reply = FALSE;
3218 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3224 * Wait until we have our arg before validating
3225 * and acting on this message.
3227 * Add one to MSG_EXT_WDTR_LEN to account for
3228 * the extended message preamble.
3230 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3233 bus_width = ahc->msgin_buf[3];
3234 saved_width = bus_width;
3235 ahc_validate_width(ahc, tinfo, &bus_width,
3238 printf("(%s:%c:%d:%d): Received WDTR "
3239 "%x filtered to %x\n",
3240 ahc_name(ahc), devinfo->channel,
3241 devinfo->target, devinfo->lun,
3242 saved_width, bus_width);
3245 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3247 * Don't send a WDTR back to the
3248 * target, since we asked first.
3249 * If the width went higher than our
3250 * request, reject it.
3252 if (saved_width > bus_width) {
3254 printf("(%s:%c:%d:%d): requested %dBit "
3255 "transfers. Rejecting...\n",
3256 ahc_name(ahc), devinfo->channel,
3257 devinfo->target, devinfo->lun,
3258 8 * (0x01 << bus_width));
3263 * Send our own WDTR in reply
3266 && devinfo->role == ROLE_INITIATOR) {
3267 printf("(%s:%c:%d:%d): Target "
3269 ahc_name(ahc), devinfo->channel,
3270 devinfo->target, devinfo->lun);
3272 ahc->msgout_index = 0;
3273 ahc->msgout_len = 0;
3274 ahc_construct_wdtr(ahc, devinfo, bus_width);
3275 ahc->msgout_index = 0;
3277 sending_reply = TRUE;
3280 * After a wide message, we are async, but
3281 * some devices don't seem to honor this portion
3282 * of the spec. Force a renegotiation of the
3283 * sync component of our transfer agreement even
3284 * if our goal is async. By updating our width
3285 * after forcing the negotiation, we avoid
3286 * renegotiating for width.
3288 ahc_update_neg_request(ahc, devinfo, tstate,
3289 tinfo, AHC_NEG_ALWAYS);
3290 ahc_set_width(ahc, devinfo, bus_width,
3291 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3293 if (sending_reply == FALSE && reject == FALSE) {
3296 * We will always have an SDTR to send.
3298 ahc->msgout_index = 0;
3299 ahc->msgout_len = 0;
3300 ahc_build_transfer_msg(ahc, devinfo);
3301 ahc->msgout_index = 0;
3304 done = MSGLOOP_MSGCOMPLETE;
3309 struct ahc_syncrate *syncrate;
3316 u_int saved_ppr_options;
3318 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3324 * Wait until we have all args before validating
3325 * and acting on this message.
3327 * Add one to MSG_EXT_PPR_LEN to account for
3328 * the extended message preamble.
3330 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3333 period = ahc->msgin_buf[3];
3334 offset = ahc->msgin_buf[5];
3335 bus_width = ahc->msgin_buf[6];
3336 saved_width = bus_width;
3337 ppr_options = ahc->msgin_buf[7];
3339 * According to the spec, a DT only
3340 * period factor with no DT option
3341 * set implies async.
3343 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3346 saved_ppr_options = ppr_options;
3347 saved_offset = offset;
3350 * Mask out any options we don't support
3351 * on any controller. Transfer options are
3352 * only available if we are negotiating wide.
3354 ppr_options &= MSG_EXT_PPR_DT_REQ;
3358 ahc_validate_width(ahc, tinfo, &bus_width,
3360 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3363 ahc_validate_offset(ahc, tinfo, syncrate,
3367 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3369 * If we are unable to do any of the
3370 * requested options (we went too low),
3371 * then we'll have to reject the message.
3373 if (saved_width > bus_width
3374 || saved_offset != offset
3375 || saved_ppr_options != ppr_options) {
3384 if (devinfo->role != ROLE_TARGET)
3385 printf("(%s:%c:%d:%d): Target "
3387 ahc_name(ahc), devinfo->channel,
3388 devinfo->target, devinfo->lun);
3390 printf("(%s:%c:%d:%d): Initiator "
3392 ahc_name(ahc), devinfo->channel,
3393 devinfo->target, devinfo->lun);
3394 ahc->msgout_index = 0;
3395 ahc->msgout_len = 0;
3396 ahc_construct_ppr(ahc, devinfo, period, offset,
3397 bus_width, ppr_options);
3398 ahc->msgout_index = 0;
3402 printf("(%s:%c:%d:%d): Received PPR width %x, "
3403 "period %x, offset %x,options %x\n"
3404 "\tFiltered to width %x, period %x, "
3405 "offset %x, options %x\n",
3406 ahc_name(ahc), devinfo->channel,
3407 devinfo->target, devinfo->lun,
3408 saved_width, ahc->msgin_buf[3],
3409 saved_offset, saved_ppr_options,
3410 bus_width, period, offset, ppr_options);
3412 ahc_set_width(ahc, devinfo, bus_width,
3413 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3415 ahc_set_syncrate(ahc, devinfo,
3417 offset, ppr_options,
3418 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3420 done = MSGLOOP_MSGCOMPLETE;
3424 /* Unknown extended message. Reject it. */
3430 #ifdef AHC_TARGET_MODE
3431 case MSG_BUS_DEV_RESET:
3432 ahc_handle_devreset(ahc, devinfo,
3434 "Bus Device Reset Received",
3435 /*verbose_level*/0);
3437 done = MSGLOOP_TERMINATED;
3441 case MSG_CLEAR_QUEUE:
3445 /* Target mode messages */
3446 if (devinfo->role != ROLE_TARGET) {
3450 tag = SCB_LIST_NULL;
3451 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3452 tag = ahc_inb(ahc, INITIATOR_TAG);
3453 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3454 devinfo->lun, tag, ROLE_TARGET,
3457 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3458 if (tstate != NULL) {
3459 struct ahc_tmode_lstate* lstate;
3461 lstate = tstate->enabled_luns[devinfo->lun];
3462 if (lstate != NULL) {
3463 ahc_queue_lstate_event(ahc, lstate,
3464 devinfo->our_scsiid,
3467 ahc_send_lstate_events(ahc, lstate);
3471 done = MSGLOOP_TERMINATED;
3475 case MSG_TERM_IO_PROC:
3483 * Setup to reject the message.
3485 ahc->msgout_index = 0;
3486 ahc->msgout_len = 1;
3487 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3488 done = MSGLOOP_MSGCOMPLETE;
3492 if (done != MSGLOOP_IN_PROG && !response)
3493 /* Clear the outgoing message buffer */
3494 ahc->msgout_len = 0;
3500 * Process a message reject message.
3503 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3506 * What we care about here is if we had an
3507 * outstanding SDTR or WDTR message for this
3508 * target. If we did, this is a signal that
3509 * the target is refusing negotiation.
3512 struct ahc_initiator_tinfo *tinfo;
3513 struct ahc_tmode_tstate *tstate;
3518 scb_index = ahc_inb(ahc, SCB_TAG);
3519 scb = ahc_lookup_scb(ahc, scb_index);
3520 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3521 devinfo->our_scsiid,
3522 devinfo->target, &tstate);
3523 /* Might be necessary */
3524 last_msg = ahc_inb(ahc, LAST_MSG);
3526 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3528 * Target does not support the PPR message.
3529 * Attempt to negotiate SPI-2 style.
3532 printf("(%s:%c:%d:%d): PPR Rejected. "
3533 "Trying WDTR/SDTR\n",
3534 ahc_name(ahc), devinfo->channel,
3535 devinfo->target, devinfo->lun);
3537 tinfo->goal.ppr_options = 0;
3538 tinfo->curr.transport_version = 2;
3539 tinfo->goal.transport_version = 2;
3540 ahc->msgout_index = 0;
3541 ahc->msgout_len = 0;
3542 ahc_build_transfer_msg(ahc, devinfo);
3543 ahc->msgout_index = 0;
3545 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3547 /* note 8bit xfers */
3548 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3549 "8bit transfers\n", ahc_name(ahc),
3550 devinfo->channel, devinfo->target, devinfo->lun);
3551 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3552 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3555 * No need to clear the sync rate. If the target
3556 * did not accept the command, our syncrate is
3557 * unaffected. If the target started the negotiation,
3558 * but rejected our response, we already cleared the
3559 * sync rate before sending our WDTR.
3561 if (tinfo->goal.offset != tinfo->curr.offset) {
3563 /* Start the sync negotiation */
3564 ahc->msgout_index = 0;
3565 ahc->msgout_len = 0;
3566 ahc_build_transfer_msg(ahc, devinfo);
3567 ahc->msgout_index = 0;
3570 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3571 /* note asynch xfers and clear flag */
3572 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3573 /*offset*/0, /*ppr_options*/0,
3574 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3576 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3577 "Using asynchronous transfers\n",
3578 ahc_name(ahc), devinfo->channel,
3579 devinfo->target, devinfo->lun);
3580 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3584 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3586 if (tag_type == MSG_SIMPLE_TASK) {
3587 printf("(%s:%c:%d:%d): refuses tagged commands. "
3588 "Performing non-tagged I/O\n", ahc_name(ahc),
3589 devinfo->channel, devinfo->target, devinfo->lun);
3590 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3593 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3594 "Performing simple queue tagged I/O only\n",
3595 ahc_name(ahc), devinfo->channel, devinfo->target,
3596 devinfo->lun, tag_type == MSG_ORDERED_TASK
3597 ? "ordered" : "head of queue");
3598 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3603 * Resend the identify for this CCB as the target
3604 * may believe that the selection is invalid otherwise.
3606 ahc_outb(ahc, SCB_CONTROL,
3607 ahc_inb(ahc, SCB_CONTROL) & mask);
3608 scb->hscb->control &= mask;
3609 aic_set_transaction_tag(scb, /*enabled*/FALSE,
3610 /*type*/MSG_SIMPLE_TASK);
3611 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3612 ahc_assert_atn(ahc);
3615 * This transaction is now at the head of
3616 * the untagged queue for this target.
3618 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3619 struct scb_tailq *untagged_q;
3622 &(ahc->untagged_queues[devinfo->target_offset]);
3623 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3624 scb->flags |= SCB_UNTAGGEDQ;
3626 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3630 * Requeue all tagged commands for this target
3631 * currently in our posession so they can be
3632 * converted to untagged commands.
3634 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3635 SCB_GET_CHANNEL(ahc, scb),
3636 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3637 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3641 * Otherwise, we ignore it.
3643 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3644 ahc_name(ahc), devinfo->channel, devinfo->target,
3651 * Process an ingnore wide residue message.
3654 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3659 scb_index = ahc_inb(ahc, SCB_TAG);
3660 scb = ahc_lookup_scb(ahc, scb_index);
3662 * XXX Actually check data direction in the sequencer?
3663 * Perhaps add datadir to some spare bits in the hscb?
3665 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3666 || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
3668 * Ignore the message if we haven't
3669 * seen an appropriate data phase yet.
3673 * If the residual occurred on the last
3674 * transfer and the transfer request was
3675 * expected to end on an odd count, do
3676 * nothing. Otherwise, subtract a byte
3677 * and update the residual count accordingly.
3681 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3682 if ((sgptr & SG_LIST_NULL) != 0
3683 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3685 * If the residual occurred on the last
3686 * transfer and the transfer request was
3687 * expected to end on an odd count, do
3691 struct ahc_dma_seg *sg;
3696 /* Pull in all of the sgptr */
3697 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3698 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3700 if ((sgptr & SG_LIST_NULL) != 0) {
3702 * The residual data count is not updated
3703 * for the command run to completion case.
3704 * Explicitly zero the count.
3706 data_cnt &= ~AHC_SG_LEN_MASK;
3709 data_addr = ahc_inl(ahc, SHADDR);
3713 sgptr &= SG_PTR_MASK;
3715 sg = ahc_sg_bus_to_virt(scb, sgptr);
3718 * The residual sg ptr points to the next S/G
3719 * to load so we must go back one.
3722 sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
3723 if (sg != scb->sg_list
3724 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3727 sglen = aic_le32toh(sg->len);
3729 * Preserve High Address and SG_LIST bits
3730 * while setting the count to 1.
3732 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3733 data_addr = aic_le32toh(sg->addr)
3734 + (sglen & AHC_SG_LEN_MASK) - 1;
3737 * Increment sg so it points to the
3741 sgptr = ahc_sg_virt_to_bus(scb, sg);
3743 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3744 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3746 * Toggle the "oddness" of the transfer length
3747 * to handle this mid-transfer ignore wide
3748 * residue. This ensures that the oddness is
3749 * correct for subsequent data transfers.
3751 ahc_outb(ahc, SCB_LUN,
3752 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3759 * Reinitialize the data pointers for the active transfer
3760 * based on its current residual.
3763 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3766 struct ahc_dma_seg *sg;
3772 scb_index = ahc_inb(ahc, SCB_TAG);
3773 scb = ahc_lookup_scb(ahc, scb_index);
3774 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3775 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3776 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3777 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3779 sgptr &= SG_PTR_MASK;
3780 sg = ahc_sg_bus_to_virt(scb, sgptr);
3782 /* The residual sg_ptr always points to the next sg */
3785 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3786 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3787 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3789 dataptr = aic_le32toh(sg->addr)
3790 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK)
3792 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3795 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3796 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3797 ahc_outb(ahc, HADDR,
3798 (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3799 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3801 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3802 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3803 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3804 ahc_outb(ahc, HADDR, dataptr);
3805 ahc_outb(ahc, HCNT + 2, resid >> 16);
3806 ahc_outb(ahc, HCNT + 1, resid >> 8);
3807 ahc_outb(ahc, HCNT, resid);
3808 if ((ahc->features & AHC_ULTRA2) == 0) {
3809 ahc_outb(ahc, STCNT + 2, resid >> 16);
3810 ahc_outb(ahc, STCNT + 1, resid >> 8);
3811 ahc_outb(ahc, STCNT, resid);
3816 * Handle the effects of issuing a bus device reset message.
3819 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3820 cam_status status, char *message, int verbose_level)
3822 #ifdef AHC_TARGET_MODE
3823 struct ahc_tmode_tstate* tstate;
3828 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3829 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3832 #ifdef AHC_TARGET_MODE
3834 * Send an immediate notify ccb to all target mord peripheral
3835 * drivers affected by this action.
3837 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3838 if (tstate != NULL) {
3839 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3840 struct ahc_tmode_lstate* lstate;
3842 lstate = tstate->enabled_luns[lun];
3846 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3847 MSG_BUS_DEV_RESET, /*arg*/0);
3848 ahc_send_lstate_events(ahc, lstate);
3854 * Go back to async/narrow transfers and renegotiate.
3856 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3857 AHC_TRANS_CUR, /*paused*/TRUE);
3858 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3859 /*period*/0, /*offset*/0, /*ppr_options*/0,
3860 AHC_TRANS_CUR, /*paused*/TRUE);
3862 if (status != CAM_SEL_TIMEOUT)
3863 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3864 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3867 && (verbose_level <= bootverbose))
3868 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3869 message, devinfo->channel, devinfo->target, found);
3872 #ifdef AHC_TARGET_MODE
3874 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3879 * To facilitate adding multiple messages together,
3880 * each routine should increment the index and len
3881 * variables instead of setting them explicitly.
3883 ahc->msgout_index = 0;
3884 ahc->msgout_len = 0;
3886 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3887 ahc_build_transfer_msg(ahc, devinfo);
3889 panic("ahc_intr: AWAITING target message with no message");
3891 ahc->msgout_index = 0;
3892 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3895 /**************************** Initialization **********************************/
3897 * Allocate a controller structure for a new device
3898 * and perform initial initializion.
3901 ahc_alloc(void *platform_arg, char *name)
3903 struct ahc_softc *ahc;
3907 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3909 printf("aic7xxx: cannot malloc softc!\n");
3910 free(name, M_DEVBUF);
3914 ahc = device_get_softc((device_t)platform_arg);
3916 memset(ahc, 0, sizeof(*ahc));
3917 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3918 M_DEVBUF, M_NOWAIT);
3919 if (ahc->seep_config == NULL) {
3921 free(ahc, M_DEVBUF);
3923 free(name, M_DEVBUF);
3926 LIST_INIT(&ahc->pending_scbs);
3927 LIST_INIT(&ahc->timedout_scbs);
3928 /* We don't know our unit number until the OSM sets it */
3931 ahc->description = NULL;
3933 ahc->channel_b = 'B';
3934 ahc->chip = AHC_NONE;
3935 ahc->features = AHC_FENONE;
3936 ahc->bugs = AHC_BUGNONE;
3937 ahc->flags = AHC_FNONE;
3939 * Default to all error reporting enabled with the
3940 * sequencer operating at its fastest speed.
3941 * The bus attach code may modify this.
3943 ahc->seqctl = FASTMODE;
3945 for (i = 0; i < AHC_NUM_TARGETS; i++)
3946 TAILQ_INIT(&ahc->untagged_queues[i]);
3947 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3956 ahc_softc_init(struct ahc_softc *ahc)
3959 /* The IRQMS bit is only valid on VL and EISA chips */
3960 if ((ahc->chip & AHC_PCI) == 0)
3961 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3964 ahc->pause = ahc->unpause | PAUSE;
3965 /* XXX The shared scb data stuff should be deprecated */
3966 if (ahc->scb_data == NULL) {
3967 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3968 M_DEVBUF, M_NOWAIT);
3969 if (ahc->scb_data == NULL)
3971 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3978 ahc_softc_insert(struct ahc_softc *ahc)
3980 struct ahc_softc *list_ahc;
3982 #if AIC_PCI_CONFIG > 0
3984 * Second Function PCI devices need to inherit some
3985 * settings from function 0.
3987 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3988 && (ahc->features & AHC_MULTI_FUNC) != 0) {
3989 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3990 aic_dev_softc_t list_pci;
3991 aic_dev_softc_t pci;
3993 list_pci = list_ahc->dev_softc;
3994 pci = ahc->dev_softc;
3995 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
3996 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
3997 struct ahc_softc *master;
3998 struct ahc_softc *slave;
4000 if (aic_get_pci_function(list_pci) == 0) {
4007 slave->flags &= ~AHC_BIOS_ENABLED;
4009 master->flags & AHC_BIOS_ENABLED;
4010 slave->flags &= ~AHC_PRIMARY_CHANNEL;
4012 master->flags & AHC_PRIMARY_CHANNEL;
4020 * Insertion sort into our list of softcs.
4022 list_ahc = TAILQ_FIRST(&ahc_tailq);
4023 while (list_ahc != NULL
4024 && ahc_softc_comp(ahc, list_ahc) <= 0)
4025 list_ahc = TAILQ_NEXT(list_ahc, links);
4026 if (list_ahc != NULL)
4027 TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
4029 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
4034 ahc_set_unit(struct ahc_softc *ahc, int unit)
4040 ahc_set_name(struct ahc_softc *ahc, char *name)
4042 if (ahc->name != NULL)
4043 free(ahc->name, M_DEVBUF);
4048 ahc_free(struct ahc_softc *ahc)
4052 ahc_terminate_recovery_thread(ahc);
4053 switch (ahc->init_level) {
4059 aic_dmamap_unload(ahc, ahc->shared_data_dmat,
4060 ahc->shared_data_dmamap);
4063 aic_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
4064 ahc->shared_data_dmamap);
4065 aic_dmamap_destroy(ahc, ahc->shared_data_dmat,
4066 ahc->shared_data_dmamap);
4069 aic_dma_tag_destroy(ahc, ahc->shared_data_dmat);
4072 aic_dma_tag_destroy(ahc, ahc->buffer_dmat);
4080 aic_dma_tag_destroy(ahc, ahc->parent_dmat);
4082 ahc_platform_free(ahc);
4083 ahc_fini_scbdata(ahc);
4084 for (i = 0; i < AHC_NUM_TARGETS; i++) {
4085 struct ahc_tmode_tstate *tstate;
4087 tstate = ahc->enabled_targets[i];
4088 if (tstate != NULL) {
4089 #ifdef AHC_TARGET_MODE
4092 for (j = 0; j < AHC_NUM_LUNS; j++) {
4093 struct ahc_tmode_lstate *lstate;
4095 lstate = tstate->enabled_luns[j];
4096 if (lstate != NULL) {
4097 xpt_free_path(lstate->path);
4098 free(lstate, M_DEVBUF);
4102 free(tstate, M_DEVBUF);
4105 #ifdef AHC_TARGET_MODE
4106 if (ahc->black_hole != NULL) {
4107 xpt_free_path(ahc->black_hole->path);
4108 free(ahc->black_hole, M_DEVBUF);
4111 if (ahc->name != NULL)
4112 free(ahc->name, M_DEVBUF);
4113 if (ahc->seep_config != NULL)
4114 free(ahc->seep_config, M_DEVBUF);
4116 free(ahc, M_DEVBUF);
4122 ahc_shutdown(void *arg)
4124 struct ahc_softc *ahc;
4127 ahc = (struct ahc_softc *)arg;
4129 /* This will reset most registers to 0, but not all */
4130 ahc_reset(ahc, /*reinit*/FALSE);
4131 ahc_outb(ahc, SCSISEQ, 0);
4132 ahc_outb(ahc, SXFRCTL0, 0);
4133 ahc_outb(ahc, DSPCISTATUS, 0);
4135 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4136 ahc_outb(ahc, i, 0);
4140 * Reset the controller and record some information about it
4141 * that is only available just after a reset. If "reinit" is
4142 * non-zero, this reset occured after initial configuration
4143 * and the caller requests that the chip be fully reinitialized
4144 * to a runable state. Chip interrupts are *not* enabled after
4145 * a reinitialization. The caller must enable interrupts via
4146 * ahc_intr_enable().
4149 ahc_reset(struct ahc_softc *ahc, int reinit)
4152 u_int sxfrctl1_a, sxfrctl1_b;
4157 * Preserve the value of the SXFRCTL1 register for all channels.
4158 * It contains settings that affect termination and we don't want
4159 * to disturb the integrity of the bus.
4163 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4167 * Save channel B's settings in case this chip
4168 * is setup for TWIN channel operation.
4170 sblkctl = ahc_inb(ahc, SBLKCTL);
4171 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4172 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4173 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4175 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4177 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4180 * Ensure that the reset has finished. We delay 1000us
4181 * prior to reading the register to make sure the chip
4182 * has sufficiently completed its reset to handle register
4188 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4191 printf("%s: WARNING - Failed chip reset! "
4192 "Trying to initialize anyway.\n", ahc_name(ahc));
4194 ahc_outb(ahc, HCNTRL, ahc->pause);
4196 /* Determine channel configuration */
4197 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4198 /* No Twin Channel PCI cards */
4199 if ((ahc->chip & AHC_PCI) != 0)
4200 sblkctl &= ~SELBUSB;
4203 /* Single Narrow Channel */
4207 ahc->features |= AHC_WIDE;
4211 ahc->features |= AHC_TWIN;
4214 printf(" Unsupported adapter type. Ignoring\n");
4221 * We must always initialize STPWEN to 1 before we
4222 * restore the saved values. STPWEN is initialized
4223 * to a tri-state condition which can only be cleared
4226 if ((ahc->features & AHC_TWIN) != 0) {
4229 sblkctl = ahc_inb(ahc, SBLKCTL);
4230 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4231 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4232 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4234 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4239 * If a recovery action has forced a chip reset,
4240 * re-initialize the chip to our liking.
4242 error = ahc->bus_chip_init(ahc);
4252 * Determine the number of SCBs available on the controller
4255 ahc_probe_scbs(struct ahc_softc *ahc) {
4258 for (i = 0; i < AHC_SCB_MAX; i++) {
4260 ahc_outb(ahc, SCBPTR, i);
4261 ahc_outb(ahc, SCB_BASE, i);
4262 if (ahc_inb(ahc, SCB_BASE) != i)
4264 ahc_outb(ahc, SCBPTR, 0);
4265 if (ahc_inb(ahc, SCB_BASE) != 0)
4272 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4276 baddr = (bus_addr_t *)arg;
4277 *baddr = segs->ds_addr;
4281 ahc_build_free_scb_list(struct ahc_softc *ahc)
4287 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4290 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4293 ahc_outb(ahc, SCBPTR, i);
4296 * Touch all SCB bytes to avoid parity errors
4297 * should one of our debugging routines read
4298 * an otherwise uninitiatlized byte.
4300 for (j = 0; j < scbsize; j++)
4301 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4303 /* Clear the control byte. */
4304 ahc_outb(ahc, SCB_CONTROL, 0);
4306 /* Set the next pointer */
4307 if ((ahc->flags & AHC_PAGESCBS) != 0)
4308 ahc_outb(ahc, SCB_NEXT, i+1);
4310 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4312 /* Make the tag number, SCSIID, and lun invalid */
4313 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4314 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4315 ahc_outb(ahc, SCB_LUN, 0xFF);
4318 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4319 /* SCB 0 heads the free list. */
4320 ahc_outb(ahc, FREE_SCBH, 0);
4323 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4326 /* Make sure that the last SCB terminates the free list */
4327 ahc_outb(ahc, SCBPTR, i-1);
4328 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4332 ahc_init_scbdata(struct ahc_softc *ahc)
4334 struct scb_data *scb_data;
4336 scb_data = ahc->scb_data;
4337 SLIST_INIT(&scb_data->free_scbs);
4338 SLIST_INIT(&scb_data->sg_maps);
4340 /* Allocate SCB resources */
4341 scb_data->scbarray =
4342 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4343 M_DEVBUF, M_NOWAIT);
4344 if (scb_data->scbarray == NULL)
4346 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4348 /* Determine the number of hardware SCBs and initialize them */
4350 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4351 if (ahc->scb_data->maxhscbs == 0) {
4352 printf("%s: No SCB space found\n", ahc_name(ahc));
4357 * Create our DMA tags. These tags define the kinds of device
4358 * accessible memory allocations and memory mappings we will
4359 * need to perform during normal operation.
4361 * Unless we need to further restrict the allocation, we rely
4362 * on the restrictions of the parent dmat, hence the common
4363 * use of MAXADDR and MAXSIZE.
4366 /* DMA tag for our hardware scb structures */
4367 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4368 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4369 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4370 /*highaddr*/BUS_SPACE_MAXADDR,
4371 /*filter*/NULL, /*filterarg*/NULL,
4372 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4374 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4375 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4379 scb_data->init_level++;
4381 /* Allocation for our hscbs */
4382 if (aic_dmamem_alloc(ahc, scb_data->hscb_dmat,
4383 (void **)&scb_data->hscbs,
4384 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4385 &scb_data->hscb_dmamap) != 0) {
4389 scb_data->init_level++;
4391 /* And permanently map them */
4392 aic_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4394 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4395 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4397 scb_data->init_level++;
4399 /* DMA tag for our sense buffers */
4400 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4401 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4402 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4403 /*highaddr*/BUS_SPACE_MAXADDR,
4404 /*filter*/NULL, /*filterarg*/NULL,
4405 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4407 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4408 /*flags*/0, &scb_data->sense_dmat) != 0) {
4412 scb_data->init_level++;
4415 if (aic_dmamem_alloc(ahc, scb_data->sense_dmat,
4416 (void **)&scb_data->sense,
4417 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4421 scb_data->init_level++;
4423 /* And permanently map them */
4424 aic_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4426 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4427 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4429 scb_data->init_level++;
4431 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4432 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4433 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4434 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4435 /*highaddr*/BUS_SPACE_MAXADDR,
4436 /*filter*/NULL, /*filterarg*/NULL,
4437 PAGE_SIZE, /*nsegments*/1,
4438 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4439 /*flags*/0, &scb_data->sg_dmat) != 0) {
4443 scb_data->init_level++;
4445 /* Perform initial CCB allocation */
4446 memset(scb_data->hscbs, 0,
4447 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4448 while (ahc_alloc_scbs(ahc) != 0)
4451 if (scb_data->numscbs == 0) {
4452 printf("%s: ahc_init_scbdata - "
4453 "Unable to allocate initial scbs\n",
4459 * Reserve the next queued SCB.
4461 ahc->next_queued_scb = ahc_get_scb(ahc);
4464 * Note that we were successfull
4474 ahc_fini_scbdata(struct ahc_softc *ahc)
4476 struct scb_data *scb_data;
4478 scb_data = ahc->scb_data;
4479 if (scb_data == NULL)
4482 switch (scb_data->init_level) {
4486 struct sg_map_node *sg_map;
4488 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4489 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4490 aic_dmamap_unload(ahc, scb_data->sg_dmat,
4492 aic_dmamem_free(ahc, scb_data->sg_dmat,
4495 free(sg_map, M_DEVBUF);
4497 aic_dma_tag_destroy(ahc, scb_data->sg_dmat);
4500 aic_dmamap_unload(ahc, scb_data->sense_dmat,
4501 scb_data->sense_dmamap);
4503 aic_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4504 scb_data->sense_dmamap);
4505 aic_dmamap_destroy(ahc, scb_data->sense_dmat,
4506 scb_data->sense_dmamap);
4508 aic_dma_tag_destroy(ahc, scb_data->sense_dmat);
4510 aic_dmamap_unload(ahc, scb_data->hscb_dmat,
4511 scb_data->hscb_dmamap);
4513 aic_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4514 scb_data->hscb_dmamap);
4515 aic_dmamap_destroy(ahc, scb_data->hscb_dmat,
4516 scb_data->hscb_dmamap);
4518 aic_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4523 if (scb_data->scbarray != NULL)
4524 free(scb_data->scbarray, M_DEVBUF);
4528 ahc_alloc_scbs(struct ahc_softc *ahc)
4530 struct scb_data *scb_data;
4531 struct scb *next_scb;
4532 struct sg_map_node *sg_map;
4533 bus_addr_t physaddr;
4534 struct ahc_dma_seg *segs;
4538 scb_data = ahc->scb_data;
4539 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4540 /* Can't allocate any more */
4543 next_scb = &scb_data->scbarray[scb_data->numscbs];
4545 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4550 /* Allocate S/G space for the next batch of SCBS */
4551 if (aic_dmamem_alloc(ahc, scb_data->sg_dmat,
4552 (void **)&sg_map->sg_vaddr,
4553 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4554 &sg_map->sg_dmamap) != 0) {
4555 free(sg_map, M_DEVBUF);
4559 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4561 aic_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4562 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4563 &sg_map->sg_physaddr, /*flags*/0);
4565 segs = sg_map->sg_vaddr;
4566 physaddr = sg_map->sg_physaddr;
4568 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4569 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4570 for (i = 0; i < newcount; i++) {
4571 struct scb_platform_data *pdata;
4575 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4576 M_DEVBUF, M_NOWAIT);
4579 next_scb->platform_data = pdata;
4580 next_scb->sg_map = sg_map;
4581 next_scb->sg_list = segs;
4583 * The sequencer always starts with the second entry.
4584 * The first entry is embedded in the scb.
4586 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4587 next_scb->ahc_softc = ahc;
4588 next_scb->flags = SCB_FLAG_NONE;
4590 error = aic_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4595 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4596 next_scb->hscb->tag = ahc->scb_data->numscbs;
4597 aic_timer_init(&next_scb->io_timer);
4598 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4599 next_scb, links.sle);
4601 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4603 ahc->scb_data->numscbs++;
4609 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4613 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4615 if ((ahc->features & AHC_TWIN) != 0)
4616 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4617 "B SCSI Id=%d, primary %c, ",
4618 ahc->our_id, ahc->our_id_b,
4619 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4625 if ((ahc->features & AHC_ULTRA) != 0) {
4627 } else if ((ahc->features & AHC_DT) != 0) {
4628 speed = "Ultra160 ";
4629 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4632 if ((ahc->features & AHC_WIDE) != 0) {
4637 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4638 speed, type, ahc->channel, ahc->our_id);
4642 if ((ahc->flags & AHC_PAGESCBS) != 0)
4643 sprintf(buf, "%d/%d SCBs",
4644 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4646 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4650 ahc_chip_init(struct ahc_softc *ahc)
4656 u_int scsiseq_template;
4659 ahc_outb(ahc, SEQ_FLAGS, 0);
4660 ahc_outb(ahc, SEQ_FLAGS2, 0);
4662 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4663 if (ahc->features & AHC_TWIN) {
4666 * Setup Channel B first.
4668 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4669 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4670 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4671 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4672 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4673 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4674 if ((ahc->features & AHC_ULTRA2) != 0)
4675 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4676 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4677 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4679 /* Select Channel A */
4680 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4682 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4683 if ((ahc->features & AHC_ULTRA2) != 0)
4684 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4686 ahc_outb(ahc, SCSIID, ahc->our_id);
4687 scsi_conf = ahc_inb(ahc, SCSICONF);
4688 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4690 |ENSTIMER|ACTNEGEN);
4691 if ((ahc->features & AHC_ULTRA2) != 0)
4692 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4693 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4694 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4696 /* There are no untagged SCBs active yet. */
4697 for (i = 0; i < 16; i++) {
4698 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4699 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4703 * The SCB based BTT allows an entry per
4704 * target and lun pair.
4706 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4707 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4711 /* All of our queues are empty */
4712 for (i = 0; i < 256; i++)
4713 ahc->qoutfifo[i] = SCB_LIST_NULL;
4714 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4716 for (i = 0; i < 256; i++)
4717 ahc->qinfifo[i] = SCB_LIST_NULL;
4719 if ((ahc->features & AHC_MULTI_TID) != 0) {
4720 ahc_outb(ahc, TARGID, 0);
4721 ahc_outb(ahc, TARGID + 1, 0);
4725 * Tell the sequencer where it can find our arrays in memory.
4727 physaddr = ahc->scb_data->hscb_busaddr;
4728 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4729 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4730 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4731 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4733 physaddr = ahc->shared_data_busaddr;
4734 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4735 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4736 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4737 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4740 * Initialize the group code to command length table.
4741 * This overrides the values in TARG_SCSIRATE, so only
4742 * setup the table after we have processed that information.
4744 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4745 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4746 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4747 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4748 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4749 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4750 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4751 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4753 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4754 ahc_outb(ahc, HS_MAILBOX, 0);
4756 /* Tell the sequencer of our initial queue positions */
4757 if ((ahc->features & AHC_TARGETMODE) != 0) {
4758 ahc->tqinfifonext = 1;
4759 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4760 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4762 ahc->qinfifonext = 0;
4763 ahc->qoutfifonext = 0;
4764 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4765 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4766 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4767 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4768 ahc_outb(ahc, SDSCB_QOFF, 0);
4770 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4771 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4772 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4775 /* We don't have any waiting selections */
4776 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4778 /* Our disconnection list is empty too */
4779 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4781 /* Message out buffer starts empty */
4782 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4785 * Setup the allowed SCSI Sequences based on operational mode.
4786 * If we are a target, we'll enalbe select in operations once
4787 * we've had a lun enabled.
4789 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4790 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4791 scsiseq_template |= ENRSELI;
4792 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4794 /* Initialize our list of free SCBs. */
4795 ahc_build_free_scb_list(ahc);
4798 * Tell the sequencer which SCB will be the next one it receives.
4800 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4803 * Load the Sequencer program and Enable the adapter
4807 printf("%s: Downloading Sequencer Program...",
4810 error = ahc_loadseq(ahc);
4814 if ((ahc->features & AHC_ULTRA2) != 0) {
4818 * Wait for up to 500ms for our transceivers
4819 * to settle. If the adapter does not have
4820 * a cable attached, the transceivers may
4821 * never settle, so don't complain if we
4825 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4834 * Start the board, ready for normal operation
4837 ahc_init(struct ahc_softc *ahc)
4846 size_t driver_data_size;
4849 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4850 ahc->flags |= AHC_SEQUENCER_DEBUG;
4853 #ifdef AHC_PRINT_SRAM
4854 printf("Scratch Ram:");
4855 for (i = 0x20; i < 0x5f; i++) {
4856 if (((i % 8) == 0) && (i != 0)) {
4859 printf (" 0x%x", ahc_inb(ahc, i));
4861 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4862 for (i = 0x70; i < 0x7f; i++) {
4863 if (((i % 8) == 0) && (i != 0)) {
4866 printf (" 0x%x", ahc_inb(ahc, i));
4871 * Reading uninitialized scratch ram may
4872 * generate parity errors.
4874 ahc_outb(ahc, CLRINT, CLRPARERR);
4875 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4880 * Assume we have a board at this stage and it has been reset.
4882 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4883 ahc->our_id = ahc->our_id_b = 7;
4886 * Default to allowing initiator operations.
4888 ahc->flags |= AHC_INITIATORROLE;
4891 * Only allow target mode features if this unit has them enabled.
4893 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4894 ahc->features &= ~AHC_TARGETMODE;
4897 /* DMA tag for mapping buffers into device visible space. */
4898 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4899 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4900 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4901 ? (bus_addr_t)0x7FFFFFFFFFULL
4902 : BUS_SPACE_MAXADDR_32BIT,
4903 /*highaddr*/BUS_SPACE_MAXADDR,
4904 /*filter*/NULL, /*filterarg*/NULL,
4905 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4906 /*nsegments*/AHC_NSEG,
4907 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4908 /*flags*/BUS_DMA_ALLOCNOW,
4909 &ahc->buffer_dmat) != 0) {
4917 * DMA tag for our command fifos and other data in system memory
4918 * the card's sequencer must be able to access. For initiator
4919 * roles, we need to allocate space for the qinfifo and qoutfifo.
4920 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4921 * When providing for the target mode role, we must additionally
4922 * provide space for the incoming target command fifo and an extra
4923 * byte to deal with a dma bug in some chip versions.
4925 driver_data_size = 2 * 256 * sizeof(uint8_t);
4926 if ((ahc->features & AHC_TARGETMODE) != 0)
4927 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4928 + /*DMA WideOdd Bug Buffer*/1;
4929 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4930 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4931 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4932 /*highaddr*/BUS_SPACE_MAXADDR,
4933 /*filter*/NULL, /*filterarg*/NULL,
4936 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4937 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4943 /* Allocation of driver data */
4944 if (aic_dmamem_alloc(ahc, ahc->shared_data_dmat,
4945 (void **)&ahc->qoutfifo,
4946 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4947 &ahc->shared_data_dmamap) != 0) {
4953 /* And permanently map it in */
4954 aic_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4955 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4956 &ahc->shared_data_busaddr, /*flags*/0);
4958 if ((ahc->features & AHC_TARGETMODE) != 0) {
4959 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4960 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4961 ahc->dma_bug_buf = ahc->shared_data_busaddr
4962 + driver_data_size - 1;
4963 /* All target command blocks start out invalid. */
4964 for (i = 0; i < AHC_TMODE_CMDS; i++)
4965 ahc->targetcmds[i].cmd_valid = 0;
4966 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4967 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4969 ahc->qinfifo = &ahc->qoutfifo[256];
4973 /* Allocate SCB data now that buffer_dmat is initialized */
4974 if (ahc->scb_data->maxhscbs == 0)
4975 if (ahc_init_scbdata(ahc) != 0)
4979 * Allocate a tstate to house information for our
4980 * initiator presence on the bus as well as the user
4981 * data for any target mode initiator.
4983 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4984 printf("%s: unable to allocate ahc_tmode_tstate. "
4985 "Failing attach\n", ahc_name(ahc));
4989 if ((ahc->features & AHC_TWIN) != 0) {
4990 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4991 printf("%s: unable to allocate ahc_tmode_tstate. "
4992 "Failing attach\n", ahc_name(ahc));
4998 * Fire up a recovery thread for this controller.
5000 error = ahc_spawn_recovery_thread(ahc);
5004 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
5005 ahc->flags |= AHC_PAGESCBS;
5007 ahc->flags &= ~AHC_PAGESCBS;
5011 if (ahc_debug & AHC_SHOW_MISC) {
5012 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
5013 "ahc_dma %u bytes\n",
5015 (u_int)sizeof(struct hardware_scb),
5016 (u_int)sizeof(struct scb),
5017 (u_int)sizeof(struct ahc_dma_seg));
5019 #endif /* AHC_DEBUG */
5022 * Look at the information that board initialization or
5023 * the board bios has left us.
5025 if (ahc->features & AHC_TWIN) {
5026 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5027 if ((scsi_conf & RESET_SCSI) != 0
5028 && (ahc->flags & AHC_INITIATORROLE) != 0)
5029 ahc->flags |= AHC_RESET_BUS_B;
5032 scsi_conf = ahc_inb(ahc, SCSICONF);
5033 if ((scsi_conf & RESET_SCSI) != 0
5034 && (ahc->flags & AHC_INITIATORROLE) != 0)
5035 ahc->flags |= AHC_RESET_BUS_A;
5038 tagenable = ALL_TARGETS_MASK;
5040 /* Grab the disconnection disable table and invert it for our needs */
5041 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
5042 printf("%s: Host Adapter Bios disabled. Using default SCSI "
5043 "device parameters\n", ahc_name(ahc));
5044 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
5045 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
5046 discenable = ALL_TARGETS_MASK;
5047 if ((ahc->features & AHC_ULTRA) != 0)
5048 ultraenb = ALL_TARGETS_MASK;
5050 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
5051 | ahc_inb(ahc, DISC_DSB));
5052 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
5053 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
5054 | ahc_inb(ahc, ULTRA_ENB);
5057 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
5060 for (i = 0; i <= max_targ; i++) {
5061 struct ahc_initiator_tinfo *tinfo;
5062 struct ahc_tmode_tstate *tstate;
5068 our_id = ahc->our_id;
5070 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
5072 our_id = ahc->our_id_b;
5075 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
5076 target_id, &tstate);
5077 /* Default to async narrow across the board */
5078 memset(tinfo, 0, sizeof(*tinfo));
5079 if (ahc->flags & AHC_USEDEFAULTS) {
5080 if ((ahc->features & AHC_WIDE) != 0)
5081 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5084 * These will be truncated when we determine the
5085 * connection type we have with the target.
5087 tinfo->user.period = ahc_syncrates->period;
5088 tinfo->user.offset = MAX_OFFSET;
5093 /* Take the settings leftover in scratch RAM. */
5094 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5096 if ((ahc->features & AHC_ULTRA2) != 0) {
5100 if ((scsirate & SOFS) == 0x0F) {
5102 * Haven't negotiated yet,
5103 * so the format is different.
5105 scsirate = (scsirate & SXFR) >> 4
5108 | (scsirate & WIDEXFER);
5109 offset = MAX_OFFSET_ULTRA2;
5111 offset = ahc_inb(ahc, TARG_OFFSET + i);
5112 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5113 /* Set to the lowest sync rate, 5MHz */
5115 maxsync = AHC_SYNCRATE_ULTRA2;
5116 if ((ahc->features & AHC_DT) != 0)
5117 maxsync = AHC_SYNCRATE_DT;
5118 tinfo->user.period =
5119 ahc_find_period(ahc, scsirate, maxsync);
5121 tinfo->user.period = 0;
5123 tinfo->user.offset = MAX_OFFSET;
5124 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5125 && (ahc->features & AHC_DT) != 0)
5126 tinfo->user.ppr_options =
5128 } else if ((scsirate & SOFS) != 0) {
5129 if ((scsirate & SXFR) == 0x40
5130 && (ultraenb & mask) != 0) {
5131 /* Treat 10MHz as a non-ultra speed */
5135 tinfo->user.period =
5136 ahc_find_period(ahc, scsirate,
5138 ? AHC_SYNCRATE_ULTRA
5139 : AHC_SYNCRATE_FAST);
5140 if (tinfo->user.period != 0)
5141 tinfo->user.offset = MAX_OFFSET;
5143 if (tinfo->user.period == 0)
5144 tinfo->user.offset = 0;
5145 if ((scsirate & WIDEXFER) != 0
5146 && (ahc->features & AHC_WIDE) != 0)
5147 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5148 tinfo->user.protocol_version = 4;
5149 if ((ahc->features & AHC_DT) != 0)
5150 tinfo->user.transport_version = 3;
5152 tinfo->user.transport_version = 2;
5153 tinfo->goal.protocol_version = 2;
5154 tinfo->goal.transport_version = 2;
5155 tinfo->curr.protocol_version = 2;
5156 tinfo->curr.transport_version = 2;
5158 tstate->ultraenb = 0;
5160 ahc->user_discenable = discenable;
5161 ahc->user_tagenable = tagenable;
5163 return (ahc->bus_chip_init(ahc));
5167 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5171 hcntrl = ahc_inb(ahc, HCNTRL);
5173 ahc->pause &= ~INTEN;
5174 ahc->unpause &= ~INTEN;
5177 ahc->pause |= INTEN;
5178 ahc->unpause |= INTEN;
5180 ahc_outb(ahc, HCNTRL, hcntrl);
5184 * Ensure that the card is paused in a location
5185 * outside of all critical sections and that all
5186 * pending work is completed prior to returning.
5187 * This routine should only be called from outside
5188 * an interrupt context.
5191 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5198 ahc->flags |= AHC_ALL_INTERRUPTS;
5204 * Give the sequencer some time to service
5205 * any active selections.
5212 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5213 intstat = ahc_inb(ahc, INTSTAT);
5214 if ((intstat & INT_PEND) == 0) {
5215 ahc_clear_critical_section(ahc);
5216 intstat = ahc_inb(ahc, INTSTAT);
5219 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5220 && ((intstat & INT_PEND) != 0
5221 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5222 if (maxloops == 0) {
5223 printf("Infinite interrupt loop, INTSTAT = %x",
5224 ahc_inb(ahc, INTSTAT));
5226 ahc_platform_flushwork(ahc);
5227 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5231 ahc_suspend(struct ahc_softc *ahc)
5234 ahc_pause_and_flushwork(ahc);
5236 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5241 #ifdef AHC_TARGET_MODE
5243 * XXX What about ATIOs that have not yet been serviced?
5244 * Perhaps we should just refuse to be suspended if we
5245 * are acting in a target role.
5247 if (ahc->pending_device != NULL) {
5257 ahc_resume(struct ahc_softc *ahc)
5260 ahc_reset(ahc, /*reinit*/TRUE);
5261 ahc_intr_enable(ahc, TRUE);
5266 /************************** Busy Target Table *********************************/
5268 * Return the untagged transaction id for a given target/channel lun.
5269 * Optionally, clear the entry.
5272 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5275 u_int target_offset;
5277 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5280 saved_scbptr = ahc_inb(ahc, SCBPTR);
5281 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5282 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5283 ahc_outb(ahc, SCBPTR, saved_scbptr);
5285 target_offset = TCL_TARGET_OFFSET(tcl);
5286 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5293 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5295 u_int target_offset;
5297 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5300 saved_scbptr = ahc_inb(ahc, SCBPTR);
5301 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5302 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5303 ahc_outb(ahc, SCBPTR, saved_scbptr);
5305 target_offset = TCL_TARGET_OFFSET(tcl);
5306 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5311 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5313 u_int target_offset;
5315 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5318 saved_scbptr = ahc_inb(ahc, SCBPTR);
5319 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5320 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5321 ahc_outb(ahc, SCBPTR, saved_scbptr);
5323 target_offset = TCL_TARGET_OFFSET(tcl);
5324 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5328 /************************** SCB and SCB queue management **********************/
5330 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5331 char channel, int lun, u_int tag, role_t role)
5333 int targ = SCB_GET_TARGET(ahc, scb);
5334 char chan = SCB_GET_CHANNEL(ahc, scb);
5335 int slun = SCB_GET_LUN(scb);
5338 match = ((chan == channel) || (channel == ALL_CHANNELS));
5340 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5342 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5344 #ifdef AHC_TARGET_MODE
5347 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5348 if (role == ROLE_INITIATOR) {
5349 match = (group != XPT_FC_GROUP_TMODE)
5350 && ((tag == scb->hscb->tag)
5351 || (tag == SCB_LIST_NULL));
5352 } else if (role == ROLE_TARGET) {
5353 match = (group == XPT_FC_GROUP_TMODE)
5354 && ((tag == scb->io_ctx->csio.tag_id)
5355 || (tag == SCB_LIST_NULL));
5357 #else /* !AHC_TARGET_MODE */
5358 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5359 #endif /* AHC_TARGET_MODE */
5366 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5372 target = SCB_GET_TARGET(ahc, scb);
5373 lun = SCB_GET_LUN(scb);
5374 channel = SCB_GET_CHANNEL(ahc, scb);
5376 ahc_search_qinfifo(ahc, target, channel, lun,
5377 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5378 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5380 ahc_platform_freeze_devq(ahc, scb);
5384 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5386 struct scb *prev_scb;
5389 if (ahc_qinfifo_count(ahc) != 0) {
5393 prev_pos = ahc->qinfifonext - 1;
5394 prev_tag = ahc->qinfifo[prev_pos];
5395 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5397 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5398 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5399 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5401 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5406 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5409 if (prev_scb == NULL) {
5410 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5412 prev_scb->hscb->next = scb->hscb->tag;
5413 ahc_sync_scb(ahc, prev_scb,
5414 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5416 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5417 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5418 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5422 ahc_qinfifo_count(struct ahc_softc *ahc)
5427 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5428 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5429 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5431 qinpos = ahc_inb(ahc, QINPOS);
5432 diff = ahc->qinfifonext - qinpos;
5437 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5438 int lun, u_int tag, role_t role, uint32_t status,
5439 ahc_search_action action)
5442 struct scb *prev_scb;
5452 qintail = ahc->qinfifonext;
5453 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5455 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5456 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5458 qinstart = ahc_inb(ahc, QINPOS);
5463 if (action == SEARCH_COMPLETE) {
5465 * Don't attempt to run any queued untagged transactions
5466 * until we are done with the abort process.
5468 ahc_freeze_untagged_queues(ahc);
5472 * Start with an empty queue. Entries that are not chosen
5473 * for removal will be re-added to the queue as we go.
5475 ahc->qinfifonext = qinpos;
5476 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5478 while (qinpos != qintail) {
5479 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5481 printf("qinpos = %d, SCB index = %d\n",
5482 qinpos, ahc->qinfifo[qinpos]);
5486 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5488 * We found an scb that needs to be acted on.
5492 case SEARCH_COMPLETE:
5497 ostat = aic_get_transaction_status(scb);
5498 if (ostat == CAM_REQ_INPROG)
5499 aic_set_transaction_status(scb, status);
5500 cstat = aic_get_transaction_status(scb);
5501 if (cstat != CAM_REQ_CMP)
5502 aic_freeze_scb(scb);
5503 if ((scb->flags & SCB_ACTIVE) == 0)
5504 printf("Inactive SCB in qinfifo\n");
5512 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5517 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5523 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5524 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5526 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5529 if (action != SEARCH_COUNT
5531 && (qinstart != ahc->qinfifonext)) {
5533 * The sequencer may be in the process of dmaing
5534 * down the SCB at the beginning of the queue.
5535 * This could be problematic if either the first,
5536 * or the second SCB is removed from the queue
5537 * (the first SCB includes a pointer to the "next"
5538 * SCB to dma). If we have removed any entries, swap
5539 * the first element in the queue with the next HSCB
5540 * so the sequencer will notice that NEXT_QUEUED_SCB
5541 * has changed during its dma attempt and will retry
5544 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5547 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5548 found, qinstart, ahc->qinfifonext);
5549 panic("First/Second Qinfifo fixup\n");
5552 * ahc_swap_with_next_hscb forces our next pointer to
5553 * point to the reserved SCB for future commands. Save
5554 * and restore our original next pointer to maintain
5557 next = scb->hscb->next;
5558 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5559 ahc_swap_with_next_hscb(ahc, scb);
5560 scb->hscb->next = next;
5561 ahc->qinfifo[qinstart] = scb->hscb->tag;
5563 /* Tell the card about the new head of the qinfifo. */
5564 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5566 /* Fixup the tail "next" pointer. */
5567 qintail = ahc->qinfifonext - 1;
5568 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5569 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5573 * Search waiting for selection list.
5575 curscbptr = ahc_inb(ahc, SCBPTR);
5576 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5577 prev = SCB_LIST_NULL;
5579 while (next != SCB_LIST_NULL) {
5582 ahc_outb(ahc, SCBPTR, next);
5583 scb_index = ahc_inb(ahc, SCB_TAG);
5584 if (scb_index >= ahc->scb_data->numscbs) {
5585 printf("Waiting List inconsistency. "
5586 "SCB index == %d, yet numscbs == %d.",
5587 scb_index, ahc->scb_data->numscbs);
5588 ahc_dump_card_state(ahc);
5589 panic("for safety");
5591 scb = ahc_lookup_scb(ahc, scb_index);
5593 printf("scb_index = %d, next = %d\n",
5595 panic("Waiting List traversal\n");
5597 if (ahc_match_scb(ahc, scb, target, channel,
5598 lun, SCB_LIST_NULL, role)) {
5600 * We found an scb that needs to be acted on.
5604 case SEARCH_COMPLETE:
5609 ostat = aic_get_transaction_status(scb);
5610 if (ostat == CAM_REQ_INPROG)
5611 aic_set_transaction_status(scb,
5613 cstat = aic_get_transaction_status(scb);
5614 if (cstat != CAM_REQ_CMP)
5615 aic_freeze_scb(scb);
5616 if ((scb->flags & SCB_ACTIVE) == 0)
5617 printf("Inactive SCB in Wait List\n");
5622 next = ahc_rem_wscb(ahc, next, prev);
5626 next = ahc_inb(ahc, SCB_NEXT);
5632 next = ahc_inb(ahc, SCB_NEXT);
5635 ahc_outb(ahc, SCBPTR, curscbptr);
5637 found += ahc_search_untagged_queues(ahc, /*aic_io_ctx_t*/NULL, target,
5638 channel, lun, status, action);
5640 if (action == SEARCH_COMPLETE)
5641 ahc_release_untagged_queues(ahc);
5646 ahc_search_untagged_queues(struct ahc_softc *ahc, aic_io_ctx_t ctx,
5647 int target, char channel, int lun, uint32_t status,
5648 ahc_search_action action)
5655 if (action == SEARCH_COMPLETE) {
5657 * Don't attempt to run any queued untagged transactions
5658 * until we are done with the abort process.
5660 ahc_freeze_untagged_queues(ahc);
5665 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5668 if (target != CAM_TARGET_WILDCARD) {
5679 for (; i < maxtarget; i++) {
5680 struct scb_tailq *untagged_q;
5681 struct scb *next_scb;
5683 untagged_q = &(ahc->untagged_queues[i]);
5684 next_scb = TAILQ_FIRST(untagged_q);
5685 while (next_scb != NULL) {
5688 next_scb = TAILQ_NEXT(scb, links.tqe);
5691 * The head of the list may be the currently
5692 * active untagged command for a device.
5693 * We're only searching for commands that
5694 * have not been started. A transaction
5695 * marked active but still in the qinfifo
5696 * is removed by the qinfifo scanning code
5699 if ((scb->flags & SCB_ACTIVE) != 0)
5702 if (ahc_match_scb(ahc, scb, target, channel, lun,
5703 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5704 || (ctx != NULL && ctx != scb->io_ctx))
5708 * We found an scb that needs to be acted on.
5712 case SEARCH_COMPLETE:
5717 ostat = aic_get_transaction_status(scb);
5718 if (ostat == CAM_REQ_INPROG)
5719 aic_set_transaction_status(scb, status);
5720 cstat = aic_get_transaction_status(scb);
5721 if (cstat != CAM_REQ_CMP)
5722 aic_freeze_scb(scb);
5727 scb->flags &= ~SCB_UNTAGGEDQ;
5728 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5736 if (action == SEARCH_COMPLETE)
5737 ahc_release_untagged_queues(ahc);
5742 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5743 int lun, u_int tag, int stop_on_first, int remove,
5753 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5754 prev = SCB_LIST_NULL;
5757 /* restore this when we're done */
5758 active_scb = ahc_inb(ahc, SCBPTR);
5760 /* Silence compiler */
5761 active_scb = SCB_LIST_NULL;
5763 while (next != SCB_LIST_NULL) {
5766 ahc_outb(ahc, SCBPTR, next);
5767 scb_index = ahc_inb(ahc, SCB_TAG);
5768 if (scb_index >= ahc->scb_data->numscbs) {
5769 printf("Disconnected List inconsistency. "
5770 "SCB index == %d, yet numscbs == %d.",
5771 scb_index, ahc->scb_data->numscbs);
5772 ahc_dump_card_state(ahc);
5773 panic("for safety");
5777 panic("Disconnected List Loop. "
5778 "cur SCBPTR == %x, prev SCBPTR == %x.",
5781 scbp = ahc_lookup_scb(ahc, scb_index);
5782 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5783 tag, ROLE_INITIATOR)) {
5787 ahc_rem_scb_from_disc_list(ahc, prev, next);
5790 next = ahc_inb(ahc, SCB_NEXT);
5796 next = ahc_inb(ahc, SCB_NEXT);
5800 ahc_outb(ahc, SCBPTR, active_scb);
5805 * Remove an SCB from the on chip list of disconnected transactions.
5806 * This is empty/unused if we are not performing SCB paging.
5809 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5813 ahc_outb(ahc, SCBPTR, scbptr);
5814 next = ahc_inb(ahc, SCB_NEXT);
5816 ahc_outb(ahc, SCB_CONTROL, 0);
5818 ahc_add_curscb_to_free_list(ahc);
5820 if (prev != SCB_LIST_NULL) {
5821 ahc_outb(ahc, SCBPTR, prev);
5822 ahc_outb(ahc, SCB_NEXT, next);
5824 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5830 * Add the SCB as selected by SCBPTR onto the on chip list of
5831 * free hardware SCBs. This list is empty/unused if we are not
5832 * performing SCB paging.
5835 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5838 * Invalidate the tag so that our abort
5839 * routines don't think it's active.
5841 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5843 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5844 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5845 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5850 * Manipulate the waiting for selection list and return the
5851 * scb that follows the one that we remove.
5854 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5859 * Select the SCB we want to abort and
5860 * pull the next pointer out of it.
5862 curscb = ahc_inb(ahc, SCBPTR);
5863 ahc_outb(ahc, SCBPTR, scbpos);
5864 next = ahc_inb(ahc, SCB_NEXT);
5866 /* Clear the necessary fields */
5867 ahc_outb(ahc, SCB_CONTROL, 0);
5869 ahc_add_curscb_to_free_list(ahc);
5871 /* update the waiting list */
5872 if (prev == SCB_LIST_NULL) {
5873 /* First in the list */
5874 ahc_outb(ahc, WAITING_SCBH, next);
5877 * Ensure we aren't attempting to perform
5878 * selection for this entry.
5880 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5883 * Select the scb that pointed to us
5884 * and update its next pointer.
5886 ahc_outb(ahc, SCBPTR, prev);
5887 ahc_outb(ahc, SCB_NEXT, next);
5891 * Point us back at the original scb position.
5893 ahc_outb(ahc, SCBPTR, curscb);
5897 /******************************** Error Handling ******************************/
5899 * Abort all SCBs that match the given description (target/channel/lun/tag),
5900 * setting their status to the passed in status if the status has not already
5901 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5902 * is paused before it is called.
5905 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5906 int lun, u_int tag, role_t role, uint32_t status)
5909 struct scb *scbp_next;
5919 * Don't attempt to run any queued untagged transactions
5920 * until we are done with the abort process.
5922 ahc_freeze_untagged_queues(ahc);
5924 /* restore this when we're done */
5925 active_scb = ahc_inb(ahc, SCBPTR);
5927 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5928 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5931 * Clean out the busy target table for any untagged commands.
5935 if (target != CAM_TARGET_WILDCARD) {
5942 if (lun == CAM_LUN_WILDCARD) {
5945 * Unless we are using an SCB based
5946 * busy targets table, there is only
5947 * one table entry for all luns of
5952 if ((ahc->flags & AHC_SCB_BTT) != 0)
5953 maxlun = AHC_NUM_LUNS;
5959 if (role != ROLE_TARGET) {
5960 for (;i < maxtarget; i++) {
5961 for (j = minlun;j < maxlun; j++) {
5965 tcl = BUILD_TCL(i << 4, j);
5966 scbid = ahc_index_busy_tcl(ahc, tcl);
5967 scbp = ahc_lookup_scb(ahc, scbid);
5969 || ahc_match_scb(ahc, scbp, target, channel,
5970 lun, tag, role) == 0)
5972 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5977 * Go through the disconnected list and remove any entries we
5978 * have queued for completion, 0'ing their control byte too.
5979 * We save the active SCB and restore it ourselves, so there
5980 * is no reason for this search to restore it too.
5982 ahc_search_disc_list(ahc, target, channel, lun, tag,
5983 /*stop_on_first*/FALSE, /*remove*/TRUE,
5984 /*save_state*/FALSE);
5988 * Go through the hardware SCB array looking for commands that
5989 * were active but not on any list. In some cases, these remnants
5990 * might not still have mappings in the scbindex array (e.g. unexpected
5991 * bus free with the same scb queued for an abort). Don't hold this
5994 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5997 ahc_outb(ahc, SCBPTR, i);
5998 scbid = ahc_inb(ahc, SCB_TAG);
5999 scbp = ahc_lookup_scb(ahc, scbid);
6000 if ((scbp == NULL && scbid != SCB_LIST_NULL)
6002 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
6003 ahc_add_curscb_to_free_list(ahc);
6007 * Go through the pending CCB list and look for
6008 * commands for this target that are still active.
6009 * These are other tagged commands that were
6010 * disconnected when the reset occurred.
6012 scbp_next = LIST_FIRST(&ahc->pending_scbs);
6013 while (scbp_next != NULL) {
6015 scbp_next = LIST_NEXT(scbp, pending_links);
6016 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
6019 ostat = aic_get_transaction_status(scbp);
6020 if (ostat == CAM_REQ_INPROG)
6021 aic_set_transaction_status(scbp, status);
6022 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
6023 aic_freeze_scb(scbp);
6024 if ((scbp->flags & SCB_ACTIVE) == 0)
6025 printf("Inactive SCB on pending list\n");
6026 ahc_done(ahc, scbp);
6030 ahc_outb(ahc, SCBPTR, active_scb);
6031 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
6032 ahc_release_untagged_queues(ahc);
6037 ahc_reset_current_bus(struct ahc_softc *ahc)
6041 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
6042 scsiseq = ahc_inb(ahc, SCSISEQ);
6043 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
6044 ahc_flush_device_writes(ahc);
6045 aic_delay(AHC_BUSRESET_DELAY);
6046 /* Turn off the bus reset */
6047 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
6049 ahc_clear_intstat(ahc);
6051 /* Re-enable reset interrupts */
6052 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
6056 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6058 struct ahc_devinfo devinfo;
6059 u_int initiator, target, max_scsiid;
6067 ahc->pending_device = NULL;
6069 ahc_compile_devinfo(&devinfo,
6070 CAM_TARGET_WILDCARD,
6071 CAM_TARGET_WILDCARD,
6073 channel, ROLE_UNKNOWN);
6076 /* Make sure the sequencer is in a safe location. */
6077 ahc_clear_critical_section(ahc);
6080 * Run our command complete fifos to ensure that we perform
6081 * completion processing on any commands that 'completed'
6082 * before the reset occurred.
6084 ahc_run_qoutfifo(ahc);
6085 #ifdef AHC_TARGET_MODE
6087 * XXX - In Twin mode, the tqinfifo may have commands
6088 * for an unaffected channel in it. However, if
6089 * we have run out of ATIO resources to drain that
6090 * queue, we may not get them all out here. Further,
6091 * the blocked transactions for the reset channel
6092 * should just be killed off, irrespecitve of whether
6093 * we are blocked on ATIO resources. Write a routine
6094 * to compact the tqinfifo appropriately.
6096 if ((ahc->flags & AHC_TARGETROLE) != 0) {
6097 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6102 * Reset the bus if we are initiating this reset
6104 sblkctl = ahc_inb(ahc, SBLKCTL);
6106 if ((ahc->features & AHC_TWIN) != 0
6107 && ((sblkctl & SELBUSB) != 0))
6109 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6110 if (cur_channel != channel) {
6111 /* Case 1: Command for another bus is active
6112 * Stealthily reset the other bus without
6113 * upsetting the current bus.
6115 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6116 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6117 #ifdef AHC_TARGET_MODE
6119 * Bus resets clear ENSELI, so we cannot
6120 * defer re-enabling bus reset interrupts
6121 * if we are in target mode.
6123 if ((ahc->flags & AHC_TARGETROLE) != 0)
6124 simode1 |= ENSCSIRST;
6126 ahc_outb(ahc, SIMODE1, simode1);
6128 ahc_reset_current_bus(ahc);
6129 ahc_clear_intstat(ahc);
6130 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6131 ahc_outb(ahc, SBLKCTL, sblkctl);
6132 restart_needed = FALSE;
6134 /* Case 2: A command from this bus is active or we're idle */
6135 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6136 #ifdef AHC_TARGET_MODE
6138 * Bus resets clear ENSELI, so we cannot
6139 * defer re-enabling bus reset interrupts
6140 * if we are in target mode.
6142 if ((ahc->flags & AHC_TARGETROLE) != 0)
6143 simode1 |= ENSCSIRST;
6145 ahc_outb(ahc, SIMODE1, simode1);
6147 ahc_reset_current_bus(ahc);
6148 ahc_clear_intstat(ahc);
6149 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6150 restart_needed = TRUE;
6154 * Clean up all the state information for the
6155 * pending transactions on this bus.
6157 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6158 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6159 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6161 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6163 #ifdef AHC_TARGET_MODE
6165 * Send an immediate notify ccb to all target more peripheral
6166 * drivers affected by this action.
6168 for (target = 0; target <= max_scsiid; target++) {
6169 struct ahc_tmode_tstate* tstate;
6172 tstate = ahc->enabled_targets[target];
6175 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6176 struct ahc_tmode_lstate* lstate;
6178 lstate = tstate->enabled_luns[lun];
6182 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6183 EVENT_TYPE_BUS_RESET, /*arg*/0);
6184 ahc_send_lstate_events(ahc, lstate);
6188 /* Notify the XPT that a bus reset occurred */
6189 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6190 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
6193 * Revert to async/narrow transfers until we renegotiate.
6195 for (target = 0; target <= max_scsiid; target++) {
6197 if (ahc->enabled_targets[target] == NULL)
6199 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6200 struct ahc_devinfo devinfo;
6202 ahc_compile_devinfo(&devinfo, target, initiator,
6204 channel, ROLE_UNKNOWN);
6205 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6206 AHC_TRANS_CUR, /*paused*/TRUE);
6207 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6208 /*period*/0, /*offset*/0,
6209 /*ppr_options*/0, AHC_TRANS_CUR,
6222 /***************************** Residual Processing ****************************/
6224 * Calculate the residual for a just completed SCB.
6227 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6229 struct hardware_scb *hscb;
6230 struct status_pkt *spkt;
6232 uint32_t resid_sgptr;
6238 * SG_RESID_VALID clear in sgptr.
6239 * 2) Transferless command
6240 * 3) Never performed any transfers.
6241 * sgptr has SG_FULL_RESID set.
6242 * 4) No residual but target did not
6243 * save data pointers after the
6244 * last transfer, so sgptr was
6246 * 5) We have a partial residual.
6247 * Use residual_sgptr to determine
6252 sgptr = aic_le32toh(hscb->sgptr);
6253 if ((sgptr & SG_RESID_VALID) == 0)
6256 sgptr &= ~SG_RESID_VALID;
6258 if ((sgptr & SG_LIST_NULL) != 0)
6262 spkt = &hscb->shared_data.status;
6263 resid_sgptr = aic_le32toh(spkt->residual_sg_ptr);
6264 if ((sgptr & SG_FULL_RESID) != 0) {
6266 resid = aic_get_transfer_length(scb);
6267 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6270 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6271 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6275 struct ahc_dma_seg *sg;
6278 * Remainder of the SG where the transfer
6281 resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6282 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6284 /* The residual sg_ptr always points to the next sg */
6288 * Add up the contents of all residual
6289 * SG segments that are after the SG where
6290 * the transfer stopped.
6292 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6294 resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
6297 if ((scb->flags & SCB_SENSE) == 0)
6298 aic_set_residual(scb, resid);
6300 aic_set_sense_residual(scb, resid);
6303 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6304 ahc_print_path(ahc, scb);
6305 printf("Handled %sResidual of %d bytes\n",
6306 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6311 /******************************* Target Mode **********************************/
6312 #ifdef AHC_TARGET_MODE
6314 * Add a target mode event to this lun's queue
6317 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6318 u_int initiator_id, u_int event_type, u_int event_arg)
6320 struct ahc_tmode_event *event;
6323 xpt_freeze_devq(lstate->path, /*count*/1);
6324 if (lstate->event_w_idx >= lstate->event_r_idx)
6325 pending = lstate->event_w_idx - lstate->event_r_idx;
6327 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6328 - (lstate->event_r_idx - lstate->event_w_idx);
6330 if (event_type == EVENT_TYPE_BUS_RESET
6331 || event_type == MSG_BUS_DEV_RESET) {
6333 * Any earlier events are irrelevant, so reset our buffer.
6334 * This has the effect of allowing us to deal with reset
6335 * floods (an external device holding down the reset line)
6336 * without losing the event that is really interesting.
6338 lstate->event_r_idx = 0;
6339 lstate->event_w_idx = 0;
6340 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6343 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6344 xpt_print_path(lstate->path);
6345 printf("immediate event %x:%x lost\n",
6346 lstate->event_buffer[lstate->event_r_idx].event_type,
6347 lstate->event_buffer[lstate->event_r_idx].event_arg);
6348 lstate->event_r_idx++;
6349 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6350 lstate->event_r_idx = 0;
6351 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6354 event = &lstate->event_buffer[lstate->event_w_idx];
6355 event->initiator_id = initiator_id;
6356 event->event_type = event_type;
6357 event->event_arg = event_arg;
6358 lstate->event_w_idx++;
6359 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6360 lstate->event_w_idx = 0;
6364 * Send any target mode events queued up waiting
6365 * for immediate notify resources.
6368 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6370 struct ccb_hdr *ccbh;
6371 struct ccb_immediate_notify *inot;
6373 while (lstate->event_r_idx != lstate->event_w_idx
6374 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6375 struct ahc_tmode_event *event;
6377 event = &lstate->event_buffer[lstate->event_r_idx];
6378 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6379 inot = (struct ccb_immediate_notify *)ccbh;
6380 switch (event->event_type) {
6381 case EVENT_TYPE_BUS_RESET:
6382 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6385 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6386 inot->arg = event->event_type;
6387 inot->seq_id = event->event_arg;
6390 inot->initiator_id = event->initiator_id;
6391 xpt_done((union ccb *)inot);
6392 lstate->event_r_idx++;
6393 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6394 lstate->event_r_idx = 0;
6399 /******************** Sequencer Program Patching/Download *********************/
6403 ahc_dumpseq(struct ahc_softc* ahc)
6407 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6408 ahc_outb(ahc, SEQADDR0, 0);
6409 ahc_outb(ahc, SEQADDR1, 0);
6410 for (i = 0; i < ahc->instruction_ram_size; i++) {
6411 uint8_t ins_bytes[4];
6413 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6414 printf("0x%08x\n", ins_bytes[0] << 24
6415 | ins_bytes[1] << 16
6423 ahc_loadseq(struct ahc_softc *ahc)
6425 struct cs cs_table[num_critical_sections];
6426 u_int begin_set[num_critical_sections];
6427 u_int end_set[num_critical_sections];
6428 struct patch *cur_patch;
6433 u_int sg_prefetch_cnt;
6435 uint8_t download_consts[7];
6438 * Start out with 0 critical sections
6439 * that apply to this firmware load.
6443 memset(begin_set, 0, sizeof(begin_set));
6444 memset(end_set, 0, sizeof(end_set));
6446 /* Setup downloadable constant table */
6447 download_consts[QOUTFIFO_OFFSET] = 0;
6448 if (ahc->targetcmds != NULL)
6449 download_consts[QOUTFIFO_OFFSET] += 32;
6450 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6451 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6452 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6453 sg_prefetch_cnt = ahc->pci_cachesize;
6454 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6455 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6456 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6457 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6458 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6460 cur_patch = patches;
6463 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6464 ahc_outb(ahc, SEQADDR0, 0);
6465 ahc_outb(ahc, SEQADDR1, 0);
6467 for (i = 0; i < sizeof(seqprog)/4; i++) {
6468 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6470 * Don't download this instruction as it
6471 * is in a patch that was removed.
6476 if (downloaded == ahc->instruction_ram_size) {
6478 * We're about to exceed the instruction
6479 * storage capacity for this chip. Fail
6482 printf("\n%s: Program too large for instruction memory "
6483 "size of %d!\n", ahc_name(ahc),
6484 ahc->instruction_ram_size);
6489 * Move through the CS table until we find a CS
6490 * that might apply to this instruction.
6492 for (; cur_cs < num_critical_sections; cur_cs++) {
6493 if (critical_sections[cur_cs].end <= i) {
6494 if (begin_set[cs_count] == TRUE
6495 && end_set[cs_count] == FALSE) {
6496 cs_table[cs_count].end = downloaded;
6497 end_set[cs_count] = TRUE;
6502 if (critical_sections[cur_cs].begin <= i
6503 && begin_set[cs_count] == FALSE) {
6504 cs_table[cs_count].begin = downloaded;
6505 begin_set[cs_count] = TRUE;
6509 ahc_download_instr(ahc, i, download_consts);
6513 ahc->num_critical_sections = cs_count;
6514 if (cs_count != 0) {
6516 cs_count *= sizeof(struct cs);
6517 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6518 if (ahc->critical_sections == NULL)
6519 panic("ahc_loadseq: Could not malloc");
6520 memcpy(ahc->critical_sections, cs_table, cs_count);
6522 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6525 printf(" %d instructions downloaded\n", downloaded);
6526 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6527 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6533 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6534 u_int start_instr, u_int *skip_addr)
6536 struct patch *cur_patch;
6537 struct patch *last_patch;
6540 num_patches = sizeof(patches)/sizeof(struct patch);
6541 last_patch = &patches[num_patches];
6542 cur_patch = *start_patch;
6544 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6546 if (cur_patch->patch_func(ahc) == 0) {
6548 /* Start rejecting code */
6549 *skip_addr = start_instr + cur_patch->skip_instr;
6550 cur_patch += cur_patch->skip_patch;
6552 /* Accepted this patch. Advance to the next
6553 * one and wait for our intruction pointer to
6560 *start_patch = cur_patch;
6561 if (start_instr < *skip_addr)
6562 /* Still skipping */
6569 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6571 union ins_formats instr;
6572 struct ins_format1 *fmt1_ins;
6573 struct ins_format3 *fmt3_ins;
6577 * The firmware is always compiled into a little endian format.
6579 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6581 fmt1_ins = &instr.format1;
6584 /* Pull the opcode */
6585 opcode = instr.format1.opcode;
6596 struct patch *cur_patch;
6602 fmt3_ins = &instr.format3;
6604 address = fmt3_ins->address;
6605 cur_patch = patches;
6608 for (i = 0; i < address;) {
6610 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6612 if (skip_addr > i) {
6615 end_addr = MIN(address, skip_addr);
6616 address_offset += end_addr - i;
6622 address -= address_offset;
6623 fmt3_ins->address = address;
6632 if (fmt1_ins->parity != 0) {
6633 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6635 fmt1_ins->parity = 0;
6636 if ((ahc->features & AHC_CMD_CHAN) == 0
6637 && opcode == AIC_OP_BMOV) {
6639 * Block move was added at the same time
6640 * as the command channel. Verify that
6641 * this is only a move of a single element
6642 * and convert the BMOV to a MOV
6643 * (AND with an immediate of FF).
6645 if (fmt1_ins->immediate != 1)
6646 panic("%s: BMOV not supported\n",
6648 fmt1_ins->opcode = AIC_OP_AND;
6649 fmt1_ins->immediate = 0xff;
6653 if ((ahc->features & AHC_ULTRA2) != 0) {
6656 /* Calculate odd parity for the instruction */
6657 for (i = 0, count = 0; i < 31; i++) {
6661 if ((instr.integer & mask) != 0)
6664 if ((count & 0x01) == 0)
6665 instr.format1.parity = 1;
6667 /* Compress the instruction for older sequencers */
6668 if (fmt3_ins != NULL) {
6671 | (fmt3_ins->source << 8)
6672 | (fmt3_ins->address << 16)
6673 | (fmt3_ins->opcode << 25);
6677 | (fmt1_ins->source << 8)
6678 | (fmt1_ins->destination << 16)
6679 | (fmt1_ins->ret << 24)
6680 | (fmt1_ins->opcode << 25);
6683 /* The sequencer is a little endian cpu */
6684 instr.integer = aic_htole32(instr.integer);
6685 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6688 panic("Unknown opcode encountered in seq program");
6694 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6695 const char *name, u_int address, u_int value,
6696 u_int *cur_column, u_int wrap_point)
6702 if (cur_column == NULL) {
6704 cur_column = &dummy_column;
6707 if (*cur_column >= wrap_point) {
6711 printed = printf("%s[0x%x]", name, value);
6712 if (table == NULL) {
6713 printed += printf(" ");
6714 *cur_column += printed;
6718 while (printed_mask != 0xFF) {
6721 for (entry = 0; entry < num_entries; entry++) {
6722 if (((value & table[entry].mask)
6723 != table[entry].value)
6724 || ((printed_mask & table[entry].mask)
6725 == table[entry].mask))
6728 printed += printf("%s%s",
6729 printed_mask == 0 ? ":(" : "|",
6731 printed_mask |= table[entry].mask;
6735 if (entry >= num_entries)
6738 if (printed_mask != 0)
6739 printed += printf(") ");
6741 printed += printf(" ");
6742 if (cur_column != NULL)
6743 *cur_column += printed;
6748 ahc_dump_card_state(struct ahc_softc *ahc)
6751 struct scb_tailq *untagged_q;
6762 uint8_t saved_scbptr;
6764 if (ahc_is_paused(ahc)) {
6771 saved_scbptr = ahc_inb(ahc, SCBPTR);
6772 last_phase = ahc_inb(ahc, LASTPHASE);
6773 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6774 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6775 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6776 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6778 printf("Card was paused\n");
6779 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6780 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6781 ahc_inb(ahc, ARG_2));
6782 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6783 ahc_inb(ahc, SCBPTR));
6785 if ((ahc->features & AHC_DT) != 0)
6786 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6787 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6788 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6789 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6790 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6791 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6792 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6793 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6794 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6795 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6796 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6797 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6798 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6799 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6800 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6801 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6802 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6803 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6804 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6808 for (i = 0; i < STACK_SIZE; i++)
6809 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6810 printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6811 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6812 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6814 printf("QINFIFO entries: ");
6815 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6816 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6817 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6819 qinpos = ahc_inb(ahc, QINPOS);
6820 qintail = ahc->qinfifonext;
6821 while (qinpos != qintail) {
6822 printf("%d ", ahc->qinfifo[qinpos]);
6827 printf("Waiting Queue entries: ");
6828 scb_index = ahc_inb(ahc, WAITING_SCBH);
6830 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6831 ahc_outb(ahc, SCBPTR, scb_index);
6832 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6833 scb_index = ahc_inb(ahc, SCB_NEXT);
6837 printf("Disconnected Queue entries: ");
6838 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6840 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6841 ahc_outb(ahc, SCBPTR, scb_index);
6842 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6843 scb_index = ahc_inb(ahc, SCB_NEXT);
6847 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6848 printf("QOUTFIFO entries: ");
6849 qoutpos = ahc->qoutfifonext;
6851 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6852 printf("%d ", ahc->qoutfifo[qoutpos]);
6857 printf("Sequencer Free SCB List: ");
6858 scb_index = ahc_inb(ahc, FREE_SCBH);
6860 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6861 ahc_outb(ahc, SCBPTR, scb_index);
6862 printf("%d ", scb_index);
6863 scb_index = ahc_inb(ahc, SCB_NEXT);
6867 printf("Sequencer SCB Info: ");
6868 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6869 ahc_outb(ahc, SCBPTR, i);
6870 cur_col = printf("\n%3d ", i);
6872 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6873 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6874 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6875 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6879 printf("Pending list: ");
6881 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6884 cur_col = printf("\n%3d ", scb->hscb->tag);
6885 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6886 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6887 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6888 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6889 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6891 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6893 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6899 printf("Kernel Free SCB list: ");
6901 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6904 printf("%d ", scb->hscb->tag);
6908 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6909 for (target = 0; target <= maxtarget; target++) {
6910 untagged_q = &ahc->untagged_queues[target];
6911 if (TAILQ_FIRST(untagged_q) == NULL)
6913 printf("Untagged Q(%d): ", target);
6915 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6918 printf("%d ", scb->hscb->tag);
6923 ahc_platform_dump_card_state(ahc);
6924 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6925 ahc_outb(ahc, SCBPTR, saved_scbptr);
6930 /*************************** Timeout Handling *********************************/
6932 ahc_timeout(struct scb *scb)
6934 struct ahc_softc *ahc;
6936 ahc = scb->ahc_softc;
6937 if ((scb->flags & SCB_ACTIVE) != 0) {
6938 if ((scb->flags & SCB_TIMEDOUT) == 0) {
6939 LIST_INSERT_HEAD(&ahc->timedout_scbs, scb,
6941 scb->flags |= SCB_TIMEDOUT;
6943 ahc_wakeup_recovery_thread(ahc);
6948 * Re-schedule a timeout for the passed in SCB if we determine that some
6949 * other SCB is in the process of recovery or an SCB with a longer
6950 * timeout is still pending. Limit our search to just "other_scb"
6951 * if it is non-NULL.
6954 ahc_other_scb_timeout(struct ahc_softc *ahc, struct scb *scb,
6955 struct scb *other_scb)
6960 ahc_print_path(ahc, scb);
6961 printf("Other SCB Timeout%s",
6962 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
6963 ? " again\n" : "\n");
6965 newtimeout = aic_get_timeout(scb);
6966 scb->flags |= SCB_OTHERTCL_TIMEOUT;
6968 if (other_scb != NULL) {
6969 if ((other_scb->flags
6970 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6971 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6973 newtimeout = MAX(aic_get_timeout(other_scb),
6977 LIST_FOREACH(other_scb, &ahc->pending_scbs, pending_links) {
6978 if ((other_scb->flags
6979 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6980 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6983 MAX(aic_get_timeout(other_scb),
6990 aic_scb_timer_reset(scb, newtimeout);
6992 ahc_print_path(ahc, scb);
6993 printf("No other SCB worth waiting for...\n");
6996 return (found != 0);
7000 * ahc_recover_commands determines if any of the commands that have currently
7001 * timedout are the root cause for this timeout. Innocent commands are given
7002 * a new timeout while we wait for the command executing on the bus to timeout.
7003 * This routine is invoked from a thread context so we are allowed to sleep.
7004 * Our lock is not held on entry.
7007 ahc_recover_commands(struct ahc_softc *ahc)
7015 * Pause the controller and manually flush any
7016 * commands that have just completed but that our
7017 * interrupt handler has yet to see.
7019 ahc_pause_and_flushwork(ahc);
7021 if (LIST_EMPTY(&ahc->timedout_scbs) != 0) {
7023 * The timedout commands have already
7024 * completed. This typically means
7025 * that either the timeout value was on
7026 * the hairy edge of what the device
7027 * requires or - more likely - interrupts
7028 * are not happening.
7030 printf("%s: Timedout SCBs already complete. "
7031 "Interrupts may not be functioning.\n", ahc_name(ahc));
7037 printf("%s: Recovery Initiated\n", ahc_name(ahc));
7038 ahc_dump_card_state(ahc);
7040 last_phase = ahc_inb(ahc, LASTPHASE);
7041 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7042 u_int active_scb_index;
7049 target = SCB_GET_TARGET(ahc, scb);
7050 channel = SCB_GET_CHANNEL(ahc, scb);
7051 lun = SCB_GET_LUN(scb);
7053 ahc_print_path(ahc, scb);
7054 printf("SCB 0x%x - timed out\n", scb->hscb->tag);
7055 if (scb->sg_count > 0) {
7056 for (i = 0; i < scb->sg_count; i++) {
7057 printf("sg[%d] - Addr 0x%x : Length %d\n",
7059 scb->sg_list[i].addr,
7060 scb->sg_list[i].len & AHC_SG_LEN_MASK);
7063 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
7065 * Been down this road before.
7066 * Do a full bus reset.
7068 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
7070 found = ahc_reset_channel(ahc, channel,
7071 /*Initiate Reset*/TRUE);
7072 printf("%s: Issued Channel %c Bus Reset. "
7073 "%d SCBs aborted\n", ahc_name(ahc), channel,
7079 * Remove the command from the timedout list in
7080 * preparation for requeing it.
7082 LIST_REMOVE(scb, timedout_links);
7083 scb->flags &= ~SCB_TIMEDOUT;
7086 * If we are a target, transition to bus free and report
7089 * The target/initiator that is holding up the bus may not
7090 * be the same as the one that triggered this timeout
7091 * (different commands have different timeout lengths).
7092 * If the bus is idle and we are actiing as the initiator
7093 * for this request, queue a BDR message to the timed out
7094 * target. Otherwise, if the timed out transaction is
7096 * Initiator transaction:
7097 * Stuff the message buffer with a BDR message and assert
7098 * ATN in the hopes that the target will let go of the bus
7099 * and go to the mesgout phase. If this fails, we'll
7100 * get another timeout 2 seconds later which will attempt
7103 * Target transaction:
7104 * Transition to BUS FREE and report the error.
7105 * It's good to be the target!
7107 saved_scbptr = ahc_inb(ahc, SCBPTR);
7108 active_scb_index = ahc_inb(ahc, SCB_TAG);
7110 if ((ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) == 0
7111 && (active_scb_index < ahc->scb_data->numscbs)) {
7112 struct scb *active_scb;
7115 * If the active SCB is not us, assume that
7116 * the active SCB has a longer timeout than
7117 * the timedout SCB, and wait for the active
7120 active_scb = ahc_lookup_scb(ahc, active_scb_index);
7121 if (active_scb != scb) {
7122 if (ahc_other_scb_timeout(ahc, scb,
7129 if ((scb->flags & SCB_TARGET_SCB) != 0) {
7132 * Send back any queued up transactions
7133 * and properly record the error condition.
7135 ahc_abort_scbs(ahc, SCB_GET_TARGET(ahc, scb),
7136 SCB_GET_CHANNEL(ahc, scb),
7142 /* Will clear us from the bus */
7147 ahc_set_recoveryscb(ahc, active_scb);
7148 ahc_outb(ahc, MSG_OUT, HOST_MSG);
7149 ahc_outb(ahc, SCSISIGO, last_phase|ATNO);
7150 ahc_print_path(ahc, active_scb);
7151 printf("BDR message in message buffer\n");
7152 active_scb->flags |= SCB_DEVICE_RESET;
7153 aic_scb_timer_reset(scb, 2 * 1000);
7154 } else if (last_phase != P_BUSFREE
7155 && (ahc_inb(ahc, SSTAT1) & REQINIT) == 0) {
7157 * SCB is not identified, there
7158 * is no pending REQ, and the sequencer
7159 * has not seen a busfree. Looks like
7160 * a stuck connection waiting to
7161 * go busfree. Reset the bus.
7163 printf("%s: Connection stuck awaiting busfree or "
7164 "Identify Msg.\n", ahc_name(ahc));
7169 if (last_phase != P_BUSFREE
7170 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) {
7171 /* Hung target selection. Goto busfree */
7172 printf("%s: Hung target selection\n",
7178 /* XXX Shouldn't panic. Just punt instead? */
7179 if ((scb->flags & SCB_TARGET_SCB) != 0)
7180 panic("Timed-out target SCB but bus idle");
7182 if (ahc_search_qinfifo(ahc, target, channel, lun,
7183 scb->hscb->tag, ROLE_INITIATOR,
7184 /*status*/0, SEARCH_COUNT) > 0) {
7185 disconnected = FALSE;
7187 disconnected = TRUE;
7192 ahc_set_recoveryscb(ahc, scb);
7194 * Actually re-queue this SCB in an attempt
7195 * to select the device before it reconnects.
7196 * In either case (selection or reselection),
7197 * we will now issue a target reset to the
7200 * Set the MK_MESSAGE control bit indicating
7201 * that we desire to send a message. We
7202 * also set the disconnected flag since
7203 * in the paging case there is no guarantee
7204 * that our SCB control byte matches the
7205 * version on the card. We don't want the
7206 * sequencer to abort the command thinking
7207 * an unsolicited reselection occurred.
7209 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
7210 scb->flags |= SCB_DEVICE_RESET;
7213 * Remove any cached copy of this SCB in the
7214 * disconnected list in preparation for the
7215 * queuing of our abort SCB. We use the
7216 * same element in the SCB, SCB_NEXT, for
7217 * both the qinfifo and the disconnected list.
7219 ahc_search_disc_list(ahc, target, channel,
7220 lun, scb->hscb->tag,
7221 /*stop_on_first*/TRUE,
7223 /*save_state*/FALSE);
7226 * In the non-paging case, the sequencer will
7227 * never re-reference the in-core SCB.
7228 * To make sure we are notified during
7229 * reslection, set the MK_MESSAGE flag in
7230 * the card's copy of the SCB.
7232 if ((ahc->flags & AHC_PAGESCBS) == 0) {
7233 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
7234 ahc_outb(ahc, SCB_CONTROL,
7235 ahc_inb(ahc, SCB_CONTROL)
7240 * Clear out any entries in the QINFIFO first
7241 * so we are the next SCB for this target
7244 ahc_search_qinfifo(ahc,
7245 SCB_GET_TARGET(ahc, scb),
7246 channel, SCB_GET_LUN(scb),
7251 ahc_print_path(ahc, scb);
7252 printf("Queuing a BDR SCB\n");
7253 ahc_qinfifo_requeue_tail(ahc, scb);
7254 ahc_outb(ahc, SCBPTR, saved_scbptr);
7255 aic_scb_timer_reset(scb, 2 * 1000);
7257 /* Go "immediatly" to the bus reset */
7258 /* This shouldn't happen */
7259 ahc_set_recoveryscb(ahc, scb);
7260 ahc_print_path(ahc, scb);
7261 printf("SCB %d: Immediate reset. "
7262 "Flags = 0x%x\n", scb->hscb->tag,
7271 * Any remaining SCBs were not the "culprit", so remove
7272 * them from the timeout list. The timer for these commands
7273 * will be reset once the recovery SCB completes.
7275 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7277 LIST_REMOVE(scb, timedout_links);
7278 scb->flags &= ~SCB_TIMEDOUT;
7287 /************************* Target Mode ****************************************/
7288 #ifdef AHC_TARGET_MODE
7290 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
7291 struct ahc_tmode_tstate **tstate,
7292 struct ahc_tmode_lstate **lstate,
7293 int notfound_failure)
7296 if ((ahc->features & AHC_TARGETMODE) == 0)
7297 return (CAM_REQ_INVALID);
7300 * Handle the 'black hole' device that sucks up
7301 * requests to unattached luns on enabled targets.
7303 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
7304 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
7306 *lstate = ahc->black_hole;
7310 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
7311 if (ccb->ccb_h.target_id > max_id)
7312 return (CAM_TID_INVALID);
7314 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
7315 return (CAM_LUN_INVALID);
7317 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
7319 if (*tstate != NULL)
7321 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
7324 if (notfound_failure != 0 && *lstate == NULL)
7325 return (CAM_PATH_INVALID);
7327 return (CAM_REQ_CMP);
7331 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
7333 struct ahc_tmode_tstate *tstate;
7334 struct ahc_tmode_lstate *lstate;
7335 struct ccb_en_lun *cel;
7344 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
7345 /*notfound_failure*/FALSE);
7347 if (status != CAM_REQ_CMP) {
7348 ccb->ccb_h.status = status;
7352 if (cam_sim_bus(sim) == 0)
7353 our_id = ahc->our_id;
7355 our_id = ahc->our_id_b;
7357 if (ccb->ccb_h.target_id != our_id) {
7359 * our_id represents our initiator ID, or
7360 * the ID of the first target to have an
7361 * enabled lun in target mode. There are
7362 * two cases that may preclude enabling a
7363 * target id other than our_id.
7365 * o our_id is for an active initiator role.
7366 * Since the hardware does not support
7367 * reselections to the initiator role at
7368 * anything other than our_id, and our_id
7369 * is used by the hardware to indicate the
7370 * ID to use for both select-out and
7371 * reselect-out operations, the only target
7372 * ID we can support in this mode is our_id.
7374 * o The MULTARGID feature is not available and
7375 * a previous target mode ID has been enabled.
7377 if ((ahc->features & AHC_MULTIROLE) != 0) {
7379 if ((ahc->features & AHC_MULTI_TID) != 0
7380 && (ahc->flags & AHC_INITIATORROLE) != 0) {
7382 * Only allow additional targets if
7383 * the initiator role is disabled.
7384 * The hardware cannot handle a re-select-in
7385 * on the initiator id during a re-select-out
7386 * on a different target id.
7388 status = CAM_TID_INVALID;
7389 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
7390 || ahc->enabled_luns > 0) {
7392 * Only allow our target id to change
7393 * if the initiator role is not configured
7394 * and there are no enabled luns which
7395 * are attached to the currently registered
7398 status = CAM_TID_INVALID;
7400 } else if ((ahc->features & AHC_MULTI_TID) == 0
7401 && ahc->enabled_luns > 0) {
7403 status = CAM_TID_INVALID;
7407 if (status != CAM_REQ_CMP) {
7408 ccb->ccb_h.status = status;
7413 * We now have an id that is valid.
7414 * If we aren't in target mode, switch modes.
7416 if ((ahc->flags & AHC_TARGETROLE) == 0
7417 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7418 ahc_flag saved_flags;
7420 printf("Configuring Target Mode\n");
7421 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
7422 ccb->ccb_h.status = CAM_BUSY;
7425 saved_flags = ahc->flags;
7426 ahc->flags |= AHC_TARGETROLE;
7427 if ((ahc->features & AHC_MULTIROLE) == 0)
7428 ahc->flags &= ~AHC_INITIATORROLE;
7430 error = ahc_loadseq(ahc);
7433 * Restore original configuration and notify
7434 * the caller that we cannot support target mode.
7435 * Since the adapter started out in this
7436 * configuration, the firmware load will succeed,
7437 * so there is no point in checking ahc_loadseq's
7440 ahc->flags = saved_flags;
7441 (void)ahc_loadseq(ahc);
7443 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
7449 target = ccb->ccb_h.target_id;
7450 lun = ccb->ccb_h.target_lun;
7451 channel = SIM_CHANNEL(ahc, sim);
7452 target_mask = 0x01 << target;
7456 if (cel->enable != 0) {
7459 /* Are we already enabled?? */
7460 if (lstate != NULL) {
7461 xpt_print_path(ccb->ccb_h.path);
7462 printf("Lun already enabled\n");
7463 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7467 if (cel->grp6_len != 0
7468 || cel->grp7_len != 0) {
7470 * Don't (yet?) support vendor
7471 * specific commands.
7473 ccb->ccb_h.status = CAM_REQ_INVALID;
7474 printf("Non-zero Group Codes\n");
7480 * Setup our data structures.
7482 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7483 tstate = ahc_alloc_tstate(ahc, target, channel);
7484 if (tstate == NULL) {
7485 xpt_print_path(ccb->ccb_h.path);
7486 printf("Couldn't allocate tstate\n");
7487 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7491 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
7492 if (lstate == NULL) {
7493 xpt_print_path(ccb->ccb_h.path);
7494 printf("Couldn't allocate lstate\n");
7495 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7498 memset(lstate, 0, sizeof(*lstate));
7499 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7500 xpt_path_path_id(ccb->ccb_h.path),
7501 xpt_path_target_id(ccb->ccb_h.path),
7502 xpt_path_lun_id(ccb->ccb_h.path));
7503 if (status != CAM_REQ_CMP) {
7504 free(lstate, M_DEVBUF);
7505 xpt_print_path(ccb->ccb_h.path);
7506 printf("Couldn't allocate path\n");
7507 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7510 SLIST_INIT(&lstate->accept_tios);
7511 SLIST_INIT(&lstate->immed_notifies);
7513 if (target != CAM_TARGET_WILDCARD) {
7514 tstate->enabled_luns[lun] = lstate;
7515 ahc->enabled_luns++;
7517 if ((ahc->features & AHC_MULTI_TID) != 0) {
7520 targid_mask = ahc_inb(ahc, TARGID)
7521 | (ahc_inb(ahc, TARGID + 1) << 8);
7523 targid_mask |= target_mask;
7524 ahc_outb(ahc, TARGID, targid_mask);
7525 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7527 ahc_update_scsiid(ahc, targid_mask);
7532 channel = SIM_CHANNEL(ahc, sim);
7533 our_id = SIM_SCSI_ID(ahc, sim);
7536 * This can only happen if selections
7539 if (target != our_id) {
7544 sblkctl = ahc_inb(ahc, SBLKCTL);
7545 cur_channel = (sblkctl & SELBUSB)
7547 if ((ahc->features & AHC_TWIN) == 0)
7549 swap = cur_channel != channel;
7551 ahc->our_id = target;
7553 ahc->our_id_b = target;
7556 ahc_outb(ahc, SBLKCTL,
7559 ahc_outb(ahc, SCSIID, target);
7562 ahc_outb(ahc, SBLKCTL, sblkctl);
7566 ahc->black_hole = lstate;
7567 /* Allow select-in operations */
7568 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7569 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7571 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7572 scsiseq = ahc_inb(ahc, SCSISEQ);
7574 ahc_outb(ahc, SCSISEQ, scsiseq);
7577 ccb->ccb_h.status = CAM_REQ_CMP;
7578 xpt_print_path(ccb->ccb_h.path);
7579 printf("Lun now enabled for target mode\n");
7584 if (lstate == NULL) {
7585 ccb->ccb_h.status = CAM_LUN_INVALID;
7589 ccb->ccb_h.status = CAM_REQ_CMP;
7590 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7591 struct ccb_hdr *ccbh;
7593 ccbh = &scb->io_ctx->ccb_h;
7594 if (ccbh->func_code == XPT_CONT_TARGET_IO
7595 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7596 printf("CTIO pending\n");
7597 ccb->ccb_h.status = CAM_REQ_INVALID;
7602 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7603 printf("ATIOs pending\n");
7604 ccb->ccb_h.status = CAM_REQ_INVALID;
7607 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7608 printf("INOTs pending\n");
7609 ccb->ccb_h.status = CAM_REQ_INVALID;
7612 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7616 xpt_print_path(ccb->ccb_h.path);
7617 printf("Target mode disabled\n");
7618 xpt_free_path(lstate->path);
7619 free(lstate, M_DEVBUF);
7622 /* Can we clean up the target too? */
7623 if (target != CAM_TARGET_WILDCARD) {
7624 tstate->enabled_luns[lun] = NULL;
7625 ahc->enabled_luns--;
7626 for (empty = 1, i = 0; i < 8; i++)
7627 if (tstate->enabled_luns[i] != NULL) {
7633 ahc_free_tstate(ahc, target, channel,
7635 if (ahc->features & AHC_MULTI_TID) {
7638 targid_mask = ahc_inb(ahc, TARGID)
7639 | (ahc_inb(ahc, TARGID + 1)
7642 targid_mask &= ~target_mask;
7643 ahc_outb(ahc, TARGID, targid_mask);
7644 ahc_outb(ahc, TARGID+1,
7645 (targid_mask >> 8));
7646 ahc_update_scsiid(ahc, targid_mask);
7651 ahc->black_hole = NULL;
7654 * We can't allow selections without
7655 * our black hole device.
7659 if (ahc->enabled_luns == 0) {
7660 /* Disallow select-in */
7663 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7665 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7666 scsiseq = ahc_inb(ahc, SCSISEQ);
7668 ahc_outb(ahc, SCSISEQ, scsiseq);
7670 if ((ahc->features & AHC_MULTIROLE) == 0) {
7671 printf("Configuring Initiator Mode\n");
7672 ahc->flags &= ~AHC_TARGETROLE;
7673 ahc->flags |= AHC_INITIATORROLE;
7675 * Returning to a configuration that
7676 * fit previously will always succeed.
7678 (void)ahc_loadseq(ahc);
7681 * Unpaused. The extra unpause
7682 * that follows is harmless.
7691 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7696 if ((ahc->features & AHC_MULTI_TID) == 0)
7697 panic("ahc_update_scsiid called on non-multitid unit\n");
7700 * Since we will rely on the TARGID mask
7701 * for selection enables, ensure that OID
7702 * in SCSIID is not set to some other ID
7703 * that we don't want to allow selections on.
7705 if ((ahc->features & AHC_ULTRA2) != 0)
7706 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7708 scsiid = ahc_inb(ahc, SCSIID);
7709 scsiid_mask = 0x1 << (scsiid & OID);
7710 if ((targid_mask & scsiid_mask) == 0) {
7713 /* ffs counts from 1 */
7714 our_id = ffs(targid_mask);
7716 our_id = ahc->our_id;
7722 if ((ahc->features & AHC_ULTRA2) != 0)
7723 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7725 ahc_outb(ahc, SCSIID, scsiid);
7729 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7731 struct target_cmd *cmd;
7734 * If the card supports auto-access pause,
7735 * we can access the card directly regardless
7736 * of whether it is paused or not.
7738 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7741 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7742 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7745 * Only advance through the queue if we
7746 * have the resources to process the command.
7748 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7752 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
7753 ahc->shared_data_dmamap,
7754 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7755 sizeof(struct target_cmd),
7756 BUS_DMASYNC_PREREAD);
7757 ahc->tqinfifonext++;
7760 * Lazily update our position in the target mode incoming
7761 * command queue as seen by the sequencer.
7763 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7764 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7767 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7768 hs_mailbox &= ~HOST_TQINPOS;
7769 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7770 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7774 ahc_outb(ahc, KERNEL_TQINPOS,
7775 ahc->tqinfifonext & HOST_TQINPOS);
7784 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7786 struct ahc_tmode_tstate *tstate;
7787 struct ahc_tmode_lstate *lstate;
7788 struct ccb_accept_tio *atio;
7794 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7795 target = SCSIID_OUR_ID(cmd->scsiid);
7796 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7799 tstate = ahc->enabled_targets[target];
7802 lstate = tstate->enabled_luns[lun];
7805 * Commands for disabled luns go to the black hole driver.
7808 lstate = ahc->black_hole;
7810 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7812 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7814 * Wait for more ATIOs from the peripheral driver for this lun.
7817 printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7820 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7822 if (ahc_debug & AHC_SHOW_TQIN) {
7823 printf("Incoming command from %d for %d:%d%s\n",
7824 initiator, target, lun,
7825 lstate == ahc->black_hole ? "(Black Holed)" : "");
7828 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7830 if (lstate == ahc->black_hole) {
7831 /* Fill in the wildcards */
7832 atio->ccb_h.target_id = target;
7833 atio->ccb_h.target_lun = lun;
7837 * Package it up and send it off to
7838 * whomever has this lun enabled.
7840 atio->sense_len = 0;
7841 atio->init_id = initiator;
7842 if (byte[0] != 0xFF) {
7843 /* Tag was included */
7844 atio->tag_action = *byte++;
7845 atio->tag_id = *byte++;
7846 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7848 atio->ccb_h.flags = 0;
7852 /* Okay. Now determine the cdb size based on the command code */
7853 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7869 /* Only copy the opcode. */
7871 printf("Reserved or VU command code type encountered\n");
7875 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7877 atio->ccb_h.status |= CAM_CDB_RECVD;
7879 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7881 * We weren't allowed to disconnect.
7882 * We're hanging on the bus until a
7883 * continue target I/O comes in response
7884 * to this accept tio.
7887 if (ahc_debug & AHC_SHOW_TQIN) {
7888 printf("Received Immediate Command %d:%d:%d - %p\n",
7889 initiator, target, lun, ahc->pending_device);
7892 ahc->pending_device = lstate;
7893 aic_freeze_ccb((union ccb *)atio);
7894 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7896 xpt_done((union ccb*)atio);