2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#78 $
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aic7xxx_93cx6.h"
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
52 #include <dev/aic7xxx/aic7xxx_osm.h>
53 #include <dev/aic7xxx/aic7xxx_inline.h>
54 #include <dev/aic7xxx/aic7xxx_93cx6.h>
57 static __inline uint64_t
58 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
64 | ((uint64_t)vendor << 32)
65 | ((uint64_t)device << 48);
70 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
71 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
72 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
73 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
74 #define ID_9005_SISL_ID 0x0005900500000000ull
75 #define ID_AIC7850 0x5078900400000000ull
76 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull
77 #define ID_AIC7855 0x5578900400000000ull
78 #define ID_AIC7859 0x3860900400000000ull
79 #define ID_AHA_2930CU 0x3860900438699004ull
80 #define ID_AIC7860 0x6078900400000000ull
81 #define ID_AIC7860C 0x6078900478609004ull
82 #define ID_AHA_1480A 0x6075900400000000ull
83 #define ID_AHA_2940AU_0 0x6178900400000000ull
84 #define ID_AHA_2940AU_1 0x6178900478619004ull
85 #define ID_AHA_2940AU_CN 0x2178900478219004ull
86 #define ID_AHA_2930C_VAR 0x6038900438689004ull
88 #define ID_AIC7870 0x7078900400000000ull
89 #define ID_AHA_2940 0x7178900400000000ull
90 #define ID_AHA_3940 0x7278900400000000ull
91 #define ID_AHA_398X 0x7378900400000000ull
92 #define ID_AHA_2944 0x7478900400000000ull
93 #define ID_AHA_3944 0x7578900400000000ull
94 #define ID_AHA_4944 0x7678900400000000ull
96 #define ID_AIC7880 0x8078900400000000ull
97 #define ID_AIC7880_B 0x8078900478809004ull
98 #define ID_AHA_2940U 0x8178900400000000ull
99 #define ID_AHA_3940U 0x8278900400000000ull
100 #define ID_AHA_2944U 0x8478900400000000ull
101 #define ID_AHA_3944U 0x8578900400000000ull
102 #define ID_AHA_398XU 0x8378900400000000ull
103 #define ID_AHA_4944U 0x8678900400000000ull
104 #define ID_AHA_2940UB 0x8178900478819004ull
105 #define ID_AHA_2930U 0x8878900478889004ull
106 #define ID_AHA_2940U_PRO 0x8778900478879004ull
107 #define ID_AHA_2940U_CN 0x0078900478009004ull
109 #define ID_AIC7895 0x7895900478959004ull
110 #define ID_AIC7895_ARO 0x7890900478939004ull
111 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
112 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
113 #define ID_AHA_3940AU 0x7895900478929004ull
114 #define ID_AHA_3944AU 0x7895900478949004ull
116 #define ID_AIC7890 0x001F9005000F9005ull
117 #define ID_AIC7890_ARO 0x00139005000F9005ull
118 #define ID_AAA_131U2 0x0013900500039005ull
119 #define ID_AHA_2930U2 0x0011900501819005ull
120 #define ID_AHA_2940U2B 0x00109005A1009005ull
121 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
122 #define ID_AHA_2940U2 0x00109005A1809005ull
123 #define ID_AHA_2950U2B 0x00109005E1009005ull
125 #define ID_AIC7892 0x008F9005FFFF9005ull
126 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
127 #define ID_AHA_29160 0x00809005E2A09005ull
128 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
129 #define ID_AHA_29160N 0x0080900562A09005ull
130 #define ID_AHA_29160C 0x0080900562209005ull
131 #define ID_AHA_29160B 0x00809005E2209005ull
132 #define ID_AHA_19160B 0x0081900562A19005ull
133 #define ID_AHA_2915_30LP 0x0082900502109005ull
135 #define ID_AIC7896 0x005F9005FFFF9005ull
136 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
137 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
138 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
139 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
140 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
142 #define ID_AIC7899 0x00CF9005FFFF9005ull
143 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
144 #define ID_AHA_3960D 0x00C09005F6209005ull
145 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
147 #define ID_AIC7810 0x1078900400000000ull
148 #define ID_AIC7815 0x7815900400000000ull
150 #define DEVID_9005_TYPE(id) ((id) & 0xF)
151 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
152 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
153 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
154 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
156 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
157 #define DEVID_9005_MAXRATE_U160 0x0
158 #define DEVID_9005_MAXRATE_ULTRA2 0x1
159 #define DEVID_9005_MAXRATE_ULTRA 0x2
160 #define DEVID_9005_MAXRATE_FAST 0x3
162 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
164 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
165 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
167 #define SUBID_9005_TYPE(id) ((id) & 0xF)
168 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
169 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
170 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
171 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
173 #define SUBID_9005_TYPE_KNOWN(id) \
174 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
175 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
176 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
177 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
179 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
180 #define SUBID_9005_MAXRATE_ULTRA2 0x0
181 #define SUBID_9005_MAXRATE_ULTRA 0x1
182 #define SUBID_9005_MAXRATE_U160 0x2
183 #define SUBID_9005_MAXRATE_RESERVED 0x3
185 #define SUBID_9005_SEEPTYPE(id) \
186 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
187 ? ((id) & 0xC0) >> 6 \
188 : ((id) & 0x300) >> 8)
189 #define SUBID_9005_SEEPTYPE_NONE 0x0
190 #define SUBID_9005_SEEPTYPE_1K 0x1
191 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
192 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
193 #define SUBID_9005_AUTOTERM(id) \
194 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
195 ? (((id) & 0x400) >> 10) == 0 \
196 : (((id) & 0x40) >> 6) == 0)
198 #define SUBID_9005_NUMCHAN(id) \
199 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
200 ? ((id) & 0x300) >> 8 \
201 : ((id) & 0xC00) >> 10)
203 #define SUBID_9005_LEGACYCONN(id) \
204 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
206 : ((id) & 0x80) >> 7)
208 #define SUBID_9005_MFUNCENB(id) \
209 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
210 ? ((id) & 0x800) >> 11 \
211 : ((id) & 0x1000) >> 12)
213 * Informational only. Should use chip register to be
214 * certain, but may be use in identification strings.
216 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
217 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
218 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
220 static ahc_device_setup_t ahc_aic785X_setup;
221 static ahc_device_setup_t ahc_aic7860_setup;
222 static ahc_device_setup_t ahc_apa1480_setup;
223 static ahc_device_setup_t ahc_aic7870_setup;
224 static ahc_device_setup_t ahc_aha394X_setup;
225 static ahc_device_setup_t ahc_aha494X_setup;
226 static ahc_device_setup_t ahc_aha398X_setup;
227 static ahc_device_setup_t ahc_aic7880_setup;
228 static ahc_device_setup_t ahc_aha2940Pro_setup;
229 static ahc_device_setup_t ahc_aha394XU_setup;
230 static ahc_device_setup_t ahc_aha398XU_setup;
231 static ahc_device_setup_t ahc_aic7890_setup;
232 static ahc_device_setup_t ahc_aic7892_setup;
233 static ahc_device_setup_t ahc_aic7895_setup;
234 static ahc_device_setup_t ahc_aic7896_setup;
235 static ahc_device_setup_t ahc_aic7899_setup;
236 static ahc_device_setup_t ahc_aha29160C_setup;
237 static ahc_device_setup_t ahc_raid_setup;
238 static ahc_device_setup_t ahc_aha394XX_setup;
239 static ahc_device_setup_t ahc_aha494XX_setup;
240 static ahc_device_setup_t ahc_aha398XX_setup;
242 struct ahc_pci_identity ahc_pci_ident_table [] =
244 /* aic7850 based controllers */
246 ID_AHA_2902_04_10_15_20C_30C,
248 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
251 /* aic7860 based controllers */
255 "Adaptec 2930CU SCSI adapter",
259 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
261 "Adaptec 1480A Ultra SCSI adapter",
265 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
267 "Adaptec 2940A Ultra SCSI adapter",
271 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
273 "Adaptec 2940A/CN Ultra SCSI adapter",
277 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
279 "Adaptec 2930C Ultra SCSI adapter (VAR)",
282 /* aic7870 based controllers */
286 "Adaptec 2940 SCSI adapter",
292 "Adaptec 3940 SCSI adapter",
298 "Adaptec 398X SCSI RAID adapter",
304 "Adaptec 2944 SCSI adapter",
310 "Adaptec 3944 SCSI adapter",
316 "Adaptec 4944 SCSI adapter",
319 /* aic7880 based controllers */
321 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
323 "Adaptec 2940 Ultra SCSI adapter",
327 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
329 "Adaptec 3940 Ultra SCSI adapter",
333 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
335 "Adaptec 2944 Ultra SCSI adapter",
339 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
341 "Adaptec 3944 Ultra SCSI adapter",
345 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
347 "Adaptec 398X Ultra SCSI RAID adapter",
352 * XXX Don't know the slot numbers
353 * so we can't identify channels
355 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
357 "Adaptec 4944 Ultra SCSI adapter",
361 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
363 "Adaptec 2930 Ultra SCSI adapter",
367 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
369 "Adaptec 2940 Pro Ultra SCSI adapter",
373 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
375 "Adaptec 2940/CN Ultra SCSI adapter",
378 /* Ignore all SISL (AAC on MB) based controllers. */
385 /* aic7890 based controllers */
389 "Adaptec 2930 Ultra2 SCSI adapter",
395 "Adaptec 2940B Ultra2 SCSI adapter",
401 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
407 "Adaptec 2940 Ultra2 SCSI adapter",
413 "Adaptec 2950 Ultra2 SCSI adapter",
419 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
425 "Adaptec AAA-131 Ultra2 RAID adapter",
428 /* aic7892 based controllers */
432 "Adaptec 29160 Ultra160 SCSI adapter",
438 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
444 "Adaptec 29160N Ultra160 SCSI adapter",
450 "Adaptec 29160C Ultra160 SCSI adapter",
456 "Adaptec 29160B Ultra160 SCSI adapter",
462 "Adaptec 19160B Ultra160 SCSI adapter",
468 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
474 "Adaptec 2915/30LP Ultra160 SCSI adapter",
477 /* aic7895 based controllers */
481 "Adaptec 2940/DUAL Ultra SCSI adapter",
487 "Adaptec 3940A Ultra SCSI adapter",
493 "Adaptec 3944A Ultra SCSI adapter",
499 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
502 /* aic7896/97 based controllers */
506 "Adaptec 3950B Ultra2 SCSI adapter",
512 "Adaptec 3950B Ultra2 SCSI adapter",
518 "Adaptec 3950D Ultra2 SCSI adapter",
524 "Adaptec 3950D Ultra2 SCSI adapter",
530 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
533 /* aic7899 based controllers */
537 "Adaptec 3960D Ultra160 SCSI adapter",
543 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
549 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
552 /* Generic chip probes for devices we don't know 'exactly' */
554 ID_AIC7850 & ID_DEV_VENDOR_MASK,
556 "Adaptec aic7850 SCSI adapter",
560 ID_AIC7855 & ID_DEV_VENDOR_MASK,
562 "Adaptec aic7855 SCSI adapter",
566 ID_AIC7859 & ID_DEV_VENDOR_MASK,
568 "Adaptec aic7859 SCSI adapter",
572 ID_AIC7860 & ID_DEV_VENDOR_MASK,
574 "Adaptec aic7860 Ultra SCSI adapter",
578 ID_AIC7870 & ID_DEV_VENDOR_MASK,
580 "Adaptec aic7870 SCSI adapter",
584 ID_AIC7880 & ID_DEV_VENDOR_MASK,
586 "Adaptec aic7880 Ultra SCSI adapter",
590 ID_AIC7890 & ID_9005_GENERIC_MASK,
591 ID_9005_GENERIC_MASK,
592 "Adaptec aic7890/91 Ultra2 SCSI adapter",
596 ID_AIC7892 & ID_9005_GENERIC_MASK,
597 ID_9005_GENERIC_MASK,
598 "Adaptec aic7892 Ultra160 SCSI adapter",
602 ID_AIC7895 & ID_DEV_VENDOR_MASK,
604 "Adaptec aic7895 Ultra SCSI adapter",
608 ID_AIC7896 & ID_9005_GENERIC_MASK,
609 ID_9005_GENERIC_MASK,
610 "Adaptec aic7896/97 Ultra2 SCSI adapter",
614 ID_AIC7899 & ID_9005_GENERIC_MASK,
615 ID_9005_GENERIC_MASK,
616 "Adaptec aic7899 Ultra160 SCSI adapter",
620 ID_AIC7810 & ID_DEV_VENDOR_MASK,
622 "Adaptec aic7810 RAID memory controller",
626 ID_AIC7815 & ID_DEV_VENDOR_MASK,
628 "Adaptec aic7815 RAID memory controller",
633 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
635 #define AHC_394X_SLOT_CHANNEL_A 4
636 #define AHC_394X_SLOT_CHANNEL_B 5
638 #define AHC_398X_SLOT_CHANNEL_A 4
639 #define AHC_398X_SLOT_CHANNEL_B 8
640 #define AHC_398X_SLOT_CHANNEL_C 12
642 #define AHC_494X_SLOT_CHANNEL_A 4
643 #define AHC_494X_SLOT_CHANNEL_B 5
644 #define AHC_494X_SLOT_CHANNEL_C 6
645 #define AHC_494X_SLOT_CHANNEL_D 7
647 #define DEVCONFIG 0x40
648 #define PCIERRGENDIS 0x80000000ul
649 #define SCBSIZE32 0x00010000ul /* aic789X only */
650 #define REXTVALID 0x00001000ul /* ultra cards only */
651 #define MPORTMODE 0x00000400ul /* aic7870+ only */
652 #define RAMPSM 0x00000200ul /* aic7870+ only */
653 #define VOLSENSE 0x00000100ul
654 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
655 #define SCBRAMSEL 0x00000080ul
656 #define MRDCEN 0x00000040ul
657 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
658 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
659 #define BERREN 0x00000008ul
660 #define DACEN 0x00000004ul
661 #define STPWLEVEL 0x00000002ul
662 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
664 #define CSIZE_LATTIME 0x0c
665 #define CACHESIZE 0x0000003ful /* only 5 bits */
666 #define LATTIME 0x0000ff00ul
668 /* PCI STATUS definitions */
676 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
677 uint16_t subvendor, uint16_t subdevice);
678 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
679 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
680 int pcheck, int fast, int large);
681 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
682 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
683 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
684 struct seeprom_config *sc);
685 static void configure_termination(struct ahc_softc *ahc,
686 struct seeprom_descriptor *sd,
687 u_int adapter_control,
690 static void ahc_new_term_detect(struct ahc_softc *ahc,
695 int *eeprom_present);
696 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
697 int *internal68_present,
698 int *externalcable_present,
699 int *eeprom_present);
700 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
701 int *externalcable_present,
702 int *eeprom_present);
703 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
704 static uint8_t read_brdctl(struct ahc_softc *ahc);
705 static void ahc_pci_intr(struct ahc_softc *ahc);
706 static int ahc_pci_chip_init(struct ahc_softc *ahc);
707 static int ahc_pci_suspend(struct ahc_softc *ahc);
708 static int ahc_pci_resume(struct ahc_softc *ahc);
711 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
712 uint16_t subdevice, uint16_t subvendor)
716 /* Default to invalid. */
719 && subvendor == 0x9005
720 && subdevice != device
721 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
723 switch (SUBID_9005_TYPE(subdevice)) {
724 case SUBID_9005_TYPE_MB:
726 case SUBID_9005_TYPE_CARD:
727 case SUBID_9005_TYPE_LCCARD:
729 * Currently only trust Adaptec cards to
730 * get the sub device info correct.
732 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
735 case SUBID_9005_TYPE_RAID:
744 struct ahc_pci_identity *
745 ahc_find_pci_device(aic_dev_softc_t pci)
752 struct ahc_pci_identity *entry;
755 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
756 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
757 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
758 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
759 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
762 * If the second function is not hooked up, ignore it.
763 * Unfortunately, not all MB vendors implement the
764 * subdevice ID as per the Adaptec spec, so do our best
765 * to sanity check it prior to accepting the subdevice
768 if (aic_get_pci_function(pci) > 0
769 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
770 && SUBID_9005_MFUNCENB(subdevice) == 0)
773 for (i = 0; i < ahc_num_pci_devs; i++) {
774 entry = &ahc_pci_ident_table[i];
775 if (entry->full_id == (full_id & entry->id_mask)) {
776 /* Honor exclusion entries. */
777 if (entry->name == NULL)
786 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
798 error = entry->setup(ahc);
801 ahc->chip |= AHC_PCI;
802 ahc->description = entry->name;
804 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
806 error = ahc_pci_map_registers(ahc);
811 * Before we continue probing the card, ensure that
812 * its interrupts are *disabled*. We don't want
813 * a misstep to hang the machine in an interrupt
816 ahc_intr_enable(ahc, FALSE);
818 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
821 * If we need to support high memory, enable dual
822 * address cycles. This bit must be set to enable
823 * high address bit generation even if we are on a
824 * 64bit bus (PCI64BIT set in devconfig).
826 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
829 printf("%s: Enabling 39Bit Addressing\n",
834 /* Ensure that pci error generation, a test feature, is disabled. */
835 devconfig |= PCIERRGENDIS;
837 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
839 /* Ensure busmastering is enabled */
840 command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
841 command |= PCIM_CMD_BUSMASTEREN;
843 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
845 /* On all PCI adapters, we allow SCB paging */
846 ahc->flags |= AHC_PAGESCBS;
848 error = ahc_softc_init(ahc);
853 * Disable PCI parity error checking. Users typically
854 * do this to work around broken PCI chipsets that get
855 * the parity timing wrong and thus generate lots of spurious
856 * errors. The chip only allows us to disable *all* parity
857 * error reporting when doing this, so CIO bus, scb ram, and
858 * scratch ram parity errors will be ignored too.
860 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
861 ahc->seqctl |= FAILDIS;
863 ahc->bus_intr = ahc_pci_intr;
864 ahc->bus_chip_init = ahc_pci_chip_init;
865 ahc->bus_suspend = ahc_pci_suspend;
866 ahc->bus_resume = ahc_pci_resume;
868 /* Remeber how the card was setup in case there is no SEEPROM */
869 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
871 if ((ahc->features & AHC_ULTRA2) != 0)
872 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
874 our_id = ahc_inb(ahc, SCSIID) & OID;
875 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
876 scsiseq = ahc_inb(ahc, SCSISEQ);
883 error = ahc_reset(ahc, /*reinit*/FALSE);
887 if ((ahc->features & AHC_DT) != 0) {
890 /* Perform ALT-Mode Setup */
891 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
892 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
893 ahc_outb(ahc, OPTIONMODE,
894 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
895 ahc_outb(ahc, SFUNCT, sfunct);
897 /* Normal mode setup */
898 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
902 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
903 dscommand0 |= MPARCKEN|CACHETHEN;
904 if ((ahc->features & AHC_ULTRA2) != 0) {
907 * DPARCKEN doesn't work correctly on
908 * some MBs so don't use it.
910 dscommand0 &= ~DPARCKEN;
914 * Handle chips that must have cache line
915 * streaming (dis/en)abled.
917 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
918 dscommand0 |= CACHETHEN;
920 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
921 dscommand0 &= ~CACHETHEN;
923 ahc_outb(ahc, DSCOMMAND0, dscommand0);
926 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
927 /*bytes*/1) & CACHESIZE;
928 ahc->pci_cachesize *= 4;
930 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
931 && ahc->pci_cachesize == 4) {
933 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
935 ahc->pci_cachesize = 0;
939 * We cannot perform ULTRA speeds without the presense
940 * of the external precision resistor.
942 if ((ahc->features & AHC_ULTRA) != 0) {
945 devconfig = aic_pci_read_config(ahc->dev_softc,
946 DEVCONFIG, /*bytes*/4);
947 if ((devconfig & REXTVALID) == 0)
948 ahc->features &= ~AHC_ULTRA;
951 /* See if we have a SEEPROM and perform auto-term */
952 check_extport(ahc, &sxfrctl1);
955 * Take the LED out of diagnostic mode
957 sblkctl = ahc_inb(ahc, SBLKCTL);
958 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
960 if ((ahc->features & AHC_ULTRA2) != 0) {
961 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
963 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
966 if (ahc->flags & AHC_USEDEFAULTS) {
968 * PCI Adapter default setup
969 * Should only be used if the adapter does not have
972 /* See if someone else set us up already */
973 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
975 printf("%s: Using left over BIOS settings\n",
977 ahc->flags &= ~AHC_USEDEFAULTS;
978 ahc->flags |= AHC_BIOS_ENABLED;
981 * Assume only one connector and always turn
987 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
989 ahc->our_id = our_id;
993 * Take a look to see if we have external SRAM.
994 * We currently do not attempt to use SRAM that is
995 * shared among multiple controllers.
997 ahc_probe_ext_scbram(ahc);
1000 * Record our termination setting for the
1001 * generic initialization routine.
1003 if ((sxfrctl1 & STPWEN) != 0)
1004 ahc->flags |= AHC_TERM_ENB_A;
1007 * Save chip register configuration data for chip resets
1008 * that occur during runtime and resume events.
1010 ahc->bus_softc.pci_softc.devconfig =
1011 aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1012 ahc->bus_softc.pci_softc.command =
1013 aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1014 ahc->bus_softc.pci_softc.csize_lattime =
1015 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1016 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1017 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1018 if ((ahc->features & AHC_DT) != 0) {
1021 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1022 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1023 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1024 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1025 ahc_outb(ahc, SFUNCT, sfunct);
1026 ahc->bus_softc.pci_softc.crccontrol1 =
1027 ahc_inb(ahc, CRCCONTROL1);
1029 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1030 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1032 if ((ahc->features & AHC_ULTRA2) != 0)
1033 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1035 /* Core initialization */
1036 error = ahc_init(ahc);
1041 * Allow interrupts now that we are completely setup.
1043 error = ahc_pci_map_int(ahc);
1049 * Link this softc in with all other ahc instances.
1051 ahc_softc_insert(ahc);
1057 * Test for the presense of external sram in an
1058 * "unshared" configuration.
1061 ahc_ext_scbram_present(struct ahc_softc *ahc)
1068 chip = ahc->chip & AHC_CHIPID_MASK;
1069 devconfig = aic_pci_read_config(ahc->dev_softc,
1070 DEVCONFIG, /*bytes*/4);
1071 single_user = (devconfig & MPORTMODE) != 0;
1073 if ((ahc->features & AHC_ULTRA2) != 0)
1074 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1075 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1077 * External SCBRAM arbitration is flakey
1078 * on these chips. Unfortunately this means
1079 * we don't use the extra SCB ram space on the
1083 else if (chip >= AHC_AIC7870)
1084 ramps = (devconfig & RAMPSM) != 0;
1088 if (ramps && single_user)
1094 * Enable external scbram.
1097 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1098 int fast, int large)
1102 if (ahc->features & AHC_MULTI_FUNC) {
1104 * Set the SCB Base addr (highest address bit)
1105 * depending on which channel we are.
1107 ahc_outb(ahc, SCBBADDR, aic_get_pci_function(ahc->dev_softc));
1110 ahc->flags &= ~AHC_LSCBS_ENABLED;
1112 ahc->flags |= AHC_LSCBS_ENABLED;
1113 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1114 if ((ahc->features & AHC_ULTRA2) != 0) {
1117 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1119 dscommand0 &= ~INTSCBRAMSEL;
1121 dscommand0 |= INTSCBRAMSEL;
1123 dscommand0 &= ~USCBSIZE32;
1125 dscommand0 |= USCBSIZE32;
1126 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1129 devconfig &= ~EXTSCBTIME;
1131 devconfig |= EXTSCBTIME;
1133 devconfig &= ~SCBRAMSEL;
1135 devconfig |= SCBRAMSEL;
1137 devconfig &= ~SCBSIZE32;
1139 devconfig |= SCBSIZE32;
1142 devconfig |= EXTSCBPEN;
1144 devconfig &= ~EXTSCBPEN;
1146 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1150 * Take a look to see if we have external SRAM.
1151 * We currently do not attempt to use SRAM that is
1152 * shared among multiple controllers.
1155 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1170 if (ahc_ext_scbram_present(ahc) == 0)
1174 * Probe for the best parameters to use.
1176 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1177 num_scbs = ahc_probe_scbs(ahc);
1178 if (num_scbs == 0) {
1179 /* The SRAM wasn't really present. */
1185 * Clear any outstanding parity error
1186 * and ensure that parity error reporting
1189 ahc_outb(ahc, SEQCTL, 0);
1190 ahc_outb(ahc, CLRINT, CLRPARERR);
1191 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1193 /* Now see if we can do parity */
1194 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1195 num_scbs = ahc_probe_scbs(ahc);
1196 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1197 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1200 /* Clear any resulting parity error */
1201 ahc_outb(ahc, CLRINT, CLRPARERR);
1202 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1204 /* Now see if we can do fast timing */
1205 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1206 test_num_scbs = ahc_probe_scbs(ahc);
1207 if (test_num_scbs == num_scbs
1208 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1209 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1213 * See if we can use large SCBs and still maintain
1214 * the same overall count of SCBs.
1216 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1217 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1218 test_num_scbs = ahc_probe_scbs(ahc);
1219 if (test_num_scbs >= num_scbs) {
1221 num_scbs = test_num_scbs;
1222 if (num_scbs >= 64) {
1224 * We have enough space to move the
1225 * "busy targets table" into SCB space
1226 * and make it qualify all the way to the
1229 ahc->flags |= AHC_SCB_BTT;
1235 * Disable parity error reporting until we
1236 * can load instruction ram.
1238 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1239 /* Clear any latched parity error */
1240 ahc_outb(ahc, CLRINT, CLRPARERR);
1241 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1242 if (bootverbose && enable) {
1243 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1244 ahc_name(ahc), fast ? "fast" : "slow",
1245 pcheck ? ", parity checking enabled" : "",
1248 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1252 * Perform some simple tests that should catch situations where
1253 * our registers are invalidly mapped.
1256 ahc_pci_test_register_access(struct ahc_softc *ahc)
1266 * Enable PCI error interrupt status, but suppress NMIs
1267 * generated by SERR raised due to target aborts.
1269 cmd = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1270 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1271 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1274 * First a simple test to see if any
1275 * registers can be read. Reading
1276 * HCNTRL has no side effects and has
1277 * at least one bit that is guaranteed to
1278 * be zero so it is a good register to
1279 * use for this test.
1281 hcntrl = ahc_inb(ahc, HCNTRL);
1286 if ((hcntrl & CHIPRST) != 0) {
1288 * The chip has not been initialized since
1289 * PCI/EISA/VLB bus reset. Don't trust
1290 * "left over BIOS data".
1292 ahc->flags |= AHC_NO_BIOS_INIT;
1296 * Next create a situation where write combining
1297 * or read prefetching could be initiated by the
1298 * CPU or host bridge. Our device does not support
1299 * either, so look for data corruption and/or flagged
1300 * PCI errors. First pause without causing another
1304 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1305 while (ahc_is_paused(ahc) == 0)
1308 /* Clear any PCI errors that occurred before our driver attached. */
1309 status1 = aic_pci_read_config(ahc->dev_softc,
1310 PCIR_STATUS + 1, /*bytes*/1);
1311 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1312 status1, /*bytes*/1);
1313 ahc_outb(ahc, CLRINT, CLRPARERR);
1315 ahc_outb(ahc, SEQCTL, PERRORDIS);
1316 ahc_outb(ahc, SCBPTR, 0);
1317 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1318 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1321 status1 = aic_pci_read_config(ahc->dev_softc,
1322 PCIR_STATUS + 1, /*bytes*/1);
1323 if ((status1 & STA) != 0)
1329 /* Silently clear any latched errors. */
1330 status1 = aic_pci_read_config(ahc->dev_softc,
1331 PCIR_STATUS + 1, /*bytes*/1);
1332 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1333 status1, /*bytes*/1);
1334 ahc_outb(ahc, CLRINT, CLRPARERR);
1335 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1336 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1341 * Check the external port logic for a serial eeprom
1342 * and termination/cable detection contrls.
1345 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1347 struct seeprom_descriptor sd;
1348 struct seeprom_config *sc;
1353 sd.sd_control_offset = SEECTL;
1354 sd.sd_status_offset = SEECTL;
1355 sd.sd_dataout_offset = SEECTL;
1356 sc = ahc->seep_config;
1359 * For some multi-channel devices, the c46 is simply too
1360 * small to work. For the other controller types, we can
1361 * get our information from either SEEPROM type. Set the
1362 * type to start our probe with accordingly.
1364 if (ahc->flags & AHC_LARGE_SEEPROM)
1365 sd.sd_chip = C56_66;
1376 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1380 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1385 start_addr = 32 * (ahc->channel - 'A');
1387 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1392 have_seeprom = ahc_verify_cksum(sc);
1394 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1396 if (have_seeprom == 0)
1397 printf ("checksum error\n");
1403 sd.sd_chip = C56_66;
1405 ahc_release_seeprom(&sd);
1407 /* Remember the SEEPROM type for later */
1408 if (sd.sd_chip == C56_66)
1409 ahc->flags |= AHC_LARGE_SEEPROM;
1412 if (!have_seeprom) {
1414 * Pull scratch ram settings and treat them as
1415 * if they are the contents of an seeprom if
1416 * the 'ADPT' signature is found in SCB2.
1417 * We manually compose the data as 16bit values
1418 * to avoid endian issues.
1420 ahc_outb(ahc, SCBPTR, 2);
1421 if (ahc_inb(ahc, SCB_BASE) == 'A'
1422 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1423 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1424 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1428 sc_data = (uint16_t *)sc;
1429 for (i = 0; i < 32; i++, sc_data++) {
1433 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1434 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1436 have_seeprom = ahc_verify_cksum(sc);
1438 ahc->flags |= AHC_SCB_CONFIG_USED;
1441 * Clear any SCB parity errors in case this data and
1442 * its associated parity was not initialized by the BIOS
1444 ahc_outb(ahc, CLRINT, CLRPARERR);
1445 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1448 if (!have_seeprom) {
1450 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1451 ahc->flags |= AHC_USEDEFAULTS;
1452 free(ahc->seep_config, M_DEVBUF);
1453 ahc->seep_config = NULL;
1456 ahc_parse_pci_eeprom(ahc, sc);
1460 * Cards that have the external logic necessary to talk to
1461 * a SEEPROM, are almost certain to have the remaining logic
1462 * necessary for auto-termination control. This assumption
1463 * hasn't failed yet...
1465 have_autoterm = have_seeprom;
1468 * Some low-cost chips have SEEPROM and auto-term control built
1469 * in, instead of using a GAL. They can tell us directly
1470 * if the termination logic is enabled.
1472 if ((ahc->features & AHC_SPIOCAP) != 0) {
1473 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1474 have_autoterm = FALSE;
1477 if (have_autoterm) {
1478 ahc->flags |= AHC_HAS_TERM_LOGIC;
1479 ahc_acquire_seeprom(ahc, &sd);
1480 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1481 ahc_release_seeprom(&sd);
1482 } else if (have_seeprom) {
1483 *sxfrctl1 &= ~STPWEN;
1484 if ((sc->adapter_control & CFSTERM) != 0)
1485 *sxfrctl1 |= STPWEN;
1487 printf("%s: Low byte termination %sabled\n",
1489 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1494 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1497 * Put the data we've collected down into SRAM
1498 * where ahc_init will find it.
1501 int max_targ = sc->max_targets & CFMAXTARG;
1503 uint16_t discenable;
1508 if ((sc->adapter_control & CFULTRAEN) != 0) {
1510 * Determine if this adapter has a "newstyle"
1513 for (i = 0; i < max_targ; i++) {
1514 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1515 ahc->flags |= AHC_NEWEEPROM_FMT;
1521 for (i = 0; i < max_targ; i++) {
1523 uint16_t target_mask;
1525 target_mask = 0x01 << i;
1526 if (sc->device_flags[i] & CFDISC)
1527 discenable |= target_mask;
1528 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1529 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1530 ultraenb |= target_mask;
1531 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1532 ultraenb |= target_mask;
1534 if ((sc->device_flags[i] & CFXFER) == 0x04
1535 && (ultraenb & target_mask) != 0) {
1536 /* Treat 10MHz as a non-ultra speed */
1537 sc->device_flags[i] &= ~CFXFER;
1538 ultraenb &= ~target_mask;
1540 if ((ahc->features & AHC_ULTRA2) != 0) {
1543 if (sc->device_flags[i] & CFSYNCH)
1544 offset = MAX_OFFSET_ULTRA2;
1547 ahc_outb(ahc, TARG_OFFSET + i, offset);
1550 * The ultra enable bits contain the
1551 * high bit of the ultra2 sync rate
1554 scsirate = (sc->device_flags[i] & CFXFER)
1555 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1556 if (sc->device_flags[i] & CFWIDEB)
1557 scsirate |= WIDEXFER;
1559 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1560 if (sc->device_flags[i] & CFSYNCH)
1562 if (sc->device_flags[i] & CFWIDEB)
1563 scsirate |= WIDEXFER;
1565 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1567 ahc->our_id = sc->brtime_id & CFSCSIID;
1569 scsi_conf = (ahc->our_id & 0x7);
1570 if (sc->adapter_control & CFSPARITY)
1571 scsi_conf |= ENSPCHK;
1572 if (sc->adapter_control & CFRESETB)
1573 scsi_conf |= RESET_SCSI;
1575 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1577 if (sc->bios_control & CFEXTEND)
1578 ahc->flags |= AHC_EXTENDED_TRANS_A;
1580 if (sc->bios_control & CFBIOSEN)
1581 ahc->flags |= AHC_BIOS_ENABLED;
1582 if (ahc->features & AHC_ULTRA
1583 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1584 /* Should we enable Ultra mode? */
1585 if (!(sc->adapter_control & CFULTRAEN))
1586 /* Treat us as a non-ultra card */
1590 if (sc->signature == CFSIGNATURE
1591 || sc->signature == CFSIGNATURE2) {
1594 /* Honor the STPWLEVEL settings */
1595 devconfig = aic_pci_read_config(ahc->dev_softc,
1596 DEVCONFIG, /*bytes*/4);
1597 devconfig &= ~STPWLEVEL;
1598 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1599 devconfig |= STPWLEVEL;
1600 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
1601 devconfig, /*bytes*/4);
1603 /* Set SCSICONF info */
1604 ahc_outb(ahc, SCSICONF, scsi_conf);
1605 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1606 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1607 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1608 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1612 configure_termination(struct ahc_softc *ahc,
1613 struct seeprom_descriptor *sd,
1614 u_int adapter_control,
1622 * Update the settings in sxfrctl1 to match the
1623 * termination settings
1628 * SEECS must be on for the GALS to latch
1629 * the data properly. Be sure to leave MS
1630 * on or we will release the seeprom.
1632 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1633 if ((adapter_control & CFAUTOTERM) != 0
1634 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1635 int internal50_present;
1636 int internal68_present;
1637 int externalcable_present;
1649 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1650 ahc_new_term_detect(ahc, &enableSEC_low,
1655 if ((adapter_control & CFSEAUTOTERM) == 0) {
1657 printf("%s: Manual SE Termination\n",
1659 enableSEC_low = (adapter_control & CFSELOWTERM);
1661 (adapter_control & CFSEHIGHTERM);
1663 if ((adapter_control & CFAUTOTERM) == 0) {
1665 printf("%s: Manual LVD Termination\n",
1667 enablePRI_low = (adapter_control & CFSTERM);
1668 enablePRI_high = (adapter_control & CFWSTERM);
1670 /* Make the table calculations below happy */
1671 internal50_present = 0;
1672 internal68_present = 1;
1673 externalcable_present = 1;
1674 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1675 aic785X_cable_detect(ahc, &internal50_present,
1676 &externalcable_present,
1678 /* Can never support a wide connector. */
1679 internal68_present = 0;
1681 aic787X_cable_detect(ahc, &internal50_present,
1682 &internal68_present,
1683 &externalcable_present,
1687 if ((ahc->features & AHC_WIDE) == 0)
1688 internal68_present = 0;
1691 && (ahc->features & AHC_ULTRA2) == 0) {
1692 printf("%s: internal 50 cable %s present",
1694 internal50_present ? "is":"not");
1696 if ((ahc->features & AHC_WIDE) != 0)
1697 printf(", internal 68 cable %s present",
1698 internal68_present ? "is":"not");
1699 printf("\n%s: external cable %s present\n",
1701 externalcable_present ? "is":"not");
1704 printf("%s: BIOS eeprom %s present\n",
1705 ahc_name(ahc), eeprom_present ? "is" : "not");
1707 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1709 * The 50 pin connector is a separate bus,
1710 * so force it to always be terminated.
1711 * In the future, perform current sensing
1712 * to determine if we are in the middle of
1713 * a properly terminated bus.
1715 internal50_present = 0;
1719 * Now set the termination based on what
1721 * Flash Enable = BRDDAT7
1722 * Secondary High Term Enable = BRDDAT6
1723 * Secondary Low Term Enable = BRDDAT5 (7890)
1724 * Primary High Term Enable = BRDDAT4 (7890)
1726 if ((ahc->features & AHC_ULTRA2) == 0
1727 && (internal50_present != 0)
1728 && (internal68_present != 0)
1729 && (externalcable_present != 0)) {
1730 printf("%s: Illegal cable configuration!!. "
1731 "Only two connectors on the "
1732 "adapter may be used at a "
1733 "time!\n", ahc_name(ahc));
1736 * Pretend there are no cables in the hope
1737 * that having all of the termination on
1738 * gives us a more stable bus.
1740 internal50_present = 0;
1741 internal68_present = 0;
1742 externalcable_present = 0;
1745 if ((ahc->features & AHC_WIDE) != 0
1746 && ((externalcable_present == 0)
1747 || (internal68_present == 0)
1748 || (enableSEC_high != 0))) {
1751 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1752 printf("%s: 68 pin termination "
1753 "Enabled\n", ahc_name(ahc));
1755 printf("%s: %sHigh byte termination "
1756 "Enabled\n", ahc_name(ahc),
1757 enableSEC_high ? "Secondary "
1762 sum = internal50_present + internal68_present
1763 + externalcable_present;
1764 if (sum < 2 || (enableSEC_low != 0)) {
1765 if ((ahc->features & AHC_ULTRA2) != 0)
1768 *sxfrctl1 |= STPWEN;
1770 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1771 printf("%s: 50 pin termination "
1772 "Enabled\n", ahc_name(ahc));
1774 printf("%s: %sLow byte termination "
1775 "Enabled\n", ahc_name(ahc),
1776 enableSEC_low ? "Secondary "
1781 if (enablePRI_low != 0) {
1782 *sxfrctl1 |= STPWEN;
1784 printf("%s: Primary Low Byte termination "
1785 "Enabled\n", ahc_name(ahc));
1789 * Setup STPWEN before setting up the rest of
1790 * the termination per the tech note on the U160 cards.
1792 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1794 if (enablePRI_high != 0) {
1797 printf("%s: Primary High Byte "
1798 "termination Enabled\n",
1802 write_brdctl(ahc, brddat);
1805 if ((adapter_control & CFSTERM) != 0) {
1806 *sxfrctl1 |= STPWEN;
1809 printf("%s: %sLow byte termination Enabled\n",
1811 (ahc->features & AHC_ULTRA2) ? "Primary "
1815 if ((adapter_control & CFWSTERM) != 0
1816 && (ahc->features & AHC_WIDE) != 0) {
1819 printf("%s: %sHigh byte termination Enabled\n",
1821 (ahc->features & AHC_ULTRA2)
1822 ? "Secondary " : "");
1826 * Setup STPWEN before setting up the rest of
1827 * the termination per the tech note on the U160 cards.
1829 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1831 if ((ahc->features & AHC_WIDE) != 0)
1832 write_brdctl(ahc, brddat);
1834 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1838 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1839 int *enableSEC_high, int *enablePRI_low,
1840 int *enablePRI_high, int *eeprom_present)
1846 * BRDDAT6 = Enable Secondary High Byte termination
1847 * BRDDAT5 = Enable Secondary Low Byte termination
1848 * BRDDAT4 = Enable Primary high byte termination
1849 * BRDDAT3 = Enable Primary low byte termination
1851 brdctl = read_brdctl(ahc);
1852 *eeprom_present = brdctl & BRDDAT7;
1853 *enableSEC_high = (brdctl & BRDDAT6);
1854 *enableSEC_low = (brdctl & BRDDAT5);
1855 *enablePRI_high = (brdctl & BRDDAT4);
1856 *enablePRI_low = (brdctl & BRDDAT3);
1860 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1861 int *internal68_present, int *externalcable_present,
1862 int *eeprom_present)
1867 * First read the status of our cables.
1868 * Set the rom bank to 0 since the
1869 * bank setting serves as a multiplexor
1870 * for the cable detection logic.
1871 * BRDDAT5 controls the bank switch.
1873 write_brdctl(ahc, 0);
1876 * Now read the state of the internal
1877 * connectors. BRDDAT6 is INT50 and
1880 brdctl = read_brdctl(ahc);
1881 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1882 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1885 * Set the rom bank to 1 and determine
1886 * the other signals.
1888 write_brdctl(ahc, BRDDAT5);
1891 * Now read the state of the external
1892 * connectors. BRDDAT6 is EXT68 and
1893 * BRDDAT7 is EPROMPS.
1895 brdctl = read_brdctl(ahc);
1896 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1897 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1901 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1902 int *externalcable_present, int *eeprom_present)
1907 spiocap = ahc_inb(ahc, SPIOCAP);
1908 spiocap &= ~SOFTCMDEN;
1909 spiocap |= EXT_BRDCTL;
1910 ahc_outb(ahc, SPIOCAP, spiocap);
1911 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1912 ahc_flush_device_writes(ahc);
1914 ahc_outb(ahc, BRDCTL, 0);
1915 ahc_flush_device_writes(ahc);
1917 brdctl = ahc_inb(ahc, BRDCTL);
1918 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1919 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1920 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1924 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1928 if ((ahc->features & AHC_SPIOCAP) != 0
1929 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1933 * Request access of the memory port. When access is
1934 * granted, SEERDY will go high. We use a 1 second
1935 * timeout which should be near 1 second more than
1936 * is needed. Reason: after the chip reset, there
1937 * should be no contention.
1939 SEEPROM_OUTB(sd, sd->sd_MS);
1940 wait = 1000; /* 1 second timeout in msec */
1941 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1942 aic_delay(1000); /* delay 1 msec */
1944 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1945 SEEPROM_OUTB(sd, 0);
1952 ahc_release_seeprom(struct seeprom_descriptor *sd)
1954 /* Release access to the memory port and the serial EEPROM. */
1955 SEEPROM_OUTB(sd, 0);
1959 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1963 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1965 if (ahc->channel == 'B')
1967 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1970 brdctl = BRDSTB|BRDCS;
1972 ahc_outb(ahc, BRDCTL, brdctl);
1973 ahc_flush_device_writes(ahc);
1975 ahc_outb(ahc, BRDCTL, brdctl);
1976 ahc_flush_device_writes(ahc);
1977 if ((ahc->features & AHC_ULTRA2) != 0)
1978 brdctl |= BRDSTB_ULTRA2;
1981 ahc_outb(ahc, BRDCTL, brdctl);
1982 ahc_flush_device_writes(ahc);
1983 if ((ahc->features & AHC_ULTRA2) != 0)
1987 ahc_outb(ahc, BRDCTL, brdctl);
1991 read_brdctl(struct ahc_softc *ahc)
1996 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1998 if (ahc->channel == 'B')
2000 } else if ((ahc->features & AHC_ULTRA2) != 0) {
2001 brdctl = BRDRW_ULTRA2;
2003 brdctl = BRDRW|BRDCS;
2005 ahc_outb(ahc, BRDCTL, brdctl);
2006 ahc_flush_device_writes(ahc);
2007 value = ahc_inb(ahc, BRDCTL);
2008 ahc_outb(ahc, BRDCTL, 0);
2013 ahc_pci_intr(struct ahc_softc *ahc)
2018 error = ahc_inb(ahc, ERROR);
2019 if ((error & PCIERRSTAT) == 0)
2022 status1 = aic_pci_read_config(ahc->dev_softc,
2023 PCIR_STATUS + 1, /*bytes*/1);
2025 if ((status1 & ~DPE) != 0
2026 || (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2027 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2029 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2033 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2034 ahc->pci_target_perr_count++;
2035 printf("%s: Data Parity Error Detected during address "
2036 "or write data phase\n", ahc_name(ahc));
2038 if (status1 & SSE) {
2039 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
2041 if (status1 & RMA) {
2042 printf("%s: Received a Master Abort\n", ahc_name(ahc));
2044 if (status1 & RTA) {
2045 printf("%s: Received a Target Abort\n", ahc_name(ahc));
2047 if (status1 & STA) {
2048 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2050 if (status1 & DPR) {
2051 printf("%s: Data Parity Error has been reported via PERR#\n",
2055 /* Clear latched errors. */
2056 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2057 status1, /*bytes*/1);
2059 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2060 printf("%s: Latched PCIERR interrupt with "
2061 "no status bits set\n", ahc_name(ahc));
2063 ahc_outb(ahc, CLRINT, CLRPARERR);
2066 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH
2067 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2069 "%s: WARNING WARNING WARNING WARNING\n"
2070 "%s: Too many PCI parity errors observed as a target.\n"
2071 "%s: Some device on this PCI bus is generating bad parity.\n"
2072 "%s: This is an error *observed by*, not *generated by*, %s.\n"
2073 "%s: PCI parity error checking has been disabled.\n"
2074 "%s: WARNING WARNING WARNING WARNING\n",
2075 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2076 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2078 ahc->seqctl |= FAILDIS;
2079 ahc->flags |= AHC_DISABLE_PCI_PERR;
2080 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2086 ahc_pci_chip_init(struct ahc_softc *ahc)
2088 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2089 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2090 if ((ahc->features & AHC_DT) != 0) {
2093 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2094 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2095 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2096 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2097 ahc_outb(ahc, SFUNCT, sfunct);
2098 ahc_outb(ahc, CRCCONTROL1,
2099 ahc->bus_softc.pci_softc.crccontrol1);
2101 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2102 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2104 if ((ahc->features & AHC_ULTRA2) != 0)
2105 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2107 return (ahc_chip_init(ahc));
2111 ahc_pci_suspend(struct ahc_softc *ahc)
2113 return (ahc_suspend(ahc));
2117 ahc_pci_resume(struct ahc_softc *ahc)
2120 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
2123 * We assume that the OS has restored our register
2124 * mappings, etc. Just update the config space registers
2125 * that the OS doesn't know about and rely on our chip
2126 * reset handler to handle the rest.
2128 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
2129 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
2130 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
2131 ahc->bus_softc.pci_softc.command, /*bytes*/1);
2132 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
2133 ahc->bus_softc.pci_softc.csize_lattime,
2135 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2136 struct seeprom_descriptor sd;
2140 sd.sd_control_offset = SEECTL;
2141 sd.sd_status_offset = SEECTL;
2142 sd.sd_dataout_offset = SEECTL;
2144 ahc_acquire_seeprom(ahc, &sd);
2145 configure_termination(ahc, &sd,
2146 ahc->seep_config->adapter_control,
2148 ahc_release_seeprom(&sd);
2150 return (ahc_resume(ahc));
2154 ahc_aic785X_setup(struct ahc_softc *ahc)
2156 aic_dev_softc_t pci;
2159 pci = ahc->dev_softc;
2161 ahc->chip = AHC_AIC7850;
2162 ahc->features = AHC_AIC7850_FE;
2163 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2164 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2166 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2167 ahc->instruction_ram_size = 512;
2172 ahc_aic7860_setup(struct ahc_softc *ahc)
2174 aic_dev_softc_t pci;
2177 pci = ahc->dev_softc;
2179 ahc->chip = AHC_AIC7860;
2180 ahc->features = AHC_AIC7860_FE;
2181 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2182 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2184 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2185 ahc->instruction_ram_size = 512;
2190 ahc_apa1480_setup(struct ahc_softc *ahc)
2194 error = ahc_aic7860_setup(ahc);
2197 ahc->features |= AHC_REMOVABLE;
2202 ahc_aic7870_setup(struct ahc_softc *ahc)
2206 ahc->chip = AHC_AIC7870;
2207 ahc->features = AHC_AIC7870_FE;
2208 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2209 ahc->instruction_ram_size = 512;
2214 ahc_aha394X_setup(struct ahc_softc *ahc)
2218 error = ahc_aic7870_setup(ahc);
2220 error = ahc_aha394XX_setup(ahc);
2225 ahc_aha398X_setup(struct ahc_softc *ahc)
2229 error = ahc_aic7870_setup(ahc);
2231 error = ahc_aha398XX_setup(ahc);
2236 ahc_aha494X_setup(struct ahc_softc *ahc)
2240 error = ahc_aic7870_setup(ahc);
2242 error = ahc_aha494XX_setup(ahc);
2247 ahc_aic7880_setup(struct ahc_softc *ahc)
2249 aic_dev_softc_t pci;
2252 pci = ahc->dev_softc;
2254 ahc->chip = AHC_AIC7880;
2255 ahc->features = AHC_AIC7880_FE;
2256 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2257 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2259 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2261 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2263 ahc->instruction_ram_size = 512;
2268 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2271 ahc->flags |= AHC_INT50_SPEEDFLEX;
2272 return (ahc_aic7880_setup(ahc));
2276 ahc_aha394XU_setup(struct ahc_softc *ahc)
2280 error = ahc_aic7880_setup(ahc);
2282 error = ahc_aha394XX_setup(ahc);
2287 ahc_aha398XU_setup(struct ahc_softc *ahc)
2291 error = ahc_aic7880_setup(ahc);
2293 error = ahc_aha398XX_setup(ahc);
2298 ahc_aic7890_setup(struct ahc_softc *ahc)
2300 aic_dev_softc_t pci;
2303 pci = ahc->dev_softc;
2305 ahc->chip = AHC_AIC7890;
2306 ahc->features = AHC_AIC7890_FE;
2307 ahc->flags |= AHC_NEWEEPROM_FMT;
2308 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2310 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2311 ahc->instruction_ram_size = 768;
2316 ahc_aic7892_setup(struct ahc_softc *ahc)
2320 ahc->chip = AHC_AIC7892;
2321 ahc->features = AHC_AIC7892_FE;
2322 ahc->flags |= AHC_NEWEEPROM_FMT;
2323 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2324 ahc->instruction_ram_size = 1024;
2329 ahc_aic7895_setup(struct ahc_softc *ahc)
2331 aic_dev_softc_t pci;
2334 pci = ahc->dev_softc;
2335 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2337 * The 'C' revision of the aic7895 has a few additional features.
2339 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2341 ahc->chip = AHC_AIC7895C;
2342 ahc->features = AHC_AIC7895C_FE;
2346 ahc->chip = AHC_AIC7895;
2347 ahc->features = AHC_AIC7895_FE;
2350 * The BIOS disables the use of MWI transactions
2351 * since it does not have the MWI bug work around
2352 * we have. Disabling MWI reduces performance, so
2355 command = aic_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2356 command |= PCIM_CMD_MWRICEN;
2357 aic_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2358 ahc->bugs |= AHC_PCI_MWI_BUG;
2361 * XXX Does CACHETHEN really not work??? What about PCI retry?
2362 * on C level chips. Need to test, but for now, play it safe.
2364 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2365 | AHC_CACHETHEN_BUG;
2371 * Cachesize must also be zero due to stray DAC
2372 * problem when sitting behind some bridges.
2374 aic_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2375 devconfig = aic_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2376 devconfig |= MRDCEN;
2377 aic_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2379 ahc->flags |= AHC_NEWEEPROM_FMT;
2380 ahc->instruction_ram_size = 512;
2385 ahc_aic7896_setup(struct ahc_softc *ahc)
2387 aic_dev_softc_t pci;
2389 pci = ahc->dev_softc;
2390 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2391 ahc->chip = AHC_AIC7896;
2392 ahc->features = AHC_AIC7896_FE;
2393 ahc->flags |= AHC_NEWEEPROM_FMT;
2394 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2395 ahc->instruction_ram_size = 768;
2400 ahc_aic7899_setup(struct ahc_softc *ahc)
2402 aic_dev_softc_t pci;
2404 pci = ahc->dev_softc;
2405 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2406 ahc->chip = AHC_AIC7899;
2407 ahc->features = AHC_AIC7899_FE;
2408 ahc->flags |= AHC_NEWEEPROM_FMT;
2409 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2410 ahc->instruction_ram_size = 1024;
2415 ahc_aha29160C_setup(struct ahc_softc *ahc)
2419 error = ahc_aic7899_setup(ahc);
2422 ahc->features |= AHC_REMOVABLE;
2427 ahc_raid_setup(struct ahc_softc *ahc)
2429 printf("RAID functionality unsupported\n");
2434 ahc_aha394XX_setup(struct ahc_softc *ahc)
2436 aic_dev_softc_t pci;
2438 pci = ahc->dev_softc;
2439 switch (aic_get_pci_slot(pci)) {
2440 case AHC_394X_SLOT_CHANNEL_A:
2443 case AHC_394X_SLOT_CHANNEL_B:
2447 printf("adapter at unexpected slot %d\n"
2448 "unable to map to a channel\n",
2449 aic_get_pci_slot(pci));
2456 ahc_aha398XX_setup(struct ahc_softc *ahc)
2458 aic_dev_softc_t pci;
2460 pci = ahc->dev_softc;
2461 switch (aic_get_pci_slot(pci)) {
2462 case AHC_398X_SLOT_CHANNEL_A:
2465 case AHC_398X_SLOT_CHANNEL_B:
2468 case AHC_398X_SLOT_CHANNEL_C:
2472 printf("adapter at unexpected slot %d\n"
2473 "unable to map to a channel\n",
2474 aic_get_pci_slot(pci));
2478 ahc->flags |= AHC_LARGE_SEEPROM;
2483 ahc_aha494XX_setup(struct ahc_softc *ahc)
2485 aic_dev_softc_t pci;
2487 pci = ahc->dev_softc;
2488 switch (aic_get_pci_slot(pci)) {
2489 case AHC_494X_SLOT_CHANNEL_A:
2492 case AHC_494X_SLOT_CHANNEL_B:
2495 case AHC_494X_SLOT_CHANNEL_C:
2498 case AHC_494X_SLOT_CHANNEL_D:
2502 printf("adapter at unexpected slot %d\n"
2503 "unable to map to a channel\n",
2504 aic_get_pci_slot(pci));
2507 ahc->flags |= AHC_LARGE_SEEPROM;