2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
40 #include <sys/module.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_llc.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/ip.h>
61 #include <netinet/tcp.h>
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
69 #include <machine/atomic.h>
70 #include <machine/bus.h>
71 #include <machine/in_cksum.h>
73 #include <dev/ale/if_alereg.h>
74 #include <dev/ale/if_alevar.h>
76 /* "device miibus" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
79 /* For more information about Tx checksum offload issues see ale_encap(). */
80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
82 MODULE_DEPEND(ale, pci, 1, 1, 1);
83 MODULE_DEPEND(ale, ether, 1, 1, 1);
84 MODULE_DEPEND(ale, miibus, 1, 1, 1);
87 static int msi_disable = 0;
88 static int msix_disable = 0;
89 TUNABLE_INT("hw.ale.msi_disable", &msi_disable);
90 TUNABLE_INT("hw.ale.msix_disable", &msix_disable);
93 * Devices supported by this driver.
95 static struct ale_dev {
96 uint16_t ale_vendorid;
97 uint16_t ale_deviceid;
100 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
101 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
104 static int ale_attach(device_t);
105 static int ale_check_boundary(struct ale_softc *);
106 static int ale_detach(device_t);
107 static int ale_dma_alloc(struct ale_softc *);
108 static void ale_dma_free(struct ale_softc *);
109 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
110 static int ale_encap(struct ale_softc *, struct mbuf **);
111 static void ale_get_macaddr(struct ale_softc *);
112 static void ale_init(void *);
113 static void ale_init_locked(struct ale_softc *);
114 static void ale_init_rx_pages(struct ale_softc *);
115 static void ale_init_tx_ring(struct ale_softc *);
116 static void ale_int_task(void *, int);
117 static int ale_intr(void *);
118 static int ale_ioctl(struct ifnet *, u_long, caddr_t);
119 static void ale_link_task(void *, int);
120 static void ale_mac_config(struct ale_softc *);
121 static int ale_miibus_readreg(device_t, int, int);
122 static void ale_miibus_statchg(device_t);
123 static int ale_miibus_writereg(device_t, int, int, int);
124 static int ale_mediachange(struct ifnet *);
125 static void ale_mediastatus(struct ifnet *, struct ifmediareq *);
126 static void ale_phy_reset(struct ale_softc *);
127 static int ale_probe(device_t);
128 static void ale_reset(struct ale_softc *);
129 static int ale_resume(device_t);
130 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
131 uint32_t, uint32_t *);
132 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
133 static int ale_rxeof(struct ale_softc *sc, int);
134 static void ale_rxfilter(struct ale_softc *);
135 static void ale_rxvlan(struct ale_softc *);
136 static void ale_setlinkspeed(struct ale_softc *);
137 static void ale_setwol(struct ale_softc *);
138 static int ale_shutdown(device_t);
139 static void ale_start(struct ifnet *);
140 static void ale_stats_clear(struct ale_softc *);
141 static void ale_stats_update(struct ale_softc *);
142 static void ale_stop(struct ale_softc *);
143 static void ale_stop_mac(struct ale_softc *);
144 static int ale_suspend(device_t);
145 static void ale_sysctl_node(struct ale_softc *);
146 static void ale_tick(void *);
147 static void ale_tx_task(void *, int);
148 static void ale_txeof(struct ale_softc *);
149 static void ale_watchdog(struct ale_softc *);
150 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
151 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS);
152 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
154 static device_method_t ale_methods[] = {
155 /* Device interface. */
156 DEVMETHOD(device_probe, ale_probe),
157 DEVMETHOD(device_attach, ale_attach),
158 DEVMETHOD(device_detach, ale_detach),
159 DEVMETHOD(device_shutdown, ale_shutdown),
160 DEVMETHOD(device_suspend, ale_suspend),
161 DEVMETHOD(device_resume, ale_resume),
164 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
165 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
166 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
171 static driver_t ale_driver = {
174 sizeof(struct ale_softc)
177 static devclass_t ale_devclass;
179 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0);
180 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0);
182 static struct resource_spec ale_res_spec_mem[] = {
183 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
187 static struct resource_spec ale_irq_spec_legacy[] = {
188 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
192 static struct resource_spec ale_irq_spec_msi[] = {
193 { SYS_RES_IRQ, 1, RF_ACTIVE },
197 static struct resource_spec ale_irq_spec_msix[] = {
198 { SYS_RES_IRQ, 1, RF_ACTIVE },
203 ale_miibus_readreg(device_t dev, int phy, int reg)
205 struct ale_softc *sc;
209 sc = device_get_softc(dev);
211 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
212 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
213 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
215 v = CSR_READ_4(sc, ALE_MDIO);
216 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
221 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
225 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
229 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
231 struct ale_softc *sc;
235 sc = device_get_softc(dev);
237 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
238 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
239 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
240 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
242 v = CSR_READ_4(sc, ALE_MDIO);
243 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
248 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
254 ale_miibus_statchg(device_t dev)
256 struct ale_softc *sc;
258 sc = device_get_softc(dev);
260 taskqueue_enqueue(taskqueue_swi, &sc->ale_link_task);
264 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
266 struct ale_softc *sc;
267 struct mii_data *mii;
271 mii = device_get_softc(sc->ale_miibus);
275 ifmr->ifm_status = mii->mii_media_status;
276 ifmr->ifm_active = mii->mii_media_active;
280 ale_mediachange(struct ifnet *ifp)
282 struct ale_softc *sc;
283 struct mii_data *mii;
284 struct mii_softc *miisc;
289 mii = device_get_softc(sc->ale_miibus);
290 if (mii->mii_instance != 0) {
291 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
292 mii_phy_reset(miisc);
294 error = mii_mediachg(mii);
301 ale_probe(device_t dev)
305 uint16_t vendor, devid;
307 vendor = pci_get_vendor(dev);
308 devid = pci_get_device(dev);
310 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) {
311 if (vendor == sp->ale_vendorid &&
312 devid == sp->ale_deviceid) {
313 device_set_desc(dev, sp->ale_name);
314 return (BUS_PROBE_DEFAULT);
323 ale_get_macaddr(struct ale_softc *sc)
328 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
329 if ((reg & SPI_VPD_ENB) != 0) {
331 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
334 if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
336 * PCI VPD capability found, let TWSI reload EEPROM.
337 * This will set ethernet address of controller.
339 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
340 TWSI_CTRL_SW_LD_START);
341 for (i = 100; i > 0; i--) {
343 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
344 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
348 device_printf(sc->ale_dev,
349 "reloading EEPROM timeout!\n");
352 device_printf(sc->ale_dev,
353 "PCI VPD capability not found!\n");
356 ea[0] = CSR_READ_4(sc, ALE_PAR0);
357 ea[1] = CSR_READ_4(sc, ALE_PAR1);
358 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
359 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
360 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
361 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
362 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
363 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
367 ale_phy_reset(struct ale_softc *sc)
370 /* Reset magic from Linux. */
371 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
372 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
373 GPHY_CTRL_PHY_PLL_ON);
375 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
376 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
377 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
380 #define ATPHY_DBG_ADDR 0x1D
381 #define ATPHY_DBG_DATA 0x1E
383 /* Enable hibernation mode. */
384 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
385 ATPHY_DBG_ADDR, 0x0B);
386 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
387 ATPHY_DBG_DATA, 0xBC00);
388 /* Set Class A/B for all modes. */
389 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
390 ATPHY_DBG_ADDR, 0x00);
391 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
392 ATPHY_DBG_DATA, 0x02EF);
393 /* Enable 10BT power saving. */
394 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
395 ATPHY_DBG_ADDR, 0x12);
396 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
397 ATPHY_DBG_DATA, 0x4C04);
398 /* Adjust 1000T power. */
399 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
400 ATPHY_DBG_ADDR, 0x04);
401 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
402 ATPHY_DBG_ADDR, 0x8BBB);
403 /* 10BT center tap voltage. */
404 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
405 ATPHY_DBG_ADDR, 0x05);
406 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
407 ATPHY_DBG_ADDR, 0x2C46);
409 #undef ATPHY_DBG_ADDR
410 #undef ATPHY_DBG_DATA
415 ale_attach(device_t dev)
417 struct ale_softc *sc;
420 int error, i, msic, msixc, pmc;
421 uint32_t rxf_len, txf_len;
424 sc = device_get_softc(dev);
427 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
429 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0);
430 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc);
431 TASK_INIT(&sc->ale_link_task, 0, ale_link_task, sc);
433 /* Map the device. */
434 pci_enable_busmaster(dev);
435 sc->ale_res_spec = ale_res_spec_mem;
436 sc->ale_irq_spec = ale_irq_spec_legacy;
437 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res);
439 device_printf(dev, "cannot allocate memory resources.\n");
443 /* Set PHY address. */
444 sc->ale_phyaddr = ALE_PHY_ADDR;
449 /* Reset the ethernet controller. */
452 /* Get PCI and chip id/revision. */
453 sc->ale_rev = pci_get_revid(dev);
454 if (sc->ale_rev >= 0xF0) {
455 /* L2E Rev. B. AR8114 */
456 sc->ale_flags |= ALE_FLAG_FASTETHER;
458 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
460 sc->ale_flags |= ALE_FLAG_JUMBO;
462 /* L2E Rev. A. AR8113 */
463 sc->ale_flags |= ALE_FLAG_FASTETHER;
467 * All known controllers seems to require 4 bytes alignment
468 * of Tx buffers to make Tx checksum offload with custom
469 * checksum generation method work.
471 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
473 * All known controllers seems to have issues on Rx checksum
474 * offload for fragmented IP datagrams.
476 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
478 * Don't use Tx CMB. It is known to cause RRS update failure
479 * under certain circumstances. Typical phenomenon of the
480 * issue would be unexpected sequence number encountered in
483 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
484 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
485 MASTER_CHIP_REV_SHIFT;
487 device_printf(dev, "PCI device revision : 0x%04x\n",
489 device_printf(dev, "Chip id/revision : 0x%04x\n",
492 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
493 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
495 * Uninitialized hardware returns an invalid chip id/revision
496 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
498 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
499 rxf_len == 0xFFFFFFF) {
500 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
501 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
506 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
508 /* Allocate IRQ resources. */
509 msixc = pci_msix_count(dev);
510 msic = pci_msi_count(dev);
512 device_printf(dev, "MSIX count : %d\n", msixc);
513 device_printf(dev, "MSI count : %d\n", msic);
516 /* Prefer MSIX over MSI. */
517 if (msix_disable == 0 || msi_disable == 0) {
518 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES &&
519 pci_alloc_msix(dev, &msixc) == 0) {
520 if (msic == ALE_MSIX_MESSAGES) {
521 device_printf(dev, "Using %d MSIX messages.\n",
523 sc->ale_flags |= ALE_FLAG_MSIX;
524 sc->ale_irq_spec = ale_irq_spec_msix;
526 pci_release_msi(dev);
528 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 &&
529 msic == ALE_MSI_MESSAGES &&
530 pci_alloc_msi(dev, &msic) == 0) {
531 if (msic == ALE_MSI_MESSAGES) {
532 device_printf(dev, "Using %d MSI messages.\n",
534 sc->ale_flags |= ALE_FLAG_MSI;
535 sc->ale_irq_spec = ale_irq_spec_msi;
537 pci_release_msi(dev);
541 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
543 device_printf(dev, "cannot allocate IRQ resources.\n");
547 /* Get DMA parameters from PCIe device control register. */
548 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
549 sc->ale_flags |= ALE_FLAG_PCIE;
550 burst = pci_read_config(dev, i + 0x08, 2);
551 /* Max read request size. */
552 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
553 DMA_CFG_RD_BURST_SHIFT;
554 /* Max payload size. */
555 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
556 DMA_CFG_WR_BURST_SHIFT;
558 device_printf(dev, "Read request size : %d bytes.\n",
559 128 << ((burst >> 12) & 0x07));
560 device_printf(dev, "TLP payload size : %d bytes.\n",
561 128 << ((burst >> 5) & 0x07));
564 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
565 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
568 /* Create device sysctl node. */
571 if ((error = ale_dma_alloc(sc) != 0))
574 /* Load station address. */
577 ifp = sc->ale_ifp = if_alloc(IFT_ETHER);
579 device_printf(dev, "cannot allocate ifnet structure.\n");
585 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
586 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
587 ifp->if_ioctl = ale_ioctl;
588 ifp->if_start = ale_start;
589 ifp->if_init = ale_init;
590 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1;
591 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
592 IFQ_SET_READY(&ifp->if_snd);
593 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4;
594 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
595 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
596 sc->ale_flags |= ALE_FLAG_PMCAP;
597 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
599 ifp->if_capenable = ifp->if_capabilities;
601 /* Set up MII bus. */
602 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
603 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,
606 device_printf(dev, "attaching PHYs failed\n");
610 ether_ifattach(ifp, sc->ale_eaddr);
612 /* VLAN capability setup. */
613 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
614 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
615 ifp->if_capenable = ifp->if_capabilities;
617 * Even though controllers supported by ale(3) have Rx checksum
618 * offload bug the workaround for fragmented frames seemed to
619 * work so far. However it seems Rx checksum offload does not
620 * work under certain conditions. So disable Rx checksum offload
621 * until I find more clue about it but allow users to override it.
623 ifp->if_capenable &= ~IFCAP_RXCSUM;
625 /* Tell the upper layer(s) we support long frames. */
626 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
628 /* Create local taskq. */
629 TASK_INIT(&sc->ale_tx_task, 1, ale_tx_task, ifp);
630 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK,
631 taskqueue_thread_enqueue, &sc->ale_tq);
632 if (sc->ale_tq == NULL) {
633 device_printf(dev, "could not create taskqueue.\n");
638 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq",
639 device_get_nameunit(sc->ale_dev));
641 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
642 msic = ALE_MSIX_MESSAGES;
643 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
644 msic = ALE_MSI_MESSAGES;
647 for (i = 0; i < msic; i++) {
648 error = bus_setup_intr(dev, sc->ale_irq[i],
649 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc,
650 &sc->ale_intrhand[i]);
655 device_printf(dev, "could not set up interrupt handler.\n");
656 taskqueue_free(sc->ale_tq);
670 ale_detach(device_t dev)
672 struct ale_softc *sc;
676 sc = device_get_softc(dev);
679 if (device_is_attached(dev)) {
681 sc->ale_flags |= ALE_FLAG_DETACH;
684 callout_drain(&sc->ale_tick_ch);
685 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
686 taskqueue_drain(sc->ale_tq, &sc->ale_tx_task);
687 taskqueue_drain(taskqueue_swi, &sc->ale_link_task);
691 if (sc->ale_tq != NULL) {
692 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
693 taskqueue_free(sc->ale_tq);
697 if (sc->ale_miibus != NULL) {
698 device_delete_child(dev, sc->ale_miibus);
699 sc->ale_miibus = NULL;
701 bus_generic_detach(dev);
709 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
710 msic = ALE_MSIX_MESSAGES;
711 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
712 msic = ALE_MSI_MESSAGES;
715 for (i = 0; i < msic; i++) {
716 if (sc->ale_intrhand[i] != NULL) {
717 bus_teardown_intr(dev, sc->ale_irq[i],
718 sc->ale_intrhand[i]);
719 sc->ale_intrhand[i] = NULL;
723 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq);
724 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0)
725 pci_release_msi(dev);
726 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res);
727 mtx_destroy(&sc->ale_mtx);
732 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
733 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
735 #if __FreeBSD_version > 800000
736 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
737 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
739 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
740 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
744 ale_sysctl_node(struct ale_softc *sc)
746 struct sysctl_ctx_list *ctx;
747 struct sysctl_oid_list *child, *parent;
748 struct sysctl_oid *tree;
749 struct ale_hw_stats *stats;
752 stats = &sc->ale_stats;
753 ctx = device_get_sysctl_ctx(sc->ale_dev);
754 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
756 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
757 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0,
758 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
759 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
760 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0,
761 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
762 /* Pull in device tunables. */
763 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
764 error = resource_int_value(device_get_name(sc->ale_dev),
765 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
767 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
768 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
769 device_printf(sc->ale_dev, "int_rx_mod value out of "
770 "range; using default: %d\n",
771 ALE_IM_RX_TIMER_DEFAULT);
772 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
775 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
776 error = resource_int_value(device_get_name(sc->ale_dev),
777 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
779 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
780 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
781 device_printf(sc->ale_dev, "int_tx_mod value out of "
782 "range; using default: %d\n",
783 ALE_IM_TX_TIMER_DEFAULT);
784 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
787 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
788 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0,
789 sysctl_hw_ale_proc_limit, "I",
790 "max number of Rx events to process");
791 /* Pull in device tunables. */
792 sc->ale_process_limit = ALE_PROC_DEFAULT;
793 error = resource_int_value(device_get_name(sc->ale_dev),
794 device_get_unit(sc->ale_dev), "process_limit",
795 &sc->ale_process_limit);
797 if (sc->ale_process_limit < ALE_PROC_MIN ||
798 sc->ale_process_limit > ALE_PROC_MAX) {
799 device_printf(sc->ale_dev,
800 "process_limit value out of range; "
801 "using default: %d\n", ALE_PROC_DEFAULT);
802 sc->ale_process_limit = ALE_PROC_DEFAULT;
806 /* Misc statistics. */
807 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
808 &stats->reset_brk_seq,
809 "Controller resets due to broken Rx sequnce number");
811 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
812 NULL, "ATE statistics");
813 parent = SYSCTL_CHILDREN(tree);
816 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
817 NULL, "Rx MAC statistics");
818 child = SYSCTL_CHILDREN(tree);
819 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
820 &stats->rx_frames, "Good frames");
821 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
822 &stats->rx_bcast_frames, "Good broadcast frames");
823 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
824 &stats->rx_mcast_frames, "Good multicast frames");
825 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
826 &stats->rx_pause_frames, "Pause control frames");
827 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
828 &stats->rx_control_frames, "Control frames");
829 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
830 &stats->rx_crcerrs, "CRC errors");
831 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
832 &stats->rx_lenerrs, "Frames with length mismatched");
833 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
834 &stats->rx_bytes, "Good octets");
835 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
836 &stats->rx_bcast_bytes, "Good broadcast octets");
837 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
838 &stats->rx_mcast_bytes, "Good multicast octets");
839 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
840 &stats->rx_runts, "Too short frames");
841 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
842 &stats->rx_fragments, "Fragmented frames");
843 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
844 &stats->rx_pkts_64, "64 bytes frames");
845 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
846 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
847 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
848 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
849 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
850 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
851 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
852 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
853 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
854 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
855 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
856 &stats->rx_pkts_1519_max, "1519 to max frames");
857 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
858 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
859 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
860 &stats->rx_fifo_oflows, "FIFO overflows");
861 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
862 &stats->rx_rrs_errs, "Return status write-back errors");
863 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
864 &stats->rx_alignerrs, "Alignment errors");
865 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
866 &stats->rx_pkts_filtered,
867 "Frames dropped due to address filtering");
870 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
871 NULL, "Tx MAC statistics");
872 child = SYSCTL_CHILDREN(tree);
873 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
874 &stats->tx_frames, "Good frames");
875 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
876 &stats->tx_bcast_frames, "Good broadcast frames");
877 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
878 &stats->tx_mcast_frames, "Good multicast frames");
879 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
880 &stats->tx_pause_frames, "Pause control frames");
881 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
882 &stats->tx_control_frames, "Control frames");
883 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
884 &stats->tx_excess_defer, "Frames with excessive derferrals");
885 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
886 &stats->tx_excess_defer, "Frames with derferrals");
887 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
888 &stats->tx_bytes, "Good octets");
889 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
890 &stats->tx_bcast_bytes, "Good broadcast octets");
891 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
892 &stats->tx_mcast_bytes, "Good multicast octets");
893 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
894 &stats->tx_pkts_64, "64 bytes frames");
895 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
896 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
897 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
898 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
899 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
900 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
901 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
902 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
903 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
904 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
905 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
906 &stats->tx_pkts_1519_max, "1519 to max frames");
907 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
908 &stats->tx_single_colls, "Single collisions");
909 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
910 &stats->tx_multi_colls, "Multiple collisions");
911 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
912 &stats->tx_late_colls, "Late collisions");
913 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
914 &stats->tx_excess_colls, "Excessive collisions");
915 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
916 &stats->tx_abort, "Aborted frames due to Excessive collisions");
917 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
918 &stats->tx_underrun, "FIFO underruns");
919 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
920 &stats->tx_desc_underrun, "Descriptor write-back errors");
921 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
922 &stats->tx_lenerrs, "Frames with length mismatched");
923 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
924 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
927 #undef ALE_SYSCTL_STAT_ADD32
928 #undef ALE_SYSCTL_STAT_ADD64
930 struct ale_dmamap_arg {
931 bus_addr_t ale_busaddr;
935 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
937 struct ale_dmamap_arg *ctx;
942 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
944 ctx = (struct ale_dmamap_arg *)arg;
945 ctx->ale_busaddr = segs[0].ds_addr;
949 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
950 * which specifies high address region of DMA blocks. Therefore these
951 * blocks should have the same high address of given 4GB address
952 * space(i.e. crossing 4GB boundary is not allowed).
955 ale_check_boundary(struct ale_softc *sc)
957 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
958 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
960 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
962 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
964 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
965 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
966 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
967 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
969 if ((ALE_ADDR_HI(tx_ring_end) !=
970 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
971 (ALE_ADDR_HI(rx_page_end[0]) !=
972 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
973 (ALE_ADDR_HI(rx_page_end[1]) !=
974 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
975 (ALE_ADDR_HI(tx_cmb_end) !=
976 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
977 (ALE_ADDR_HI(rx_cmb_end[0]) !=
978 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
979 (ALE_ADDR_HI(rx_cmb_end[1]) !=
980 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
983 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
984 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
985 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
986 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
987 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
994 ale_dma_alloc(struct ale_softc *sc)
996 struct ale_txdesc *txd;
998 struct ale_dmamap_arg ctx;
999 int error, guard_size, i;
1001 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
1002 guard_size = ALE_JUMBO_FRAMELEN;
1004 guard_size = ALE_MAX_FRAMELEN;
1005 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
1007 lowaddr = BUS_SPACE_MAXADDR;
1009 /* Create parent DMA tag. */
1010 error = bus_dma_tag_create(
1011 bus_get_dma_tag(sc->ale_dev), /* parent */
1012 1, 0, /* alignment, boundary */
1013 lowaddr, /* lowaddr */
1014 BUS_SPACE_MAXADDR, /* highaddr */
1015 NULL, NULL, /* filter, filterarg */
1016 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1018 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1020 NULL, NULL, /* lockfunc, lockarg */
1021 &sc->ale_cdata.ale_parent_tag);
1023 device_printf(sc->ale_dev,
1024 "could not create parent DMA tag.\n");
1028 /* Create DMA tag for Tx descriptor ring. */
1029 error = bus_dma_tag_create(
1030 sc->ale_cdata.ale_parent_tag, /* parent */
1031 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
1032 BUS_SPACE_MAXADDR, /* lowaddr */
1033 BUS_SPACE_MAXADDR, /* highaddr */
1034 NULL, NULL, /* filter, filterarg */
1035 ALE_TX_RING_SZ, /* maxsize */
1037 ALE_TX_RING_SZ, /* maxsegsize */
1039 NULL, NULL, /* lockfunc, lockarg */
1040 &sc->ale_cdata.ale_tx_ring_tag);
1042 device_printf(sc->ale_dev,
1043 "could not create Tx ring DMA tag.\n");
1047 /* Create DMA tag for Rx pages. */
1048 for (i = 0; i < ALE_RX_PAGES; i++) {
1049 error = bus_dma_tag_create(
1050 sc->ale_cdata.ale_parent_tag, /* parent */
1051 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
1052 BUS_SPACE_MAXADDR, /* lowaddr */
1053 BUS_SPACE_MAXADDR, /* highaddr */
1054 NULL, NULL, /* filter, filterarg */
1055 sc->ale_pagesize, /* maxsize */
1057 sc->ale_pagesize, /* maxsegsize */
1059 NULL, NULL, /* lockfunc, lockarg */
1060 &sc->ale_cdata.ale_rx_page[i].page_tag);
1062 device_printf(sc->ale_dev,
1063 "could not create Rx page %d DMA tag.\n", i);
1068 /* Create DMA tag for Tx coalescing message block. */
1069 error = bus_dma_tag_create(
1070 sc->ale_cdata.ale_parent_tag, /* parent */
1071 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1072 BUS_SPACE_MAXADDR, /* lowaddr */
1073 BUS_SPACE_MAXADDR, /* highaddr */
1074 NULL, NULL, /* filter, filterarg */
1075 ALE_TX_CMB_SZ, /* maxsize */
1077 ALE_TX_CMB_SZ, /* maxsegsize */
1079 NULL, NULL, /* lockfunc, lockarg */
1080 &sc->ale_cdata.ale_tx_cmb_tag);
1082 device_printf(sc->ale_dev,
1083 "could not create Tx CMB DMA tag.\n");
1087 /* Create DMA tag for Rx coalescing message block. */
1088 for (i = 0; i < ALE_RX_PAGES; i++) {
1089 error = bus_dma_tag_create(
1090 sc->ale_cdata.ale_parent_tag, /* parent */
1091 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1092 BUS_SPACE_MAXADDR, /* lowaddr */
1093 BUS_SPACE_MAXADDR, /* highaddr */
1094 NULL, NULL, /* filter, filterarg */
1095 ALE_RX_CMB_SZ, /* maxsize */
1097 ALE_RX_CMB_SZ, /* maxsegsize */
1099 NULL, NULL, /* lockfunc, lockarg */
1100 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1102 device_printf(sc->ale_dev,
1103 "could not create Rx page %d CMB DMA tag.\n", i);
1108 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1109 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1110 (void **)&sc->ale_cdata.ale_tx_ring,
1111 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1112 &sc->ale_cdata.ale_tx_ring_map);
1114 device_printf(sc->ale_dev,
1115 "could not allocate DMA'able memory for Tx ring.\n");
1118 ctx.ale_busaddr = 0;
1119 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1120 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1121 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1122 if (error != 0 || ctx.ale_busaddr == 0) {
1123 device_printf(sc->ale_dev,
1124 "could not load DMA'able memory for Tx ring.\n");
1127 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1130 for (i = 0; i < ALE_RX_PAGES; i++) {
1131 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1132 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1133 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1134 &sc->ale_cdata.ale_rx_page[i].page_map);
1136 device_printf(sc->ale_dev,
1137 "could not allocate DMA'able memory for "
1138 "Rx page %d.\n", i);
1141 ctx.ale_busaddr = 0;
1142 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1143 sc->ale_cdata.ale_rx_page[i].page_map,
1144 sc->ale_cdata.ale_rx_page[i].page_addr,
1145 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1146 if (error != 0 || ctx.ale_busaddr == 0) {
1147 device_printf(sc->ale_dev,
1148 "could not load DMA'able memory for "
1149 "Rx page %d.\n", i);
1152 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1156 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1157 (void **)&sc->ale_cdata.ale_tx_cmb,
1158 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1159 &sc->ale_cdata.ale_tx_cmb_map);
1161 device_printf(sc->ale_dev,
1162 "could not allocate DMA'able memory for Tx CMB.\n");
1165 ctx.ale_busaddr = 0;
1166 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1167 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1168 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1169 if (error != 0 || ctx.ale_busaddr == 0) {
1170 device_printf(sc->ale_dev,
1171 "could not load DMA'able memory for Tx CMB.\n");
1174 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1177 for (i = 0; i < ALE_RX_PAGES; i++) {
1178 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1179 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1180 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1181 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1183 device_printf(sc->ale_dev, "could not allocate "
1184 "DMA'able memory for Rx page %d CMB.\n", i);
1187 ctx.ale_busaddr = 0;
1188 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1189 sc->ale_cdata.ale_rx_page[i].cmb_map,
1190 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1191 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1192 if (error != 0 || ctx.ale_busaddr == 0) {
1193 device_printf(sc->ale_dev, "could not load DMA'able "
1194 "memory for Rx page %d CMB.\n", i);
1197 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1201 * Tx descriptors/RXF0/CMB DMA blocks share the same
1202 * high address region of 64bit DMA address space.
1204 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1205 (error = ale_check_boundary(sc)) != 0) {
1206 device_printf(sc->ale_dev, "4GB boundary crossed, "
1207 "switching to 32bit DMA addressing mode.\n");
1210 * Limit max allowable DMA address space to 32bit
1213 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1218 * Create Tx buffer parent tag.
1219 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1220 * needs separate parent DMA tag as parent DMA address space
1221 * could be restricted to be within 32bit address space by
1222 * 4GB boundary crossing.
1224 error = bus_dma_tag_create(
1225 bus_get_dma_tag(sc->ale_dev), /* parent */
1226 1, 0, /* alignment, boundary */
1227 BUS_SPACE_MAXADDR, /* lowaddr */
1228 BUS_SPACE_MAXADDR, /* highaddr */
1229 NULL, NULL, /* filter, filterarg */
1230 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1232 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1234 NULL, NULL, /* lockfunc, lockarg */
1235 &sc->ale_cdata.ale_buffer_tag);
1237 device_printf(sc->ale_dev,
1238 "could not create parent buffer DMA tag.\n");
1242 /* Create DMA tag for Tx buffers. */
1243 error = bus_dma_tag_create(
1244 sc->ale_cdata.ale_buffer_tag, /* parent */
1245 1, 0, /* alignment, boundary */
1246 BUS_SPACE_MAXADDR, /* lowaddr */
1247 BUS_SPACE_MAXADDR, /* highaddr */
1248 NULL, NULL, /* filter, filterarg */
1249 ALE_TSO_MAXSIZE, /* maxsize */
1250 ALE_MAXTXSEGS, /* nsegments */
1251 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1253 NULL, NULL, /* lockfunc, lockarg */
1254 &sc->ale_cdata.ale_tx_tag);
1256 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1260 /* Create DMA maps for Tx buffers. */
1261 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1262 txd = &sc->ale_cdata.ale_txdesc[i];
1264 txd->tx_dmamap = NULL;
1265 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1268 device_printf(sc->ale_dev,
1269 "could not create Tx dmamap.\n");
1279 ale_dma_free(struct ale_softc *sc)
1281 struct ale_txdesc *txd;
1285 if (sc->ale_cdata.ale_tx_tag != NULL) {
1286 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1287 txd = &sc->ale_cdata.ale_txdesc[i];
1288 if (txd->tx_dmamap != NULL) {
1289 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1291 txd->tx_dmamap = NULL;
1294 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1295 sc->ale_cdata.ale_tx_tag = NULL;
1297 /* Tx descriptor ring. */
1298 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1299 if (sc->ale_cdata.ale_tx_ring_map != NULL)
1300 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1301 sc->ale_cdata.ale_tx_ring_map);
1302 if (sc->ale_cdata.ale_tx_ring_map != NULL &&
1303 sc->ale_cdata.ale_tx_ring != NULL)
1304 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1305 sc->ale_cdata.ale_tx_ring,
1306 sc->ale_cdata.ale_tx_ring_map);
1307 sc->ale_cdata.ale_tx_ring = NULL;
1308 sc->ale_cdata.ale_tx_ring_map = NULL;
1309 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1310 sc->ale_cdata.ale_tx_ring_tag = NULL;
1312 /* Rx page block. */
1313 for (i = 0; i < ALE_RX_PAGES; i++) {
1314 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1315 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
1317 sc->ale_cdata.ale_rx_page[i].page_tag,
1318 sc->ale_cdata.ale_rx_page[i].page_map);
1319 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
1320 sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1322 sc->ale_cdata.ale_rx_page[i].page_tag,
1323 sc->ale_cdata.ale_rx_page[i].page_addr,
1324 sc->ale_cdata.ale_rx_page[i].page_map);
1325 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1326 sc->ale_cdata.ale_rx_page[i].page_map = NULL;
1327 bus_dma_tag_destroy(
1328 sc->ale_cdata.ale_rx_page[i].page_tag);
1329 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1333 for (i = 0; i < ALE_RX_PAGES; i++) {
1334 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1335 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
1337 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1338 sc->ale_cdata.ale_rx_page[i].cmb_map);
1339 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
1340 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1342 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1343 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1344 sc->ale_cdata.ale_rx_page[i].cmb_map);
1345 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1346 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
1347 bus_dma_tag_destroy(
1348 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1349 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1353 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1354 if (sc->ale_cdata.ale_tx_cmb_map != NULL)
1355 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1356 sc->ale_cdata.ale_tx_cmb_map);
1357 if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
1358 sc->ale_cdata.ale_tx_cmb != NULL)
1359 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1360 sc->ale_cdata.ale_tx_cmb,
1361 sc->ale_cdata.ale_tx_cmb_map);
1362 sc->ale_cdata.ale_tx_cmb = NULL;
1363 sc->ale_cdata.ale_tx_cmb_map = NULL;
1364 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1365 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1367 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1368 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1369 sc->ale_cdata.ale_buffer_tag = NULL;
1371 if (sc->ale_cdata.ale_parent_tag != NULL) {
1372 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1373 sc->ale_cdata.ale_parent_tag = NULL;
1378 ale_shutdown(device_t dev)
1381 return (ale_suspend(dev));
1385 * Note, this driver resets the link speed to 10/100Mbps by
1386 * restarting auto-negotiation in suspend/shutdown phase but we
1387 * don't know whether that auto-negotiation would succeed or not
1388 * as driver has no control after powering off/suspend operation.
1389 * If the renegotiation fail WOL may not work. Running at 1Gbps
1390 * will draw more power than 375mA at 3.3V which is specified in
1391 * PCI specification and that would result in complete
1392 * shutdowning power to ethernet controller.
1395 * Save current negotiated media speed/duplex/flow-control to
1396 * softc and restore the same link again after resuming. PHY
1397 * handling such as power down/resetting to 100Mbps may be better
1398 * handled in suspend method in phy driver.
1401 ale_setlinkspeed(struct ale_softc *sc)
1403 struct mii_data *mii;
1406 mii = device_get_softc(sc->ale_miibus);
1409 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1410 (IFM_ACTIVE | IFM_AVALID)) {
1411 switch IFM_SUBTYPE(mii->mii_media_active) {
1422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1423 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1424 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1425 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1426 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1430 * Poll link state until ale(4) get a 10/100Mbps link.
1432 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1434 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1435 == (IFM_ACTIVE | IFM_AVALID)) {
1436 switch (IFM_SUBTYPE(
1437 mii->mii_media_active)) {
1447 pause("alelnk", hz);
1450 if (i == MII_ANEGTICKS_GIGE)
1451 device_printf(sc->ale_dev,
1452 "establishing a link failed, WOL may not work!");
1455 * No link, force MAC to have 100Mbps, full-duplex link.
1456 * This is the last resort and may/may not work.
1458 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1459 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1464 ale_setwol(struct ale_softc *sc)
1471 ALE_LOCK_ASSERT(sc);
1473 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1475 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1476 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1477 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1478 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1479 /* Force PHY power down. */
1480 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1481 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1482 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1483 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1484 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1489 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1490 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1491 ale_setlinkspeed(sc);
1495 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1496 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1497 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1498 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1499 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1501 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1502 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1503 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1504 reg |= MAC_CFG_RX_ENB;
1505 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1507 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1508 /* WOL disabled, PHY power down. */
1509 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1510 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1511 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1512 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1513 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1514 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1515 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1516 GPHY_CTRL_PWDOWN_HW);
1519 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1520 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1521 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1522 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1523 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1527 ale_suspend(device_t dev)
1529 struct ale_softc *sc;
1531 sc = device_get_softc(dev);
1542 ale_resume(device_t dev)
1544 struct ale_softc *sc;
1549 sc = device_get_softc(dev);
1552 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1553 /* Disable PME and clear PME status. */
1554 pmstat = pci_read_config(sc->ale_dev,
1555 pmc + PCIR_POWER_STATUS, 2);
1556 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1557 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1558 pci_write_config(sc->ale_dev,
1559 pmc + PCIR_POWER_STATUS, pmstat, 2);
1565 if ((ifp->if_flags & IFF_UP) != 0) {
1566 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1567 ale_init_locked(sc);
1575 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1577 struct ale_txdesc *txd, *txd_last;
1578 struct tx_desc *desc;
1582 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1584 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1585 int error, i, nsegs, prod, si;
1587 ALE_LOCK_ASSERT(sc);
1589 M_ASSERTPKTHDR((*m_head));
1596 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1598 * AR81xx requires offset of TCP/UDP payload in its Tx
1599 * descriptor to perform hardware Tx checksum offload.
1600 * Additionally, TSO requires IP/TCP header size and
1601 * modification of IP/TCP header in order to make TSO
1602 * engine work. This kind of operation takes many CPU
1603 * cycles on FreeBSD so fast host CPU is required to
1604 * get smooth TSO performance.
1606 struct ether_header *eh;
1608 if (M_WRITABLE(m) == 0) {
1609 /* Get a writable copy. */
1610 m = m_dup(*m_head, M_DONTWAIT);
1611 /* Release original mbufs. */
1621 * Buggy-controller requires 4 byte aligned Tx buffer
1622 * to make custom checksum offload work.
1624 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 &&
1625 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 &&
1626 (mtod(m, intptr_t) & 3) != 0) {
1627 m = m_defrag(*m_head, M_DONTWAIT);
1635 ip_off = sizeof(struct ether_header);
1636 m = m_pullup(m, ip_off);
1641 eh = mtod(m, struct ether_header *);
1643 * Check if hardware VLAN insertion is off.
1644 * Additional check for LLC/SNAP frame?
1646 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1647 ip_off = sizeof(struct ether_vlan_header);
1648 m = m_pullup(m, ip_off);
1654 m = m_pullup(m, ip_off + sizeof(struct ip));
1659 ip = (struct ip *)(mtod(m, char *) + ip_off);
1660 poff = ip_off + (ip->ip_hl << 2);
1661 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1664 * AR81xx requires the first descriptor should
1665 * not include any TCP playload for TSO case.
1666 * (i.e. ethernet header + IP + TCP header only)
1667 * m_pullup(9) above will ensure this too.
1668 * However it's not correct if the first mbuf
1669 * of the chain does not use cluster.
1671 m = m_pullup(m, poff + sizeof(struct tcphdr));
1676 ip = (struct ip *)(mtod(m, char *) + ip_off);
1677 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1678 m = m_pullup(m, poff + (tcp->th_off << 2));
1684 * AR81xx requires IP/TCP header size and offset as
1685 * well as TCP pseudo checksum which complicates
1686 * TSO configuration. I guess this comes from the
1687 * adherence to Microsoft NDIS Large Send
1688 * specification which requires insertion of
1689 * pseudo checksum by upper stack. The pseudo
1690 * checksum that NDIS refers to doesn't include
1691 * TCP payload length so ale(4) should recompute
1692 * the pseudo checksum here. Hopefully this wouldn't
1693 * be much burden on modern CPUs.
1694 * Reset IP checksum and recompute TCP pseudo
1695 * checksum as NDIS specification said.
1698 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1699 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1704 si = prod = sc->ale_cdata.ale_tx_prod;
1705 txd = &sc->ale_cdata.ale_txdesc[prod];
1707 map = txd->tx_dmamap;
1709 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1710 *m_head, txsegs, &nsegs, 0);
1711 if (error == EFBIG) {
1712 m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS);
1719 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1720 *m_head, txsegs, &nsegs, 0);
1726 } else if (error != 0)
1734 /* Check descriptor overrun. */
1735 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) {
1736 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1739 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1742 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1743 /* Request TSO and set MSS. */
1744 cflags |= ALE_TD_TSO;
1745 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT);
1746 /* Set IP/TCP header size. */
1747 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT;
1748 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT;
1749 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1751 * AR81xx supports Tx custom checksum offload feature
1752 * that offloads single 16bit checksum computation.
1753 * So you can choose one among IP, TCP and UDP.
1754 * Normally driver sets checksum start/insertion
1755 * position from the information of TCP/UDP frame as
1756 * TCP/UDP checksum takes more time than that of IP.
1757 * However it seems that custom checksum offload
1758 * requires 4 bytes aligned Tx buffers due to hardware
1760 * AR81xx also supports explicit Tx checksum computation
1761 * if it is told that the size of IP header and TCP
1762 * header(for UDP, the header size does not matter
1763 * because it's fixed length). However with this scheme
1764 * TSO does not work so you have to choose one either
1765 * TSO or explicit Tx checksum offload. I chosen TSO
1766 * plus custom checksum offload with work-around which
1767 * will cover most common usage for this consumer
1768 * ethernet controller. The work-around takes a lot of
1769 * CPU cycles if Tx buffer is not aligned on 4 bytes
1772 cflags |= ALE_TD_CXSUM;
1773 /* Set checksum start offset. */
1774 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1775 /* Set checksum insertion position of TCP/UDP. */
1776 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1777 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1780 /* Configure VLAN hardware tag insertion. */
1781 if ((m->m_flags & M_VLANTAG) != 0) {
1782 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1783 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1784 cflags |= ALE_TD_INSERT_VLAN_TAG;
1788 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1790 * Make sure the first fragment contains
1791 * only ethernet and IP/TCP header with options.
1793 hdrlen = poff + (tcp->th_off << 2);
1794 desc = &sc->ale_cdata.ale_tx_ring[prod];
1795 desc->addr = htole64(txsegs[i].ds_addr);
1796 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag);
1797 desc->flags = htole32(cflags);
1798 sc->ale_cdata.ale_tx_cnt++;
1799 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1800 if (m->m_len - hdrlen > 0) {
1801 /* Handle remaining payload of the first fragment. */
1802 desc = &sc->ale_cdata.ale_tx_ring[prod];
1803 desc->addr = htole64(txsegs[i].ds_addr + hdrlen);
1804 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) |
1806 desc->flags = htole32(cflags);
1807 sc->ale_cdata.ale_tx_cnt++;
1808 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1812 for (; i < nsegs; i++) {
1813 desc = &sc->ale_cdata.ale_tx_ring[prod];
1814 desc->addr = htole64(txsegs[i].ds_addr);
1815 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1816 desc->flags = htole32(cflags);
1817 sc->ale_cdata.ale_tx_cnt++;
1818 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1820 /* Update producer index. */
1821 sc->ale_cdata.ale_tx_prod = prod;
1822 /* Set TSO header on the first descriptor. */
1823 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1824 desc = &sc->ale_cdata.ale_tx_ring[si];
1825 desc->flags |= htole32(ALE_TD_TSO_HDR);
1828 /* Finally set EOP on the last descriptor. */
1829 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1830 desc = &sc->ale_cdata.ale_tx_ring[prod];
1831 desc->flags |= htole32(ALE_TD_EOP);
1833 /* Swap dmamap of the first and the last. */
1834 txd = &sc->ale_cdata.ale_txdesc[prod];
1835 map = txd_last->tx_dmamap;
1836 txd_last->tx_dmamap = txd->tx_dmamap;
1837 txd->tx_dmamap = map;
1840 /* Sync descriptors. */
1841 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1842 sc->ale_cdata.ale_tx_ring_map,
1843 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1849 ale_tx_task(void *arg, int pending)
1853 ifp = (struct ifnet *)arg;
1858 ale_start(struct ifnet *ifp)
1860 struct ale_softc *sc;
1861 struct mbuf *m_head;
1868 /* Reclaim transmitted frames. */
1869 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1872 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1873 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) {
1878 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1879 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1883 * Pack the data into the transmit ring. If we
1884 * don't have room, set the OACTIVE flag and wait
1885 * for the NIC to drain the ring.
1887 if (ale_encap(sc, &m_head)) {
1890 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1891 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1897 * If there's a BPF listener, bounce a copy of this frame
1900 ETHER_BPF_MTAP(ifp, m_head);
1905 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1906 sc->ale_cdata.ale_tx_prod);
1907 /* Set a timeout in case the chip goes out to lunch. */
1908 sc->ale_watchdog_timer = ALE_TX_TIMEOUT;
1915 ale_watchdog(struct ale_softc *sc)
1919 ALE_LOCK_ASSERT(sc);
1921 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer)
1925 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1926 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n");
1928 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1929 ale_init_locked(sc);
1932 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n");
1934 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1935 ale_init_locked(sc);
1936 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1937 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task);
1941 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1943 struct ale_softc *sc;
1945 struct mii_data *mii;
1949 ifr = (struct ifreq *)data;
1953 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1954 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1955 ifr->ifr_mtu > ETHERMTU))
1957 else if (ifp->if_mtu != ifr->ifr_mtu) {
1959 ifp->if_mtu = ifr->ifr_mtu;
1960 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1961 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1962 ale_init_locked(sc);
1969 if ((ifp->if_flags & IFF_UP) != 0) {
1970 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1971 if (((ifp->if_flags ^ sc->ale_if_flags)
1972 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1975 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0)
1976 ale_init_locked(sc);
1979 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1982 sc->ale_if_flags = ifp->if_flags;
1988 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1994 mii = device_get_softc(sc->ale_miibus);
1995 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1999 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2000 if ((mask & IFCAP_TXCSUM) != 0 &&
2001 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2002 ifp->if_capenable ^= IFCAP_TXCSUM;
2003 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2004 ifp->if_hwassist |= ALE_CSUM_FEATURES;
2006 ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
2008 if ((mask & IFCAP_RXCSUM) != 0 &&
2009 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
2010 ifp->if_capenable ^= IFCAP_RXCSUM;
2011 if ((mask & IFCAP_TSO4) != 0 &&
2012 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2013 ifp->if_capenable ^= IFCAP_TSO4;
2014 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2015 ifp->if_hwassist |= CSUM_TSO;
2017 ifp->if_hwassist &= ~CSUM_TSO;
2020 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2021 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2022 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2023 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2024 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2025 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2026 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2027 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2028 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2029 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2030 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2031 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2032 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2033 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2034 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2035 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2036 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
2040 VLAN_CAPABILITIES(ifp);
2043 error = ether_ioctl(ifp, cmd, data);
2051 ale_mac_config(struct ale_softc *sc)
2053 struct mii_data *mii;
2056 ALE_LOCK_ASSERT(sc);
2058 mii = device_get_softc(sc->ale_miibus);
2059 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2060 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2061 MAC_CFG_SPEED_MASK);
2062 /* Reprogram MAC with resolved speed/duplex. */
2063 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2066 reg |= MAC_CFG_SPEED_10_100;
2069 reg |= MAC_CFG_SPEED_1000;
2072 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2073 reg |= MAC_CFG_FULL_DUPLEX;
2075 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2076 reg |= MAC_CFG_TX_FC;
2077 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2078 reg |= MAC_CFG_RX_FC;
2081 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2085 ale_link_task(void *arg, int pending)
2087 struct ale_softc *sc;
2088 struct mii_data *mii;
2092 sc = (struct ale_softc *)arg;
2095 mii = device_get_softc(sc->ale_miibus);
2097 if (mii == NULL || ifp == NULL ||
2098 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2103 sc->ale_flags &= ~ALE_FLAG_LINK;
2104 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2105 (IFM_ACTIVE | IFM_AVALID)) {
2106 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2109 sc->ale_flags |= ALE_FLAG_LINK;
2112 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
2113 sc->ale_flags |= ALE_FLAG_LINK;
2120 /* Stop Rx/Tx MACs. */
2123 /* Program MACs with resolved speed/duplex/flow-control. */
2124 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
2126 /* Reenable Tx/Rx MACs. */
2127 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2128 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2129 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2136 ale_stats_clear(struct ale_softc *sc)
2142 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2143 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2144 i += sizeof(uint32_t);
2146 /* Read Tx statistics. */
2147 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2148 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2149 i += sizeof(uint32_t);
2154 ale_stats_update(struct ale_softc *sc)
2156 struct ale_hw_stats *stat;
2157 struct smb sb, *smb;
2162 ALE_LOCK_ASSERT(sc);
2165 stat = &sc->ale_stats;
2168 /* Read Rx statistics. */
2169 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2170 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2171 i += sizeof(uint32_t);
2173 /* Read Tx statistics. */
2174 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2175 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2176 i += sizeof(uint32_t);
2180 stat->rx_frames += smb->rx_frames;
2181 stat->rx_bcast_frames += smb->rx_bcast_frames;
2182 stat->rx_mcast_frames += smb->rx_mcast_frames;
2183 stat->rx_pause_frames += smb->rx_pause_frames;
2184 stat->rx_control_frames += smb->rx_control_frames;
2185 stat->rx_crcerrs += smb->rx_crcerrs;
2186 stat->rx_lenerrs += smb->rx_lenerrs;
2187 stat->rx_bytes += smb->rx_bytes;
2188 stat->rx_runts += smb->rx_runts;
2189 stat->rx_fragments += smb->rx_fragments;
2190 stat->rx_pkts_64 += smb->rx_pkts_64;
2191 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2192 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2193 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2194 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2195 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2196 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2197 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2198 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2199 stat->rx_rrs_errs += smb->rx_rrs_errs;
2200 stat->rx_alignerrs += smb->rx_alignerrs;
2201 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2202 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2203 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2206 stat->tx_frames += smb->tx_frames;
2207 stat->tx_bcast_frames += smb->tx_bcast_frames;
2208 stat->tx_mcast_frames += smb->tx_mcast_frames;
2209 stat->tx_pause_frames += smb->tx_pause_frames;
2210 stat->tx_excess_defer += smb->tx_excess_defer;
2211 stat->tx_control_frames += smb->tx_control_frames;
2212 stat->tx_deferred += smb->tx_deferred;
2213 stat->tx_bytes += smb->tx_bytes;
2214 stat->tx_pkts_64 += smb->tx_pkts_64;
2215 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2216 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2217 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2218 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2219 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2220 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2221 stat->tx_single_colls += smb->tx_single_colls;
2222 stat->tx_multi_colls += smb->tx_multi_colls;
2223 stat->tx_late_colls += smb->tx_late_colls;
2224 stat->tx_excess_colls += smb->tx_excess_colls;
2225 stat->tx_abort += smb->tx_abort;
2226 stat->tx_underrun += smb->tx_underrun;
2227 stat->tx_desc_underrun += smb->tx_desc_underrun;
2228 stat->tx_lenerrs += smb->tx_lenerrs;
2229 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2230 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2231 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2233 /* Update counters in ifnet. */
2234 ifp->if_opackets += smb->tx_frames;
2236 ifp->if_collisions += smb->tx_single_colls +
2237 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2238 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
2242 * tx_pkts_truncated counter looks suspicious. It constantly
2243 * increments with no sign of Tx errors. This may indicate
2244 * the counter name is not correct one so I've removed the
2245 * counter in output errors.
2247 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
2250 ifp->if_ipackets += smb->rx_frames;
2252 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2253 smb->rx_runts + smb->rx_pkts_truncated +
2254 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2261 struct ale_softc *sc;
2264 sc = (struct ale_softc *)arg;
2266 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2267 if ((status & ALE_INTRS) == 0)
2268 return (FILTER_STRAY);
2269 /* Disable interrupts. */
2270 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2271 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2273 return (FILTER_HANDLED);
2277 ale_int_task(void *arg, int pending)
2279 struct ale_softc *sc;
2284 sc = (struct ale_softc *)arg;
2286 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2287 more = atomic_readandclear_int(&sc->ale_morework);
2289 status |= INTR_RX_PKT;
2290 if ((status & ALE_INTRS) == 0)
2293 /* Acknowledge interrupts but still disable interrupts. */
2294 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2298 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2299 more = ale_rxeof(sc, sc->ale_process_limit);
2301 atomic_set_int(&sc->ale_morework, 1);
2302 else if (more == EIO) {
2304 sc->ale_stats.reset_brk_seq++;
2305 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2306 ale_init_locked(sc);
2311 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2312 if ((status & INTR_DMA_RD_TO_RST) != 0)
2313 device_printf(sc->ale_dev,
2314 "DMA read error! -- resetting\n");
2315 if ((status & INTR_DMA_WR_TO_RST) != 0)
2316 device_printf(sc->ale_dev,
2317 "DMA write error! -- resetting\n");
2319 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2320 ale_init_locked(sc);
2324 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2325 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task);
2328 if (more == EAGAIN ||
2329 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {
2330 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2335 /* Re-enable interrupts. */
2336 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2340 ale_txeof(struct ale_softc *sc)
2343 struct ale_txdesc *txd;
2344 uint32_t cons, prod;
2347 ALE_LOCK_ASSERT(sc);
2351 if (sc->ale_cdata.ale_tx_cnt == 0)
2354 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2355 sc->ale_cdata.ale_tx_ring_map,
2356 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2357 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2358 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2359 sc->ale_cdata.ale_tx_cmb_map,
2360 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2361 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2363 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2364 cons = sc->ale_cdata.ale_tx_cons;
2366 * Go through our Tx list and free mbufs for those
2367 * frames which have been transmitted.
2369 for (prog = 0; cons != prod; prog++,
2370 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2371 if (sc->ale_cdata.ale_tx_cnt <= 0)
2374 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2375 sc->ale_cdata.ale_tx_cnt--;
2376 txd = &sc->ale_cdata.ale_txdesc[cons];
2377 if (txd->tx_m != NULL) {
2378 /* Reclaim transmitted mbufs. */
2379 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2380 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2381 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2389 sc->ale_cdata.ale_tx_cons = cons;
2391 * Unarm watchdog timer only when there is no pending
2392 * Tx descriptors in queue.
2394 if (sc->ale_cdata.ale_tx_cnt == 0)
2395 sc->ale_watchdog_timer = 0;
2400 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2401 uint32_t length, uint32_t *prod)
2403 struct ale_rx_page *rx_page;
2406 /* Update consumer position. */
2407 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2409 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2411 * End of Rx page reached, let hardware reuse
2415 *rx_page->cmb_addr = 0;
2416 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2417 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2418 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2420 /* Switch to alternate Rx page. */
2421 sc->ale_cdata.ale_rx_curp ^= 1;
2423 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2424 /* Page flipped, sync CMB and Rx page. */
2425 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2426 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2427 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2428 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2429 /* Sync completed, cache updated producer index. */
2430 *prod = *rx_page->cmb_addr;
2436 * It seems that AR81xx controller can compute partial checksum.
2437 * The partial checksum value can be used to accelerate checksum
2438 * computation for fragmented TCP/UDP packets. Upper network stack
2439 * already takes advantage of the partial checksum value in IP
2440 * reassembly stage. But I'm not sure the correctness of the
2441 * partial hardware checksum assistance due to lack of data sheet.
2442 * In addition, the Rx feature of controller that requires copying
2443 * for every frames effectively nullifies one of most nice offload
2444 * capability of controller.
2447 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2454 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2455 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2456 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2458 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2459 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2460 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2461 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2462 m->m_pkthdr.csum_flags |=
2463 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2464 m->m_pkthdr.csum_data = 0xffff;
2467 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2468 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2469 p = mtod(m, char *);
2471 if ((status & ALE_RD_802_3) != 0)
2472 p += LLC_SNAPFRAMELEN;
2473 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2474 (status & ALE_RD_VLAN) != 0)
2475 p += ETHER_VLAN_ENCAP_LEN;
2476 ip = (struct ip *)p;
2477 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2479 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2481 m->m_pkthdr.csum_data = 0xffff;
2485 * Don't mark bad checksum for TCP/UDP frames
2486 * as fragmented frames may always have set
2487 * bad checksummed bit of frame status.
2491 /* Process received frames. */
2493 ale_rxeof(struct ale_softc *sc, int count)
2495 struct ale_rx_page *rx_page;
2499 uint32_t length, prod, seqno, status, vtags;
2503 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2504 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2505 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2506 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2507 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2509 * Don't directly access producer index as hardware may
2510 * update it while Rx handler is in progress. It would
2511 * be even better if there is a way to let hardware
2512 * know how far driver processed its received frames.
2513 * Alternatively, hardware could provide a way to disable
2514 * CMB updates until driver acknowledges the end of CMB
2517 prod = *rx_page->cmb_addr;
2518 for (prog = 0; prog < count; prog++) {
2519 if (rx_page->cons >= prod)
2521 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2522 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2523 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2525 * Normally I believe this should not happen unless
2526 * severe driver bug or corrupted memory. However
2527 * it seems to happen under certain conditions which
2528 * is triggered by abrupt Rx events such as initiation
2529 * of bulk transfer of remote host. It's not easy to
2530 * reproduce this and I doubt it could be related
2531 * with FIFO overflow of hardware or activity of Tx
2532 * CMB updates. I also remember similar behaviour
2533 * seen on RealTek 8139 which uses resembling Rx
2537 device_printf(sc->ale_dev,
2538 "garbled seq: %u, expected: %u -- "
2539 "resetting!\n", seqno,
2540 sc->ale_cdata.ale_rx_seqno);
2543 /* Frame received. */
2544 sc->ale_cdata.ale_rx_seqno++;
2545 length = ALE_RX_BYTES(le32toh(rs->length));
2546 status = le32toh(rs->flags);
2547 if ((status & ALE_RD_ERROR) != 0) {
2549 * We want to pass the following frames to upper
2550 * layer regardless of error status of Rx return
2553 * o IP/TCP/UDP checksum is bad.
2554 * o frame length and protocol specific length
2557 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2558 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2559 ALE_RD_TRUNC)) != 0) {
2560 ale_rx_update_page(sc, &rx_page, length, &prod);
2565 * m_devget(9) is major bottle-neck of ale(4)(It comes
2566 * from hardware limitation). For jumbo frames we could
2567 * get a slightly better performance if driver use
2568 * m_getjcl(9) with proper buffer size argument. However
2569 * that would make code more complicated and I don't
2570 * think users would expect good Rx performance numbers
2571 * on these low-end consumer ethernet controller.
2573 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2574 ETHER_ALIGN, ifp, NULL);
2577 ale_rx_update_page(sc, &rx_page, length, &prod);
2580 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2581 (status & ALE_RD_IPV4) != 0)
2582 ale_rxcsum(sc, m, status);
2583 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2584 (status & ALE_RD_VLAN) != 0) {
2585 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2586 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
2587 m->m_flags |= M_VLANTAG;
2590 /* Pass it to upper layer. */
2591 (*ifp->if_input)(ifp, m);
2593 ale_rx_update_page(sc, &rx_page, length, &prod);
2596 return (count > 0 ? 0 : EAGAIN);
2602 struct ale_softc *sc;
2603 struct mii_data *mii;
2605 sc = (struct ale_softc *)arg;
2607 ALE_LOCK_ASSERT(sc);
2609 mii = device_get_softc(sc->ale_miibus);
2611 ale_stats_update(sc);
2613 * Reclaim Tx buffers that have been transferred. It's not
2614 * needed here but it would release allocated mbuf chains
2615 * faster and limit the maximum delay to a hz.
2619 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2623 ale_reset(struct ale_softc *sc)
2628 /* Initialize PCIe module. From Linux. */
2629 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2631 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2632 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2634 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2638 device_printf(sc->ale_dev, "master reset timeout!\n");
2640 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2641 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2647 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2653 struct ale_softc *sc;
2655 sc = (struct ale_softc *)xsc;
2657 ale_init_locked(sc);
2662 ale_init_locked(struct ale_softc *sc)
2665 struct mii_data *mii;
2666 uint8_t eaddr[ETHER_ADDR_LEN];
2668 uint32_t reg, rxf_hi, rxf_lo;
2670 ALE_LOCK_ASSERT(sc);
2673 mii = device_get_softc(sc->ale_miibus);
2675 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2678 * Cancel any pending I/O.
2682 * Reset the chip to a known state.
2685 /* Initialize Tx descriptors, DMA memory blocks. */
2686 ale_init_rx_pages(sc);
2687 ale_init_tx_ring(sc);
2689 /* Reprogram the station address. */
2690 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2691 CSR_WRITE_4(sc, ALE_PAR0,
2692 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2693 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2695 * Clear WOL status and disable all WOL feature as WOL
2696 * would interfere Rx operation under normal environments.
2698 CSR_READ_4(sc, ALE_WOL_CFG);
2699 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2701 * Set Tx descriptor/RXF0/CMB base addresses. They share
2702 * the same high address part of DMAable region.
2704 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2705 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2706 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2707 CSR_WRITE_4(sc, ALE_TPD_CNT,
2708 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2709 /* Set Rx page base address, note we use single queue. */
2710 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2711 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2712 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2713 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2714 /* Set Tx/Rx CMB addresses. */
2715 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2716 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2717 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2718 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2719 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2720 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2721 /* Mark RXF0 is valid. */
2722 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2723 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2725 * No need to initialize RFX1/RXF2/RXF3. We don't use
2729 /* Set Rx page size, excluding guard frame size. */
2730 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2731 /* Tell hardware that we're ready to load DMA blocks. */
2732 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2734 /* Set Rx/Tx interrupt trigger threshold. */
2735 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2736 (4 << INT_TRIG_TX_THRESH_SHIFT));
2739 * Set interrupt trigger timer, its purpose and relation
2740 * with interrupt moderation mechanism is not clear yet.
2742 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2743 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2744 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2746 /* Configure interrupt moderation timer. */
2747 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2748 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2749 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2750 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2751 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2752 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2753 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2754 reg |= MASTER_IM_RX_TIMER_ENB;
2755 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2756 reg |= MASTER_IM_TX_TIMER_ENB;
2757 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2758 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2760 /* Set Maximum frame size of controller. */
2761 if (ifp->if_mtu < ETHERMTU)
2762 sc->ale_max_frame_size = ETHERMTU;
2764 sc->ale_max_frame_size = ifp->if_mtu;
2765 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2767 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2768 /* Configure IPG/IFG parameters. */
2769 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2770 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2771 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2772 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2773 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2774 /* Set parameters for half-duplex media. */
2775 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2776 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2777 HDPX_CFG_LCOL_MASK) |
2778 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2779 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2780 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2781 HDPX_CFG_ABEBT_MASK) |
2782 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2783 HDPX_CFG_JAMIPG_MASK));
2785 /* Configure Tx jumbo frame parameters. */
2786 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2787 if (ifp->if_mtu < ETHERMTU)
2788 reg = sc->ale_max_frame_size;
2789 else if (ifp->if_mtu < 6 * 1024)
2790 reg = (sc->ale_max_frame_size * 2) / 3;
2792 reg = sc->ale_max_frame_size / 2;
2793 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2794 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2795 TX_JUMBO_THRESH_UNIT_SHIFT);
2797 /* Configure TxQ. */
2798 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2799 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2800 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2801 TXQ_CFG_TPD_BURST_MASK;
2802 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2804 /* Configure Rx jumbo frame & flow control parameters. */
2805 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2806 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2807 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2808 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2809 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2810 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2811 RX_JUMBO_LKAH_MASK));
2812 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2813 rxf_hi = (reg * 7) / 10;
2814 rxf_lo = (reg * 3)/ 10;
2815 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2816 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2817 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2818 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2819 RX_FIFO_PAUSE_THRESH_HI_MASK));
2823 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2824 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2826 /* Configure RxQ. */
2827 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2828 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2830 /* Configure DMA parameters. */
2832 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2833 reg |= DMA_CFG_TXCMB_ENB;
2834 CSR_WRITE_4(sc, ALE_DMA_CFG,
2835 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2836 sc->ale_dma_rd_burst | reg |
2837 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2838 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2839 DMA_CFG_RD_DELAY_CNT_MASK) |
2840 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2841 DMA_CFG_WR_DELAY_CNT_MASK));
2844 * Hardware can be configured to issue SMB interrupt based
2845 * on programmed interval. Since there is a callout that is
2846 * invoked for every hz in driver we use that instead of
2847 * relying on periodic SMB interrupt.
2849 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2850 /* Clear MAC statistics. */
2851 ale_stats_clear(sc);
2854 * Configure Tx/Rx MACs.
2855 * - Auto-padding for short frames.
2856 * - Enable CRC generation.
2857 * Actual reconfiguration of MAC for resolved speed/duplex
2858 * is followed after detection of link establishment.
2859 * AR81xx always does checksum computation regardless of
2860 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2861 * cause Rx handling issue for fragmented IP datagrams due
2864 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2865 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2866 MAC_CFG_PREAMBLE_MASK);
2867 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2868 reg |= MAC_CFG_SPEED_10_100;
2870 reg |= MAC_CFG_SPEED_1000;
2871 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2873 /* Set up the receive filter. */
2877 /* Acknowledge all pending interrupts and clear it. */
2878 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2879 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2880 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2882 sc->ale_flags &= ~ALE_FLAG_LINK;
2883 /* Switch to the current media. */
2886 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2888 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2889 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2893 ale_stop(struct ale_softc *sc)
2896 struct ale_txdesc *txd;
2900 ALE_LOCK_ASSERT(sc);
2902 * Mark the interface down and cancel the watchdog timer.
2905 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2906 sc->ale_flags &= ~ALE_FLAG_LINK;
2907 callout_stop(&sc->ale_tick_ch);
2908 sc->ale_watchdog_timer = 0;
2909 ale_stats_update(sc);
2910 /* Disable interrupts. */
2911 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2912 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2913 /* Disable queue processing and DMA. */
2914 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2915 reg &= ~TXQ_CFG_ENB;
2916 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2917 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2918 reg &= ~RXQ_CFG_ENB;
2919 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2920 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2921 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2922 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2924 /* Stop Rx/Tx MACs. */
2926 /* Disable interrupts which might be touched in taskq handler. */
2927 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2930 * Free TX mbufs still in the queues.
2932 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2933 txd = &sc->ale_cdata.ale_txdesc[i];
2934 if (txd->tx_m != NULL) {
2935 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2936 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2937 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2946 ale_stop_mac(struct ale_softc *sc)
2951 ALE_LOCK_ASSERT(sc);
2953 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2954 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2955 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2956 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2959 for (i = ALE_TIMEOUT; i > 0; i--) {
2960 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2966 device_printf(sc->ale_dev,
2967 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2971 ale_init_tx_ring(struct ale_softc *sc)
2973 struct ale_txdesc *txd;
2976 ALE_LOCK_ASSERT(sc);
2978 sc->ale_cdata.ale_tx_prod = 0;
2979 sc->ale_cdata.ale_tx_cons = 0;
2980 sc->ale_cdata.ale_tx_cnt = 0;
2982 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2983 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2984 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2985 txd = &sc->ale_cdata.ale_txdesc[i];
2988 *sc->ale_cdata.ale_tx_cmb = 0;
2989 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2990 sc->ale_cdata.ale_tx_cmb_map,
2991 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2992 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2993 sc->ale_cdata.ale_tx_ring_map,
2994 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2998 ale_init_rx_pages(struct ale_softc *sc)
3000 struct ale_rx_page *rx_page;
3003 ALE_LOCK_ASSERT(sc);
3005 atomic_set_int(&sc->ale_morework, 0);
3006 sc->ale_cdata.ale_rx_seqno = 0;
3007 sc->ale_cdata.ale_rx_curp = 0;
3009 for (i = 0; i < ALE_RX_PAGES; i++) {
3010 rx_page = &sc->ale_cdata.ale_rx_page[i];
3011 bzero(rx_page->page_addr, sc->ale_pagesize);
3012 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
3014 *rx_page->cmb_addr = 0;
3015 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
3016 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3017 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
3018 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3023 ale_rxvlan(struct ale_softc *sc)
3028 ALE_LOCK_ASSERT(sc);
3031 reg = CSR_READ_4(sc, ALE_MAC_CFG);
3032 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3033 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3034 reg |= MAC_CFG_VLAN_TAG_STRIP;
3035 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
3039 ale_rxfilter(struct ale_softc *sc)
3042 struct ifmultiaddr *ifma;
3047 ALE_LOCK_ASSERT(sc);
3051 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
3052 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3053 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3054 rxcfg |= MAC_CFG_BCAST;
3055 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3056 if ((ifp->if_flags & IFF_PROMISC) != 0)
3057 rxcfg |= MAC_CFG_PROMISC;
3058 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3059 rxcfg |= MAC_CFG_ALLMULTI;
3060 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
3061 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3062 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3066 /* Program new filter. */
3067 bzero(mchash, sizeof(mchash));
3069 if_maddr_rlock(ifp);
3070 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) {
3071 if (ifma->ifma_addr->sa_family != AF_LINK)
3073 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3074 ifma->ifma_addr), ETHER_ADDR_LEN);
3075 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3077 if_maddr_runlock(ifp);
3079 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3080 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3081 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3085 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3091 value = *(int *)arg1;
3092 error = sysctl_handle_int(oidp, &value, 0, req);
3093 if (error || req->newptr == NULL)
3095 if (value < low || value > high)
3097 *(int *)arg1 = value;
3103 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)
3105 return (sysctl_int_range(oidp, arg1, arg2, req,
3106 ALE_PROC_MIN, ALE_PROC_MAX));
3110 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
3113 return (sysctl_int_range(oidp, arg1, arg2, req,
3114 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));