2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/endian.h>
37 #include <sys/ctype.h>
40 #include <sys/taskqueue.h>
42 #include <machine/bus.h>
44 #include <dev/ata/ata-all.h>
45 #include <dev/ata/ata-pci.h>
49 static int ata_generic_status(device_t dev);
50 static int ata_wait(struct ata_channel *ch, int unit, u_int8_t);
51 static void ata_pio_read(struct ata_request *, int);
52 static void ata_pio_write(struct ata_request *, int);
53 static void ata_tf_read(struct ata_request *);
54 static void ata_tf_write(struct ata_request *);
57 * low level ATA functions
60 ata_generic_hw(device_t dev)
62 struct ata_channel *ch = device_get_softc(dev);
64 ch->hw.begin_transaction = ata_begin_transaction;
65 ch->hw.end_transaction = ata_end_transaction;
66 ch->hw.status = ata_generic_status;
67 ch->hw.softreset = NULL;
68 ch->hw.command = ata_generic_command;
69 ch->hw.tf_read = ata_tf_read;
70 ch->hw.tf_write = ata_tf_write;
71 ch->hw.pm_read = NULL;
72 ch->hw.pm_write = NULL;
75 /* must be called with ATA channel locked and state_mtx held */
77 ata_begin_transaction(struct ata_request *request)
79 struct ata_channel *ch = device_get_softc(request->parent);
82 ATA_DEBUG_RQ(request, "begin transaction");
84 /* disable ATAPI DMA writes if HW doesn't support it */
85 if ((ch->flags & ATA_NO_ATAPI_DMA) &&
86 (request->flags & ATA_R_ATAPI) == ATA_R_ATAPI)
87 request->flags &= ~ATA_R_DMA;
88 if ((ch->flags & ATA_ATAPI_DMA_RO) &&
89 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
90 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
91 request->flags &= ~ATA_R_DMA;
93 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
95 /* ATA PIO data transfer and control commands */
98 /* record command direction here as our request might be gone later */
99 int write = (request->flags & ATA_R_WRITE);
102 if (ch->hw.command(request)) {
103 device_printf(request->parent, "error issuing %s command\n",
104 ata_cmd2str(request));
105 request->result = EIO;
109 /* device reset doesn't interrupt */
110 if (request->u.ata.command == ATA_DEVICE_RESET) {
112 int timeout = 1000000;
115 request->status = ATA_IDX_INB(ch, ATA_STATUS);
116 } while (request->status & ATA_S_BUSY && timeout--);
117 if (request->status & ATA_S_ERROR)
118 request->error = ATA_IDX_INB(ch, ATA_ERROR);
122 /* if write command output the data */
124 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) {
125 device_printf(request->parent,
126 "timeout waiting for write DRQ\n");
127 request->result = EIO;
130 ata_pio_write(request, request->transfersize);
135 /* ATA DMA data transfer commands */
137 /* check sanity, setup SG list and DMA engine */
138 if ((error = ch->dma.load(request, NULL, &dummy))) {
139 device_printf(request->parent, "setting up DMA failed\n");
140 request->result = error;
144 /* start DMA engine if necessary */
145 if ((ch->flags & ATA_DMA_BEFORE_CMD) &&
146 ch->dma.start && ch->dma.start(request)) {
147 device_printf(request->parent, "error starting DMA\n");
148 request->result = EIO;
153 if (ch->hw.command(request)) {
154 device_printf(request->parent, "error issuing %s command\n",
155 ata_cmd2str(request));
156 request->result = EIO;
160 /* start DMA engine */
161 if (!(ch->flags & ATA_DMA_BEFORE_CMD) &&
162 ch->dma.start && ch->dma.start(request)) {
163 device_printf(request->parent, "error starting DMA\n");
164 request->result = EIO;
169 /* ATAPI PIO commands */
171 /* is this just a POLL DSC command ? */
172 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
173 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit));
175 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
176 request->result = EBUSY;
180 /* start ATAPI operation */
181 if (ch->hw.command(request)) {
182 device_printf(request->parent, "error issuing ATA PACKET command\n");
183 request->result = EIO;
188 /* ATAPI DMA commands */
189 case ATA_R_ATAPI|ATA_R_DMA:
190 /* is this just a POLL DSC command ? */
191 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
192 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit));
194 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
195 request->result = EBUSY;
199 /* check sanity, setup SG list and DMA engine */
200 if ((error = ch->dma.load(request, NULL, &dummy))) {
201 device_printf(request->parent, "setting up DMA failed\n");
202 request->result = error;
206 /* start ATAPI operation */
207 if (ch->hw.command(request)) {
208 device_printf(request->parent, "error issuing ATA PACKET command\n");
209 request->result = EIO;
213 /* start DMA engine */
214 if (ch->dma.start && ch->dma.start(request)) {
215 request->result = EIO;
221 printf("ata_begin_transaction OOPS!!!\n");
224 if (ch->dma.unload) {
225 ch->dma.unload(request);
227 return ATA_OP_FINISHED;
230 callout_reset(&request->callout, request->timeout * hz,
231 (timeout_t*)ata_timeout, request);
232 return ATA_OP_CONTINUES;
235 /* must be called with ATA channel locked and state_mtx held */
237 ata_end_transaction(struct ata_request *request)
239 struct ata_channel *ch = device_get_softc(request->parent);
242 ATA_DEBUG_RQ(request, "end transaction");
244 /* clear interrupt and get status */
245 request->status = ATA_IDX_INB(ch, ATA_STATUS);
247 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
249 /* ATA PIO data transfer and control commands */
252 /* on timeouts we have no data or anything so just return */
253 if (request->flags & ATA_R_TIMEOUT)
256 /* on control commands read back registers to the request struct */
257 if (request->flags & ATA_R_CONTROL) {
258 ch->hw.tf_read(request);
261 /* if we got an error we are done with the HW */
262 if (request->status & ATA_S_ERROR) {
263 request->error = ATA_IDX_INB(ch, ATA_ERROR);
267 /* are we moving data ? */
268 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
270 /* if read data get it */
271 if (request->flags & ATA_R_READ) {
272 int flags = ATA_S_DRQ;
274 if (request->u.ata.command != ATA_ATAPI_IDENTIFY)
275 flags |= ATA_S_READY;
276 if (ata_wait(ch, request->unit, flags) < 0) {
277 device_printf(request->parent,
278 "timeout waiting for read DRQ\n");
279 request->result = EIO;
282 ata_pio_read(request, request->transfersize);
285 /* update how far we've gotten */
286 request->donecount += request->transfersize;
288 /* do we need a scoop more ? */
289 if (request->bytecount > request->donecount) {
291 /* set this transfer size according to HW capabilities */
292 request->transfersize =
293 min((request->bytecount - request->donecount),
294 request->transfersize);
296 /* if data write command, output the data */
297 if (request->flags & ATA_R_WRITE) {
299 /* if we get an error here we are done with the HW */
300 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) {
301 device_printf(request->parent,
302 "timeout waiting for write DRQ\n");
303 request->status = ATA_IDX_INB(ch, ATA_STATUS);
307 /* output data and return waiting for new interrupt */
308 ata_pio_write(request, request->transfersize);
312 /* if data read command, return & wait for interrupt */
313 if (request->flags & ATA_R_READ)
320 /* ATA DMA data transfer commands */
323 /* stop DMA engine and get status */
325 request->dma->status = ch->dma.stop(request);
327 /* did we get error or data */
328 if (request->status & ATA_S_ERROR)
329 request->error = ATA_IDX_INB(ch, ATA_ERROR);
330 else if (request->dma->status & ATA_BMSTAT_ERROR)
331 request->status |= ATA_S_ERROR;
332 else if (!(request->flags & ATA_R_TIMEOUT))
333 request->donecount = request->bytecount;
335 /* release SG list etc */
336 ch->dma.unload(request);
341 /* ATAPI PIO commands */
343 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
345 /* on timeouts we have no data or anything so just return */
346 if (request->flags & ATA_R_TIMEOUT)
349 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
350 (request->status & ATA_S_DRQ)) {
353 /* this seems to be needed for some (slow) devices */
356 if (!(request->status & ATA_S_DRQ)) {
357 device_printf(request->parent, "command interrupt without DRQ\n");
358 request->status = ATA_S_ERROR;
361 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
362 (request->flags & ATA_R_ATAPI16) ? 8 : 6);
363 /* return wait for interrupt */
367 if (request->flags & ATA_R_READ) {
368 request->status = ATA_S_ERROR;
369 device_printf(request->parent,
370 "%s trying to write on read buffer\n",
371 ata_cmd2str(request));
375 ata_pio_write(request, length);
376 request->donecount += length;
378 /* set next transfer size according to HW capabilities */
379 request->transfersize = min((request->bytecount-request->donecount),
380 request->transfersize);
381 /* return wait for interrupt */
385 if (request->flags & ATA_R_WRITE) {
386 request->status = ATA_S_ERROR;
387 device_printf(request->parent,
388 "%s trying to read on write buffer\n",
389 ata_cmd2str(request));
392 ata_pio_read(request, length);
393 request->donecount += length;
395 /* set next transfer size according to HW capabilities */
396 request->transfersize = min((request->bytecount-request->donecount),
397 request->transfersize);
398 /* return wait for interrupt */
401 case ATAPI_P_DONEDRQ:
402 device_printf(request->parent,
403 "WARNING - %s DONEDRQ non conformant device\n",
404 ata_cmd2str(request));
405 if (request->flags & ATA_R_READ) {
406 ata_pio_read(request, length);
407 request->donecount += length;
409 else if (request->flags & ATA_R_WRITE) {
410 ata_pio_write(request, length);
411 request->donecount += length;
414 request->status = ATA_S_ERROR;
419 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
420 request->error = ATA_IDX_INB(ch, ATA_ERROR);
424 device_printf(request->parent, "unknown transfer phase\n");
425 request->status = ATA_S_ERROR;
431 /* ATAPI DMA commands */
432 case ATA_R_ATAPI|ATA_R_DMA:
434 /* stop DMA engine and get status */
436 request->dma->status = ch->dma.stop(request);
438 /* did we get error or data */
439 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
440 request->error = ATA_IDX_INB(ch, ATA_ERROR);
441 else if (request->dma->status & ATA_BMSTAT_ERROR)
442 request->status |= ATA_S_ERROR;
443 else if (!(request->flags & ATA_R_TIMEOUT))
444 request->donecount = request->bytecount;
446 /* release SG list etc */
447 ch->dma.unload(request);
453 printf("ata_end_transaction OOPS!!\n");
456 callout_stop(&request->callout);
457 return ATA_OP_FINISHED;
460 return ATA_OP_CONTINUES;
463 /* must be called with ATA channel locked and state_mtx held */
465 ata_generic_reset(device_t dev)
467 struct ata_channel *ch = device_get_softc(dev);
469 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
470 u_int8_t err = 0, lsb = 0, msb = 0;
471 int mask = 0, timeout;
473 /* do we have any signs of ATA/ATAPI HW being present ? */
474 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
476 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
477 if (((ostat0 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) &&
483 /* in some setups we dont want to test for a slave */
484 if (!(ch->flags & ATA_NO_SLAVE)) {
485 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE));
487 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
488 if (((ostat1 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) &&
496 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
497 mask, ostat0, ostat1);
499 /* if nothing showed up there is no need to get any further */
500 /* XXX SOS is that too strong?, we just might loose devices here */
505 /* reset (both) devices on this channel */
506 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
508 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
510 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
512 ATA_IDX_INB(ch, ATA_ERROR);
514 /* wait for BUSY to go inactive */
515 for (timeout = 0; timeout < 310; timeout++) {
516 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
517 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER));
519 if (ch->flags & ATA_STATUS_IS_LONG)
520 stat0 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff;
522 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
523 err = ATA_IDX_INB(ch, ATA_ERROR);
524 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
525 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
528 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
529 stat0, err, lsb, msb);
530 if (stat0 == err && lsb == err && msb == err &&
531 timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
533 if (!(stat0 & ATA_S_BUSY)) {
534 if ((err & 0x7f) == ATA_E_ILI) {
535 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
536 ch->devices |= ATA_ATAPI_MASTER;
538 else if (stat0 & ATA_S_READY) {
539 ch->devices |= ATA_ATA_MASTER;
542 else if ((stat0 & 0x0f) && err == lsb && err == msb) {
548 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
549 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
550 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE));
552 if (ch->flags & ATA_STATUS_IS_LONG)
553 stat1 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff;
555 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
556 err = ATA_IDX_INB(ch, ATA_ERROR);
557 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
558 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
561 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
562 stat1, err, lsb, msb);
563 if (stat1 == err && lsb == err && msb == err &&
564 timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
566 if (!(stat1 & ATA_S_BUSY)) {
567 if ((err & 0x7f) == ATA_E_ILI) {
568 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
569 ch->devices |= ATA_ATAPI_SLAVE;
571 else if (stat1 & ATA_S_READY) {
572 ch->devices |= ATA_ATA_SLAVE;
575 else if ((stat1 & 0x0f) && err == lsb && err == msb) {
581 if ((ch->flags & ATA_KNOWN_PRESENCE) == 0 &&
582 timeout > ((mask == 0x03) ? 20 : 10)) {
583 if ((mask & 0x01) && stat0 == 0xff)
585 if ((mask & 0x02) && stat1 == 0xff)
588 if (((mask & 0x01) == 0 || !(stat0 & ATA_S_BUSY)) &&
589 ((mask & 0x02) == 0 || !(stat1 & ATA_S_BUSY)))
595 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n",
596 stat0, stat1, ch->devices);
599 /* must be called with ATA channel locked and state_mtx held */
601 ata_generic_status(device_t dev)
603 struct ata_channel *ch = device_get_softc(dev);
605 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
607 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
614 ata_wait(struct ata_channel *ch, int unit, u_int8_t mask)
621 /* wait at max 1 second for device to get !BUSY */
622 while (timeout < 1000000) {
623 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
625 /* if drive fails status, reselect the drive and try again */
626 if (status == 0xff) {
627 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit));
634 if (!(status & ATA_S_BUSY))
637 if (timeout > 1000) {
646 if (timeout >= 1000000)
649 return (status & ATA_S_ERROR);
653 /* wait 50 msec for bits wanted */
656 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
657 if ((status & mask) == mask)
658 return (status & ATA_S_ERROR);
665 ata_generic_command(struct ata_request *request)
667 struct ata_channel *ch = device_get_softc(request->parent);
670 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit));
672 /* ready to issue command ? */
673 if (ata_wait(ch, request->unit, 0) < 0) {
674 device_printf(request->parent, "timeout waiting to issue command\n");
675 request->flags |= ATA_R_TIMEOUT;
679 /* enable interrupt */
680 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
682 if (request->flags & ATA_R_ATAPI) {
686 /* issue packet command to controller */
687 if (request->flags & ATA_R_DMA) {
688 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
689 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
690 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
693 ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
694 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
695 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
697 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
699 /* command interrupt device ? just return and wait for interrupt */
700 if (request->flags & ATA_R_ATAPI_INTR)
703 /* command processed ? */
704 res = ata_wait(ch, request->unit, 0);
707 device_printf(request->parent,
708 "timeout waiting for PACKET command\n");
709 request->flags |= ATA_R_TIMEOUT;
713 /* wait for ready to write ATAPI command block */
715 int reason = ATA_IDX_INB(ch, ATA_IREASON);
716 int status = ATA_IDX_INB(ch, ATA_STATUS);
718 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
719 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
724 device_printf(request->parent,
725 "timeout waiting for ATAPI ready\n");
726 request->flags |= ATA_R_TIMEOUT;
730 /* this seems to be needed for some (slow) devices */
733 /* output command block */
734 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
735 (request->flags & ATA_R_ATAPI16) ? 8 : 6);
738 ch->hw.tf_write(request);
740 /* issue command to controller */
741 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
747 ata_tf_read(struct ata_request *request)
749 struct ata_channel *ch = device_get_softc(request->parent);
751 if (request->flags & ATA_R_48BIT) {
752 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
753 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
755 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
756 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
757 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
759 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
760 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
761 request->u.ata.lba |=
762 (ATA_IDX_INB(ch, ATA_SECTOR) |
763 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
764 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
767 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
768 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
769 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
770 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
771 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
776 ata_tf_write(struct ata_request *request)
778 struct ata_channel *ch = device_get_softc(request->parent);
780 struct ata_device *atadev = device_get_softc(request->dev);
783 if (request->flags & ATA_R_48BIT) {
784 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
785 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
786 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
787 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
788 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
789 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
790 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
791 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
792 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
793 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
794 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
797 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
798 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
800 if (atadev->flags & ATA_D_USE_CHS) {
803 if (atadev->param.atavalid & ATA_FLAG_54_58) {
804 heads = atadev->param.current_heads;
805 sectors = atadev->param.current_sectors;
808 heads = atadev->param.heads;
809 sectors = atadev->param.sectors;
812 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
813 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
814 (request->u.ata.lba / (sectors * heads)));
815 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
816 (request->u.ata.lba / (sectors * heads)) >> 8);
817 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) |
818 (((request->u.ata.lba% (sectors * heads)) /
823 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
824 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
825 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
826 ATA_IDX_OUTB(ch, ATA_DRIVE,
827 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
828 ((request->u.ata.lba >> 24) & 0x0f));
836 ata_pio_read(struct ata_request *request, int length)
838 struct ata_channel *ch = device_get_softc(request->parent);
839 int size = min(request->transfersize, length);
843 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) {
844 ATA_IDX_INSW_STRM(ch, ATA_DATA,
845 (void*)((uintptr_t)request->data+request->donecount),
846 size / sizeof(int16_t));
848 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)buf, 1);
849 ((uint8_t *)request->data + request->donecount +
850 (size & ~1))[0] = buf[0];
853 ATA_IDX_INSL_STRM(ch, ATA_DATA,
854 (void*)((uintptr_t)request->data+request->donecount),
855 size / sizeof(int32_t));
857 if (request->transfersize < length) {
858 device_printf(request->parent, "WARNING - %s read data overrun %d>%d\n",
859 ata_cmd2str(request), length, request->transfersize);
860 for (resid = request->transfersize + (size & 1); resid < length;
861 resid += sizeof(int16_t))
862 ATA_IDX_INW(ch, ATA_DATA);
867 ata_pio_write(struct ata_request *request, int length)
869 struct ata_channel *ch = device_get_softc(request->parent);
870 int size = min(request->transfersize, length);
874 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) {
875 ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
876 (void*)((uintptr_t)request->data+request->donecount),
877 size / sizeof(int16_t));
879 buf[0] = ((uint8_t *)request->data + request->donecount +
881 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)buf, 1);
884 ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
885 (void*)((uintptr_t)request->data+request->donecount),
886 size / sizeof(int32_t));
888 if (request->transfersize < length) {
889 device_printf(request->parent, "WARNING - %s write data underrun %d>%d\n",
890 ata_cmd2str(request), length, request->transfersize);
891 for (resid = request->transfersize + (size & 1); resid < length;
892 resid += sizeof(int16_t))
893 ATA_IDX_OUTW(ch, ATA_DATA, 0);