2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
39 #include <sys/mutex.h>
41 #include <sys/taskqueue.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
47 #include <dev/ata/ata-all.h>
51 ata_sata_phy_check_events(device_t dev, int port)
53 struct ata_channel *ch = device_get_softc(dev);
54 u_int32_t error, status;
56 ata_sata_scr_read(ch, port, ATA_SERROR, &error);
58 /* Check that SError value is sane. */
59 if (error == 0xffffffff)
62 /* Clear set error bits/interrupt. */
64 ata_sata_scr_write(ch, port, ATA_SERROR, error);
66 /* if we have a connection event deal with it */
67 if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) {
69 ata_sata_scr_read(ch, port, ATA_SSTATUS, &status);
70 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
71 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
72 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) {
73 device_printf(dev, "CONNECT requested\n");
75 device_printf(dev, "DISCONNECT requested\n");
77 taskqueue_enqueue(taskqueue_thread, &ch->conntask);
82 ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val)
85 if (ch->hw.pm_read != NULL)
86 return (ch->hw.pm_read(ch->dev, port, reg, val));
87 if (ch->r_io[reg].res) {
88 *val = ATA_IDX_INL(ch, reg);
95 ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val)
98 if (ch->hw.pm_write != NULL)
99 return (ch->hw.pm_write(ch->dev, port, reg, val));
100 if (ch->r_io[reg].res) {
101 ATA_IDX_OUTL(ch, reg, val);
108 ata_sata_connect(struct ata_channel *ch, int port, int quick)
113 /* wait up to 1 second for "connect well" */
114 timeout = (quick == 2) ? 0 : 100;
117 if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status))
119 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
120 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
121 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
130 device_printf(ch->dev, "SATA connect timeout status=%08x\n",
133 device_printf(ch->dev, "p%d: SATA connect timeout status=%08x\n",
136 } else if (port < 0) {
137 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n",
140 device_printf(ch->dev, "p%d: SATA connect time=%dms status=%08x\n",
141 port, t * 10, status);
145 /* clear SATA error register */
146 ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff);
148 return ((t > timeout) ? 0 : 1);
152 ata_sata_phy_reset(device_t dev, int port, int quick)
154 struct ata_channel *ch = device_get_softc(dev);
155 int loop, retry, sata_rev;
159 sata_rev = ch->user[port < 0 ? 0 : port].revision;
167 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
169 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) {
170 ata_sata_scr_write(ch, port, ATA_SCONTROL,
171 ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 :
172 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER));
173 return ata_sata_connect(ch, port, quick);
179 device_printf(dev, "hard reset ...\n");
181 device_printf(dev, "p%d: hard reset ...\n", port);
185 val1 = ATA_SC_SPD_SPEED_GEN1;
186 else if (sata_rev == 2)
187 val1 = ATA_SC_SPD_SPEED_GEN2;
188 else if (sata_rev == 3)
189 val1 = ATA_SC_SPD_SPEED_GEN3;
192 for (retry = 0; retry < 10; retry++) {
193 for (loop = 0; loop < 10; loop++) {
194 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, ATA_SC_DET_RESET |
195 val1 | ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))
198 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
200 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
204 for (loop = 0; loop < 10; loop++) {
205 if (ata_sata_scr_write(ch, port, ATA_SCONTROL,
206 ATA_SC_DET_IDLE | val1 | ((ch->pm_level > 0) ? 0 :
207 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)))
210 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
212 if ((val & ATA_SC_DET_MASK) == 0)
213 return ata_sata_connect(ch, port, 0);
217 /* Clear SATA error register. */
218 ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff);
222 device_printf(dev, "hard reset failed\n");
224 device_printf(dev, "p%d: hard reset failed\n", port);
231 ata_sata_setmode(device_t dev, int target, int mode)
234 return (min(mode, ATA_UDMA5));
238 ata_sata_getrev(device_t dev, int target)
240 struct ata_channel *ch = device_get_softc(dev);
242 if (ch->r_io[ATA_SSTATUS].res)
243 return ((ATA_IDX_INL(ch, ATA_SSTATUS) & 0x0f0) >> 4);
248 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
251 if (request->flags & ATA_R_ATAPI) {
252 fis[0] = 0x27; /* host to device */
253 fis[1] = 0x80 | (request->unit & 0x0f);
254 fis[2] = ATA_PACKET_CMD;
255 if (request->flags & (ATA_R_READ | ATA_R_WRITE))
258 fis[5] = request->transfersize;
259 fis[6] = request->transfersize >> 8;
262 fis[15] = ATA_A_4BIT;
266 fis[0] = 0x27; /* host to device */
267 fis[1] = 0x80 | (request->unit & 0x0f);
268 fis[2] = request->u.ata.command;
269 fis[3] = request->u.ata.feature;
270 fis[4] = request->u.ata.lba;
271 fis[5] = request->u.ata.lba >> 8;
272 fis[6] = request->u.ata.lba >> 16;
274 if (!(request->flags & ATA_R_48BIT))
275 fis[7] |= (ATA_D_IBM | (request->u.ata.lba >> 24 & 0x0f));
276 fis[8] = request->u.ata.lba >> 24;
277 fis[9] = request->u.ata.lba >> 32;
278 fis[10] = request->u.ata.lba >> 40;
279 fis[11] = request->u.ata.feature >> 8;
280 fis[12] = request->u.ata.count;
281 fis[13] = request->u.ata.count >> 8;
282 fis[15] = ATA_A_4BIT;
289 ata_pm_identify(device_t dev)
291 struct ata_channel *ch = device_get_softc(dev);
292 u_int32_t pm_chipid, pm_revision, pm_ports;
295 /* get PM vendor & product data */
296 if (ch->hw.pm_read(dev, ATA_PM, 0, &pm_chipid)) {
297 device_printf(dev, "error getting PM vendor data\n");
301 /* get PM revision data */
302 if (ch->hw.pm_read(dev, ATA_PM, 1, &pm_revision)) {
303 device_printf(dev, "error getting PM revison data\n");
307 /* get number of HW ports on the PM */
308 if (ch->hw.pm_read(dev, ATA_PM, 2, &pm_ports)) {
309 device_printf(dev, "error getting PM port info\n");
312 pm_ports &= 0x0000000f;
314 /* chip specific quirks */
317 /* This PM declares 6 ports, while only 5 of them are real.
318 * Port 5 is enclosure management bridge port, which has implementation
319 * problems, causing probe faults. Hide it for now. */
320 device_printf(dev, "SiI 3726 (rev=%x) Port Multiplier with %d (5) ports\n",
321 pm_revision, pm_ports);
326 /* This PM declares 7 ports, while only 5 of them are real.
327 * Port 5 is some fake "Config Disk" with 640 sectors size,
328 * port 6 is enclosure management bridge port.
329 * Both fake ports has implementation problems, causing
330 * probe faults. Hide them for now. */
331 device_printf(dev, "SiI 4726 (rev=%x) Port Multiplier with %d (5) ports\n",
332 pm_revision, pm_ports);
337 device_printf(dev, "Port Multiplier (id=%08x rev=%x) with %d ports\n",
338 pm_chipid, pm_revision, pm_ports);
341 /* reset all ports and register if anything connected */
342 for (port=0; port < pm_ports; port++) {
345 if (!ata_sata_phy_reset(dev, port, 1))
349 * XXX: I have no idea how to properly wait for PMP port hardreset
350 * completion. Without this delay soft reset does not completes
355 signature = ch->hw.softreset(dev, port);
358 device_printf(dev, "p%d: SIGNATURE=%08x\n", port, signature);
360 /* figure out whats there */
361 switch (signature >> 16) {
363 ch->devices |= (ATA_ATA_MASTER << port);
366 ch->devices |= (ATA_ATAPI_MASTER << port);